Merge pull request #44 from Tiwalun/stm32wb55-support

Add RCC and SYSCFG for STM32WB55
2021-06-11 22:46:34 +02:00 · 2021-06-11 22:46:34 +02:00 · 8e71f3da8e
commit 8e71f3da8e
parent bd443787e2 6c872019d0
3 changed files with 2041 additions and 0 deletions
--- a/data/registers/rcc_wb55.yaml
+++ b/data/registers/rcc_wb55.yaml
--- a/data/registers/syscfg_wb55.yaml
+++ b/data/registers/syscfg_wb55.yaml
@ -0,0 +1,400 @@
+---
+block/SYSCFG:
+  description: System configuration controller
+  items:
+    - name: MEMRMP
+      description: memory remap register
+      byte_offset: 0
+      fieldset: MEMRMP
+    - name: CFGR1
+      description: configuration register 1
+      byte_offset: 4
+      fieldset: CFGR1
+    - name: EXTICR
+      description: external interrupt configuration register 1
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 8
+      fieldset: EXTICR
+    - name: SCSR
+      description: SCSR
+      byte_offset: 24
+      fieldset: SCSR
+    - name: CFGR2
+      description: CFGR2
+      byte_offset: 28
+      fieldset: CFGR2
+    - name: SWPR
+      description: SRAM2 write protection register
+      byte_offset: 32
+      access: Write
+      fieldset: SWPR
+    - name: SKR
+      description: SKR
+      byte_offset: 36
+      access: Write
+      fieldset: SKR
+    - name: SWPR2
+      description: SRAM2 write protection register 2
+      byte_offset: 40
+      access: Write
+      fieldset: SWPR2
+    - name: IMR1
+      description: CPU1 interrupt mask register 1
+      byte_offset: 44
+      fieldset: IMR1
+    - name: IMR2
+      description: CPU1 interrupt mask register 2
+      byte_offset: 48
+      fieldset: IMR2
+    - name: C2IMR1
+      description: CPU2 interrupt mask register 1
+      byte_offset: 52
+      fieldset: C2IMR1
+    - name: C2IMR2
+      description: CPU2 interrupt mask register 1
+      byte_offset: 56
+      fieldset: C2IMR2
+    - name: SIPCR
+      description: secure IP control register
+      byte_offset: 60
+      fieldset: SIPCR
+fieldset/C2IMR1:
+  description: CPU2 interrupt mask register 1
+  fields:
+    - name: RTCSTAMP
+      description: Peripheral RTCSTAMP interrupt mask to CPU2
+      bit_offset: 0
+      bit_size: 1
+    - name: RTCWKUP
+      description: Peripheral RTCWKUP interrupt mask to CPU2
+      bit_offset: 3
+      bit_size: 1
+    - name: RTCALARM
+      description: Peripheral RTCALARM interrupt mask to CPU2
+      bit_offset: 4
+      bit_size: 1
+    - name: RCC
+      description: Peripheral RCC interrupt mask to CPU2
+      bit_offset: 5
+      bit_size: 1
+    - name: FLASH
+      description: Peripheral FLASH interrupt mask to CPU2
+      bit_offset: 6
+      bit_size: 1
+    - name: PKA
+      description: Peripheral PKA interrupt mask to CPU2
+      bit_offset: 8
+      bit_size: 1
+    - name: RNG
+      description: Peripheral RNG interrupt mask to CPU2
+      bit_offset: 9
+      bit_size: 1
+    - name: AES
+      description: Peripheral AES1 interrupt mask to CPU2
+      bit_offset: 10
+      bit_size: 1
+      array:
+        len: 1
+        stride: 0
+    - name: COMP
+      description: Peripheral COMP interrupt mask to CPU2
+      bit_offset: 11
+      bit_size: 1
+    - name: ADC
+      description: Peripheral ADC interrupt mask to CPU2
+      bit_offset: 12
+      bit_size: 1
+fieldset/C2IMR2:
+  description: CPU2 interrupt mask register 1
+  fields:
+    - name: DMA1_CH1_IM
+      description: Peripheral DMA1 CH1 interrupt mask to CPU2
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA1_CH2_IM
+      description: Peripheral DMA1 CH2 interrupt mask to CPU2
+      bit_offset: 1
+      bit_size: 1
+    - name: DMA1_CH3_IM
+      description: Peripheral DMA1 CH3 interrupt mask to CPU2
+      bit_offset: 2
+      bit_size: 1
+    - name: DMA1_CH4_IM
+      description: Peripheral DMA1 CH4 interrupt mask to CPU2
+      bit_offset: 3
+      bit_size: 1
+    - name: DMA1_CH5_IM
+      description: Peripheral DMA1 CH5 interrupt mask to CPU2
+      bit_offset: 4
+      bit_size: 1
+    - name: DMA1_CH6_IM
+      description: Peripheral DMA1 CH6 interrupt mask to CPU2
+      bit_offset: 5
+      bit_size: 1
+    - name: DMA1_CH7_IM
+      description: Peripheral DMA1 CH7 interrupt mask to CPU2
+      bit_offset: 6
+      bit_size: 1
+    - name: DMA2_CH1_IM
+      description: Peripheral DMA2 CH1 interrupt mask to CPU1
+      bit_offset: 8
+      bit_size: 1
+    - name: DMA2_CH2_IM
+      description: Peripheral DMA2 CH2 interrupt mask to CPU1
+      bit_offset: 9
+      bit_size: 1
+    - name: DMA2_CH3_IM
+      description: Peripheral DMA2 CH3 interrupt mask to CPU1
+      bit_offset: 10
+      bit_size: 1
+    - name: DMA2_CH4_IM
+      description: Peripheral DMA2 CH4 interrupt mask to CPU1
+      bit_offset: 11
+      bit_size: 1
+    - name: DMA2_CH5_IM
+      description: Peripheral DMA2 CH5 interrupt mask to CPU1
+      bit_offset: 12
+      bit_size: 1
+    - name: DMA2_CH6_IM
+      description: Peripheral DMA2 CH6 interrupt mask to CPU1
+      bit_offset: 13
+      bit_size: 1
+    - name: DMA2_CH7_IM
+      description: Peripheral DMA2 CH7 interrupt mask to CPU1
+      bit_offset: 14
+      bit_size: 1
+    - name: DMAM_UX1_IM
+      description: Peripheral DMAM UX1 interrupt mask to CPU1
+      bit_offset: 15
+      bit_size: 1
+    - name: PVM1IM
+      description: Peripheral PVM1IM interrupt mask to CPU1
+      bit_offset: 16
+      bit_size: 1
+    - name: PVM3IM
+      description: Peripheral PVM3IM interrupt mask to CPU1
+      bit_offset: 18
+      bit_size: 1
+    - name: PVDIM
+      description: Peripheral PVDIM interrupt mask to CPU1
+      bit_offset: 20
+      bit_size: 1
+    - name: TSCIM
+      description: Peripheral TSCIM interrupt mask to CPU1
+      bit_offset: 21
+      bit_size: 1
+    - name: LCDIM
+      description: Peripheral LCDIM interrupt mask to CPU1
+      bit_offset: 22
+      bit_size: 1
+fieldset/CFGR1:
+  description: configuration register 1
+  fields:
+    - name: BOOSTEN
+      description: I/O analog switch voltage booster enable
+      bit_offset: 8
+      bit_size: 1
+    - name: I2C_PB6_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB6
+      bit_offset: 16
+      bit_size: 1
+    - name: I2C_PB7_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB7
+      bit_offset: 17
+      bit_size: 1
+    - name: I2C_PB8_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB8
+      bit_offset: 18
+      bit_size: 1
+    - name: I2C_PB9_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB9
+      bit_offset: 19
+      bit_size: 1
+    - name: I2C1_FMP
+      description: I2C1 Fast-mode Plus driving capability activation
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C3_FMP
+      description: I2C3 Fast-mode Plus driving capability activation
+      bit_offset: 22
+      bit_size: 1
+    - name: FPU_IE
+      description: Floating Point Unit interrupts enable bits
+      bit_offset: 26
+      bit_size: 6
+fieldset/CFGR2:
+  description: CFGR2
+  fields:
+    - name: CLL
+      description: Cortex-M4 LOCKUP (Hardfault) output enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: SPL
+      description: SRAM2 parity lock bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PVDL
+      description: PVD lock enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: ECCL
+      description: ECC Lock
+      bit_offset: 3
+      bit_size: 1
+    - name: SPF
+      description: SRAM2 parity error flag
+      bit_offset: 8
+      bit_size: 1
+fieldset/EXTICR:
+  description: external interrupt configuration register 1
+  fields:
+    - name: EXTI
+      description: EXTI 0 configuration bits
+      bit_offset: 0
+      bit_size: 3
+      array:
+        len: 4
+        stride: 4
+fieldset/IMR1:
+  description: CPU1 interrupt mask register 1
+  fields:
+    - name: TIM1IM
+      description: Peripheral TIM1 interrupt mask to CPU1
+      bit_offset: 13
+      bit_size: 1
+    - name: TIM16IM
+      description: Peripheral TIM16 interrupt mask to CPU1
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM17IM
+      description: Peripheral TIM17 interrupt mask to CPU1
+      bit_offset: 15
+      bit_size: 1
+    - name: EXIT5IM
+      description: Peripheral EXIT5 interrupt mask to CPU1
+      bit_offset: 21
+      bit_size: 1
+    - name: EXIT6IM
+      description: Peripheral EXIT6 interrupt mask to CPU1
+      bit_offset: 22
+      bit_size: 1
+    - name: EXIT7IM
+      description: Peripheral EXIT7 interrupt mask to CPU1
+      bit_offset: 23
+      bit_size: 1
+    - name: EXIT8IM
+      description: Peripheral EXIT8 interrupt mask to CPU1
+      bit_offset: 24
+      bit_size: 1
+    - name: EXIT9IM
+      description: Peripheral EXIT9 interrupt mask to CPU1
+      bit_offset: 25
+      bit_size: 1
+    - name: EXIT10IM
+      description: Peripheral EXIT10 interrupt mask to CPU1
+      bit_offset: 26
+      bit_size: 1
+    - name: EXIT11IM
+      description: Peripheral EXIT11 interrupt mask to CPU1
+      bit_offset: 27
+      bit_size: 1
+    - name: EXIT12IM
+      description: Peripheral EXIT12 interrupt mask to CPU1
+      bit_offset: 28
+      bit_size: 1
+    - name: EXIT13IM
+      description: Peripheral EXIT13 interrupt mask to CPU1
+      bit_offset: 29
+      bit_size: 1
+    - name: EXIT14IM
+      description: Peripheral EXIT14 interrupt mask to CPU1
+      bit_offset: 30
+      bit_size: 1
+    - name: EXIT15IM
+      description: Peripheral EXIT15 interrupt mask to CPU1
+      bit_offset: 31
+      bit_size: 1
+fieldset/IMR2:
+  description: CPU1 interrupt mask register 2
+  fields:
+    - name: PVM1IM
+      description: Peripheral PVM1 interrupt mask to CPU1
+      bit_offset: 16
+      bit_size: 1
+    - name: PVM3IM
+      description: Peripheral PVM3 interrupt mask to CPU1
+      bit_offset: 18
+      bit_size: 1
+    - name: PVDIM
+      description: Peripheral PVD interrupt mask to CPU1
+      bit_offset: 20
+      bit_size: 1
+fieldset/MEMRMP:
+  description: memory remap register
+  fields:
+    - name: MEM_MODE
+      description: Memory mapping selection
+      bit_offset: 0
+      bit_size: 3
+fieldset/SCSR:
+  description: SCSR
+  fields:
+    - name: SRAM2ER
+      description: SRAM2 Erase
+      bit_offset: 0
+      bit_size: 1
+    - name: SRAM2BSY
+      description: SRAM2 busy by erase operation
+      bit_offset: 1
+      bit_size: 1
+    - name: C2RFD
+      description: CPU2 SRAM fetch (execution) disable.
+      bit_offset: 31
+      bit_size: 1
+fieldset/SIPCR:
+  description: secure IP control register
+  fields:
+    - name: SAES
+      description: "Enable AES1 KEY[7:0] security."
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 2
+        stride: 1
+    - name: SPKA
+      description: Enable PKA security
+      bit_offset: 2
+      bit_size: 1
+    - name: SRNG
+      description: Enable True RNG security
+      bit_offset: 3
+      bit_size: 1
+fieldset/SKR:
+  description: SKR
+  fields:
+    - name: KEY
+      description: SRAM2 write protection key for software erase
+      bit_offset: 0
+      bit_size: 8
+fieldset/SWPR:
+  description: SRAM2 write protection register
+  fields:
+    - name: PWP
+      description: P0WP
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
+fieldset/SWPR2:
+  description: SRAM2 write protection register 2
+  fields:
+    - name: PWP
+      description: P32WP
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
--- a/parse.py
+++ b/parse.py
@ -244,11 +244,13 @@ perimap = [
    ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
    ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
    ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
+    ('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
    ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
    ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
    ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
    ('.*:STM32H7AB_rcc_v1_0', ''),  # rcc_h7ab/RCC
    ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
+    ('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
    ('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'),
    ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
    ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
@ -263,6 +265,7 @@ rng_clock_map = [
    ('STM32L4.*:RNG:.*', 'AHB2'),
    ('STM32F4.*:RNG:.*', 'AHB2'),
    ('STM32H7.*:RNG:.*', 'AHB2'),
+    ('STM32WB55.*:RNG:.*', 'AHB3')
 ]