Manually maintain memory maps instead of parsing them from cubeprogdb.
First step towards fixing #301 The cubeprogdb has turned out to be a quite bad data source. It's not granular enough (it has one entry per chip die, not per chip) so the previous code joined the data with the C headers and cubedb to fill in the gaps, essentialy "guessing" stuff. This has been quite error prone (see #301) and hard to make fixes to. Instead, we're going to manually maintain memory maps in a .rs file. This way, if something is wrong we can simply go and fix it. This commit just migrates the existing data, even if it's wrong. (it does fix a few very minor mistakes). Next steps is actually fixing the memory maps.
This commit is contained in:
Dario Nieuwenhuis
parent
9d3d5c9690
commit
8e26f36a8e
@ -58,7 +58,9 @@ mod xml {
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}
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}
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pub struct Chip {
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pub struct Chip {
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#[allow(dead_code)]
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flash: u32,
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flash: u32,
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#[allow(dead_code)]
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ram: u32,
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ram: u32,
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group_idx: usize,
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group_idx: usize,
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packages: Vec<stm32_data_serde::chip::Package>,
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packages: Vec<stm32_data_serde::chip::Package>,
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@ -903,7 +905,6 @@ fn process_group(
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peripheral_to_clock: &rcc::ParsedRccs,
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peripheral_to_clock: &rcc::ParsedRccs,
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dma_channels: &dma::DmaChannels,
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dma_channels: &dma::DmaChannels,
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chips: &HashMap<String, Chip>,
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chips: &HashMap<String, Chip>,
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memories: &memory::Memories,
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docs: &docs::Docs,
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docs: &docs::Docs,
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) -> Result<(), anyhow::Error> {
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) -> Result<(), anyhow::Error> {
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let chip_name = group.chip_names[0].clone();
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let chip_name = group.chip_names[0].clone();
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@ -942,7 +943,7 @@ fn process_group(
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.collect();
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.collect();
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for chip_name in &group.chip_names {
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for chip_name in &group.chip_names {
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process_chip(chips, chip_name, h, memories, docs, &group, &cores)?;
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process_chip(chips, chip_name, h, docs, &group, &cores)?;
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}
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}
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Ok(())
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Ok(())
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@ -1338,159 +1339,21 @@ fn process_core(
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fn process_chip(
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fn process_chip(
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chips: &HashMap<String, Chip>,
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chips: &HashMap<String, Chip>,
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chip_name: &str,
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chip_name: &str,
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h: &header::ParsedHeader,
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_h: &header::ParsedHeader,
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memories: &memory::Memories,
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docs: &docs::Docs,
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docs: &docs::Docs,
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group: &ChipGroup,
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group: &ChipGroup,
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cores: &[stm32_data_serde::chip::Core],
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cores: &[stm32_data_serde::chip::Core],
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) -> Result<(), anyhow::Error> {
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) -> Result<(), anyhow::Error> {
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let chip = chips.get(chip_name).unwrap();
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let chip = chips.get(chip_name).unwrap();
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let flash_size = chip.flash * 1024;
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let ram_total = chip.ram * 1024;
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let memory = memories.get(group.die.as_ref().unwrap());
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let mut flash_remaining = flash_size;
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let mut memory_regions = Vec::new();
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let mut found = HashSet::<&str>::new();
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for each in [
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// We test FLASH_BANKx _before_ FLASH as we prefer their definition over the legacy one
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"FLASH_BANK1",
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"FLASH_BANK2",
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"FLASH",
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"D1_AXIFLASH",
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"D1_AXIICP",
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] {
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if let Some(address) = h.defines.get("all").unwrap().0.get(&format!("{each}_BASE")) {
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let (key, banks) = match each {
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"FLASH" => (
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"BANK_1",
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Some([memory::FlashBank::Bank1, memory::FlashBank::Bank2].as_ref()),
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),
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"FLASH_BANK1" => ("BANK_1", Some([memory::FlashBank::Bank1].as_ref())),
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"FLASH_BANK2" => ("BANK_2", Some([memory::FlashBank::Bank2].as_ref())),
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each => (each, None),
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};
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if found.contains(key) {
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continue;
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}
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found.insert(key);
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if let Some(banks) = banks {
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for bank in banks {
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let bank_name = match bank {
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memory::FlashBank::Bank1 => "BANK_1",
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memory::FlashBank::Bank2 => "BANK_2",
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};
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let regions: Vec<_> = memory
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.flash_regions
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.iter()
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.filter(|region| region.bank == *bank)
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.enumerate()
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.map_while(|(index, region)| {
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let size = if *bank == memory::FlashBank::Bank1 || *bank == memory::FlashBank::Bank2 {
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// Truncate region to the total amount of remaining chip flash
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let size = std::cmp::min(region.bytes, flash_remaining);
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flash_remaining -= size;
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if size == 0 {
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// No more regions are present on this chip
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return None;
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}
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size
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} else {
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region.bytes
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};
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Some((index, region.address, size, region.settings.clone()))
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})
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.collect();
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let has_multiple_regions = regions.len() > 1;
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for (index, address, size, settings) in regions {
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let name = if has_multiple_regions {
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format!("{}_REGION_{}", bank_name, index + 1)
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} else {
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bank_name.to_string()
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};
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memory_regions.push(stm32_data_serde::chip::Memory {
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name,
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kind: stm32_data_serde::chip::memory::Kind::Flash,
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address,
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size,
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settings: Some(settings.clone()),
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});
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}
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}
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} else {
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memory_regions.push(stm32_data_serde::chip::Memory {
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name: key.to_string(),
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kind: stm32_data_serde::chip::memory::Kind::Flash,
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address: u32::try_from(*address).unwrap(),
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size: 0,
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settings: None,
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})
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}
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}
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}
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let mut found = HashSet::new();
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for each in [
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"SRAM",
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"SRAM1",
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"SRAM2",
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"D1_AXISRAM",
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"D1_ITCMRAM",
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"D1_DTCMRAM",
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"D1_AHBSRAM",
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"D2_AXISRAM",
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"D3_BKPSRAM",
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"D3_SRAM",
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] {
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if let Some(address) = h.defines.get("all").unwrap().0.get(&format!("{each}_BASE")) {
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let key = match each {
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"D1_AXISRAM" => "SRAM",
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"SRAM1" => "SRAM",
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each => each,
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};
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if found.contains(key) {
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continue;
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}
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found.insert(key);
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let size = if key == "SRAM" {
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// if memory.ram.bytes != ram_total {
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// println!(
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// "SRAM mismatch for chip {} with die {}: Expected {} was {}",
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// chip_name,
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// group.die.as_ref().unwrap(),
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// ram_total,
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// memory.ram.bytes,
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// );
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// }
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std::cmp::min(memory.ram.bytes, ram_total)
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} else {
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0
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};
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memory_regions.push(stm32_data_serde::chip::Memory {
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name: key.to_string(),
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kind: stm32_data_serde::chip::memory::Kind::Ram,
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address: u32::try_from(*address).unwrap(),
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size,
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settings: None,
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})
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}
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}
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memory_regions.sort_by_key(|m| (m.address, m.name.clone()));
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let docs = docs.documents_for(chip_name);
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let docs = docs.documents_for(chip_name);
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let chip = stm32_data_serde::Chip {
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let chip = stm32_data_serde::Chip {
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name: chip_name.to_string(),
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name: chip_name.to_string(),
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family: group.family.clone().unwrap(),
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family: group.family.clone().unwrap(),
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line: group.line.clone().unwrap(),
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line: group.line.clone().unwrap(),
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die: group.die.clone().unwrap(),
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die: group.die.clone().unwrap(),
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device_id: memory.device_id,
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device_id: u16::from_str_radix(&group.die.as_ref().unwrap()[3..], 16).unwrap(),
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packages: chip.packages.clone(),
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packages: chip.packages.clone(),
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memory: memory_regions,
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memory: memory::get(chip_name),
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docs,
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docs,
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cores: cores.to_vec(),
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cores: cores.to_vec(),
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};
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};
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@ -1531,7 +1394,6 @@ pub fn dump_all_chips(
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peripheral_to_clock: rcc::ParsedRccs,
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peripheral_to_clock: rcc::ParsedRccs,
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dma_channels: dma::DmaChannels,
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dma_channels: dma::DmaChannels,
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chips: std::collections::HashMap<String, Chip>,
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chips: std::collections::HashMap<String, Chip>,
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memories: memory::Memories,
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docs: docs::Docs,
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docs: docs::Docs,
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) -> Result<(), anyhow::Error> {
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) -> Result<(), anyhow::Error> {
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std::fs::create_dir_all("build/data/chips")?;
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std::fs::create_dir_all("build/data/chips")?;
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@ -1552,7 +1414,6 @@ pub fn dump_all_chips(
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&peripheral_to_clock,
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&peripheral_to_clock,
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&dma_channels,
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&dma_channels,
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&chips,
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&chips,
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&memories,
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&docs,
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&docs,
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)
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)
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})
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})
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@ -69,9 +69,6 @@ fn main() -> anyhow::Result<()> {
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let registers = registers::Registers::parse()?;
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let registers = registers::Registers::parse()?;
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registers.write()?;
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registers.write()?;
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// stopwatch.section("Parsing memories");
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let memories = memory::Memories::parse()?;
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// stopwatch.section("Parsing interrupts");
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// stopwatch.section("Parsing interrupts");
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let chip_interrupts = interrupts::ChipInterrupts::parse()?;
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let chip_interrupts = interrupts::ChipInterrupts::parse()?;
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@ -99,7 +96,6 @@ fn main() -> anyhow::Result<()> {
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peripheral_to_clock,
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peripheral_to_clock,
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dma_channels,
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dma_channels,
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chips,
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chips,
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memories,
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docs,
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docs,
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)?;
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)?;
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@ -1,285 +1,330 @@
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use std::cmp::Ordering;
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use regex::Regex;
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use std::collections::HashMap;
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use stm32_data_serde::chip::memory::{self, Settings};
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use std::fs;
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use stm32_data_serde::chip::Memory;
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#[derive(Debug, PartialEq)]
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struct Mem {
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pub struct Memory {
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name: &'static str,
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pub device_id: u16,
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address: u32,
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pub ram: Ram,
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size: u32,
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pub flash_size: u32,
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pub flash_regions: Vec<FlashRegion>,
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}
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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macro_rules! mem {
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pub struct Ram {
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($($name:ident $addr:literal $size:literal),*) => {
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pub address: u32,
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&[
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pub bytes: u32,
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$(
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}
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Mem {
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name: stringify!($name),
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#[derive(Clone, Debug, PartialEq)]
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address: $addr,
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pub struct FlashRegion {
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size: $size*1024,
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pub bank: FlashBank,
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},
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pub address: u32,
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)*
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pub bytes: u32,
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]
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pub settings: stm32_data_serde::chip::memory::Settings,
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}
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FlashBank {
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Bank1,
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Bank2,
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}
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mod xml {
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use serde::Deserialize;
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pub fn from_hex<'de, T, D>(deserializer: D) -> Result<T, D::Error>
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where
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D: serde::Deserializer<'de>,
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T: num::Num,
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T::FromStrRadixErr: std::fmt::Display,
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{
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use serde::de::Error;
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let s: &str = Deserialize::deserialize(deserializer)?;
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let s = s.trim();
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let (prefix, num) = s.split_at(2);
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if prefix != "0x" && prefix != "0X" {
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panic!("no hex prefix");
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}
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T::from_str_radix(num, 16).map_err(D::Error::custom)
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}
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pub fn opt_from_hex<'de, T, D>(deserializer: D) -> Result<Option<T>, D::Error>
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where
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D: serde::Deserializer<'de>,
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T: num::Num,
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T::FromStrRadixErr: std::fmt::Display,
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{
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Ok(Some(from_hex(deserializer)?))
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}
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#[derive(Debug, Deserialize, PartialEq)]
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pub struct Root {
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#[serde(rename = "Device")]
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pub device: root::Device,
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}
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mod root {
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use serde::Deserialize;
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use super::from_hex;
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|
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#[derive(Debug, Deserialize, PartialEq)]
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pub struct Device {
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#[serde(rename = "DeviceID", deserialize_with = "from_hex")]
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pub device_id: u16,
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#[serde(rename = "Name")]
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pub name: String,
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#[serde(rename = "Peripherals")]
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pub peripherals: device::Peripherals,
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}
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mod device {
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use serde::Deserialize;
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|
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#[derive(Debug, Deserialize, PartialEq)]
|
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pub struct Peripherals {
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#[serde(rename = "Peripheral")]
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pub peripharal: Vec<peripherals::Peripheral>,
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}
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|
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mod peripherals {
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use serde::Deserialize;
|
|
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|
|
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use super::super::super::opt_from_hex;
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|
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#[derive(Debug, Deserialize, PartialEq)]
|
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pub struct Peripheral {
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#[serde(rename = "Name")]
|
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// pub name: peripheral::Name,
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pub name: String,
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#[serde(rename = "ErasedValue", deserialize_with = "opt_from_hex", default)]
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|
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pub erased_value: Option<u8>,
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#[serde(rename = "Configuration", default)]
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pub configuration: Vec<peripheral::Configuration>,
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}
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|
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mod peripheral {
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use serde::Deserialize;
|
|
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|
|
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use super::super::super::super::opt_from_hex;
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|
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|
|
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#[derive(Debug, Deserialize, PartialEq)]
|
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pub struct Configuration {
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#[serde(rename = "Parameters", default)]
|
|
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pub parameters: Option<configuration::Parameters>,
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#[serde(rename = "Organization", default)]
|
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pub organization: Option<String>,
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#[serde(rename = "Allignement", deserialize_with = "opt_from_hex", default)]
|
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pub allignement: Option<u32>,
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#[serde(rename = "Bank")]
|
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pub bank: Vec<configuration::Bank>,
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}
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|
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|
|
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mod configuration {
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|
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use serde::Deserialize;
|
|
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|
|
||||||
use super::super::super::super::super::{from_hex, opt_from_hex};
|
|
||||||
|
|
||||||
#[derive(Debug, Deserialize, PartialEq)]
|
|
||||||
pub struct Parameters {
|
|
||||||
#[serde(deserialize_with = "from_hex")]
|
|
||||||
pub address: u32,
|
|
||||||
#[serde(deserialize_with = "from_hex")]
|
|
||||||
pub size: u32,
|
|
||||||
#[serde(deserialize_with = "opt_from_hex", default)]
|
|
||||||
pub occurence: Option<u32>,
|
|
||||||
}
|
|
||||||
|
|
||||||
#[derive(Debug, Deserialize, PartialEq)]
|
|
||||||
pub struct Bank {
|
|
||||||
#[serde(default)]
|
|
||||||
pub name: Option<String>,
|
|
||||||
#[serde(rename = "Field", default)]
|
|
||||||
pub field: Vec<bank::Field>,
|
|
||||||
}
|
|
||||||
|
|
||||||
mod bank {
|
|
||||||
use serde::Deserialize;
|
|
||||||
|
|
||||||
#[derive(Debug, Deserialize, PartialEq)]
|
|
||||||
pub struct Field {
|
|
||||||
#[serde(rename = "Parameters")]
|
|
||||||
pub parameters: super::Parameters,
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
pub struct Memories(HashMap<u16, Memory>);
|
|
||||||
|
|
||||||
impl Memories {
|
|
||||||
pub fn parse() -> anyhow::Result<Self> {
|
|
||||||
let mut paths: Vec<_> = glob::glob("sources/cubeprogdb/db/*.xml")
|
|
||||||
.unwrap()
|
|
||||||
.map(Result::unwrap)
|
|
||||||
.collect();
|
|
||||||
paths.sort();
|
|
||||||
|
|
||||||
let mut memories = HashMap::new();
|
|
||||||
|
|
||||||
for f in paths {
|
|
||||||
// println!("Parsing {f:?}");
|
|
||||||
let file = fs::read_to_string(f)?;
|
|
||||||
let parsed: xml::Root = quick_xml::de::from_str(&file)?;
|
|
||||||
// dbg!(&parsed);
|
|
||||||
|
|
||||||
let device_id = parsed.device.device_id;
|
|
||||||
|
|
||||||
let mut ram = None;
|
|
||||||
let mut flash_size = None;
|
|
||||||
let mut flash_regions = vec![];
|
|
||||||
|
|
||||||
for mut peripheral in parsed.device.peripherals.peripharal {
|
|
||||||
if peripheral.name == "Embedded SRAM" && ram.is_none() {
|
|
||||||
let config = peripheral.configuration.first().unwrap();
|
|
||||||
let parameters = config.parameters.as_ref().unwrap();
|
|
||||||
ram = Some(Ram {
|
|
||||||
address: parameters.address,
|
|
||||||
bytes: parameters.size,
|
|
||||||
});
|
|
||||||
}
|
|
||||||
|
|
||||||
enum BlockKind {
|
|
||||||
Main,
|
|
||||||
}
|
|
||||||
let kind = match peripheral.name.as_str() {
|
|
||||||
"Embedded Flash" => Some(BlockKind::Main),
|
|
||||||
"OTP" => None,
|
|
||||||
_ => None,
|
|
||||||
};
|
};
|
||||||
|
}
|
||||||
|
|
||||||
if let Some(kind) = kind {
|
#[rustfmt::skip]
|
||||||
peripheral.configuration.sort_by(|a, b| {
|
static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[
|
||||||
// Prefer largest size
|
("STM32C01..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 6)),
|
||||||
let ordering = b
|
("STM32C01..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
|
||||||
.parameters
|
("STM32C03..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 12)),
|
||||||
.as_ref()
|
("STM32C03..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 12)),
|
||||||
.unwrap()
|
("STM32F0...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
|
||||||
.size
|
("STM32F0[35]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
|
||||||
.partial_cmp(&a.parameters.as_ref().unwrap().size)
|
("STM32F0[47]..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
|
||||||
.unwrap();
|
("STM32F03..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 4)),
|
||||||
|
("STM32F03..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 4)),
|
||||||
|
("STM32F04..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 6)),
|
||||||
|
("STM32F05..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)),
|
||||||
|
("STM32F05..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)),
|
||||||
|
("STM32F07..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
|
||||||
|
("STM32F07..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
|
||||||
|
("STM32F09..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
|
||||||
|
("STM32F1.[12].6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 6)),
|
||||||
|
("STM32F1.[12].8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 10)),
|
||||||
|
("STM32F1.[12].B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
|
||||||
|
("STM32F1.[57].B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 64)),
|
||||||
|
("STM32F1.[57].C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 64)),
|
||||||
|
("STM32F1.0.6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 4)),
|
||||||
|
("STM32F1.0.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
|
||||||
|
("STM32F1.0.B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 8)),
|
||||||
|
("STM32F1.0.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 24)),
|
||||||
|
("STM32F1.0.D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 32)),
|
||||||
|
("STM32F1.0.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 32)),
|
||||||
|
("STM32F1.1.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
|
||||||
|
("STM32F1.1.D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 48)),
|
||||||
|
("STM32F1.1.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 48)),
|
||||||
|
("STM32F1.1.F", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 256, SRAM 0x20000000 80)),
|
||||||
|
("STM32F1.1.G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM 0x20000000 80)),
|
||||||
|
("STM32F1.3.6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 10)),
|
||||||
|
("STM32F1.3.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20)),
|
||||||
|
("STM32F1.3.B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20)),
|
||||||
|
("STM32F1.3.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 48)),
|
||||||
|
("STM32F1.3.D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 64)),
|
||||||
|
("STM32F1.3.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 64)),
|
||||||
|
("STM32F1.3.F", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 256, SRAM 0x20000000 96)),
|
||||||
|
("STM32F1.3.G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM 0x20000000 96)),
|
||||||
|
("STM32F1.5.8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 64)),
|
||||||
|
("STM32F10[012].4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 4)),
|
||||||
|
("STM32F103.4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 6)),
|
||||||
|
("STM32F2...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 64, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F2...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F2...F", mem!(BANK_1 0x08000000 768, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F2...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F2.5.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F2.7.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F3...4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 12)),
|
||||||
|
("STM32F3...D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 64)),
|
||||||
|
("STM32F3...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 64)),
|
||||||
|
("STM32F3.[12].6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 16)),
|
||||||
|
("STM32F3.[34].6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 12)),
|
||||||
|
("STM32F3([17]..8|0[12].8)", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
|
||||||
|
("STM32F3([23]..8|03.8)", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 12)),
|
||||||
|
("STM32F3[05]..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 40)),
|
||||||
|
("STM32F30..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
|
||||||
|
("STM32F37..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 24)),
|
||||||
|
("STM32F37..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
|
||||||
|
("STM32F4...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 32)),
|
||||||
|
("STM32F4...D", mem!(BANK_1 0x08000000 384, SRAM 0x20000000 64)),
|
||||||
|
("STM32F4...H", mem!(BANK_1 0x08000000 1536, SRAM 0x20000000 320, SRAM2 0x20040000 0)),
|
||||||
|
("STM32F4.[567].E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F4.1.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 64)),
|
||||||
|
("STM32F4.1.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 64)),
|
||||||
|
("STM32F4.2.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 256)),
|
||||||
|
("STM32F4.6.C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F4(1[57].G|0..G)", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F4[23]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 192, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F4[23]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 192, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F4[67]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 320, SRAM2 0x20028000 0)),
|
||||||
|
("STM32F4[67]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 320, SRAM2 0x20028000 0)),
|
||||||
|
("STM32F40..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 64)),
|
||||||
|
("STM32F41..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
|
||||||
|
("STM32F412.G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 256)),
|
||||||
|
("STM32F413.G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 320, SRAM2 0x20040000 0)),
|
||||||
|
("STM32F429.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 192, SRAM2 0x2001c000 0)),
|
||||||
|
("STM32F469.E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 320, SRAM2 0x20028000 0)),
|
||||||
|
("STM32F7...C", mem!(BANK_1 0x08000000 256, SRAM 0x20010000 192, SRAM2 0x2003c000 0)),
|
||||||
|
("STM32F7...I", mem!(BANK_1 0x08000000 2048, SRAM 0x20020000 384, SRAM2 0x2007c000 0)),
|
||||||
|
("STM32F7[23]..E", mem!(BANK_1 0x08000000 512, SRAM 0x20010000 192, SRAM2 0x2003c000 0)),
|
||||||
|
("STM32F7[45]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20010000 320, SRAM2 0x2004c000 0)),
|
||||||
|
("STM32F73..8", mem!(BANK_1 0x08000000 64, SRAM 0x20010000 192, SRAM2 0x2003c000 0)),
|
||||||
|
("STM32F74..E", mem!(BANK_1 0x08000000 512, SRAM 0x20010000 320, SRAM2 0x2004c000 0)),
|
||||||
|
("STM32F75..8", mem!(BANK_1 0x08000000 64, SRAM 0x20010000 320, SRAM2 0x2004c000 0)),
|
||||||
|
("STM32F76..G", mem!(BANK_1 0x08000000 1024, SRAM 0x20020000 384, SRAM2 0x2007c000 0)),
|
||||||
|
("STM32G0...4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)),
|
||||||
|
("STM32G0...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128)),
|
||||||
|
("STM32G0...E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM 0x20000000 128)),
|
||||||
|
("STM32G0[34]..[68]", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)),
|
||||||
|
("STM32G0[56]..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 16)),
|
||||||
|
("STM32G0[56]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
|
||||||
|
("STM32G0[78]..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)),
|
||||||
|
("STM32G07..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 32)),
|
||||||
|
("STM32G07..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 32)),
|
||||||
|
("STM32G0B..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 128)),
|
||||||
|
("STM32G4...6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
|
||||||
|
("STM32G4...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
|
||||||
|
("STM32G4[34]..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20, SRAM2 0x20004000 0)),
|
||||||
|
("STM32G4[78]..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
|
||||||
|
("STM32G4[9A]..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 32, SRAM2 0x20014000 0)),
|
||||||
|
("STM32G47..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
|
||||||
|
("STM32G47..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96, SRAM2 0x20014000 0)),
|
||||||
|
("STM32G49..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32, SRAM2 0x20014000 0)),
|
||||||
|
("STM32H5...B", mem!(BANK_1 0x08000000 64, BANK_2 0x08010000 64, SRAM 0x20000000 32, SRAM2 0x20004000 0)),
|
||||||
|
("STM32H5...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 256, SRAM2 0x20040000 0)),
|
||||||
|
("STM32H5...I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 256, SRAM2 0x20040000 0)),
|
||||||
|
("STM32H7...E", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 512, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 128, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
|
||||||
|
("STM32H7[23]..G", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 1024, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 128, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
|
||||||
|
("STM32H7[45]..I", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, D2_AXISRAM 0x10000000 0, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 512, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
|
||||||
|
("STM32H7[AB]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x24000000 1024)),
|
||||||
|
("STM32H73..B", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 128, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 128, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
|
||||||
|
("STM32H74..G", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 1024, D2_AXISRAM 0x10000000 0, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 512, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
|
||||||
|
("STM32H75..B", mem!(D1_ITCMRAM 0x00000000 0, D1_AXIFLASH 0x08000000 0, BANK_1 0x08000000 128, D2_AXISRAM 0x10000000 0, D1_AXIICP 0x1ff00000 0, D1_DTCMRAM 0x20000000 0, SRAM 0x24000000 512, D3_SRAM 0x38000000 0, D3_BKPSRAM 0x38800000 0)),
|
||||||
|
("STM32H7A..G", mem!(BANK_1 0x08000000 1024, SRAM 0x24000000 1024)),
|
||||||
|
("STM32H7B..B", mem!(BANK_1 0x08000000 128, SRAM 0x24000000 1024)),
|
||||||
|
("STM32L0...3", mem!(BANK_1 0x08000000 8, SRAM 0x20000000 2)),
|
||||||
|
("STM32L0...6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)),
|
||||||
|
("STM32L0...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 20)),
|
||||||
|
("STM32L0...Z", mem!(BANK_1 0x08000000 192, SRAM 0x20000000 20)),
|
||||||
|
("STM32L0[12]..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 2)),
|
||||||
|
("STM32L0[156]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
|
||||||
|
("STM32L0[34]..4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)),
|
||||||
|
("STM32L0[78]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 20)),
|
||||||
|
("STM32L1...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 10)),
|
||||||
|
("STM32L1...C..", mem!(BANK_1 0x08000000 192, BANK_2 0x08030000 64, SRAM 0x20000000 32)),
|
||||||
|
("STM32L1...D..", mem!(BANK_1 0x08000000 128, BANK_2 0x08040000 256, SRAM 0x20000000 80)),
|
||||||
|
("STM32L1...D", mem!(BANK_1 0x08000000 192, BANK_2 0x08030000 192, SRAM 0x20000000 48)),
|
||||||
|
("STM32L1...E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM 0x20000000 80)),
|
||||||
|
("STM32L1(6.[RV]C|5.[CRUV]C)", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32)),
|
||||||
|
("STM32L1[56].[QZ]C", mem!(BANK_1 0x08000000 192, BANK_2 0x08030000 64, SRAM 0x20000000 32)),
|
||||||
|
("STM32L10..6..", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 10)),
|
||||||
|
("STM32L10..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 4)),
|
||||||
|
("STM32L10..8..", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 10)),
|
||||||
|
("STM32L10..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)),
|
||||||
|
("STM32L10..B..", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 10)),
|
||||||
|
("STM32L10..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 16)),
|
||||||
|
("STM32L15..6..", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 16)),
|
||||||
|
("STM32L15..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 10)),
|
||||||
|
("STM32L15..8..", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)),
|
||||||
|
("STM32L15..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 10)),
|
||||||
|
("STM32L15..B..", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 16)),
|
||||||
|
("STM32L4...8", mem!(BANK_1 0x08000000 64, SRAM2 0x10000000 0, SRAM 0x20000000 40)),
|
||||||
|
("STM32L4...I", mem!(BANK_1 0x08000000 2048, SRAM2 0x10000000 0, SRAM 0x20000000 192)),
|
||||||
|
("STM32L4[12]..B", mem!(BANK_1 0x08000000 128, SRAM2 0x10000000 0, SRAM 0x20000000 40)),
|
||||||
|
("STM32L4[34]..C", mem!(BANK_1 0x08000000 256, SRAM2 0x10000000 0, SRAM 0x20000000 48)),
|
||||||
|
("STM32L4[56]..E", mem!(BANK_1 0x08000000 512, SRAM2 0x10000000 0, SRAM 0x20000000 128)),
|
||||||
|
("STM32L4[78]..G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM2 0x10000000 0, SRAM 0x20000000 96)),
|
||||||
|
("STM32L4[9A]..G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM2 0x10000000 0, SRAM 0x20000000 256)),
|
||||||
|
("STM32L4[PQR]..G", mem!(BANK_1 0x08000000 1024, SRAM2 0x10000000 0, SRAM 0x20000000 192)),
|
||||||
|
("STM32L43..B", mem!(BANK_1 0x08000000 128, SRAM2 0x10000000 0, SRAM 0x20000000 48)),
|
||||||
|
("STM32L45..C", mem!(BANK_1 0x08000000 256, SRAM2 0x10000000 0, SRAM 0x20000000 128)),
|
||||||
|
("STM32L47..C", mem!(BANK_1 0x08000000 256, SRAM2 0x10000000 0, SRAM 0x20000000 96)),
|
||||||
|
("STM32L47..E", mem!(BANK_1 0x08000000 512, SRAM2 0x10000000 0, SRAM 0x20000000 96)),
|
||||||
|
("STM32L49..E", mem!(BANK_1 0x08000000 512, SRAM2 0x10000000 0, SRAM 0x20000000 256)),
|
||||||
|
("STM32L4P..E", mem!(BANK_1 0x08000000 512, SRAM2 0x10000000 0, SRAM 0x20000000 192)),
|
||||||
|
("STM32L5...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 256, SRAM2 0x20030000 0)),
|
||||||
|
("STM32L5...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 256, SRAM2 0x20030000 0)),
|
||||||
|
("STM32U5...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 64, SRAM2 0x20030000 0)),
|
||||||
|
("STM32U5...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 64, SRAM2 0x20030000 0)),
|
||||||
|
("STM32U5...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 64, SRAM2 0x20030000 0)),
|
||||||
|
("STM32U5...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 768, SRAM2 0x20030000 0)),
|
||||||
|
("STM32U5...J", mem!(BANK_1 0x08000000 4096, SRAM 0x20000000 32, SRAM2 0x200c0000 0)),
|
||||||
|
("STM32U5[78]..I", mem!(BANK_1 0x08000000 2048, SRAM 0x20000000 768, SRAM2 0x20030000 0)),
|
||||||
|
("STM32U59..I", mem!(BANK_1 0x08000000 2048, SRAM 0x20000000 32, SRAM2 0x200c0000 0)),
|
||||||
|
("STM32WB...Y", mem!(BANK_1 0x08000000 640, SRAM 0x20000000 192)),
|
||||||
|
("STM32WB.(0C|5V)G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128)),
|
||||||
|
("STM32WB.(5C|5R)G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 192)),
|
||||||
|
("STM32WB1..C", mem!(BANK_1 0x08000000 320, SRAM 0x20000000 12)),
|
||||||
|
("STM32WB3..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96)),
|
||||||
|
("STM32WB3..E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96)),
|
||||||
|
("STM32WB5..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128)),
|
||||||
|
("STM32WB5.[CR]E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 192)),
|
||||||
|
("STM32WB5.VE", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 128)),
|
||||||
|
("STM32WBA...E", mem!(BANK_1 0x08000000 512, SRAM 0x20000000 96, SRAM2 0x20010000 0)),
|
||||||
|
("STM32WBA...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 128, SRAM2 0x20010000 0)),
|
||||||
|
("STM32WL...8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
|
||||||
|
("STM32WL...B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
|
||||||
|
("STM32WL...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 12, SRAM2 0x20008000 0)),
|
||||||
|
]);
|
||||||
|
|
||||||
// ... then prefer single ordering over dual
|
struct FlashInfo {
|
||||||
if ordering == Ordering::Equal {
|
write_size: u32,
|
||||||
// Possible values are Single and Dual
|
erase_size: &'static [(u32, u32)],
|
||||||
b.organization.partial_cmp(&a.organization).unwrap()
|
erase_value: u8,
|
||||||
|
}
|
||||||
|
|
||||||
|
#[rustfmt::skip]
|
||||||
|
static FLASH_INFO: RegexMap<FlashInfo> = RegexMap::new(&[
|
||||||
|
("STM32C0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32F030.C", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32F070.6", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 1*1024, 0)] }),
|
||||||
|
("STM32F0[79].*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32F0.*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 1*1024, 0)] }),
|
||||||
|
("STM32F10[0123].[468B]", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 1*1024, 0)] }),
|
||||||
|
("STM32F1.*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32F2.*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 16*1024, 4), (64*1024, 1), ( 128*1024, 0)] }),
|
||||||
|
("STM32F3.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32F4.*", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 16*1024, 4), (64*1024, 1), ( 128*1024, 0)] }),
|
||||||
|
("STM32F7[4567].*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 32*1024, 4), (128*1024, 1), ( 256*1024, 0)] }),
|
||||||
|
("STM32F7.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 16*1024, 4), (64*1024, 1), ( 128*1024, 0)] }),
|
||||||
|
("STM32G0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32G4[78].*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }),
|
||||||
|
("STM32G4.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32H5.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }),
|
||||||
|
("STM32H7[AB].*", FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[( 8*1024, 0)] }),
|
||||||
|
("STM32H7.*", FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[(128*1024, 0)] }),
|
||||||
|
("STM32L4[PQRS].*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 8*1024, 0)] }),
|
||||||
|
("STM32L4.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32L0.*", FlashInfo{ erase_value: 0x00, write_size: 4, erase_size: &[( 128, 0)] }),
|
||||||
|
("STM32L1.*", FlashInfo{ erase_value: 0x00, write_size: 4, erase_size: &[( 256, 0)] }),
|
||||||
|
("STM32L5.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }),
|
||||||
|
("STM32U5[78].*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }),
|
||||||
|
("STM32U5.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 16*1024, 0)] }),
|
||||||
|
("STM32WBA.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }),
|
||||||
|
("STM32WB1.*", FlashInfo{ erase_value: 0x00, write_size: 8, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32WB.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }),
|
||||||
|
("STM32WL.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
("STM32.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }),
|
||||||
|
]);
|
||||||
|
|
||||||
|
struct RegexMap<T: 'static> {
|
||||||
|
map: &'static [(&'static str, T)],
|
||||||
|
}
|
||||||
|
|
||||||
|
impl<T: 'static> RegexMap<T> {
|
||||||
|
const fn new(map: &'static [(&'static str, T)]) -> Self {
|
||||||
|
Self { map }
|
||||||
|
}
|
||||||
|
|
||||||
|
fn get(&self, key: &str) -> Option<&T> {
|
||||||
|
for (k, v) in self.map {
|
||||||
|
if Regex::new(&format!("^{k}$")).unwrap().is_match(key) {
|
||||||
|
return Some(v);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
None
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn get(chip: &str) -> Vec<Memory> {
|
||||||
|
let mems = *MEMS.get(chip).unwrap();
|
||||||
|
let flash = FLASH_INFO.get(chip).unwrap();
|
||||||
|
|
||||||
|
let mut res = Vec::new();
|
||||||
|
|
||||||
|
for mem in mems {
|
||||||
|
if mem.name.starts_with("BANK") {
|
||||||
|
if flash.erase_size.len() == 1 || mem.size <= flash.erase_size[0].0 * flash.erase_size[0].1 {
|
||||||
|
res.push(Memory {
|
||||||
|
name: mem.name.to_string(),
|
||||||
|
address: mem.address,
|
||||||
|
size: mem.size,
|
||||||
|
kind: memory::Kind::Flash,
|
||||||
|
settings: Some(Settings {
|
||||||
|
write_size: flash.write_size,
|
||||||
|
erase_size: flash.erase_size[0].0,
|
||||||
|
erase_value: flash.erase_value,
|
||||||
|
}),
|
||||||
|
});
|
||||||
} else {
|
} else {
|
||||||
ordering
|
let mut offs = 0;
|
||||||
|
for (i, &(erase_size, count)) in flash.erase_size.iter().enumerate() {
|
||||||
|
if offs >= mem.size {
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
|
let left = mem.size - offs;
|
||||||
|
let mut size = left;
|
||||||
|
if i != flash.erase_size.len() - 1 {
|
||||||
|
size = size.min(erase_size * count);
|
||||||
|
}
|
||||||
|
res.push(Memory {
|
||||||
|
name: format!("{}_REGION_{}", mem.name, i + 1),
|
||||||
|
address: mem.address + offs,
|
||||||
|
size: size,
|
||||||
|
kind: memory::Kind::Flash,
|
||||||
|
settings: Some(Settings {
|
||||||
|
write_size: flash.write_size,
|
||||||
|
erase_size: erase_size,
|
||||||
|
erase_value: flash.erase_value,
|
||||||
|
}),
|
||||||
});
|
});
|
||||||
let config = peripheral.configuration.first().unwrap();
|
offs += size;
|
||||||
|
|
||||||
if flash_size.is_none() {
|
|
||||||
let parameters = config.parameters.as_ref().unwrap();
|
|
||||||
|
|
||||||
flash_size = Some(parameters.size);
|
|
||||||
}
|
|
||||||
|
|
||||||
for bank in config.bank.iter() {
|
|
||||||
let flash_bank = match kind {
|
|
||||||
BlockKind::Main => match bank.name.as_deref() {
|
|
||||||
Some("Bank 1") => Some(FlashBank::Bank1),
|
|
||||||
Some("Bank 2") => Some(FlashBank::Bank2),
|
|
||||||
Some("EEPROM1") => None,
|
|
||||||
Some("EEPROM2") => None,
|
|
||||||
None => {
|
|
||||||
assert_eq!(1, config.bank.len());
|
|
||||||
Some(FlashBank::Bank1)
|
|
||||||
}
|
|
||||||
Some(other) => unimplemented!("Unsupported flash bank {}", other),
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
if let Some(flash_bank) = flash_bank {
|
|
||||||
let erase_value = peripheral.erased_value.unwrap();
|
|
||||||
let write_size = config.allignement.unwrap();
|
|
||||||
flash_regions.extend(bank.field.iter().map(|field| FlashRegion {
|
|
||||||
bank: flash_bank,
|
|
||||||
address: field.parameters.address,
|
|
||||||
bytes: field.parameters.occurence.unwrap() * field.parameters.size,
|
|
||||||
settings: stm32_data_serde::chip::memory::Settings {
|
|
||||||
erase_value,
|
|
||||||
write_size,
|
|
||||||
erase_size: field.parameters.size,
|
|
||||||
},
|
|
||||||
}));
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
} else {
|
||||||
|
let mut kind = memory::Kind::Ram;
|
||||||
|
if mem.name.contains("FLASH") || mem.name.contains("AXIICP") {
|
||||||
|
kind = memory::Kind::Flash;
|
||||||
|
}
|
||||||
|
res.push(Memory {
|
||||||
|
name: mem.name.to_string(),
|
||||||
|
address: mem.address,
|
||||||
|
size: mem.size,
|
||||||
|
kind,
|
||||||
|
settings: None,
|
||||||
|
});
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
memories.insert(
|
res.sort_by_key(|m| (m.address, m.name.clone()));
|
||||||
device_id,
|
|
||||||
Memory {
|
|
||||||
device_id,
|
|
||||||
ram: ram.unwrap(),
|
|
||||||
flash_size: flash_size.unwrap_or_default(),
|
|
||||||
flash_regions,
|
|
||||||
},
|
|
||||||
);
|
|
||||||
}
|
|
||||||
|
|
||||||
Ok(Self(memories))
|
res
|
||||||
}
|
|
||||||
|
|
||||||
pub fn get(&self, die: &str) -> &Memory {
|
|
||||||
assert!(die.starts_with("DIE"));
|
|
||||||
let device_id = u16::from_str_radix(&die[3..], 16).unwrap();
|
|
||||||
|
|
||||||
self.0.get(&device_id).unwrap()
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user