diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 110e547..8517e93 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -551,7 +551,7 @@ fn corename(d: &str) -> String { fn merge_periph_pins_info( chip_name: &str, periph_name: &str, - core_pins: &mut Vec, + core_pins: &mut [stm32_data_serde::chip::core::peripheral::Pin], af_pins: &[stm32_data_serde::chip::core::peripheral::Pin], ) { if chip_name.contains("STM32F1") { @@ -931,7 +931,7 @@ fn process_core( let fdcans = peri_kinds .keys() .filter_map(|pname| { - regex!(r"^FDCAN(?[0-9]+)$") + regex!(r"^FDCAN(?P[0-9]+)$") .captures(pname) .map(|cap| cap["idx"].to_string()) }) @@ -997,15 +997,15 @@ fn process_core( defines.get_peri_addr("ADC1") } else if chip_name.starts_with("STM32H7") && pname == "HRTIM" { defines.get_peri_addr("HRTIM1") - } else if let Some(cap) = regex!(r"^FDCANRAM(?[0-9]+)$").captures(&pname) { - defines.get_peri_addr("FDCANRAM").and_then(|addr| { + } else if let Some(cap) = regex!(r"^FDCANRAM(?P[0-9]+)$").captures(&pname) { + defines.get_peri_addr("FDCANRAM").map(|addr| { if chip_name.starts_with("STM32H7") { - Some(addr) + addr } else { - let idx = u32::from_str_radix(&cap["idx"], 10).unwrap(); + let idx = cap["idx"].parse::().unwrap(); // FIXME: this offset should not be hardcoded, but I think // it appears in no data sources (only in RMs) - Some(addr + (idx - 1) * 0x350) + addr + (idx - 1) * 0x350 } }) } else { diff --git a/stm32-data-gen/src/interrupts.rs b/stm32-data-gen/src/interrupts.rs index e849abd..c067cc2 100644 --- a/stm32-data-gen/src/interrupts.rs +++ b/stm32-data-gen/src/interrupts.rs @@ -338,12 +338,12 @@ impl ChipInterrupts { let mut irqs = irqs.clone(); // If there's a duplicate irqs in a signal other than "global", keep the non-global one. - if irqs.len() != 1 && signal != &"GLOBAL" { + if irqs.len() != 1 && signal != "GLOBAL" { irqs.retain(|irq| !globals.contains(irq)); } // If there's still duplicate irqs, keep the one that doesn't match the peri name. - if irqs.len() != 1 && signal != &"GLOBAL" { + if irqs.len() != 1 && signal != "GLOBAL" { irqs.retain(|irq| irq != &p.name); } diff --git a/stm32-data-gen/src/memory.rs b/stm32-data-gen/src/memory.rs index ae2ee6e..817bea7 100644 --- a/stm32-data-gen/src/memory.rs +++ b/stm32-data-gen/src/memory.rs @@ -233,7 +233,7 @@ impl Memories { for bank in config.bank.iter() { let flash_bank = match kind { - BlockKind::Main => match bank.name.as_ref().map(|x| x.as_str()) { + BlockKind::Main => match bank.name.as_deref() { Some("Bank 1") => Some(FlashBank::Bank1), Some("Bank 2") => Some(FlashBank::Bank2), Some("EEPROM1") => None, diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index f0eb457..541b168 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -21,12 +21,11 @@ where Entry::Vacant(e) => { e.insert(value); } - Entry::Occupied(mut e) => match compare(&value, e.get()) { - Ordering::Less => { + Entry::Occupied(mut e) => { + if compare(&value, e.get()) == Ordering::Less { e.insert(value); } - _ => {} - }, + } }; } @@ -178,7 +177,7 @@ impl PeripheralToClock { let mut family_muxes = HashMap::new(); for (reg, body) in &ir.fieldsets { let key = format!("fieldset/{reg}"); - if let Some(_) = regex!(r"^fieldset/CCIPR\d?$").captures(&key) { + if regex!(r"^fieldset/CCIPR\d?$").captures(&key).is_some() { for field in &body.fields { if let Some(peri) = field.name.strip_suffix("SEL") { check_mux(reg, &field.name)?; @@ -194,7 +193,7 @@ impl PeripheralToClock { ); } } - } else if let Some(_) = regex!(r"^fieldset/CFGR\d?$").captures(&key) { + } else if regex!(r"^fieldset/CFGR\d?$").captures(&key).is_some() { for field in &body.fields { if let Some(peri) = field.name.strip_suffix("SW") { check_mux(reg, &field.name)?; @@ -210,7 +209,7 @@ impl PeripheralToClock { ); } } - } else if let Some(_) = regex!(r"^fieldset/D\d?CCIPR$").captures(&key) { + } else if regex!(r"^fieldset/D\d?CCIPR$").captures(&key).is_some() { for field in &body.fields { if let Some(peri) = field.name.strip_suffix("SEL") { if family_muxes.get(peri).is_some() && reg != "D1CCIPR" { @@ -275,7 +274,7 @@ impl PeripheralToClock { } } - let mux = family_muxes.get(peri).map(|peri| peri.clone()); + let mux = family_muxes.get(peri).cloned(); match family_clocks.entry(peri.to_string()) { Entry::Vacant(e) => { diff --git a/stm32-data-macros/src/lib.rs b/stm32-data-macros/src/lib.rs index 555504e..9a956eb 100644 --- a/stm32-data-macros/src/lib.rs +++ b/stm32-data-macros/src/lib.rs @@ -1,6 +1,5 @@ use proc_macro2::TokenStream; use quote::quote; -use syn; use syn::Data; #[proc_macro_derive(EnumDebug)] @@ -48,5 +47,4 @@ fn impl_enum_derive(ast: &syn::DeriveInput) -> TokenStream { } } } - .into() } diff --git a/stm32-metapac-gen/src/data.rs b/stm32-metapac-gen/src/data.rs index 1609351..c52443c 100644 --- a/stm32-metapac-gen/src/data.rs +++ b/stm32-metapac-gen/src/data.rs @@ -55,6 +55,7 @@ pub mod ir { }) .collect(); + #[allow(clippy::redundant_field_names)] Block { name: name.to_string(), items: items, @@ -94,6 +95,7 @@ pub mod ir { }) .collect(); + #[allow(clippy::redundant_field_names)] FieldSet { name: name.strip_prefix("regs::").unwrap().to_owned(), fields: fields, @@ -120,6 +122,7 @@ pub mod ir { }) .collect(); + #[allow(clippy::redundant_field_names)] Enum { name: name.strip_prefix("vals::").unwrap().to_owned(), description: enumm.description.clone(),