diff --git a/data/registers/comp_v3.yaml b/data/registers/comp_v3.yaml
new file mode 100644
index 0000000..b0436bf
--- /dev/null
+++ b/data/registers/comp_v3.yaml
@@ -0,0 +1,109 @@
+block/COMP:
+  description: Comparator.
+  items:
+    - name: CSR
+      description: Comparator control and status register.
+      byte_offset: 0
+      fieldset: CSR
+fieldset/CSR:
+  description: control and status register.
+  fields:
+    - name: EN
+      description: Enable
+      bit_offset: 0
+      bit_size: 1
+    - name: PWRMODE
+      description: Power Mode.
+      bit_offset: 2
+      bit_size: 2
+      enum: PWRMODE
+    - name: INMSEL
+      description: Input minus selection bits.
+      bit_offset: 4
+      bit_size: 3
+    - name: INPSEL
+      description: Input plus selection bit.
+      bit_offset: 7
+      bit_size: 2
+    - name: POLARITY
+      description: Polarity selection bit.
+      bit_offset: 15
+      bit_size: 1
+      enum: POLARITY
+    - name: HYST
+      description: Hysteresis selection bits.
+      bit_offset: 16
+      bit_size: 2
+      enum: HYST
+    - name: BLANKING
+      description: Blanking source selection bits.
+      bit_offset: 18
+      bit_size: 3
+      enum: BLANKING
+    - name: BRGEN
+      description: Scaler bridge enable.
+      bit_offset: 22
+      bit_size: 1
+    - name: SCALEN
+      description: Voltage scaler enable bit.
+      bit_offset: 23
+      bit_size: 1
+    - name: INMESEL
+      description: Input minus extended selection bits.
+      bit_offset: 25
+      bit_size: 2
+    - name: VALUE
+      description: Output status bit.
+      bit_offset: 30
+      bit_size: 1
+    - name: LOCK
+      description: Register lock bit.
+      bit_offset: 31
+      bit_size: 1
+enum/BLANKING:
+  bit_size: 3
+  variants:
+    - name: NoBlanking
+      description: No blanking.
+      value: 0
+    - name: TIM1OC5
+      description: TIM1 OC5 selected as blanking source.
+      value: 1
+    - name: TIM2OC3
+      description: TIM2 OC3 selected as blanking source.
+      value: 2
+enum/HYST:
+  bit_size: 2
+  variants:
+    - name: None
+      value: 0
+    - name: Low
+      value: 1
+    - name: Medium
+      value: 2
+    - name: High
+      value: 3
+enum/POLARITY:
+  bit_size: 1
+  variants:
+    - name: NotInverted
+      description: Output is not inverted.
+      value: 0
+    - name: Inverted
+      description: Output is inverted.
+      value: 1
+enum/PWRMODE:
+  bit_size: 2
+  variants:
+    - name: HighSpeed
+      description: High speed / full power.
+      value: 0
+    - name: MediumSpeed
+      description: Medium speed / medium power.
+      value: 1
+    - name: LowSpeed
+      description: Low speed / low power.
+      value: 2
+    - name: VeryLowSpeed
+      description: Very-low speed / ultra-low power.
+      value: 3
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index d90f45f..6b82661 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -538,6 +538,7 @@ impl PeriMatcher {
             (".*:CRYP:cryp1_v2_2.*", ("cryp", "v2", "CRYP")),
             ("STM32G0.1.*:.*:COMP:.*", ("comp", "v1", "COMP")),
             ("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")),
+            ("STM32WLE.*:.*:COMP:.*", ("comp", "v3", "COMP")),
         ];
 
         Self {