diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index d600c9f..f24f660 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -702,7 +702,7 @@ enum/MCOSEL: - name: NoMCO description: MCO output disabled, no clock on MCO value: 0 - - name: SYSCLK + - name: SYS description: System clock selected value: 4 - name: HSI diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml index 72cfc99..571b8d5 100644 --- a/data/registers/rcc_f100.yaml +++ b/data/registers/rcc_f100.yaml @@ -673,7 +673,7 @@ enum/MCOSEL: - name: NoMCO description: MCO output disabled, no clock on MCO value: 0 - - name: SYSCLK + - name: SYS description: System clock selected value: 4 - name: HSI diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index 85ae278..87cc095 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -724,7 +724,7 @@ enum/HPRE: enum/I2S2SRC: bit_size: 1 variants: - - name: SYSCLK + - name: SYS description: System clock (SYSCLK) selected as I2S clock entry value: 0 - name: PLL3 @@ -736,7 +736,7 @@ enum/MCOSEL: - name: NoMCO description: MCO output disabled, no clock on MCO value: 0 - - name: SYSCLK + - name: SYS description: System clock selected value: 4 - name: HSI @@ -934,7 +934,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 2 enum/USBPRE: diff --git a/data/registers/rcc_f2.yaml b/data/registers/rcc_f2.yaml index 97fadee..faa9af4 100644 --- a/data/registers/rcc_f2.yaml +++ b/data/registers/rcc_f2.yaml @@ -1232,7 +1232,7 @@ enum/MCO1SEL: enum/MCO2SEL: bit_size: 2 variants: - - name: SYSCLK + - name: SYS description: System clock (SYSCLK) selected value: 0 - name: PLLI2S diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 032063a..b395f0a 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1787,7 +1787,7 @@ enum/CKDFSDMSEL: - name: PCLK2 description: APB2 clock used as Kernel clock value: 0 - - name: SYSCLK + - name: SYS description: System clock used as Kernel clock value: 1 enum/CLK48SEL: @@ -1814,7 +1814,7 @@ enum/FMPICSEL: - name: APB description: APB clock selected as I2C clock value: 0 - - name: SYSCLK + - name: SYS description: System clock selected as I2C clock value: 1 - name: HSI @@ -1916,7 +1916,7 @@ enum/MCO1SEL: enum/MCO2SEL: bit_size: 2 variants: - - name: SYSCLK + - name: SYS description: System clock (SYSCLK) selected value: 0 - name: PLLI2S @@ -3455,7 +3455,7 @@ enum/SDIOSEL: - name: CLK48 description: 48 MHz clock is selected as SD clock value: 0 - - name: SYSCLK + - name: SYS description: System clock is selected as SD clock value: 1 enum/SPDIFRXSEL: diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml index 1ed702f..544d5f1 100644 --- a/data/registers/rcc_f410.yaml +++ b/data/registers/rcc_f410.yaml @@ -798,7 +798,7 @@ enum/FMPICSEL: - name: APB description: APB clock selected as I2C clock value: 0 - - name: SYSCLK + - name: SYS description: System clock selected as I2C clock value: 1 - name: HSI @@ -879,7 +879,7 @@ enum/MCO1SEL: enum/MCO2SEL: bit_size: 2 variants: - - name: SYSCLK + - name: SYS description: System clock (SYSCLK) selected value: 0 - name: PLLI2S diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index 3ae7959..67f055d 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -1725,7 +1725,7 @@ enum/DFSDMSEL: - name: PCLK2 description: APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source value: 0 - - name: SYSCLK + - name: SYS description: System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source value: 1 enum/DSISEL: @@ -1773,7 +1773,7 @@ enum/ICSEL: - name: APB description: APB clock selected as I2C clock value: 0 - - name: SYSCLK + - name: SYS description: System clock selected as I2C clock value: 1 - name: HSI @@ -1836,7 +1836,7 @@ enum/MCO1SEL: enum/MCO2SEL: bit_size: 2 variants: - - name: SYSCLK + - name: SYS description: System clock (SYSCLK) selected value: 0 - name: PLLI2S @@ -3129,7 +3129,7 @@ enum/SDMMCSEL: - name: CLK48 description: 48 MHz clock is selected as SD clock value: 0 - - name: SYSCLK + - name: SYS description: System clock is selected as SD clock value: 1 enum/SPREADSEL: @@ -3168,7 +3168,7 @@ enum/USART1SEL: - name: PCLK2 description: APB2 clock (PCLK2) is selected as USART clock value: 0 - - name: SYSCLK + - name: SYS description: System clock is selected as USART clock value: 1 - name: HSI @@ -3183,7 +3183,7 @@ enum/USART2SEL: - name: PCLK1 description: APB1 clock (PCLK1) is selected as USART clock value: 0 - - name: SYSCLK + - name: SYS description: System clock is selected as USART clock value: 1 - name: HSI diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 1baeb1f..2f45aef 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -3751,7 +3751,7 @@ enum/MCO1SEL: enum/MCO2SEL: bit_size: 3 variants: - - name: SYSCLK + - name: SYS description: System clock selected for micro-controller clock output value: 0 - name: PLL2_P diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index 23b482d..c1956c5 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -2686,7 +2686,7 @@ enum/MCO1SEL: enum/MCO2SEL: bit_size: 3 variants: - - name: SYSCLK + - name: SYS description: System clock selected for micro-controller clock output value: 0 - name: PLL2_P diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index 0116ae9..0c88ad0 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -3751,7 +3751,7 @@ enum/MCO1SEL: enum/MCO2SEL: bit_size: 3 variants: - - name: SYSCLK + - name: SYS description: System clock selected for micro-controller clock output value: 0 - name: PLL2_P diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index cd369fe..84d18e0 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -1033,7 +1033,7 @@ enum/MCOSEL: - name: DISABLE description: No clock value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK clock selected value: 1 - name: HSI diff --git a/data/registers/rcc_l0_v2.yaml b/data/registers/rcc_l0_v2.yaml index 14a5d1a..541a909 100644 --- a/data/registers/rcc_l0_v2.yaml +++ b/data/registers/rcc_l0_v2.yaml @@ -1072,7 +1072,7 @@ enum/MCOSEL: - name: DISABLE description: No clock value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK clock selected value: 1 - name: HSI diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml index 7f168b0..775d0df 100644 --- a/data/registers/rcc_l1.yaml +++ b/data/registers/rcc_l1.yaml @@ -886,7 +886,7 @@ enum/MCOSEL: - name: DISABLE description: No clock value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK clock selected value: 1 - name: HSI diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index e4bcc3b..8f7e0ab 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -2017,7 +2017,7 @@ enum/MCOSEL: - name: None description: MCO output disabled, no clock on MCO value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK system clock selected value: 1 - name: MSI diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index 49d509c..790f6d9 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -2432,10 +2432,10 @@ fieldset/SRDAMR: enum/ADCDACSEL: bit_size: 3 variants: - - name: HCLK + - name: HCLK1 description: HCLK clock selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - name: PLL2_R @@ -2444,16 +2444,16 @@ enum/ADCDACSEL: - name: HSE description: HSE clock selected value: 3 - - name: HSI16 + - name: HSI description: HSI16 clock selected value: 4 - - name: MSI_K + - name: MSIK description: MSIK clock selected value: 5 enum/ADFSEL: bit_size: 3 variants: - - name: HCLK + - name: HCLK1 description: HCLK selected value: 0 - name: PLL1_P @@ -2558,7 +2558,7 @@ enum/HSEEXT: enum/HSPISEL: bit_size: 2 variants: - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 0 - name: PLL1_Q @@ -2591,10 +2591,10 @@ enum/ICSEL: - name: PCLK1 description: PCLK1 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: MSIK @@ -2609,7 +2609,7 @@ enum/LPTIMSEL: - name: LSI description: LSI selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: LSE @@ -2621,10 +2621,10 @@ enum/LPUARTSEL: - name: PCLK3 description: PCLK3 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: LSE @@ -2699,13 +2699,13 @@ enum/MCOSEL: - name: DISABLE description: MCO output disabled, no clock on MCO value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK system clock selected value: 1 - name: MSIS description: MSIS clock selected value: 2 - - name: HSI16 + - name: HSI description: HSI16 clock selected value: 3 - name: HSE @@ -2729,7 +2729,7 @@ enum/MCOSEL: enum/MDFSEL: bit_size: 3 variants: - - name: HCLK + - name: HCLK1 description: HCLK selected value: 0 - name: PLL1_P @@ -2852,7 +2852,7 @@ enum/MSIXSRANGE: enum/OCTOSPISEL: bit_size: 2 variants: - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 0 - name: MSIK @@ -2873,10 +2873,10 @@ enum/OTGHSSEL: - name: PLL1_P description: PLL1 “P” (pll1_q_ck) selected, value: 1 - - name: HSE_DIV2 + - name: HSE_DIV_2 description: HSE/2 selected value: 2 - - name: PLL1_P_DIV2 + - name: PLL1_P_DIV_2 description: PLL1 “P” divided by 2 (pll1_p_ck/2) selected value: 3 enum/PLLDIV: @@ -4236,13 +4236,13 @@ enum/PLLRGE: enum/PLLSRC: bit_size: 2 variants: - - name: NONE + - name: DISABLE description: No clock sent to PLL3 value: 0 - name: MSIS description: MSIS clock selected as PLL3 clock entry value: 1 - - name: HSI16 + - name: HSI description: HSI16 clock selected as PLL3 clock entry value: 2 - name: HSE @@ -4281,10 +4281,10 @@ enum/RNGSEL: - name: HSI48 description: HSI48 selected value: 0 - - name: HSI48_DIV2 + - name: HSI48_DIV_2 description: HSI48 / 2 selected, can be used in Range 4 value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 enum/RTCSEL: @@ -4308,7 +4308,7 @@ enum/SAESSEL: - name: SHSI description: SHSI selected value: 0 - - name: SHSI_DIV2 + - name: SHSI_DIV_2 description: SHSI / 2 selected, can be used in Range 4 value: 1 enum/SAISEL: @@ -4326,7 +4326,7 @@ enum/SAISEL: - name: AUDIOCLK description: input pin AUDIOCLK selected value: 3 - - name: HSI16 + - name: HSI description: HSI16 clock selected value: 4 enum/SDMMCSEL: @@ -4353,10 +4353,10 @@ enum/SPISEL: - name: PCLK2 description: PCLK2 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: MSIK @@ -4368,7 +4368,7 @@ enum/STOPKERWUCK: - name: MSIK description: MSIK oscillator automatically enabled when exiting Stop mode value: 0 - - name: HSI16 + - name: HSI description: HSI16 oscillator automatically enabled when exiting Stop mode value: 1 enum/STOPWUCK: @@ -4377,7 +4377,7 @@ enum/STOPWUCK: - name: MSIS description: MSIS oscillator selected as wakeup from stop clock and CSS backup clock value: 0 - - name: HSI16 + - name: HSI description: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock value: 1 enum/SW: @@ -4386,7 +4386,7 @@ enum/SW: - name: MSIS description: MSIS selected as system clock value: 0 - - name: HSI16 + - name: HSI description: HSI16 selected as system clock value: 1 - name: HSE @@ -4398,7 +4398,7 @@ enum/SW: enum/SYSTICKSEL: bit_size: 2 variants: - - name: HCLK_DIV8 + - name: HCLK1_DIV_8 description: HCLK/8 selected value: 0 - name: LSI @@ -4410,7 +4410,7 @@ enum/SYSTICKSEL: enum/TIMICSEL: bit_size: 3 variants: - - name: NONE + - name: DISABLE description: No sources can be selected by TIM16, TIM17 and LPTIM2 as internal input capture value: 0 - name: HSI256_MSIS1024_MSIS4 @@ -4431,10 +4431,10 @@ enum/UARTSEL: - name: PCLK1 description: PCLK1 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: LSE @@ -4446,10 +4446,10 @@ enum/USARTSEL: - name: PCLK2 description: PCLK2 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: LSE diff --git a/data/registers/rcc_wb.yaml b/data/registers/rcc_wb.yaml index eee325a..fc09aea 100644 --- a/data/registers/rcc_wb.yaml +++ b/data/registers/rcc_wb.yaml @@ -1748,13 +1748,13 @@ enum/MCOSEL: - name: DISABLE description: No clock value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK clock selected value: 1 - name: MSI description: MSI oscillator clock selected value: 2 - - name: HSI16 + - name: HSI description: HSI oscillator clock selected value: 3 - name: HSE @@ -2146,7 +2146,7 @@ enum/PLLSRC: - name: MSI description: MSI selected as PLL entry clock source value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected as PLL entry clock source value: 2 - name: HSE @@ -2190,9 +2190,9 @@ enum/SW: variants: - name: MSI value: 0 - - name: HSI16 + - name: HSI value: 1 - name: HSE value: 2 - - name: PLL + - name: PLL1_R value: 3 diff --git a/data/registers/rcc_wba.yaml b/data/registers/rcc_wba.yaml index 382d876..1be8ea5 100644 --- a/data/registers/rcc_wba.yaml +++ b/data/registers/rcc_wba.yaml @@ -1204,7 +1204,7 @@ enum/ADCSEL: - name: HCLK1 description: hclk1 clock selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - name: PLL1_P @@ -1213,7 +1213,7 @@ enum/ADCSEL: - name: HSE description: HSE clock selected value: 3 - - name: HSI16 + - name: HSI description: HSI16 clock selected value: 4 enum/HDIV5: @@ -1276,10 +1276,10 @@ enum/ICSEL: - name: PCLK1 description: pclk1 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 enum/LPTIMSEL: @@ -1291,7 +1291,7 @@ enum/LPTIMSEL: - name: LSI description: LSI selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: LSE @@ -1303,10 +1303,10 @@ enum/LPUARTSEL: - name: PCLK7 description: pclk7 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: LSE @@ -1387,7 +1387,7 @@ enum/MCOSEL: - name: SYSCLKPRE description: sysclkpre system clock after PLL1RCLKPRE division selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 clock selected value: 3 - name: HSE @@ -1441,10 +1441,10 @@ enum/PLLRGE: enum/PLLSRC: bit_size: 2 variants: - - name: NONE + - name: DISABLE description: no clock sent to PLL1 value: 0 - - name: HSI16 + - name: HSI description: HSI16 clock selected as PLL1 clock entry value: 2 - name: HSE @@ -1489,7 +1489,7 @@ enum/RNGSEL: - name: LSI description: LSI selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: PLL1_Q @@ -1516,16 +1516,16 @@ enum/SPISEL: - name: PCLK2 description: pclk2 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 enum/SW: bit_size: 2 variants: - - name: HSI16 + - name: HSI description: HSI16 selected as system clock value: 0 - name: HSE @@ -1537,7 +1537,7 @@ enum/SW: enum/SYSTICKSEL: bit_size: 2 variants: - - name: HCLK1_DIV8 + - name: HCLK1_DIV_8 description: hclk1 divided by 8 selected value: 0 - name: LSI @@ -1549,10 +1549,10 @@ enum/SYSTICKSEL: enum/TIMICSEL: bit_size: 1 variants: - - name: Div1 + - name: HSI description: HSI16 divider disabled value: 0 - - name: HSI16_DIV_256 + - name: HSI_DIV_256 description: HSI16/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture value: 1 enum/USARTSEL: @@ -1561,10 +1561,10 @@ enum/USARTSEL: - name: PCLK1 description: pclk1 selected value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK selected value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected value: 2 - name: LSE diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index d3a59cc..ba57b58 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -1443,13 +1443,13 @@ fieldset/PLLCFGR: enum/ADCSEL: bit_size: 2 variants: - - name: HSI16 + - name: HSI description: HSI16 used as ADC clock source value: 1 - - name: PLLPCLK + - name: PLL1_P description: PLLPCLK used as ADC clock source value: 2 - - name: SYSCLK + - name: SYS description: SYSCLK used as ADC clock source value: 3 enum/HPRE: @@ -1536,13 +1536,13 @@ enum/MCOSEL: - name: DISABLE description: No clock value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK clock selected value: 1 - name: MSI description: MSI oscillator clock selected value: 2 - - name: HSI16 + - name: HSI description: HSI oscillator clock selected value: 3 - name: HSE @@ -1557,7 +1557,7 @@ enum/MCOSEL: - name: LSE description: LSE oscillator clock selected value: 8 - - name: PLLPCLK + - name: PLL1_P description: Main PLLCLK oscillator clock selected value: 13 - name: PLLQCLK @@ -1970,7 +1970,7 @@ enum/PLLSRC: - name: MSI description: MSI selected as PLL entry clock source value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected as PLL entry clock source value: 2 - name: HSE @@ -2014,9 +2014,9 @@ enum/SW: variants: - name: MSI value: 0 - - name: HSI16 + - name: HSI value: 1 - name: HSE value: 2 - - name: PLLR + - name: PLL1_R value: 3 diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index 6acc113..f03a08e 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -1064,13 +1064,13 @@ fieldset/PLLCFGR: enum/ADCSEL: bit_size: 2 variants: - - name: HSI16 + - name: HSI description: HSI16 used as ADC clock source value: 1 - - name: PLLPCLK + - name: PLL1_P description: PLLPCLK used as ADC clock source value: 2 - - name: SYSCLK + - name: SYS description: SYSCLK used as ADC clock source value: 3 enum/HPRE: @@ -1157,19 +1157,19 @@ enum/MCOSEL: - name: DISABLE description: No clock value: 0 - - name: SYSCLK + - name: SYS description: SYSCLK clock selected value: 1 - name: MSI description: MSI oscillator clock selected value: 2 - - name: HSI16 + - name: HSI description: HSI oscillator clock selected value: 3 - name: HSE description: HSE oscillator clock selected value: 4 - - name: PLLRCLK + - name: PLL1_R description: Main PLLRCLK clock selected value: 5 - name: LSI @@ -1178,10 +1178,10 @@ enum/MCOSEL: - name: LSE description: LSE oscillator clock selected value: 8 - - name: PLLPCLK + - name: PLL1_P description: Main PLLCLK oscillator clock selected value: 13 - - name: PLLQCLK + - name: PLL1_Q description: Main PLLQCLK oscillator clock selected value: 14 enum/MSIRANGE: @@ -1591,7 +1591,7 @@ enum/PLLSRC: - name: MSI description: MSI selected as PLL entry clock source value: 1 - - name: HSI16 + - name: HSI description: HSI16 selected as PLL entry clock source value: 2 - name: HSE @@ -1635,9 +1635,9 @@ enum/SW: variants: - name: MSI value: 0 - - name: HSI16 + - name: HSI value: 1 - name: HSE value: 2 - - name: PLLR + - name: PLL1_R value: 3 diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index 6fb0c79..749f5cb 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -15,10 +15,6 @@ pub struct PeripheralToClock( impl PeripheralToClock { pub fn parse(registers: &Registers) -> anyhow::Result { let mut peripheral_to_clock = HashMap::new(); - let checked_rccs = HashSet::from([ - "c0", "f0", "f1", "f100", "f1c1", "f2", "f3", "f3_v2", "f4", "f410", "f7", "g0", "g4", "h5", "h50", "h7", - "h7ab", "h7rm0433", "l0", "l0_v2", "l1", "l4", "l4plus", "l5", - ]); let allowed_variants = HashSet::from([ "DISABLE", "SYS", @@ -60,10 +56,13 @@ impl PeripheralToClock { "PLL3_Q", "PLL3_R", "HSI", + "SHSI", "HSI48", "LSI", "CSI", "MSI", + "MSIS", + "MSIK", "HSE", "LSE", "AUDIOCLK", @@ -79,6 +78,12 @@ impl PeripheralToClock { "RTCCLK", "RTC_WKUP", "DSIPHY", + "ICLK", + "DCLK", + "HSI256_MSIS1024_MSIS4", + "HSI256_MSIS1024_MSIK4", + "HSI256_MSIK1024_MSIS4", + "HSI256_MSIK1024_MSIK4", ]); for (rcc_name, ir) in ®isters.registers { @@ -110,10 +115,6 @@ impl PeripheralToClock { }; let check_mux = |register: &String, field: &String| -> Result<(), anyhow::Error> { - if !checked_rccs.contains(&rcc_name) { - return Ok(()); - } - let block_map = match rcc_enum_map.get(register) { Some(block_map) => block_map, _ => return Ok(()), @@ -125,7 +126,7 @@ impl PeripheralToClock { }; for v in &enumm.variants { - if let Some(captures) = regex!(r"^([A-Z0-9]+)_DIV_\d+?$").captures(v.name.as_str()) { + if let Some(captures) = regex!(r"^([A-Z0-9_]+)_DIV_\d+?$").captures(v.name.as_str()) { let name = captures.get(1).unwrap(); if !allowed_variants.contains(name.as_str()) {