diff --git a/d b/d index 97996ca..be4f74e 100755 --- a/d +++ b/d @@ -4,7 +4,7 @@ set -e cd $(dirname $0) CMD=$1 -REV=74b97817d4c4ed0db9d19a8eac46720b3c5b0d57 +REV=709c1060ac2ec57f6042f2b4eb9cf8c1821a6c57 shift case "$CMD" in diff --git a/d.ps1 b/d.ps1 index 6772f52..af2d8a1 100644 --- a/d.ps1 +++ b/d.ps1 @@ -6,13 +6,15 @@ param ( [string]$peri ) +$REV="74b97817d4c4ed0db9d19a8eac46720b3c5b0d57" + Switch ($CMD) { "download-all" { rm -r -Force ./sources/ -ErrorAction SilentlyContinue git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/ cd ./sources/ - git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c + git checkout $REV cd .. } "install-chiptool" { @@ -41,4 +43,4 @@ Switch ($CMD) default { echo "unknown command" } -} \ No newline at end of file +} diff --git a/data/dmamux/H7RS_GPDMA.yaml b/data/dmamux/H7RS_GPDMA.yaml new file mode 100644 index 0000000..28e9183 --- /dev/null +++ b/data/dmamux/H7RS_GPDMA.yaml @@ -0,0 +1,110 @@ +ADC1: 0 +ADC2: 1 +CRYP_IN: 2 +CRYP_OUT: 3 +SAES_OUT: 4 +SAES_IN: 5 +HASH: 6 +TIM1_CC: 7 +TIM1_CC: 8 +TIM1_CC: 9 +TIM1_CC: 10 +TIM1_UP: 11 +TIM1_TRG: 12 +TIM1_COM: 13 +TIM2_CC: 14 +TIM2_CC: 15 +TIM2_CC: 16 +TIM2_CC: 17 +TIM2_UP: 18 +TIM2_TRG: 19 +TIM3_CC: 20 +TIM3_CC: 21 +TIM3_CC: 22 +TIM3_CC: 23 +TIM3_UP: 24 +TIM3_TRG: 25 +TIM4_CC: 26 +TIM4_CC: 27 +TIM4_CC: 28 +TIM4_CC: 29 +TIM4_UP: 30 +TIM4_TRG: 31 +TIM5_CC: 32 +TIM5_CC: 33 +TIM5_CC: 34 +TIM5_CC: 35 +TIM5_UP: 36 +TIM5_TRG: 37 +TIM6_UP: 38 +TIM7_UP: 39 +TIM15_CC: 40 +TIM15_CC: 41 +TIM15_UP: 42 +TIM15_TRG: 43 +TIM15_COM: 44 +TIM16_CC: 45 +TIM16_UP: 46 +TIM16_COM: 47 +TIM17_CC: 48 +TIM17_UP: 49 +TIM17_COM: 50 +SPI1_RX: 51 +SPI1_TX: 52 +SPI2_RX: 53 +SPI2_TX: 54 +SPI3_RX: 55 +SPI3_TX: 56 +SPI4_RX: 57 +SPI4_TX: 58 +SPI5_RX: 59 +SPI5_TX: 60 +SPI6_RX: 61 +SPI6_TX: 62 +SAI1_A: 63 +SAI1_B: 64 +SAI2_A: 65 +SAI2_B: 66 +I2C1_RX: 67 +I2C1_TX: 68 +I2C2_RX: 69 +I2C2_TX: 70 +I2C3_RX: 71 +I2C3_TX: 72 +USART1_RX: 73 +USART1_TX: 74 +USART2_RX: 75 +USART2_TX: 76 +USART3_RX: 77 +USART3_TX: 78 +UART4_RX: 79 +UART4_TX: 80 +UART5_RX: 81 +UART5_TX: 82 +UART7_RX: 83 +UART7_TX: 84 +UART8_RX: 85 +UART8_TX: 86 +CORDIC_READ: 87 +CORDIC_WRITE: 88 +LPTIM1_IC1: 89 +LPTIM1_IC2: 90 +LPTIM1_UE: 91 +LPTIM2_IC1: 92 +LPTIM2_IC2: 93 +LPTIM2_UE: 94 +SPDIFRX_DAT: 95 +SPDIFRX_CTRL: 96 +ADF1_FLT0: 97 +UCPD_TX: 98 +UCPD_RX: 99 +PSSI: 100 +LPUART1_RX: 101 +LPUART1_TX: 102 +LPTIM3_IC1: 103 +LPTIM3_IC2: 104 +LPTIM3_UE: 105 +I3C1_RX: 106 +I3C1_TX: 107 +I3C1_TC: 108 +I3C1_RS: 109 diff --git a/data/dmamux/H7RS_HPDMA.yaml b/data/dmamux/H7RS_HPDMA.yaml new file mode 100644 index 0000000..ca5c3f3 --- /dev/null +++ b/data/dmamux/H7RS_HPDMA.yaml @@ -0,0 +1,20 @@ +JPEG_RX: 0 +JPEG_TX: 1 +XSPI1_RX: 2 +XSPI2_RX: 3 +SPI3_RX: 4 +SPI3_TX: 5 +SPI4_RX: 6 +SPI4_TX: 7 +ADC1: 8 +ADC2: 9 +ADF1_FLT0: 10 +UART4_RX: 11 +UART4_TX: 12 +UART5_RX: 13 +UART5_TX: 14 +UART7_RX: 15 +UART7_TX: 16 +LPTIM2_IC1: 17 +LPTIM2_IC2: 18 +LPTIM2_UE: 19 diff --git a/data/dmamux/U5_LPDMA.yaml b/data/dmamux/U5_LPDMA.yaml new file mode 100644 index 0000000..4cee06f --- /dev/null +++ b/data/dmamux/U5_LPDMA.yaml @@ -0,0 +1,17 @@ +LPUART1_RX: 0 +LPUART1_TX: 1 +SPI3_RX: 2 +SPI3_TX: 3 +I2C3_RX: 4 +I2C3_TX: 5 +I2C3_EVC: 6 +ADC4: 7 +DAC1_CH1: 8 +DAC1_CH2: 9 +ADF1_FLT0: 10 +LPTIM1_IC1: 11 +LPTIM1_IC2: 12 +LPTIM1_UE: 13 +LPTIM3_IC1: 14 +LPTIM3_IC2: 15 +LPTIM3_UE: 16 diff --git a/data/registers/adc_g4.yaml b/data/registers/adc_g4.yaml index 57b75d3..a260c0d 100644 --- a/data/registers/adc_g4.yaml +++ b/data/registers/adc_g4.yaml @@ -129,16 +129,16 @@ fieldset/CALFACT: fieldset/CFGR: description: configuration register 1 fields: - - name: DMAEN - description: Direct memory access enable - bit_offset: 0 - bit_size: 1 - enum: DMAEN - name: DMACFG description: direct memory access configuration bit_offset: 0 bit_size: 1 enum: DMACFG + - name: DMAEN + description: Direct memory access enable + bit_offset: 0 + bit_size: 1 + enum: DMAEN - name: RES description: data resolution bit_offset: 3 @@ -154,12 +154,12 @@ fieldset/CFGR: bit_size: 2 enum: EXTEN - name: OVRMOD - description: overrun mode + description: overrun mode bit_offset: 12 bit_size: 1 enum: OVRMOD - name: CONT - description: single / continuous conversion mode for regular conversions + description: single / continuous conversion mode for regular conversions bit_offset: 13 bit_size: 1 - name: AUTDLY @@ -171,7 +171,7 @@ fieldset/CFGR: bit_offset: 15 bit_size: 1 - name: DISCEN - description: discontinuous mode for regular channels + description: discontinuous mode for regular channels bit_offset: 16 bit_size: 1 - name: DISCNUM @@ -188,7 +188,7 @@ fieldset/CFGR: bit_size: 1 enum: JQM - name: AWD1SGL - description: enable the watchdog 1 on a single channel or on all channels + description: enable the watchdog 1 on a single channel or on all channels bit_offset: 22 bit_size: 1 enum: AWD1SGL @@ -321,6 +321,13 @@ fieldset/DR: description: group regular conversion data bit_offset: 0 bit_size: 16 +fieldset/GCOMP: + description: Gain compensation coefficient + fields: + - name: GCOMPCOEFF + description: Gain compensation coefficient + bit_offset: 0 + bit_size: 14 fieldset/IER: description: interrupt enable register fields: @@ -445,43 +452,6 @@ fieldset/JSQR: array: len: 4 stride: 6 -fieldset/TR1: - description: analog watchdog threshold register 1 - fields: - - name: LT1 - description: analog watchdog 1 lower threshold - bit_offset: 0 - bit_size: 12 - - name: AWDFILT - description: analog watchdog filtering parameter - bit_offset: 12 - bit_size: 3 - - name: HT1 - description: analog watchdog 1 higher threshold - bit_offset: 16 - bit_size: 12 -fieldset/TR2: - description: analog watchdog threshold register 2 - fields: - - name: LT2 - description: analog watchdog 2 lower threshold - bit_offset: 0 - bit_size: 8 - - name: HT2 - description: analog watchdog 2 higher threshold - bit_offset: 16 - bit_size: 8 -fieldset/TR3: - description: analog watchdog threshold register 3 - fields: - - name: LT3 - description: analog watchdog 3 lower threshold - bit_offset: 0 - bit_size: 8 - - name: HT3 - description: analog watchdog 3 higher threshold - bit_offset: 16 - bit_size: 8 fieldset/OFR: description: offset number x register fields: @@ -498,7 +468,7 @@ fieldset/OFR: bit_offset: 25 bit_size: 1 - name: OFFSET1_CH - description: Channel selection for the data offset + description: Channel selection for the data offset bit_offset: 26 bit_size: 5 - name: OFFSET_EN @@ -575,13 +545,43 @@ fieldset/SQR4: array: len: 2 stride: 6 -fieldset/GCOMP: - description: Gain compensation coefficient +fieldset/TR1: + description: analog watchdog threshold register 1 fields: - - name: GCOMPCOEFF - description: Gain compensation coefficient + - name: LT1 + description: analog watchdog 1 lower threshold bit_offset: 0 - bit_size: 14 + bit_size: 12 + - name: AWDFILT + description: analog watchdog filtering parameter + bit_offset: 12 + bit_size: 3 + - name: HT1 + description: analog watchdog 1 higher threshold + bit_offset: 16 + bit_size: 12 +fieldset/TR2: + description: analog watchdog threshold register 2 + fields: + - name: LT2 + description: analog watchdog 2 lower threshold + bit_offset: 0 + bit_size: 8 + - name: HT2 + description: analog watchdog 2 higher threshold + bit_offset: 16 + bit_size: 8 +fieldset/TR3: + description: analog watchdog threshold register 3 + fields: + - name: LT3 + description: analog watchdog 3 lower threshold + bit_offset: 0 + bit_size: 8 + - name: HT3 + description: analog watchdog 3 higher threshold + bit_offset: 16 + bit_size: 8 enum/ADCALDIF: bit_size: 1 variants: @@ -615,15 +615,6 @@ enum/DIFSEL: - name: Differential description: Input channel is configured in differential mode value: 1 -enum/DMAEN: - bit_size: 1 - variants: - - name: Disable - description: DMA disable - value: 0 - - name: Enable - description: DMA enable - value: 1 enum/DMACFG: bit_size: 1 variants: @@ -633,6 +624,15 @@ enum/DMACFG: - name: CircularMode description: DMA Circular mode selected value: 1 +enum/DMAEN: + bit_size: 1 + variants: + - name: Disable + description: DMA disable + value: 0 + - name: Enable + description: DMA enable + value: 1 enum/EXTEN: bit_size: 2 variants: @@ -740,4 +740,4 @@ enum/TROVS: value: 0 - name: Triggered description: Each oversampled conversion for a channel needs a new trigger - value: 1 \ No newline at end of file + value: 1 diff --git a/data/registers/adc_u0.yaml b/data/registers/adc_u0.yaml new file mode 100644 index 0000000..8288135 --- /dev/null +++ b/data/registers/adc_u0.yaml @@ -0,0 +1,460 @@ +block/ADC: + description: Analog to Digital Converter + items: + - name: ISR + description: ADC interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: ADC interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: ADC control register + byte_offset: 8 + fieldset: CR + - name: CFGR1 + description: ADC configuration register 1 + byte_offset: 12 + fieldset: CFGR1 + - name: CFGR2 + description: ADC configuration register 2 + byte_offset: 16 + fieldset: CFGR2 + - name: SMPR + description: ADC sampling time register + byte_offset: 20 + fieldset: SMPR + - name: AWD1TR + description: watchdog threshold register + byte_offset: 32 + fieldset: AWD1TR + - name: AWD2TR + description: watchdog threshold register + byte_offset: 36 + fieldset: AWD2TR + - name: CHSELR + description: channel selection register + byte_offset: 40 + fieldset: CHSELR + - name: CHSELR_1 + description: channel selection register CHSELRMOD = 1 in ADC_CFGR1 + byte_offset: 40 + fieldset: CHSELR_1 + - name: AWD3TR + description: watchdog threshold register + byte_offset: 44 + fieldset: AWD3TR + - name: DR + description: ADC group regular conversion data register + byte_offset: 64 + access: Read + fieldset: DR + - name: AWD2CR + description: ADC analog watchdog 2 configuration register + byte_offset: 160 + fieldset: AWD2CR + - name: AWD3CR + description: ADC analog watchdog 3 configuration register + byte_offset: 164 + fieldset: AWD3CR + - name: CALFACT + description: ADC calibration factors register + byte_offset: 180 + fieldset: CALFACT + - name: CCR + description: ADC common control register + byte_offset: 776 + fieldset: CCR +fieldset/AWD1TR: + description: watchdog threshold register + fields: + - name: LT1 + description: ADC analog watchdog 1 threshold low + bit_offset: 0 + bit_size: 12 + - name: HT1 + description: ADC analog watchdog 1 threshold high + bit_offset: 16 + bit_size: 12 +fieldset/AWD2CR: + description: ADC analog watchdog 2 configuration register + fields: + - name: AWD2CH + description: ADC analog watchdog 2 monitored channel selection + bit_offset: 0 + bit_size: 19 +fieldset/AWD2TR: + description: watchdog threshold register + fields: + - name: LT2 + description: ADC analog watchdog 2 threshold low + bit_offset: 0 + bit_size: 12 + - name: HT2 + description: ADC analog watchdog 2 threshold high + bit_offset: 16 + bit_size: 12 +fieldset/AWD3CR: + description: ADC analog watchdog 3 configuration register + fields: + - name: AWD3CH + description: ADC analog watchdog 3 monitored channel selection + bit_offset: 0 + bit_size: 19 +fieldset/AWD3TR: + description: watchdog threshold register + fields: + - name: LT3 + description: ADC analog watchdog 3 threshold high + bit_offset: 0 + bit_size: 12 + - name: HT3 + description: ADC analog watchdog 3 threshold high + bit_offset: 16 + bit_size: 12 +fieldset/CALFACT: + description: ADC calibration factors register + fields: + - name: CALFACT + description: ADC calibration factor in single-ended mode + bit_offset: 0 + bit_size: 7 +fieldset/CCR: + description: ADC common control register + fields: + - name: PRESC + description: ADC prescaler + bit_offset: 18 + bit_size: 4 + - name: VREFEN + description: VREFINT enable + bit_offset: 22 + bit_size: 1 + - name: TSEN + description: Temperature sensor enable + bit_offset: 23 + bit_size: 1 + - name: VBATEN + description: VBAT enable + bit_offset: 24 + bit_size: 1 +fieldset/CFGR1: + description: ADC configuration register 1 + fields: + - name: DMAEN + description: ADC DMA transfer enable + bit_offset: 0 + bit_size: 1 + - name: DMACFG + description: ADC DMA transfer configuration + bit_offset: 1 + bit_size: 1 + - name: SCANDIR + description: Scan sequence direction + bit_offset: 2 + bit_size: 1 + - name: RES + description: ADC data resolution + bit_offset: 3 + bit_size: 2 + enum: RES + - name: ALIGN + description: ADC data alignement + bit_offset: 5 + bit_size: 1 + - name: EXTSEL + description: ADC group regular external trigger source + bit_offset: 6 + bit_size: 3 + - name: EXTEN + description: ADC group regular external trigger polarity + bit_offset: 10 + bit_size: 2 + - name: OVRMOD + description: ADC group regular overrun configuration + bit_offset: 12 + bit_size: 1 + - name: CONT + description: ADC group regular continuous conversion mode + bit_offset: 13 + bit_size: 1 + - name: WAIT + description: Wait conversion mode + bit_offset: 14 + bit_size: 1 + - name: AUTOFF + description: Auto-off mode + bit_offset: 15 + bit_size: 1 + - name: DISCEN + description: ADC group regular sequencer discontinuous mode + bit_offset: 16 + bit_size: 1 + - name: CHSELRMOD + description: Mode selection of the ADC_CHSELR register + bit_offset: 21 + bit_size: 1 + - name: AWD1SGL + description: ADC analog watchdog 1 monitoring a single channel or all channels + bit_offset: 22 + bit_size: 1 + - name: AWD1EN + description: ADC analog watchdog 1 enable on scope ADC group regular + bit_offset: 23 + bit_size: 1 + - name: AWDCH1CH + description: ADC analog watchdog 1 monitored channel selection + bit_offset: 26 + bit_size: 5 +fieldset/CFGR2: + description: ADC configuration register 2 + fields: + - name: OVSE + description: ADC oversampler enable on scope ADC group regular + bit_offset: 0 + bit_size: 1 + - name: OVSR + description: ADC oversampling ratio + bit_offset: 2 + bit_size: 3 + - name: OVSS + description: ADC oversampling shift + bit_offset: 5 + bit_size: 4 + - name: TOVS + description: ADC oversampling discontinuous mode (triggered mode) for ADC group regular + bit_offset: 9 + bit_size: 1 + - name: LFTRIG + description: Low frequency trigger mode enable + bit_offset: 29 + bit_size: 1 + - name: CKMODE + description: ADC clock mode + bit_offset: 30 + bit_size: 2 +fieldset/CHSELR: + description: channel selection register + fields: + - name: CHSEL + description: Channel-x selection + bit_offset: 0 + bit_size: 19 +fieldset/CHSELR_1: + description: channel selection register CHSELRMOD = 1 in ADC_CFGR1 + fields: + - name: SQ1 + description: conversion of the sequence + bit_offset: 0 + bit_size: 4 + - name: SQ2 + description: conversion of the sequence + bit_offset: 4 + bit_size: 4 + - name: SQ3 + description: conversion of the sequence + bit_offset: 8 + bit_size: 4 + - name: SQ4 + description: conversion of the sequence + bit_offset: 12 + bit_size: 4 + - name: SQ5 + description: conversion of the sequence + bit_offset: 16 + bit_size: 4 + - name: SQ6 + description: conversion of the sequence + bit_offset: 20 + bit_size: 4 + - name: SQ7 + description: conversion of the sequence + bit_offset: 24 + bit_size: 4 + - name: SQ8 + description: conversion of the sequence + bit_offset: 28 + bit_size: 4 +fieldset/CR: + description: ADC control register + fields: + - name: ADEN + description: ADC enable + bit_offset: 0 + bit_size: 1 + - name: ADDIS + description: ADC disable + bit_offset: 1 + bit_size: 1 + - name: ADSTART + description: ADC group regular conversion start + bit_offset: 2 + bit_size: 1 + - name: ADSTP + description: ADC group regular conversion stop + bit_offset: 4 + bit_size: 1 + - name: ADVREGEN + description: ADC voltage regulator enable + bit_offset: 28 + bit_size: 1 + - name: ADCAL + description: ADC calibration + bit_offset: 31 + bit_size: 1 +fieldset/DR: + description: ADC group regular conversion data register + fields: + - name: regularDATA + description: ADC group regular conversion data + bit_offset: 0 + bit_size: 16 +fieldset/IER: + description: ADC interrupt enable register + fields: + - name: ADRDYIE + description: ADC ready interrupt + bit_offset: 0 + bit_size: 1 + - name: EOSMPIE + description: ADC group regular end of sampling interrupt + bit_offset: 1 + bit_size: 1 + - name: EOCIE + description: ADC group regular end of unitary conversion interrupt + bit_offset: 2 + bit_size: 1 + - name: EOSIE + description: ADC group regular end of sequence conversions interrupt + bit_offset: 3 + bit_size: 1 + - name: OVRIE + description: ADC group regular overrun interrupt + bit_offset: 4 + bit_size: 1 + - name: AWD1IE + description: ADC analog watchdog 1 interrupt + bit_offset: 7 + bit_size: 1 + - name: AWD2IE + description: ADC analog watchdog 2 interrupt + bit_offset: 8 + bit_size: 1 + - name: AWD3IE + description: ADC analog watchdog 3 interrupt + bit_offset: 9 + bit_size: 1 + - name: EOCALIE + description: End of calibration interrupt enable + bit_offset: 11 + bit_size: 1 + - name: CCRDYIE + description: Channel Configuration Ready Interrupt enable + bit_offset: 13 + bit_size: 1 +fieldset/ISR: + description: ADC interrupt and status register + fields: + - name: ADRDY + description: ADC ready flag + bit_offset: 0 + bit_size: 1 + - name: EOSMP + description: ADC group regular end of sampling flag + bit_offset: 1 + bit_size: 1 + - name: EOC + description: ADC group regular end of unitary conversion flag + bit_offset: 2 + bit_size: 1 + - name: EOS + description: ADC group regular end of sequence conversions flag + bit_offset: 3 + bit_size: 1 + - name: OVR + description: ADC group regular overrun flag + bit_offset: 4 + bit_size: 1 + - name: AWD1 + description: ADC analog watchdog 1 flag + bit_offset: 7 + bit_size: 1 + - name: AWD2 + description: ADC analog watchdog 2 flag + bit_offset: 8 + bit_size: 1 + - name: AWD3 + description: ADC analog watchdog 3 flag + bit_offset: 9 + bit_size: 1 + - name: EOCAL + description: End Of Calibration flag + bit_offset: 11 + bit_size: 1 + - name: CCRDY + description: Channel Configuration Ready flag + bit_offset: 13 + bit_size: 1 +fieldset/SMPR: + description: ADC sampling time register + fields: + - name: SMP1 + description: Sampling time selection + bit_offset: 0 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP2 + description: Sampling time selection + bit_offset: 4 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMPSEL + description: Channel sampling time selection + bit_offset: 8 + bit_size: 1 + array: + len: 19 + stride: 0 +enum/RES: + bit_size: 2 + variants: + - name: Bits12 + description: 12-bit resolution + value: 0 + - name: Bits10 + description: 10-bit resolution + value: 1 + - name: Bits8 + description: 8-bit resolution + value: 2 + - name: Bits6 + description: 6-bit resolution + value: 3 +enum/SAMPLE_TIME: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 ADC cycles + value: 0 + - name: Cycles3_5 + description: 3.5 ADC cycles + value: 1 + - name: Cycles7_5 + description: 7.5 ADC cycles + value: 2 + - name: Cycles12_5 + description: 12.5 ADC cycles + value: 3 + - name: Cycles19_5 + description: 19.5 ADC cycles + value: 4 + - name: Cycles39_5 + description: 39.5 ADC cycles + value: 5 + - name: Cycles79_5 + description: 79.5 ADC cycles + value: 6 + - name: Cycles160_5 + description: 160.5 ADC cycles + value: 7 diff --git a/data/registers/comp_u0.yaml b/data/registers/comp_u0.yaml new file mode 100644 index 0000000..4cd00f6 --- /dev/null +++ b/data/registers/comp_u0.yaml @@ -0,0 +1,138 @@ +block/COMP: + description: Comparator. + items: + - name: CSR + description: Comparator control and status register. + byte_offset: 0 + fieldset: CSR +fieldset/CSR: + description: control and status register. + fields: + - name: EN + description: Enable + bit_offset: 0 + bit_size: 1 + - name: INMSEL + description: Input minus selection bits. + bit_offset: 4 + bit_size: 4 + - name: INPSEL + description: Input plus selection bit. + bit_offset: 8 + bit_size: 3 + - name: WINMODE + description: Comparator 1 noninverting input selector for window mode. + bit_offset: 14 + bit_size: 1 + enum: WINMODE + - name: WINOUT + description: Comparator 1 output selector. + bit_offset: 14 + bit_size: 1 + enum: WINOUT + - name: POLARITY + description: Polarity selection bit. + bit_offset: 15 + bit_size: 1 + enum: POLARITY + - name: HYST + description: Hysteresis selection bits. + bit_offset: 16 + bit_size: 2 + enum: HYST + - name: PWRMODE + description: Power Mode. + bit_offset: 18 + bit_size: 2 + enum: PWRMODE + - name: BLANKSEL + description: Blanking source selection bits. + bit_offset: 20 + bit_size: 5 + enum: BLANKING + - name: BRGEN + description: Scaler bridge enable. + bit_offset: 22 + bit_size: 1 + - name: VALUE + description: Output status bit. + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: Register lock bit. + bit_offset: 31 + bit_size: 1 +enum/BLANKING: + bit_size: 5 + variants: + - name: NoBlanking + description: No blanking. + value: 0 + - name: TIM1OC4 + description: TIM1 OC4 enabled as blanking source + value: 1 + - name: TIM1OC5 + description: TIM1 OC5 enabled as blanking source + value: 2 + - name: TIM2OC3 + description: TIM5 OC3 enabled as blanking source + value: 4 + - name: TIM3OC3 + description: TIM3 OC3 enabled as blanking source + value: 8 + - name: TIM15OC2 + description: TIM15 OC2 enabled as blanking source + value: 16 +enum/HYST: + bit_size: 2 + variants: + - name: None + value: 0 + - name: Low + value: 1 + - name: Medium + value: 2 + - name: High + value: 3 +enum/POLARITY: + bit_size: 1 + variants: + - name: NotInverted + description: Output is not inverted. + value: 0 + - name: Inverted + description: Output is inverted. + value: 1 +enum/PWRMODE: + bit_size: 2 + variants: + - name: HighSpeed + description: High speed / full power. + value: 0 + - name: MediumSpeed + description: Medium speed / medium power. + value: 1 + - name: LowSpeed + description: Low speed / low power. + value: 2 + - name: VeryLowSpeed + description: Very-low speed / ultra-low power. + value: 3 +enum/WINMODE: + bit_size: 1 + variants: + - name: ThisInpsel + description: Signal selected with INPSEL[2:0] bitfield of this register. + value: 0 + - name: OtherInpsel + description: Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode). + value: 1 +enum/WINOUT: + bit_size: 1 + variants: + - name: COMP1_VALUE + description: Comparator 1 value. + value: 0 + - name: COMP1_VALUE XOR COMP2_VALUE + description: Comparator 1 value XOR comparator 2 value (required for window mode). + value: 1 diff --git a/data/registers/crc_v2.yaml b/data/registers/crc_v2.yaml index 6616d3e..b3e4206 100644 --- a/data/registers/crc_v2.yaml +++ b/data/registers/crc_v2.yaml @@ -1,13 +1,13 @@ block/CRC: description: Cyclic Redundancy Check calculation unit items: - - name: DR32 - description: Data register - byte_offset: 0 - name: DR16 description: Data register - half-word sized byte_offset: 0 bit_size: 16 + - name: DR32 + description: Data register + byte_offset: 0 - name: DR8 description: Data register - byte sized byte_offset: 0 diff --git a/data/registers/crc_v3.yaml b/data/registers/crc_v3.yaml index 9cb0a16..02cdb0e 100644 --- a/data/registers/crc_v3.yaml +++ b/data/registers/crc_v3.yaml @@ -1,13 +1,13 @@ block/CRC: description: Cyclic Redundancy Check calculation unit items: - - name: DR32 - description: Data register - byte_offset: 0 - name: DR16 description: Data register - half-word sized byte_offset: 0 bit_size: 16 + - name: DR32 + description: Data register + byte_offset: 0 - name: DR8 description: Data register - byte sized byte_offset: 0 diff --git a/data/registers/cryp_v4.yaml b/data/registers/cryp_v4.yaml new file mode 100644 index 0000000..3ae1fa3 --- /dev/null +++ b/data/registers/cryp_v4.yaml @@ -0,0 +1,215 @@ +block/CRYP: + description: Cryptographic processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: DIN + description: data input register. + byte_offset: 8 + - name: DOUT + description: data output register. + byte_offset: 12 + access: Read + - name: DMACR + description: DMA control register. + byte_offset: 16 + fieldset: DMACR + - name: IMSCR + description: interrupt mask set/clear register. + byte_offset: 20 + fieldset: IMSCR + - name: RISR + description: raw interrupt status register. + byte_offset: 24 + access: Read + fieldset: RISR + - name: MISR + description: masked interrupt status register. + byte_offset: 28 + access: Read + fieldset: MISR + - name: KEY + description: Cluster KEY%s, containing K?LR, K?RR. + array: + len: 4 + stride: 8 + byte_offset: 32 + block: KEY + - name: INIT + description: Cluster INIT%s, containing IV?LR, IV?RR. + array: + len: 2 + stride: 8 + byte_offset: 64 + block: INIT + - name: CSGCMCCMR + description: context swap register. + array: + len: 8 + stride: 4 + byte_offset: 80 + - name: CSGCMR + description: context swap register. + array: + len: 8 + stride: 4 + byte_offset: 112 +block/INIT: + description: Cluster INIT%s, containing IV?LR, IV?RR. + items: + - name: IVLR + description: initialization vector registers. + byte_offset: 0 + - name: IVRR + description: initialization vector registers. + byte_offset: 4 +block/KEY: + description: Cluster KEY%s, containing K?LR, K?RR. + items: + - name: KLR + description: key registers. + byte_offset: 0 + access: Write + - name: KRR + description: key registers. + byte_offset: 4 + access: Write +fieldset/CR: + description: control register. + fields: + - name: ALGODIR + description: Algorithm direction. + bit_offset: 2 + bit_size: 1 + - name: ALGOMODE0 + description: Algorithm mode. + bit_offset: 3 + bit_size: 3 + - name: DATATYPE + description: Data type selection. + bit_offset: 6 + bit_size: 2 + - name: KEYSIZE + description: Key size selection (AES mode only). + bit_offset: 8 + bit_size: 2 + - name: FFLUSH + description: FIFO flush. + bit_offset: 14 + bit_size: 1 + - name: CRYPEN + description: Cryptographic processor enable. + bit_offset: 15 + bit_size: 1 + - name: GCM_CCMPH + description: GCM_CCMPH. + bit_offset: 16 + bit_size: 2 + - name: ALGOMODE3 + description: ALGOMODE. + bit_offset: 19 + bit_size: 1 + - name: NPBLB + description: Number of Padding Bytes in Last Block of payload. + bit_offset: 20 + bit_size: 4 + - name: KMOD + description: 'Key mode selection This bitfield defines how the CRYP key can be used by the application. KEYSIZE must be correctly initialized when setting KMOD[1:0] different from zero. Others: Reserved Attempts to write the bitfield are ignored when BUSY is set.' + bit_offset: 24 + bit_size: 2 + enum: KMOD + - name: IPRST + description: CRYP peripheral software reset Setting the bit resets the CRYP peripheral, putting all registers to their default values, except the IPRST bit itself. This bit must be kept cleared while writing any configuration registers. + bit_offset: 31 + bit_size: 1 +fieldset/DMACR: + description: DMA control register. + fields: + - name: DIEN + description: DMA input enable. + bit_offset: 0 + bit_size: 1 + - name: DOEN + description: DMA output enable. + bit_offset: 1 + bit_size: 1 +fieldset/IMSCR: + description: interrupt mask set/clear register. + fields: + - name: INIM + description: Input FIFO service interrupt mask. + bit_offset: 0 + bit_size: 1 + - name: OUTIM + description: Output FIFO service interrupt mask. + bit_offset: 1 + bit_size: 1 +fieldset/MISR: + description: masked interrupt status register. + fields: + - name: INMIS + description: Input FIFO service masked interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTMIS + description: Output FIFO service masked interrupt status. + bit_offset: 1 + bit_size: 1 +fieldset/RISR: + description: raw interrupt status register. + fields: + - name: INRIS + description: Input FIFO service raw interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTRIS + description: Output FIFO service raw interrupt status. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: IFEM + description: Input FIFO empty. + bit_offset: 0 + bit_size: 1 + - name: IFNF + description: Input FIFO not full. + bit_offset: 1 + bit_size: 1 + - name: OFNE + description: Output FIFO not empty. + bit_offset: 2 + bit_size: 1 + - name: OFFU + description: Output FIFO full. + bit_offset: 3 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 4 + bit_size: 1 + - name: KERF + description: 'Key error flag This read-only bit is set by hardware when key information failed to load into key registers. KERF is triggered upon any of the following errors: CRYP_KxR/LR register write does not respect the correct order (refer to Section 60.4.16: CRYP key registers for details). CRYP fails to load the key shared by SAES peripheral (KMOD = 0x2). KERF must be cleared by the application software, otherwise KEYVALID cannot be set. It can be done through IPRST bit of CRYP_CR, or when a correct key writing sequence starts.' + bit_offset: 6 + bit_size: 1 + - name: KEYVALID + description: 'Key valid flag This read-only bit is set by hardware when the key of size defined by KEYSIZE is loaded in CRYP_KxR/LR key registers. The CRYPEN bit can only be set when KEYVALID is set. In normal mode when KMOD[1:0] is at zero, the key must be written in the key registers in the correct sequence, otherwise the KERF flag is set and KEYVALID remains cleared. When KMOD[1:0] is different from zero, the BUSY flag is automatically set by CRYP. When the key is loaded successfully, BUSY is cleared and KEYVALID set. Upon an error, KERF is set, BUSY cleared and KEYVALID remains cleared. If set, KERF must be cleared, otherwise KEYVALID cannot be set. For further information on key loading, refer to Section 60.4.16: CRYP key registers.' + bit_offset: 7 + bit_size: 1 +enum/KMOD: + bit_size: 2 + variants: + - name: Normal + description: Normal-key mode. Key registers are freely usable. + value: 0 + - name: Shared + description: Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register. + value: 2 diff --git a/data/registers/dsihost_u5.yaml b/data/registers/dsihost_u5.yaml new file mode 100644 index 0000000..07ac993 --- /dev/null +++ b/data/registers/dsihost_u5.yaml @@ -0,0 +1,1718 @@ +block/DSIHOST: + description: DSI Host. + items: + - name: VR + description: DSI Host version register. + byte_offset: 0 + fieldset: VR + - name: CR + description: DSI Host control register. + byte_offset: 4 + fieldset: CR + - name: CCR + description: DSI Host clock control register. + byte_offset: 8 + fieldset: CCR + - name: LVCIDR + description: DSI Host LTDC VCID register. + byte_offset: 12 + fieldset: LVCIDR + - name: LCOLCR + description: DSI Host LTDC color coding register. + byte_offset: 16 + fieldset: LCOLCR + - name: LPCR + description: DSI Host LTDC polarity configuration register. + byte_offset: 20 + fieldset: LPCR + - name: LPMCR + description: DSI Host low-power mode configuration register. + byte_offset: 24 + fieldset: LPMCR + - name: PCR + description: DSI Host protocol configuration register. + byte_offset: 44 + fieldset: PCR + - name: GVCIDR + description: DSI Host generic VCID register. + byte_offset: 48 + fieldset: GVCIDR + - name: MCR + description: DSI Host mode configuration register. + byte_offset: 52 + fieldset: MCR + - name: VMCR + description: DSI Host video mode configuration register. + byte_offset: 56 + fieldset: VMCR + - name: VPCR + description: DSI Host video packet configuration register. + byte_offset: 60 + fieldset: VPCR + - name: VCCR + description: DSI Host video chunks configuration register. + byte_offset: 64 + fieldset: VCCR + - name: VNPCR + description: DSI Host video null packet configuration register. + byte_offset: 68 + fieldset: VNPCR + - name: VHSACR + description: DSI Host video HSA configuration register. + byte_offset: 72 + fieldset: VHSACR + - name: VHBPCR + description: DSI Host video HBP configuration register. + byte_offset: 76 + fieldset: VHBPCR + - name: VLCR + description: DSI Host video line configuration register. + byte_offset: 80 + fieldset: VLCR + - name: VVSACR + description: DSI Host video VSA configuration register. + byte_offset: 84 + fieldset: VVSACR + - name: VVBPCR + description: DSI Host video VBP configuration register. + byte_offset: 88 + fieldset: VVBPCR + - name: VVFPCR + description: DSI Host video VFP configuration register. + byte_offset: 92 + fieldset: VVFPCR + - name: VVACR + description: DSI Host video VA configuration register. + byte_offset: 96 + fieldset: VVACR + - name: LCCR + description: DSI Host LTDC command configuration register. + byte_offset: 100 + fieldset: LCCR + - name: CMCR + description: DSI Host command mode configuration register. + byte_offset: 104 + fieldset: CMCR + - name: GHCR + description: DSI Host generic header configuration register. + byte_offset: 108 + fieldset: GHCR + - name: GPDR + description: DSI Host generic payload data register. + byte_offset: 112 + fieldset: GPDR + - name: GPSR + description: DSI Host generic packet status register. + byte_offset: 116 + fieldset: GPSR + - name: TCCR0 + description: DSI Host timeout counter configuration register 0. + byte_offset: 120 + fieldset: TCCR0 + - name: TCCR1 + description: DSI Host timeout counter configuration register 1. + byte_offset: 124 + fieldset: TCCR1 + - name: TCCR2 + description: DSI Host timeout counter configuration register 2. + byte_offset: 128 + fieldset: TCCR2 + - name: TCCR3 + description: DSI Host timeout counter configuration register 3. + byte_offset: 132 + fieldset: TCCR3 + - name: TCCR4 + description: DSI Host timeout counter configuration register 4. + byte_offset: 136 + fieldset: TCCR4 + - name: TCCR5 + description: DSI Host timeout counter configuration register 5. + byte_offset: 140 + fieldset: TCCR5 + - name: CLCR + description: DSI Host clock lane configuration register. + byte_offset: 148 + fieldset: CLCR + - name: CLTCR + description: DSI Host clock lane timer configuration register. + byte_offset: 152 + fieldset: CLTCR + - name: DLTCR + description: DSI Host data lane timer configuration register. + byte_offset: 156 + fieldset: DLTCR + - name: PCTLR + description: DSI Host PHY control register. + byte_offset: 160 + fieldset: PCTLR + - name: PCONFR + description: DSI Host PHY configuration register. + byte_offset: 164 + fieldset: PCONFR + - name: PUCR + description: DSI Host PHY ULPS control register. + byte_offset: 168 + fieldset: PUCR + - name: PTTCR + description: DSI Host PHY TX triggers configuration register. + byte_offset: 172 + fieldset: PTTCR + - name: PSR + description: DSI Host PHY status register. + byte_offset: 176 + fieldset: PSR + - name: ISR0 + description: DSI Host interrupt and status register 0. + byte_offset: 188 + fieldset: ISR0 + - name: ISR1 + description: DSI Host interrupt and status register 1. + byte_offset: 192 + fieldset: ISR1 + - name: IER0 + description: DSI Host interrupt enable register 0. + byte_offset: 196 + fieldset: IER0 + - name: IER1 + description: DSI Host interrupt enable register 1. + byte_offset: 200 + fieldset: IER1 + - name: FIR0 + description: DSI Host force interrupt register 0. + byte_offset: 216 + fieldset: FIR0 + - name: FIR1 + description: DSI Host force interrupt register 1. + byte_offset: 220 + fieldset: FIR1 + - name: DLTRCR + description: DSI Host data lane timer read configuration register. + byte_offset: 244 + fieldset: DLTRCR + - name: VSCR + description: DSI Host video shadow control register. + byte_offset: 256 + fieldset: VSCR + - name: LCVCIDR + description: DSI Host LTDC current VCID register. + byte_offset: 268 + fieldset: LCVCIDR + - name: LCCCR + description: DSI Host LTDC current color coding register. + byte_offset: 272 + fieldset: LCCCR + - name: LPMCCR + description: DSI Host low-power mode current configuration register. + byte_offset: 280 + fieldset: LPMCCR + - name: VMCCR + description: DSI Host video mode current configuration register. + byte_offset: 312 + fieldset: VMCCR + - name: VPCCR + description: DSI Host video packet current configuration register. + byte_offset: 316 + fieldset: VPCCR + - name: VCCCR + description: DSI Host video chunks current configuration register. + byte_offset: 320 + fieldset: VCCCR + - name: VNPCCR + description: DSI Host video null packet current configuration register. + byte_offset: 324 + fieldset: VNPCCR + - name: VHSACCR + description: DSI Host video HSA current configuration register. + byte_offset: 328 + fieldset: VHSACCR + - name: VHBPCCR + description: DSI Host video HBP current configuration register. + byte_offset: 332 + fieldset: VHBPCCR + - name: VLCCR + description: DSI Host video line current configuration register. + byte_offset: 336 + fieldset: VLCCR + - name: VVSACCR + description: DSI Host video VSA current configuration register. + byte_offset: 340 + fieldset: VVSACCR + - name: VVBPCCR + description: DSI Host video VBP current configuration register. + byte_offset: 344 + fieldset: VVBPCCR + - name: VVFPCCR + description: DSI Host video VFP current configuration register. + byte_offset: 348 + fieldset: VVFPCCR + - name: VVACCR + description: DSI Host video VA current configuration register. + byte_offset: 352 + fieldset: VVACCR + - name: FBSR + description: DSI Host FIFO and buffer status register. + byte_offset: 360 + fieldset: FBSR + - name: WCFGR + description: DSI Wrapper configuration register. + byte_offset: 1024 + fieldset: WCFGR + - name: WCR + description: DSI Wrapper control register. + byte_offset: 1028 + fieldset: WCR + - name: WIER + description: DSI Wrapper interrupt enable register. + byte_offset: 1032 + fieldset: WIER + - name: WISR + description: DSI Wrapper interrupt and status register. + byte_offset: 1036 + fieldset: WISR + - name: WIFCR + description: DSI Wrapper interrupt flag clear register. + byte_offset: 1040 + fieldset: WIFCR + - name: WPCR0 + description: DSI Wrapper PHY configuration register 0. + byte_offset: 1048 + fieldset: WPCR0 + - name: WRPCR + description: DSI Wrapper regulator and PLL control register. + byte_offset: 1072 + fieldset: WRPCR + - name: BCFGR + description: DSI bias configuration register. + byte_offset: 2056 + fieldset: BCFGR + - name: DPCBCR + description: DSI D-PHY clock band control register. + byte_offset: 3076 + fieldset: DPCBCR + - name: DPCSRCR + description: DSI D-PHY clock skew rate control register. + byte_offset: 3124 + fieldset: DPCSRCR + - name: DPDL0BCR + description: DSI D-PHY data lane 0 band control register. + byte_offset: 3184 + fieldset: DPDL0BCR + - name: DPDL0SRCR + description: DSI D-PHY data lane 0 skew rate control register. + byte_offset: 3232 + fieldset: DPDL0SRCR + - name: DPDL1BCR + description: DSI D-PHY data lane 1 band control register. + byte_offset: 3336 + fieldset: DPDL1BCR + - name: DPDL1SRCR + description: DSI D-PHY data lane 1 skew rate control register. + byte_offset: 3384 + fieldset: DPDL1SRCR +fieldset/BCFGR: + description: DSI bias configuration register. + fields: + - name: PWRUP + description: Power-up This bit powers-up the reference bias for the MIPI D-PHY. + bit_offset: 6 + bit_size: 1 +fieldset/CCR: + description: DSI Host clock control register. + fields: + - name: TXECKDIV + description: TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation. + bit_offset: 0 + bit_size: 8 + - name: TOCKDIV + description: Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error. + bit_offset: 8 + bit_size: 8 +fieldset/CLCR: + description: DSI Host clock lane configuration register. + fields: + - name: DPCC + description: D-PHY clock control This bit controls the D-PHY clock state:. + bit_offset: 0 + bit_size: 1 + - name: ACR + description: Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows. + bit_offset: 1 + bit_size: 1 +fieldset/CLTCR: + description: DSI Host clock lane timer configuration register. + fields: + - name: LP2HS_TIME + description: "Low-power to high-speed time This field configures the maximum time that the D-PHY clock lane takes to go from lowâ\x80\x91power to high-speed transmission measured in lane byte clock cycles." + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: "High-speed to low-power time This field configures the maximum time that the D-PHY clock lane takes to go from highâ\x80\x91speed to low-power transmission measured in lane byte clock cycles." + bit_offset: 16 + bit_size: 10 +fieldset/CMCR: + description: DSI Host command mode configuration register. + fields: + - name: TEARE + description: Tearing effect acknowledge request enable This bit enables the tearing effect acknowledge request:. + bit_offset: 0 + bit_size: 1 + - name: ARE + description: Acknowledge request enable This bit enables the acknowledge request after each packet transmission:. + bit_offset: 1 + bit_size: 1 + - name: GSW0TX + description: Generic short write zero parameters transmission This bit configures the generic short write packet with zero parameters command transmission type:. + bit_offset: 8 + bit_size: 1 + - name: GSW1TX + description: Generic short write one parameters transmission This bit configures the generic short write packet with one parameters command transmission type:. + bit_offset: 9 + bit_size: 1 + - name: GSW2TX + description: Generic short write two parameters transmission This bit configures the generic short write packet with two parameters command transmission type:. + bit_offset: 10 + bit_size: 1 + - name: GSR0TX + description: Generic short read zero parameters transmission This bit configures the generic short read packet with zero parameters command transmission type:. + bit_offset: 11 + bit_size: 1 + - name: GSR1TX + description: Generic short read one parameters transmission This bit configures the generic short read packet with one parameters command transmission type:. + bit_offset: 12 + bit_size: 1 + - name: GSR2TX + description: Generic short read two parameters transmission This bit configures the generic short read packet with two parameters command transmission type:. + bit_offset: 13 + bit_size: 1 + - name: GLWTX + description: Generic long write transmission This bit configures the generic long write packet command transmission type :. + bit_offset: 14 + bit_size: 1 + - name: DSW0TX + description: DCS short write zero parameter transmission This bit configures the DCS short write packet with zero parameter command transmission type:. + bit_offset: 16 + bit_size: 1 + - name: DSW1TX + description: DCS short read one parameter transmission This bit configures the DCS short read packet with one parameter command transmission type:. + bit_offset: 17 + bit_size: 1 + - name: DSR0TX + description: DCS short read zero parameter transmission This bit configures the DCS short read packet with zero parameter command transmission type:. + bit_offset: 18 + bit_size: 1 + - name: DLWTX + description: DCS long write transmission This bit configures the DCS long write packet command transmission type:. + bit_offset: 19 + bit_size: 1 + - name: MRDPS + description: Maximum read packet size This bit configures the maximum read packet size command transmission type:. + bit_offset: 24 + bit_size: 1 +fieldset/CR: + description: DSI Host control register. + fields: + - name: EN + description: Enable This bit configures the DSI Host in either power-up mode or to reset. + bit_offset: 0 + bit_size: 1 +fieldset/DLTCR: + description: DSI Host data lane timer configuration register. + fields: + - name: LP2HS_TIME + description: Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles. + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles. + bit_offset: 16 + bit_size: 10 +fieldset/DLTRCR: + description: DSI Host data lane timer read configuration register. + fields: + - name: MRD_TIME + description: Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress. + bit_offset: 0 + bit_size: 15 +fieldset/DPCBCR: + description: DSI D-PHY clock band control register. + fields: + - name: BC + description: 'Band control This field selects the frequency band used by the D-PHY. Others: Reserved.' + bit_offset: 3 + bit_size: 5 +fieldset/DPCSRCR: + description: DSI D-PHY clock skew rate control register. + fields: + - name: SRC + description: 'Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.' + bit_offset: 0 + bit_size: 8 +fieldset/DPDL0BCR: + description: DSI D-PHY data lane 0 band control register. + fields: + - name: BC + description: 'Band control This field selects the frequency band used by the D-PHY. Others: Reserved.' + bit_offset: 0 + bit_size: 5 +fieldset/DPDL0SRCR: + description: DSI D-PHY data lane 0 skew rate control register. + fields: + - name: SRC + description: 'Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.' + bit_offset: 0 + bit_size: 8 +fieldset/DPDL1BCR: + description: DSI D-PHY data lane 1 band control register. + fields: + - name: BC + description: 'Band control This field selects the frequency band used by the D-PHY. Others: Reserved.' + bit_offset: 0 + bit_size: 5 +fieldset/DPDL1SRCR: + description: DSI D-PHY data lane 1 skew rate control register. + fields: + - name: SRC + description: 'Slew rate control This field selects the slew rate for HS-TX speed. Others: Reserved.' + bit_offset: 0 + bit_size: 8 +fieldset/FBSR: + description: DSI Host FIFO and buffer status register. + fields: + - name: VCWFE + description: Video mode command write FIFO empty This bit indicates the empty status of the video mode write command FIFO:. + bit_offset: 0 + bit_size: 1 + - name: VCWFF + description: Video mode command write FIFO full This bit indicates the full status of the video mode write command FIFO:. + bit_offset: 1 + bit_size: 1 + - name: VPWFE + description: Video mode payload write FIFO empty This bit indicates the empty status of the video mode write payload FIFO:. + bit_offset: 2 + bit_size: 1 + - name: VPWFF + description: Video mode payload write FIFO full This bit indicates the full status of the video mode write payload FIFO:. + bit_offset: 3 + bit_size: 1 + - name: ACWFE + description: Adapted command mode command write FIFO empty This bit indicates the empty status of the adapted command mode write command FIFO:. + bit_offset: 4 + bit_size: 1 + - name: ACWFF + description: Adapted command mode command write FIFO full This bit indicates the full status of the adapted command mode write command FIFO:. + bit_offset: 5 + bit_size: 1 + - name: APWFE + description: Adapted command mode payload write FIFO empty This bit indicates the empty status of the adapted command mode write payload FIFO:. + bit_offset: 6 + bit_size: 1 + - name: APWFF + description: Adapted command mode payload write FIFO full This bit indicates the full status of the adapted command mode write payload FIFO:. + bit_offset: 7 + bit_size: 1 + - name: VPBE + description: Video mode payload buffer empty This bit indicates the empty status of the video mode payload internal buffer:. + bit_offset: 16 + bit_size: 1 + - name: VPBF + description: Video mode payload buffer full This bit indicates the full status of the video mode payload internal buffer:. + bit_offset: 17 + bit_size: 1 + - name: ACBE + description: Adapted command mode command buffer empty This bit indicates the empty status of the adapted command mode command internal buffer:. + bit_offset: 20 + bit_size: 1 + - name: ACBF + description: Adapted command mode command buffer full This bit indicates the full status of the adapted command mode command internal buffer:. + bit_offset: 21 + bit_size: 1 + - name: APBE + description: Adapted command mode payload buffer empty This bit indicates the empty status of the adapted command mode payload internal buffer:. + bit_offset: 22 + bit_size: 1 + - name: APBF + description: Adapted command mode payload buffer full This bit indicates the full status of the adapted command mode payload internal buffer:. + bit_offset: 23 + bit_size: 1 +fieldset/FIR0: + description: DSI Host force interrupt register 0. + fields: + - name: FAE0 + description: Force acknowledge error 0 Writing one to this bit forces an acknowledge error 0. + bit_offset: 0 + bit_size: 1 + - name: FAE1 + description: Force acknowledge error 1 Writing one to this bit forces an acknowledge error 1. + bit_offset: 1 + bit_size: 1 + - name: FAE2 + description: Force acknowledge error 2 Writing one to this bit forces an acknowledge error 2. + bit_offset: 2 + bit_size: 1 + - name: FAE3 + description: Force acknowledge error 3 Writing one to this bit forces an acknowledge error 3. + bit_offset: 3 + bit_size: 1 + - name: FAE4 + description: Force acknowledge error 4 Writing one to this bit forces an acknowledge error 4. + bit_offset: 4 + bit_size: 1 + - name: FAE5 + description: Force acknowledge error 5 Writing one to this bit forces an acknowledge error 5. + bit_offset: 5 + bit_size: 1 + - name: FAE6 + description: Force acknowledge error 6 Writing one to this bit forces an acknowledge error 6. + bit_offset: 6 + bit_size: 1 + - name: FAE7 + description: Force acknowledge error 7 Writing one to this bit forces an acknowledge error 7. + bit_offset: 7 + bit_size: 1 + - name: FAE8 + description: Force acknowledge error 8 Writing one to this bit forces an acknowledge error 8. + bit_offset: 8 + bit_size: 1 + - name: FAE9 + description: Force acknowledge error 9 Writing one to this bit forces an acknowledge error 9. + bit_offset: 9 + bit_size: 1 + - name: FAE10 + description: Force acknowledge error 10 Writing one to this bit forces an acknowledge error 10. + bit_offset: 10 + bit_size: 1 + - name: FAE11 + description: Force acknowledge error 11 Writing one to this bit forces an acknowledge error 11. + bit_offset: 11 + bit_size: 1 + - name: FAE12 + description: Force acknowledge error 12 Writing one to this bit forces an acknowledge error 12. + bit_offset: 12 + bit_size: 1 + - name: FAE13 + description: Force acknowledge error 13 Writing one to this bit forces an acknowledge error 13. + bit_offset: 13 + bit_size: 1 + - name: FAE14 + description: Force acknowledge error 14 Writing one to this bit forces an acknowledge error 14. + bit_offset: 14 + bit_size: 1 + - name: FAE15 + description: Force acknowledge error 15 Writing one to this bit forces an acknowledge error 15. + bit_offset: 15 + bit_size: 1 + - name: FPE0 + description: Force PHY error 0 Writing one to this bit forces a PHY error 0. + bit_offset: 16 + bit_size: 1 + - name: FPE1 + description: Force PHY error 1 Writing one to this bit forces a PHY error 1. + bit_offset: 17 + bit_size: 1 + - name: FPE2 + description: Force PHY error 2 Writing one to this bit forces a PHY error 2. + bit_offset: 18 + bit_size: 1 + - name: FPE3 + description: Force PHY error 3 Writing one to this bit forces a PHY error 3. + bit_offset: 19 + bit_size: 1 + - name: FPE4 + description: Force PHY error 4 Writing one to this bit forces a PHY error 4. + bit_offset: 20 + bit_size: 1 +fieldset/FIR1: + description: DSI Host force interrupt register 1. + fields: + - name: FTOHSTX + description: Force timeout high-speed transmission Writing one to this bit forces a timeout high-speed transmission. + bit_offset: 0 + bit_size: 1 + - name: FTOLPRX + description: Force timeout low-power reception Writing one to this bit forces a timeout low-power reception. + bit_offset: 1 + bit_size: 1 + - name: FECCSE + description: Force ECC single-bit error Writing one to this bit forces a ECC single-bit error. + bit_offset: 2 + bit_size: 1 + - name: FECCME + description: Force ECC multi-bit error Writing one to this bit forces a ECC multi-bit error. + bit_offset: 3 + bit_size: 1 + - name: FCRCE + description: Force CRC error Writing one to this bit forces a CRC error. + bit_offset: 4 + bit_size: 1 + - name: FPSE + description: Force packet size error Writing one to this bit forces a packet size error. + bit_offset: 5 + bit_size: 1 + - name: FEOTPE + description: Force EoTp error Writing one to this bit forces a EoTp error. + bit_offset: 6 + bit_size: 1 + - name: FLPWRE + description: Force LTDC payload write error Writing one to this bit forces a LTDC payload write error. + bit_offset: 7 + bit_size: 1 + - name: FGCWRE + description: Force generic command write error Writing one to this bit forces a generic command write error. + bit_offset: 8 + bit_size: 1 + - name: FGPWRE + description: Force generic payload write error Writing one to this bit forces a generic payload write error. + bit_offset: 9 + bit_size: 1 + - name: FGPTXE + description: Force generic payload transmit error Writing one to this bit forces a generic payload transmit error. + bit_offset: 10 + bit_size: 1 + - name: FGPRDE + description: Force generic payload read error Writing one to this bit forces a generic payload read error. + bit_offset: 11 + bit_size: 1 + - name: FGPRXE + description: Force generic payload receive error Writing one to this bit forces a generic payload receive error. + bit_offset: 12 + bit_size: 1 + - name: FPBUE + description: Force payload buffer underflow error Writing one to this bit forces a payload undrflow error. + bit_offset: 19 + bit_size: 1 +fieldset/GHCR: + description: DSI Host generic header configuration register. + fields: + - name: DT + description: Type This field configures the packet data type of the header packet. + bit_offset: 0 + bit_size: 6 + - name: VCID + description: Channel This field configures the virtual channel ID of the header packet. + bit_offset: 6 + bit_size: 2 + - name: WCLSB + description: WordCount LSB This field configures the less significant byte of the header packet word count for long packets, or data 0 for short packets. + bit_offset: 8 + bit_size: 8 + - name: WCMSB + description: WordCount MSB This field configures the most significant byte of the header packet's word count for long packets, or data 1 for short packets. + bit_offset: 16 + bit_size: 8 +fieldset/GPDR: + description: DSI Host generic payload data register. + fields: + - name: DATA1 + description: Payload byte 1 This field indicates the byte 1 of the packet payload. + bit_offset: 0 + bit_size: 8 + - name: DATA2 + description: Payload byte 2 This field indicates the byte 2 of the packet payload. + bit_offset: 8 + bit_size: 8 + - name: DATA3 + description: Payload byte 3 This field indicates the byte 3 of the packet payload. + bit_offset: 16 + bit_size: 8 + - name: DATA4 + description: Payload byte 4 This field indicates the byte 4 of the packet payload. + bit_offset: 24 + bit_size: 8 +fieldset/GPSR: + description: DSI Host generic packet status register. + fields: + - name: CMDFE + description: Command FIFO empty This bit indicates the empty status of the generic command FIFO:. + bit_offset: 0 + bit_size: 1 + - name: CMDFF + description: Command FIFO full This bit indicates the full status of the generic command FIFO:. + bit_offset: 1 + bit_size: 1 + - name: PWRFE + description: Payload write FIFO empty This bit indicates the empty status of the generic write payload FIFO:. + bit_offset: 2 + bit_size: 1 + - name: PWRFF + description: Payload write FIFO full This bit indicates the full status of the generic write payload FIFO:. + bit_offset: 3 + bit_size: 1 + - name: PRDFE + description: Payload read FIFO empty This bit indicates the empty status of the generic read payload FIFO:. + bit_offset: 4 + bit_size: 1 + - name: PRDFF + description: Payload read FIFO full This bit indicates the full status of the generic read payload FIFO:. + bit_offset: 5 + bit_size: 1 + - name: RCB + description: Read command busy This bit is set when a read command is issued and cleared when the entire response is stored in the FIFO:. + bit_offset: 6 + bit_size: 1 + - name: CMDBE + description: Command buffer empty This bit indicates the empty status of the generic payload internal buffer:. + bit_offset: 16 + bit_size: 1 + - name: CMDBF + description: Command buffer full This bit indicates the full status of the generic command internal buffer:. + bit_offset: 17 + bit_size: 1 + - name: PBE + description: Payload buffer empty This bit indicates the empty status of the generic payload internal buffer:. + bit_offset: 18 + bit_size: 1 + - name: PBF + description: Payload buffer full This bit indicates the full status of the generic payload internal buffer:. + bit_offset: 19 + bit_size: 1 +fieldset/GVCIDR: + description: DSI Host generic VCID register. + fields: + - name: VCIDRX + description: Virtual channel ID for reception This field indicates the generic interface read-back virtual channel identification. + bit_offset: 0 + bit_size: 2 + - name: VCIDTX + description: Virtual channel ID for transmission This field indicates the generic interface virtual channel identification where the generic packet is automatically generated and transmitted. + bit_offset: 16 + bit_size: 2 +fieldset/IER0: + description: DSI Host interrupt enable register 0. + fields: + - name: AE0IE + description: Acknowledge error 0 interrupt enable This bit enables the interrupt generation on acknowledge error 0. + bit_offset: 0 + bit_size: 1 + - name: AE1IE + description: Acknowledge error 1 interrupt enable This bit enables the interrupt generation on acknowledge error 1. + bit_offset: 1 + bit_size: 1 + - name: AE2IE + description: Acknowledge error 2 interrupt enable This bit enables the interrupt generation on acknowledge error 2. + bit_offset: 2 + bit_size: 1 + - name: AE3IE + description: Acknowledge error 3 interrupt enable This bit enables the interrupt generation on acknowledge error 3. + bit_offset: 3 + bit_size: 1 + - name: AE4IE + description: Acknowledge error 4 interrupt enable This bit enables the interrupt generation on acknowledge error 4. + bit_offset: 4 + bit_size: 1 + - name: AE5IE + description: Acknowledge error 5 interrupt enable This bit enables the interrupt generation on acknowledge error 5. + bit_offset: 5 + bit_size: 1 + - name: AE6IE + description: Acknowledge error 6 interrupt enable This bit enables the interrupt generation on acknowledge error 6. + bit_offset: 6 + bit_size: 1 + - name: AE7IE + description: Acknowledge error 7 interrupt enable This bit enables the interrupt generation on acknowledge error 7. + bit_offset: 7 + bit_size: 1 + - name: AE8IE + description: Acknowledge error 8 interrupt enable This bit enables the interrupt generation on acknowledge error 8. + bit_offset: 8 + bit_size: 1 + - name: AE9IE + description: Acknowledge error 9 interrupt enable This bit enables the interrupt generation on acknowledge error 9. + bit_offset: 9 + bit_size: 1 + - name: AE10IE + description: Acknowledge error 10 interrupt enable This bit enables the interrupt generation on acknowledge error 10. + bit_offset: 10 + bit_size: 1 + - name: AE11IE + description: Acknowledge error 11 interrupt enable This bit enables the interrupt generation on acknowledge error 11. + bit_offset: 11 + bit_size: 1 + - name: AE12IE + description: Acknowledge error 12 interrupt enable This bit enables the interrupt generation on acknowledge error 12. + bit_offset: 12 + bit_size: 1 + - name: AE13IE + description: Acknowledge error 13 interrupt enable This bit enables the interrupt generation on acknowledge error 13. + bit_offset: 13 + bit_size: 1 + - name: AE14IE + description: Acknowledge error 14 interrupt enable This bit enables the interrupt generation on acknowledge error 14. + bit_offset: 14 + bit_size: 1 + - name: AE15IE + description: Acknowledge error 15 interrupt enable This bit enables the interrupt generation on acknowledge error 15. + bit_offset: 15 + bit_size: 1 + - name: PE0IE + description: PHY error 0 interrupt enable This bit enables the interrupt generation on PHY error 0. + bit_offset: 16 + bit_size: 1 + - name: PE1IE + description: PHY error 1 interrupt enable This bit enables the interrupt generation on PHY error 1. + bit_offset: 17 + bit_size: 1 + - name: PE2IE + description: PHY error 2 interrupt enable This bit enables the interrupt generation on PHY error 2. + bit_offset: 18 + bit_size: 1 + - name: PE3IE + description: PHY error 3 interrupt enable This bit enables the interrupt generation on PHY error 4. + bit_offset: 19 + bit_size: 1 + - name: PE4IE + description: PHY error 4 interrupt enable This bit enables the interrupt generation on PHY error 4. + bit_offset: 20 + bit_size: 1 +fieldset/IER1: + description: DSI Host interrupt enable register 1. + fields: + - name: TOHSTXIE + description: Timeout high-speed transmission interrupt enable This bit enables the interrupt generation on timeout high-speed transmission. + bit_offset: 0 + bit_size: 1 + - name: TOLPRXIE + description: Timeout low-power reception interrupt enable This bit enables the interrupt generation on timeout low-power reception. + bit_offset: 1 + bit_size: 1 + - name: ECCSEIE + description: ECC single-bit error interrupt enable This bit enables the interrupt generation on ECC single-bit error. + bit_offset: 2 + bit_size: 1 + - name: ECCMEIE + description: ECC multi-bit error interrupt enable This bit enables the interrupt generation on ECC multi-bit error. + bit_offset: 3 + bit_size: 1 + - name: CRCEIE + description: CRC error interrupt enable This bit enables the interrupt generation on CRC error. + bit_offset: 4 + bit_size: 1 + - name: PSEIE + description: Packet size error interrupt enable This bit enables the interrupt generation on packet size error. + bit_offset: 5 + bit_size: 1 + - name: EOTPEIE + description: EoTp error interrupt enable This bit enables the interrupt generation on EoTp error. + bit_offset: 6 + bit_size: 1 + - name: LPWREIE + description: LTDC payload write error interrupt enable This bit enables the interrupt generation on LTDC payload write error. + bit_offset: 7 + bit_size: 1 + - name: GCWREIE + description: Generic command write error interrupt enable This bit enables the interrupt generation on generic command write error. + bit_offset: 8 + bit_size: 1 + - name: GPWREIE + description: Generic payload write error interrupt enable This bit enables the interrupt generation on generic payload write error. + bit_offset: 9 + bit_size: 1 + - name: GPTXEIE + description: Generic payload transmit error interrupt enable This bit enables the interrupt generation on generic payload transmit error. + bit_offset: 10 + bit_size: 1 + - name: GPRDEIE + description: Generic payload read error interrupt enable This bit enables the interrupt generation on generic payload read error. + bit_offset: 11 + bit_size: 1 + - name: GPRXEIE + description: Generic payload receive error interrupt enable This bit enables the interrupt generation on generic payload receive error. + bit_offset: 12 + bit_size: 1 + - name: PBUEIE + description: Payload buffer underflow error interrupt enable This bit enables the interrupt generation on payload buffer underflow error. + bit_offset: 19 + bit_size: 1 +fieldset/ISR0: + description: DSI Host interrupt and status register 0. + fields: + - name: AE0 + description: Acknowledge error 0 This bit retrieves the SoT error from the acknowledge error report. + bit_offset: 0 + bit_size: 1 + - name: AE1 + description: Acknowledge error 1 This bit retrieves the SoT sync error from the acknowledge error report. + bit_offset: 1 + bit_size: 1 + - name: AE2 + description: Acknowledge error 2 This bit retrieves the EoT sync error from the acknowledge error report. + bit_offset: 2 + bit_size: 1 + - name: AE3 + description: Acknowledge error 3 This bit retrieves the escape mode entry command error from the acknowledge error report. + bit_offset: 3 + bit_size: 1 + - name: AE4 + description: Acknowledge error 4 This bit retrieves the LP transmit sync error from the acknowledge error report. + bit_offset: 4 + bit_size: 1 + - name: AE5 + description: Acknowledge error 5 This bit retrieves the peripheral timeout error from the acknowledge error report. + bit_offset: 5 + bit_size: 1 + - name: AE6 + description: Acknowledge error 6 This bit retrieves the false control error from the acknowledge error report. + bit_offset: 6 + bit_size: 1 + - name: AE7 + description: Acknowledge error 7 This bit retrieves the reserved (specific to the device) from the acknowledge error report. + bit_offset: 7 + bit_size: 1 + - name: AE8 + description: Acknowledge error 8 This bit retrieves the ECC error, single-bit (detected and corrected) from the acknowledge error report. + bit_offset: 8 + bit_size: 1 + - name: AE9 + description: Acknowledge error 9 This bit retrieves the ECC error, multi-bit (detected, not corrected) from the acknowledge error report. + bit_offset: 9 + bit_size: 1 + - name: AE10 + description: Acknowledge error 10 This bit retrieves the checksum error (long packet only) from the acknowledge error report. + bit_offset: 10 + bit_size: 1 + - name: AE11 + description: Acknowledge error 11 This bit retrieves the not recognized DSI data type from the acknowledge error report. + bit_offset: 11 + bit_size: 1 + - name: AE12 + description: Acknowledge error 12 This bit retrieves the DSI VC ID Invalid from the acknowledge error report. + bit_offset: 12 + bit_size: 1 + - name: AE13 + description: Acknowledge error 13 This bit retrieves the invalid transmission length from the acknowledge error report. + bit_offset: 13 + bit_size: 1 + - name: AE14 + description: Acknowledge error 14 This bit retrieves the reserved (specific to the device) from the acknowledge error report. + bit_offset: 14 + bit_size: 1 + - name: AE15 + description: Acknowledge error 15 This bit retrieves the DSI protocol violation from the acknowledge error report. + bit_offset: 15 + bit_size: 1 + - name: PE0 + description: PHY error 0 This bit indicates the ErrEsc escape entry error from lane 0. + bit_offset: 16 + bit_size: 1 + - name: PE1 + description: PHY error 1 This bit indicates the ErrSyncEsc low-power transmission synchronization error from lane 0. + bit_offset: 17 + bit_size: 1 + - name: PE2 + description: PHY error 2 This bit indicates the ErrControl error from lane 0. + bit_offset: 18 + bit_size: 1 + - name: PE3 + description: PHY error 3 This bit indicates the LP0 contention error ErrContentionLP0 from lane 0. + bit_offset: 19 + bit_size: 1 + - name: PE4 + description: PHY error 4 This bit indicates the LP1 contention error ErrContentionLP1 from lane 0. + bit_offset: 20 + bit_size: 1 +fieldset/ISR1: + description: DSI Host interrupt and status register 1. + fields: + - name: TOHSTX + description: Timeout high-speed transmission This bit indicates that the high-speed transmission timeout counter reached the end and contention is detected. + bit_offset: 0 + bit_size: 1 + - name: TOLPRX + description: Timeout low-power reception This bit indicates that the low-power reception timeout counter reached the end and contention is detected. + bit_offset: 1 + bit_size: 1 + - name: ECCSE + description: ECC single-bit error This bit indicates that the ECC single error is detected and corrected in a received packet. + bit_offset: 2 + bit_size: 1 + - name: ECCME + description: ECC multi-bit error This bit indicates that the ECC multiple error is detected in a received packet. + bit_offset: 3 + bit_size: 1 + - name: CRCE + description: CRC error This bit indicates that the CRC error is detected in the received packet payload. + bit_offset: 4 + bit_size: 1 + - name: PSE + description: Packet size error This bit indicates that the packet size error is detected during the packet reception. + bit_offset: 5 + bit_size: 1 + - name: EOTPE + description: EoTp error This bit indicates that the EoTp packet is not received at the end of the incoming peripheral transmission. + bit_offset: 6 + bit_size: 1 + - name: LPWRE + description: LTDC payload write error This bit indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted. + bit_offset: 7 + bit_size: 1 + - name: GCWRE + description: Generic command write error This bit indicates that the system tried to write a command through the generic interface and the FIFO is full. Therefore, the command is not written. + bit_offset: 8 + bit_size: 1 + - name: GPWRE + description: Generic payload write error This bit indicates that the system tried to write a payload data through the generic interface and the FIFO is full. Therefore, the payload is not written. + bit_offset: 9 + bit_size: 1 + - name: GPTXE + description: Generic payload transmit error This bit indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent. + bit_offset: 10 + bit_size: 1 + - name: GPRDE + description: Generic payload read error This bit indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted. + bit_offset: 11 + bit_size: 1 + - name: GPRXE + description: Generic payload receive error This bit indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted. + bit_offset: 12 + bit_size: 1 + - name: PBUE + description: Payload buffer underflow error This bit indicates that underflow has occurred when reading payload to build DSI packet for video mode. + bit_offset: 19 + bit_size: 1 +fieldset/LCCCR: + description: DSI Host LTDC current color coding register. + fields: + - name: COLC + description: 'Color coding This field returns the current LTDC interface color coding. 0110-1111: reserved If LTDC interface in command mode is chosen and currently works in the command mode (CMDM=1), then 0110-1111: 24-bit.' + bit_offset: 0 + bit_size: 4 + - name: LPE + description: Loosely packed enable This bit returns the current state of the loosely packed variant to 18-bit configurations. + bit_offset: 8 + bit_size: 1 +fieldset/LCCR: + description: DSI Host LTDC command configuration register. + fields: + - name: CMDSIZE + description: Command size This field configures the maximum allowed size for an LTDC write memory command, measured in pixels. Automatic partitioning of data obtained from LTDC is permanently enabled. + bit_offset: 0 + bit_size: 16 +fieldset/LCOLCR: + description: DSI Host LTDC color coding register. + fields: + - name: COLC + description: 'Color coding This field configures the DPI color coding. Others: Reserved.' + bit_offset: 0 + bit_size: 4 + - name: LPE + description: Loosely packet enable This bit enables the loosely packed variant to 18-bit configuration. + bit_offset: 8 + bit_size: 1 +fieldset/LCVCIDR: + description: DSI Host LTDC current VCID register. + fields: + - name: VCID + description: Virtual channel ID This field returns the virtual channel ID for the LTDC interface. + bit_offset: 0 + bit_size: 2 +fieldset/LPCR: + description: DSI Host LTDC polarity configuration register. + fields: + - name: DEP + description: Data enable polarity This bit configures the polarity of data enable pin. + bit_offset: 0 + bit_size: 1 + - name: VSP + description: VSYNC polarity This bit configures the polarity of VSYNC pin. + bit_offset: 1 + bit_size: 1 + - name: HSP + description: HSYNC polarity This bit configures the polarity of HSYNC pin. + bit_offset: 2 + bit_size: 1 +fieldset/LPMCCR: + description: DSI Host low-power mode current configuration register. + fields: + - name: VLPSIZE + description: VACT largest packet size This field returns the current size, in bytes, of the largest packet that can fit in a line during VACT regions, for the transmission of commands in low-power mode. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: Largest packet size This field is returns the current size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions, for the transmission of commands in low-power mode. + bit_offset: 16 + bit_size: 8 +fieldset/LPMCR: + description: DSI Host low-power mode configuration register. + fields: + - name: VLPSIZE + description: VACT largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VACT regions. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: Largest packet size This field is used for the transmission of commands in low-power mode. It defines the size, in bytes, of the largest packet that can fit in a line during VSA, VBP and VFP regions. + bit_offset: 16 + bit_size: 8 +fieldset/LVCIDR: + description: DSI Host LTDC VCID register. + fields: + - name: VCID + description: Virtual channel ID These bits configure the virtual channel ID for the LTDC interface traffic. + bit_offset: 0 + bit_size: 2 +fieldset/MCR: + description: DSI Host mode configuration register. + fields: + - name: CMDM + description: Command mode This bit configures the DSI Host in either video or command mode. + bit_offset: 0 + bit_size: 1 +fieldset/PCONFR: + description: DSI Host PHY configuration register. + fields: + - name: NL + description: 'Number of lanes This field configures the number of active data lanes: Others: Reserved.' + bit_offset: 0 + bit_size: 2 + - name: SW_TIME + description: Stop wait time This field configures the minimum wait period to request a high-speed transmission after the Stop state. + bit_offset: 8 + bit_size: 8 +fieldset/PCR: + description: DSI Host protocol configuration register. + fields: + - name: ETTXE + description: EoTp transmission enable This bit enables the EoTP transmission. + bit_offset: 0 + bit_size: 1 + - name: ETRXE + description: EoTp reception enable This bit enables the EoTp reception. + bit_offset: 1 + bit_size: 1 + - name: BTAE + description: Bus-turn-around enable This bit enables the bus-turn-around (BTA) request. + bit_offset: 2 + bit_size: 1 + - name: ECCRXE + description: ECC reception enable This bit enables the ECC reception, error correction and reporting. + bit_offset: 3 + bit_size: 1 + - name: CRCRXE + description: CRC reception enable This bit enables the CRC reception and error reporting. + bit_offset: 4 + bit_size: 1 + - name: ETTXLPE + description: EoTp transmission in low-power enable This bit enables the EoTP transmission in low-power. + bit_offset: 5 + bit_size: 1 +fieldset/PCTLR: + description: DSI Host PHY control register. + fields: + - name: DEN + description: Digital enable When set to 0, this bit places the digital section of the D-PHY in the reset state. + bit_offset: 1 + bit_size: 1 + - name: CKE + description: Clock enable This bit enables the D-PHY clock lane module:. + bit_offset: 2 + bit_size: 1 +fieldset/PSR: + description: DSI Host PHY status register. + fields: + - name: PD + description: PHY direction This bit indicates the status of phydirection D-PHY signal. + bit_offset: 1 + bit_size: 1 + - name: PSSC + description: PHY stop state clock lane This bit indicates the status of phystopstateclklane D-PHY signal. + bit_offset: 2 + bit_size: 1 + - name: UANC + description: ULPS active not clock lane This bit indicates the status of ulpsactivenotclklane D-PHY signal. + bit_offset: 3 + bit_size: 1 + - name: PSS0 + description: PHY stop state lane 0 This bit indicates the status of phystopstate0lane D-PHY signal. + bit_offset: 4 + bit_size: 1 + - name: UAN0 + description: ULPS active not lane 1 This bit indicates the status of ulpsactivenot0lane D-PHY signal. + bit_offset: 5 + bit_size: 1 + - name: RUE0 + description: RX ULPS escape lane 0 This bit indicates the status of rxulpsesc0lane D-PHY signal. + bit_offset: 6 + bit_size: 1 + - name: PSS1 + description: PHY stop state lane 1 This bit indicates the status of phystopstate1lane D-PHY signal. + bit_offset: 7 + bit_size: 1 + - name: UAN1 + description: ULPS active not lane 1 This bit indicates the status of ulpsactivenot1lane D-PHY signal. + bit_offset: 8 + bit_size: 1 +fieldset/PTTCR: + description: DSI Host PHY TX triggers configuration register. + fields: + - name: TX_TRIG + description: Transmission trigger Escape mode transmit trigger 0-3. Only one bit of TX_TRIG is asserted at any given time. + bit_offset: 0 + bit_size: 4 +fieldset/PUCR: + description: DSI Host PHY ULPS control register. + fields: + - name: URCL + description: ULPS request on clock lane ULPS mode request on clock lane. + bit_offset: 0 + bit_size: 1 + - name: UECL + description: ULPS exit on clock lane ULPS mode exit on clock lane. + bit_offset: 1 + bit_size: 1 + - name: URDL + description: ULPS request on data lane ULPS mode request on all active data lanes. + bit_offset: 2 + bit_size: 1 + - name: UEDL + description: ULPS exit on data lane ULPS mode exit on all active data lanes. + bit_offset: 3 + bit_size: 1 +fieldset/TCCR0: + description: DSI Host timeout counter configuration register 0. + fields: + - name: LPRX_TOCNT + description: Low-power reception timeout counter This field configures the timeout counter that triggers a low-power reception timeout contention detection (measured in TOCKDIV cycles). + bit_offset: 0 + bit_size: 16 + - name: HSTX_TOCNT + description: "High-speed transmission timeout counter This field configures the timeout counter that triggers a high-speed transmission timeout contention detection (measured in TOCKDIV cycles). If using the non-burst mode and there is no enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link returns the low-power state once per frame, then configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\x89¥ the time of one FRAME data transmission * (1 + 10%) In burst mode, RGB pixel packets are time-compressed, leaving more time during a scan line. Therefore, if in burst mode and there is enough time to switch from high-speed to low-power and back in the period from one line data finishing to the next line sync start, the DSI link can return low-power mode and back in this time interval to save power. For this, configure the TOCKDIV and HSTX_TOCNT to be in accordance with: HSTX_TOCNT * lanebyteclkperiod * TOCKDIV â\x89¥ the time of one LINE data transmission * (1 + 10%)." + bit_offset: 16 + bit_size: 16 +fieldset/TCCR1: + description: DSI Host timeout counter configuration register 1. + fields: + - name: HSRD_TOCNT + description: High-speed read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a high-speed read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR2: + description: DSI Host timeout counter configuration register 2. + fields: + - name: LPRD_TOCNT + description: Low-power read timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power read operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR3: + description: DSI Host timeout counter configuration register 3. + fields: + - name: HSWR_TOCNT + description: High-speed write timeout counter This field sets a period for which the DSI Host keeps the link inactive after sending a high-speed write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + bit_offset: 0 + bit_size: 16 + - name: PM + description: 'Presp mode When set to 1, this bit ensures that the peripheral response timeout caused by HSWR_TOCNT is used only once per LTDC frame in command mode, when both the following conditions are met: dpivsync_edpiwms has risen and fallen. Packets originated from LTDC in command mode have been transmitted and its FIFO is empty again. In this scenario no non-LTDC command requests are sent to the D-PHY, even if there is traffic from generic interface ready to be sent, making it return to stop state. When it does so, PRESP_TO counter is activated and only when it finishes does the controller send any other traffic that is ready.' + bit_offset: 24 + bit_size: 1 +fieldset/TCCR4: + description: DSI Host timeout counter configuration register 4. + fields: + - name: LPWR_TOCNT + description: Low-power write timeout counter This field sets a period for which the DSI Host keeps the link still, after sending a low-power write operation. This period is measured in cycles of lanebyteclk. The counting starts when the D-PHY enters the Stop state and causes no interrupts. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR5: + description: DSI Host timeout counter configuration register 5. + fields: + - name: BTA_TOCNT + description: "Bus-turn-around timeout counter This field sets a period for which the DSI Host keeps the link still, after completing a bus-turn-around. This period is measured in cycles of lanebyteclk. The counting starts when the Dâ\x80\x91PHY enters the Stop state and causes no interrupts." + bit_offset: 0 + bit_size: 16 +fieldset/VCCCR: + description: DSI Host video chunks current configuration register. + fields: + - name: NUMC + description: Number of chunks This field returns the number of chunks being transmitted during a line period. + bit_offset: 0 + bit_size: 13 +fieldset/VCCR: + description: DSI Host video chunks configuration register. + fields: + - name: NUMC + description: Number of chunks This register configures the number of chunks to be transmitted during a line period (a chunk consists of a video packet and a null packet). If set to 0 or 1, the video line is transmitted in a single packet. If set to 1, the packet is part of a chunk, so a null packet follows it if NPSIZE > 0. Otherwise, multiple chunks are used to transmit each video line. + bit_offset: 0 + bit_size: 13 +fieldset/VHBPCCR: + description: DSI Host video HBP current configuration register. + fields: + - name: HBP + description: Horizontal back-porch duration This field returns the horizontal back-porch period in lane byte clock cycles. + bit_offset: 0 + bit_size: 12 +fieldset/VHBPCR: + description: DSI Host video HBP configuration register. + fields: + - name: HBP + description: Horizontal back-porch duration This fields configures the horizontal back-porch period in lane byte clock cycles. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACCR: + description: DSI Host video HSA current configuration register. + fields: + - name: HSA + description: Horizontal synchronism active duration This fields returns the horizontal synchronism active period in lane byte clock cycles. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACR: + description: DSI Host video HSA configuration register. + fields: + - name: HSA + description: Horizontal synchronism active duration This fields configures the horizontal synchronism active period in lane byte clock cycles. + bit_offset: 0 + bit_size: 12 +fieldset/VLCCR: + description: DSI Host video line current configuration register. + fields: + - name: HLINE + description: Horizontal line duration This field returns the current total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. + bit_offset: 0 + bit_size: 15 +fieldset/VLCR: + description: DSI Host video line configuration register. + fields: + - name: HLINE + description: Horizontal line duration This fields configures the total of the horizontal line period (HSA+HBP+HACT+HFP) counted in lane byte clock cycles. + bit_offset: 0 + bit_size: 15 +fieldset/VMCCR: + description: DSI Host video mode current configuration register. + fields: + - name: VMT + description: 'Video mode type This field returns the current video mode transmission type: 1x: Burst mode.' + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: Low-power vertical sync time enable This bit returns the current state of return to low-power inside the vertical sync time (VSA) period when timing allows. + bit_offset: 2 + bit_size: 1 + - name: LPVBPE + description: Low-power vertical back-porch enable This bit returns the current state of return to low-power inside the vertical back-porch (VBP) period when timing allows. + bit_offset: 3 + bit_size: 1 + - name: LPVFPE + description: Low-power vertical front-porch enable This bit returns the current state of return to low-power inside the vertical front-porch (VFP) period when timing allows. + bit_offset: 4 + bit_size: 1 + - name: LPVAE + description: Low-power vertical active enable This bit returns the current state of return to low-power inside the vertical active (VACT) period when timing allows. + bit_offset: 5 + bit_size: 1 + - name: LPHBPE + description: Low-power horizontal back-porch enable This bit returns the current state of return to low-power inside the horizontal back-porch (HBP) period when timing allows. + bit_offset: 6 + bit_size: 1 + - name: LPHFE + description: Low-power horizontal front-porch enable This bit returns the current state of return to low-power inside the horizontal front-porch (HFP) period when timing allows. + bit_offset: 7 + bit_size: 1 + - name: FBTAAE + description: Frame BTA acknowledge enable This bit returns the current state of request for an acknowledge response at the end of a frame. + bit_offset: 8 + bit_size: 1 + - name: LPCE + description: Low-power command enable This bit returns the current command transmission state in low-power mode. + bit_offset: 9 + bit_size: 1 +fieldset/VMCR: + description: DSI Host video mode configuration register. + fields: + - name: VMT + description: 'Video mode type This field configures the video mode transmission type : 1x: Burst mode.' + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: Low-power vertical sync active enable This bit enables to return to low-power inside the vertical sync time (VSA) period when timing allows. + bit_offset: 8 + bit_size: 1 + - name: LPVBPE + description: Low-power vertical back-porch enable This bit enables to return to low-power inside the vertical back-porch (VBP) period when timing allows. + bit_offset: 9 + bit_size: 1 + - name: LPVFPE + description: Low-power vertical front-porch enable This bit enables to return to low-power inside the vertical front-porch (VFP) period when timing allows. + bit_offset: 10 + bit_size: 1 + - name: LPVAE + description: Low-power vertical active enable This bit enables to return to low-power inside the vertical active (VACT) period when timing allows. + bit_offset: 11 + bit_size: 1 + - name: LPHBPE + description: Low-power horizontal back-porch enable This bit enables the return to low-power inside the horizontal back-porch (HBP) period when timing allows. + bit_offset: 12 + bit_size: 1 + - name: LPHFPE + description: Low-power horizontal front-porch enable This bit enables the return to low-power inside the horizontal front-porch (HFP) period when timing allows. + bit_offset: 13 + bit_size: 1 + - name: FBTAAE + description: Frame bus-turn-around acknowledge enable This bit enables the request for an acknowledge response at the end of a frame. + bit_offset: 14 + bit_size: 1 + - name: LPCE + description: Low-power command enable This bit enables the command transmission only in low-power mode. + bit_offset: 15 + bit_size: 1 + - name: PGE + description: Pattern generator enable This bit enables the video mode pattern generator. + bit_offset: 16 + bit_size: 1 + - name: PGM + description: Pattern generator mode This bit configures the pattern generator mode. + bit_offset: 20 + bit_size: 1 + - name: PGO + description: Pattern generator orientation This bit configures the color bar orientation. + bit_offset: 24 + bit_size: 1 +fieldset/VNPCCR: + description: DSI Host video null packet current configuration register. + fields: + - name: NPSIZE + description: Null packet size This field returns the number of bytes inside a null packet. + bit_offset: 0 + bit_size: 13 +fieldset/VNPCR: + description: DSI Host video null packet configuration register. + fields: + - name: NPSIZE + description: Null packet size This field configures the number of bytes inside a null packet. Setting to 0 disables the null packets. + bit_offset: 0 + bit_size: 13 +fieldset/VPCCR: + description: DSI Host video packet current configuration register. + fields: + - name: VPSIZE + description: Video packet size This field returns the number of pixels in a single video packet. + bit_offset: 0 + bit_size: 14 +fieldset/VPCR: + description: DSI Host video packet configuration register. + fields: + - name: VPSIZE + description: Video packet size This field configures the number of pixels in a single video packet. For 18-bit not loosely packed data types, this number must be a multiple of 4. For YCbCr data types, it must be a multiple of 2 as described in the DSI specification. + bit_offset: 0 + bit_size: 14 +fieldset/VR: + description: DSI Host version register. + fields: + - name: VERSION + description: Version of the DSI Host This read-only register contains the version of the DSI Host. + bit_offset: 0 + bit_size: 32 +fieldset/VSCR: + description: DSI Host video shadow control register. + fields: + - name: EN + description: Enable When set to 1, DSI Host LTDC interface receives the active configuration from the auxiliary registers. When this bit is set along with the UR bit, the auxiliary registers are automatically updated. + bit_offset: 0 + bit_size: 1 + - name: UR + description: Update register When set to 1, the LTDC registers are copied to the auxiliary registers. After copying, this bit is auto cleared. + bit_offset: 8 + bit_size: 1 +fieldset/VVACCR: + description: DSI Host video VA current configuration register. + fields: + - name: VA + description: Vertical active duration This field returns the current vertical active period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 14 +fieldset/VVACR: + description: DSI Host video VA configuration register. + fields: + - name: VA + description: Vertical active duration This fields configures the vertical active period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 14 +fieldset/VVBPCCR: + description: DSI Host video VBP current configuration register. + fields: + - name: VBP + description: Vertical back-porch duration This field returns the current vertical back-porch period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVBPCR: + description: DSI Host video VBP configuration register. + fields: + - name: VBP + description: Vertical back-porch duration This fields configures the vertical back-porch period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCCR: + description: DSI Host video VFP current configuration register. + fields: + - name: VFP + description: Vertical front-porch duration This field returns the current vertical front-porch period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCR: + description: DSI Host video VFP configuration register. + fields: + - name: VFP + description: Vertical front-porch duration This fields configures the vertical front-porch period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACCR: + description: DSI Host video VSA current configuration register. + fields: + - name: VSA + description: Vertical synchronism active duration This field returns the current vertical synchronism active period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACR: + description: DSI Host video VSA configuration register. + fields: + - name: VSA + description: Vertical synchronism active duration This fields configures the vertical synchronism active period measured in number of horizontal lines. + bit_offset: 0 + bit_size: 10 +fieldset/WCFGR: + description: DSI Wrapper configuration register. + fields: + - name: DSIM + description: DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + bit_offset: 0 + bit_size: 1 + - name: COLMUX + description: Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0). + bit_offset: 1 + bit_size: 3 + - name: TESRC + description: TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + bit_offset: 4 + bit_size: 1 + - name: TEPOL + description: TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + bit_offset: 5 + bit_size: 1 + - name: AR + description: Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (CR.EN = 0). + bit_offset: 6 + bit_size: 1 + - name: VSPOL + description: VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (WCR.DSIEN = 0 and CR.EN = 0). + bit_offset: 7 + bit_size: 1 +fieldset/WCR: + description: DSI Wrapper control register. + fields: + - name: COLM + description: Color mode This bit controls the display color mode in video mode. + bit_offset: 0 + bit_size: 1 + - name: SHTDN + description: Shutdown This bit controls the display shutdown in video mode. + bit_offset: 1 + bit_size: 1 + - name: LTDCEN + description: LTDC enable This bit enables the LTDC for a frame transfer in adapted command mode. + bit_offset: 2 + bit_size: 1 + - name: DSIEN + description: DSI enable This bit enables the DSI Wrapper. + bit_offset: 3 + bit_size: 1 +fieldset/WIER: + description: DSI Wrapper interrupt enable register. + fields: + - name: TEIE + description: Tearing effect interrupt enable This bit enables the tearing effect interrupt. + bit_offset: 0 + bit_size: 1 + - name: ERIE + description: End of refresh interrupt enable This bit enables the end of refresh interrupt. + bit_offset: 1 + bit_size: 1 + - name: PLLLIE + description: PLL lock interrupt enable This bit enables the PLL lock interrupt. + bit_offset: 9 + bit_size: 1 + - name: PLLUIE + description: PLL unlock interrupt enable This bit enables the PLL unlock interrupt. + bit_offset: 10 + bit_size: 1 +fieldset/WIFCR: + description: DSI Wrapper interrupt flag clear register. + fields: + - name: CTEIF + description: Clear tearing effect interrupt flag Write 1 clears the TEIF flag in the WSR register. + bit_offset: 0 + bit_size: 1 + - name: CERIF + description: Clear end of refresh interrupt flag Write 1 clears the ERIF flag in the WSR register. + bit_offset: 1 + bit_size: 1 + - name: CPLLLIF + description: Clear PLL lock interrupt flag Write 1 clears the PLLLIF flag in the WSR register. + bit_offset: 9 + bit_size: 1 + - name: CPLLUIF + description: Clear PLL unlock interrupt flag Write 1 clears the PLLUIF flag in the WSR register. + bit_offset: 10 + bit_size: 1 +fieldset/WISR: + description: DSI Wrapper interrupt and status register. + fields: + - name: TEIF + description: Tearing effect interrupt flag This bit is set when a tearing effect event occurs. + bit_offset: 0 + bit_size: 1 + - name: ERIF + description: End of refresh interrupt flag This bit is set when the transfer of a frame in adapted command mode is finished. + bit_offset: 1 + bit_size: 1 + - name: BUSY + description: Busy flag This bit is set when the transfer of a frame in adapted command mode is ongoing. + bit_offset: 2 + bit_size: 1 + - name: PLLLS + description: PLL lock status This bit is set when the PLL is locked and cleared when it is unlocked. + bit_offset: 8 + bit_size: 1 + - name: PLLLIF + description: PLL lock interrupt flag This bit is set when the PLL becomes locked. + bit_offset: 9 + bit_size: 1 + - name: PLLUIF + description: PLL unlock interrupt flag This bit is set when the PLL becomes unlocked. + bit_offset: 10 + bit_size: 1 +fieldset/WPCR0: + description: DSI Wrapper PHY configuration register 0. + fields: + - name: SWCL + description: Swap clock lane pins This bit swaps the pins on clock lane. + bit_offset: 6 + bit_size: 1 + - name: SWDL0 + description: Swap data lane 0 pins This bit swaps the pins on data lane 0. + bit_offset: 7 + bit_size: 1 + - name: SWDL1 + description: Swap data lane 1 pins This bit swaps the pins on clock lane. + bit_offset: 8 + bit_size: 1 + - name: FTXSMCL + description: Force in TX Stop mode the clock lane This bit forces the clock lane in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. + bit_offset: 12 + bit_size: 1 + - name: FTXSMDL + description: Force in TX Stop mode the data lanes This bit forces the data lanes in TX stop mode. It is used to initialize a lane module in transmit mode. It causes the lane module to immediately jump to transmit control mode and to begin transmitting a stop state (LP-11). It can be used to go back in TX mode after a wrong BTA sequence. + bit_offset: 13 + bit_size: 1 +fieldset/WRPCR: + description: DSI Wrapper regulator and PLL control register. + fields: + - name: PLLEN + description: PLL enable This bit enables the D-PHY PLL. + bit_offset: 0 + bit_size: 1 + - name: NDIV + description: 'PLL loop division factor This field configures the PLL loop division factor. 2: PLL loop divided by 2x2 ... 511: PLL loop divided by 511x2.' + bit_offset: 2 + bit_size: 9 + - name: IDF + description: 'PLL input division factor This field configures the PLL input division factor. 2: PLL input divided by 2 ... 511: PLL input divided by 511.' + bit_offset: 11 + bit_size: 9 + - name: ODF + description: 'PLL output division factor This field configures the PLL output division factor. 2: PLL output divided by 2 ... 511: PLL output divided by 511.' + bit_offset: 20 + bit_size: 9 diff --git a/data/registers/dsihost_v1.yaml b/data/registers/dsihost_v1.yaml new file mode 100644 index 0000000..d3a4330 --- /dev/null +++ b/data/registers/dsihost_v1.yaml @@ -0,0 +1,1741 @@ +block/DSIHOST: + description: DSI Host. + items: + - name: VR + description: DSI Host Version Register. + byte_offset: 0 + access: Read + fieldset: VR + - name: CR + description: DSI Host Control Register. + byte_offset: 4 + fieldset: CR + - name: CCR + description: DSI HOST Clock Control Register. + byte_offset: 8 + fieldset: CCR + - name: LVCIDR + description: DSI Host LTDC VCID Register. + byte_offset: 12 + fieldset: LVCIDR + - name: LCOLCR + description: DSI Host LTDC Color Coding Register. + byte_offset: 16 + fieldset: LCOLCR + - name: LPCR + description: DSI Host LTDC Polarity Configuration Register. + byte_offset: 20 + fieldset: LPCR + - name: LPMCR + description: DSI Host Low-Power mode Configuration Register. + byte_offset: 24 + fieldset: LPMCR + - name: PCR + description: DSI Host Protocol Configuration Register. + byte_offset: 44 + fieldset: PCR + - name: GVCIDR + description: DSI Host Generic VCID Register. + byte_offset: 48 + fieldset: GVCIDR + - name: MCR + description: DSI Host mode Configuration Register. + byte_offset: 52 + fieldset: MCR + - name: VMCR + description: DSI Host Video mode Configuration Register. + byte_offset: 56 + fieldset: VMCR + - name: VPCR + description: DSI Host Video Packet Configuration Register. + byte_offset: 60 + fieldset: VPCR + - name: VCCR + description: DSI Host Video Chunks Configuration Register. + byte_offset: 64 + fieldset: VCCR + - name: VNPCR + description: DSI Host Video Null Packet Configuration Register. + byte_offset: 68 + fieldset: VNPCR + - name: VHSACR + description: DSI Host Video HSA Configuration Register. + byte_offset: 72 + fieldset: VHSACR + - name: VHBPCR + description: DSI Host Video HBP Configuration Register. + byte_offset: 76 + fieldset: VHBPCR + - name: VLCR + description: DSI Host Video Line Configuration Register. + byte_offset: 80 + fieldset: VLCR + - name: VVSACR + description: DSI Host Video VSA Configuration Register. + byte_offset: 84 + fieldset: VVSACR + - name: VVBPCR + description: DSI Host Video VBP Configuration Register. + byte_offset: 88 + fieldset: VVBPCR + - name: VVFPCR + description: DSI Host Video VFP Configuration Register. + byte_offset: 92 + fieldset: VVFPCR + - name: VVACR + description: DSI Host Video VA Configuration Register. + byte_offset: 96 + fieldset: VVACR + - name: LCCR + description: DSI Host LTDC Command Configuration Register. + byte_offset: 100 + fieldset: LCCR + - name: CMCR + description: DSI Host Command mode Configuration Register. + byte_offset: 104 + fieldset: CMCR + - name: GHCR + description: DSI Host Generic Header Configuration Register. + byte_offset: 108 + fieldset: GHCR + - name: GPDR + description: DSI Host Generic Payload Data Register. + byte_offset: 112 + fieldset: GPDR + - name: GPSR + description: DSI Host Generic Packet Status Register. + byte_offset: 116 + access: Read + fieldset: GPSR + - name: TCCR0 + description: DSI Host Timeout Counter Configuration Register 0. + byte_offset: 120 + fieldset: TCCR0 + - name: TCCR1 + description: DSI Host Timeout Counter Configuration Register 1. + byte_offset: 124 + fieldset: TCCR1 + - name: TCCR2 + description: DSI Host Timeout Counter Configuration Register 2. + byte_offset: 128 + fieldset: TCCR2 + - name: TCCR3 + description: DSI Host Timeout Counter Configuration Register 3. + byte_offset: 132 + fieldset: TCCR3 + - name: TCCR4 + description: DSI Host Timeout Counter Configuration Register 4. + byte_offset: 136 + fieldset: TCCR4 + - name: TCCR5 + description: DSI Host Timeout Counter Configuration Register 5. + byte_offset: 140 + fieldset: TCCR5 + - name: CLCR + description: DSI Host Clock Lane Configuration Register. + byte_offset: 148 + fieldset: CLCR + - name: CLTCR + description: DSI Host Clock Lane Timer Configuration Register. + byte_offset: 152 + fieldset: CLTCR + - name: DLTCR + description: DSI Host Data Lane Timer Configuration Register. + byte_offset: 156 + fieldset: DLTCR + - name: PCTLR + description: DSI Host PHY Control Register. + byte_offset: 160 + fieldset: PCTLR + - name: PCONFR + description: DSI Host PHY Configuration Register. + byte_offset: 164 + fieldset: PCONFR + - name: PUCR + description: DSI Host PHY ULPS Control Register. + byte_offset: 168 + fieldset: PUCR + - name: PTTCR + description: DSI Host PHY TX Triggers Configuration Register. + byte_offset: 172 + fieldset: PTTCR + - name: PSR + description: DSI Host PHY Status Register. + byte_offset: 176 + access: Read + fieldset: PSR + - name: ISR0 + description: DSI Host Interrupt & Status Register 0. + byte_offset: 188 + access: Read + fieldset: ISR0 + - name: ISR1 + description: DSI Host Interrupt & Status Register 1. + byte_offset: 192 + access: Read + fieldset: ISR1 + - name: IER0 + description: DSI Host Interrupt Enable Register 0. + byte_offset: 196 + fieldset: IER0 + - name: IER1 + description: DSI Host Interrupt Enable Register 1. + byte_offset: 200 + fieldset: IER1 + - name: FIR0 + description: DSI Host Force Interrupt Register 0. + byte_offset: 216 + access: Write + fieldset: FIR0 + - name: FIR1 + description: DSI Host Force Interrupt Register 1. + byte_offset: 220 + access: Write + fieldset: FIR1 + - name: VSCR + description: DSI Host Video Shadow Control Register. + byte_offset: 256 + fieldset: VSCR + - name: LCVCIDR + description: DSI Host LTDC Current VCID Register. + byte_offset: 268 + access: Read + fieldset: LCVCIDR + - name: LCCCR + description: DSI Host LTDC Current Color Coding Register. + byte_offset: 272 + access: Read + fieldset: LCCCR + - name: LPMCCR + description: DSI Host Low-Power mode Current Configuration Register. + byte_offset: 280 + access: Read + fieldset: LPMCCR + - name: VMCCR + description: DSI Host Video mode Current Configuration Register. + byte_offset: 312 + access: Read + fieldset: VMCCR + - name: VPCCR + description: DSI Host Video Packet Current Configuration Register. + byte_offset: 316 + access: Read + fieldset: VPCCR + - name: VCCCR + description: DSI Host Video Chunks Current Configuration Register. + byte_offset: 320 + access: Read + fieldset: VCCCR + - name: VNPCCR + description: DSI Host Video Null Packet Current Configuration Register. + byte_offset: 324 + access: Read + fieldset: VNPCCR + - name: VHSACCR + description: DSI Host Video HSA Current Configuration Register. + byte_offset: 328 + access: Read + fieldset: VHSACCR + - name: VHBPCCR + description: DSI Host Video HBP Current Configuration Register. + byte_offset: 332 + access: Read + fieldset: VHBPCCR + - name: VLCCR + description: DSI Host Video Line Current Configuration Register. + byte_offset: 336 + access: Read + fieldset: VLCCR + - name: VVSACCR + description: DSI Host Video VSA Current Configuration Register. + byte_offset: 340 + access: Read + fieldset: VVSACCR + - name: VVBPCCR + description: DSI Host Video VBP Current Configuration Register. + byte_offset: 344 + access: Read + fieldset: VVBPCCR + - name: VVFPCCR + description: DSI Host Video VFP Current Configuration Register. + byte_offset: 348 + access: Read + fieldset: VVFPCCR + - name: VVACCR + description: DSI Host Video VA Current Configuration Register. + byte_offset: 352 + access: Read + fieldset: VVACCR + - name: WCFGR + description: DSI Wrapper Configuration Register. + byte_offset: 1024 + fieldset: WCFGR + - name: WCR + description: DSI Wrapper Control Register. + byte_offset: 1028 + fieldset: WCR + - name: WIER + description: DSI Wrapper Interrupt Enable Register. + byte_offset: 1032 + fieldset: WIER + - name: WISR + description: DSI Wrapper Interrupt & Status Register. + byte_offset: 1036 + access: Read + fieldset: WISR + - name: WIFCR + description: DSI Wrapper Interrupt Flag Clear Register. + byte_offset: 1040 + fieldset: WIFCR + - name: WPCR0 + description: DSI Wrapper PHY Configuration Register 0. + byte_offset: 1048 + fieldset: WPCR0 + - name: WPCR1 + description: DSI Wrapper PHY Configuration Register 1. + byte_offset: 1052 + fieldset: WPCR1 + - name: WPCR2 + description: DSI Wrapper PHY Configuration Register 2. + byte_offset: 1056 + fieldset: WPCR2 + - name: WPCR3 + description: DSI Wrapper PHY Configuration Register 3. + byte_offset: 1060 + fieldset: WPCR3 + - name: WPCR4 + description: DSI Wrapper PHY Configuration Register 4. + byte_offset: 1064 + fieldset: WPCR4 + - name: WRPCR + description: DSI Wrapper Regulator and PLL Control Register. + byte_offset: 1072 + fieldset: WRPCR +fieldset/CCR: + description: DSI HOST Clock Control Register. + fields: + - name: TXECKDIV + description: TX Escape Clock Division. + bit_offset: 0 + bit_size: 8 + - name: TOCKDIV + description: Timeout Clock Division. + bit_offset: 8 + bit_size: 8 +fieldset/CLCR: + description: DSI Host Clock Lane Configuration Register. + fields: + - name: DPCC + description: D-PHY Clock Control. + bit_offset: 0 + bit_size: 1 + - name: ACR + description: Automatic Clock lane Control. + bit_offset: 1 + bit_size: 1 +fieldset/CLTCR: + description: DSI Host Clock Lane Timer Configuration Register. + fields: + - name: LP2HS_TIME + description: Low-Power to High-Speed Time. + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: High-Speed to Low-Power Time. + bit_offset: 16 + bit_size: 10 +fieldset/CMCR: + description: DSI Host Command mode Configuration Register. + fields: + - name: TEARE + description: Tearing Effect Acknowledge Request Enable. + bit_offset: 0 + bit_size: 1 + - name: ARE + description: Acknowledge Request Enable. + bit_offset: 1 + bit_size: 1 + - name: GSW0TX + description: Generic Short Write Zero parameters Transmission. + bit_offset: 8 + bit_size: 1 + - name: GSW1TX + description: Generic Short Write One parameters Transmission. + bit_offset: 9 + bit_size: 1 + - name: GSW2TX + description: Generic Short Write Two parameters Transmission. + bit_offset: 10 + bit_size: 1 + - name: GSR0TX + description: Generic Short Read Zero parameters Transmission. + bit_offset: 11 + bit_size: 1 + - name: GSR1TX + description: Generic Short Read One parameters Transmission. + bit_offset: 12 + bit_size: 1 + - name: GSR2TX + description: Generic Short Read Two parameters Transmission. + bit_offset: 13 + bit_size: 1 + - name: GLWTX + description: Generic Long Write Transmission. + bit_offset: 14 + bit_size: 1 + - name: DSW0TX + description: DCS Short Write Zero parameter Transmission. + bit_offset: 16 + bit_size: 1 + - name: DSW1TX + description: DCS Short Read One parameter Transmission. + bit_offset: 17 + bit_size: 1 + - name: DSR0TX + description: DCS Short Read Zero parameter Transmission. + bit_offset: 18 + bit_size: 1 + - name: DLWTX + description: DCS Long Write Transmission. + bit_offset: 19 + bit_size: 1 + - name: MRDPS + description: Maximum Read Packet Size. + bit_offset: 24 + bit_size: 1 +fieldset/CR: + description: DSI Host Control Register. + fields: + - name: EN + description: Enable. + bit_offset: 0 + bit_size: 1 +fieldset/DLTCR: + description: DSI Host Data Lane Timer Configuration Register. + fields: + - name: MRD_TIME + description: Maximum Read Time. + bit_offset: 0 + bit_size: 15 + - name: LP2HS_TIME + description: Low-Power To High-Speed Time. + bit_offset: 16 + bit_size: 8 + - name: HS2LP_TIME + description: High-Speed To Low-Power Time. + bit_offset: 24 + bit_size: 8 +fieldset/FIR0: + description: DSI Host Force Interrupt Register 0. + fields: + - name: FAE0 + description: Force Acknowledge Error 0. + bit_offset: 0 + bit_size: 1 + - name: FAE1 + description: Force Acknowledge Error 1. + bit_offset: 1 + bit_size: 1 + - name: FAE2 + description: Force Acknowledge Error 2. + bit_offset: 2 + bit_size: 1 + - name: FAE3 + description: Force Acknowledge Error 3. + bit_offset: 3 + bit_size: 1 + - name: FAE4 + description: Force Acknowledge Error 4. + bit_offset: 4 + bit_size: 1 + - name: FAE5 + description: Force Acknowledge Error 5. + bit_offset: 5 + bit_size: 1 + - name: FAE6 + description: Force Acknowledge Error 6. + bit_offset: 6 + bit_size: 1 + - name: FAE7 + description: Force Acknowledge Error 7. + bit_offset: 7 + bit_size: 1 + - name: FAE8 + description: Force Acknowledge Error 8. + bit_offset: 8 + bit_size: 1 + - name: FAE9 + description: Force Acknowledge Error 9. + bit_offset: 9 + bit_size: 1 + - name: FAE10 + description: Force Acknowledge Error 10. + bit_offset: 10 + bit_size: 1 + - name: FAE11 + description: Force Acknowledge Error 11. + bit_offset: 11 + bit_size: 1 + - name: FAE12 + description: Force Acknowledge Error 12. + bit_offset: 12 + bit_size: 1 + - name: FAE13 + description: Force Acknowledge Error 13. + bit_offset: 13 + bit_size: 1 + - name: FAE14 + description: Force Acknowledge Error 14. + bit_offset: 14 + bit_size: 1 + - name: FAE15 + description: Force Acknowledge Error 15. + bit_offset: 15 + bit_size: 1 + - name: FPE0 + description: Force PHY Error 0. + bit_offset: 16 + bit_size: 1 + - name: FPE1 + description: Force PHY Error 1. + bit_offset: 17 + bit_size: 1 + - name: FPE2 + description: Force PHY Error 2. + bit_offset: 18 + bit_size: 1 + - name: FPE3 + description: Force PHY Error 3. + bit_offset: 19 + bit_size: 1 + - name: FPE4 + description: Force PHY Error 4. + bit_offset: 20 + bit_size: 1 +fieldset/FIR1: + description: DSI Host Force Interrupt Register 1. + fields: + - name: FTOHSTX + description: Force Timeout High-Speed Transmission. + bit_offset: 0 + bit_size: 1 + - name: FTOLPRX + description: Force Timeout Low-Power Reception. + bit_offset: 1 + bit_size: 1 + - name: FECCSE + description: Force ECC Single-bit Error. + bit_offset: 2 + bit_size: 1 + - name: FECCME + description: Force ECC Multi-bit Error. + bit_offset: 3 + bit_size: 1 + - name: FCRCE + description: Force CRC Error. + bit_offset: 4 + bit_size: 1 + - name: FPSE + description: Force Packet Size Error. + bit_offset: 5 + bit_size: 1 + - name: FEOTPE + description: Force EoTp Error. + bit_offset: 6 + bit_size: 1 + - name: FLPWRE + description: Force LTDC Payload Write Error. + bit_offset: 7 + bit_size: 1 + - name: FGCWRE + description: Force Generic Command Write Error. + bit_offset: 8 + bit_size: 1 + - name: FGPWRE + description: Force Generic Payload Write Error. + bit_offset: 9 + bit_size: 1 + - name: FGPTXE + description: Force Generic Payload Transmit Error. + bit_offset: 10 + bit_size: 1 + - name: FGPRDE + description: Force Generic Payload Read Error. + bit_offset: 11 + bit_size: 1 + - name: FGPRXE + description: Force Generic Payload Receive Error. + bit_offset: 12 + bit_size: 1 +fieldset/GHCR: + description: DSI Host Generic Header Configuration Register. + fields: + - name: DT + description: Type. + bit_offset: 0 + bit_size: 6 + - name: VCID + description: Channel. + bit_offset: 6 + bit_size: 2 + - name: WCLSB + description: WordCount LSB. + bit_offset: 8 + bit_size: 8 + - name: WCMSB + description: WordCount MSB. + bit_offset: 16 + bit_size: 8 +fieldset/GPDR: + description: DSI Host Generic Payload Data Register. + fields: + - name: DATA1 + description: Payload Byte 1. + bit_offset: 0 + bit_size: 8 + - name: DATA2 + description: Payload Byte 2. + bit_offset: 8 + bit_size: 8 + - name: DATA3 + description: Payload Byte 3. + bit_offset: 16 + bit_size: 8 + - name: DATA4 + description: Payload Byte 4. + bit_offset: 24 + bit_size: 8 +fieldset/GPSR: + description: DSI Host Generic Packet Status Register. + fields: + - name: CMDFE + description: Command FIFO Empty. + bit_offset: 0 + bit_size: 1 + - name: CMDFF + description: Command FIFO Full. + bit_offset: 1 + bit_size: 1 + - name: PWRFE + description: Payload Write FIFO Empty. + bit_offset: 2 + bit_size: 1 + - name: PWRFF + description: Payload Write FIFO Full. + bit_offset: 3 + bit_size: 1 + - name: PRDFE + description: Payload Read FIFO Empty. + bit_offset: 4 + bit_size: 1 + - name: PRDFF + description: Payload Read FIFO Full. + bit_offset: 5 + bit_size: 1 + - name: RCB + description: Read Command Busy. + bit_offset: 6 + bit_size: 1 +fieldset/GVCIDR: + description: DSI Host Generic VCID Register. + fields: + - name: VCID + description: Virtual Channel ID. + bit_offset: 0 + bit_size: 2 +fieldset/IER0: + description: DSI Host Interrupt Enable Register 0. + fields: + - name: AE0IE + description: Acknowledge Error 0 Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: AE1IE + description: Acknowledge Error 1 Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: AE2IE + description: Acknowledge Error 2 Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: AE3IE + description: Acknowledge Error 3 Interrupt Enable. + bit_offset: 3 + bit_size: 1 + - name: AE4IE + description: Acknowledge Error 4 Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: AE5IE + description: Acknowledge Error 5 Interrupt Enable. + bit_offset: 5 + bit_size: 1 + - name: AE6IE + description: Acknowledge Error 6 Interrupt Enable. + bit_offset: 6 + bit_size: 1 + - name: AE7IE + description: Acknowledge Error 7 Interrupt Enable. + bit_offset: 7 + bit_size: 1 + - name: AE8IE + description: Acknowledge Error 8 Interrupt Enable. + bit_offset: 8 + bit_size: 1 + - name: AE9IE + description: Acknowledge Error 9 Interrupt Enable. + bit_offset: 9 + bit_size: 1 + - name: AE10IE + description: Acknowledge Error 10 Interrupt Enable. + bit_offset: 10 + bit_size: 1 + - name: AE11IE + description: Acknowledge Error 11 Interrupt Enable. + bit_offset: 11 + bit_size: 1 + - name: AE12IE + description: Acknowledge Error 12 Interrupt Enable. + bit_offset: 12 + bit_size: 1 + - name: AE13IE + description: Acknowledge Error 13 Interrupt Enable. + bit_offset: 13 + bit_size: 1 + - name: AE14IE + description: Acknowledge Error 14 Interrupt Enable. + bit_offset: 14 + bit_size: 1 + - name: AE15IE + description: Acknowledge Error 15 Interrupt Enable. + bit_offset: 15 + bit_size: 1 + - name: PE0IE + description: PHY Error 0 Interrupt Enable. + bit_offset: 16 + bit_size: 1 + - name: PE1IE + description: PHY Error 1 Interrupt Enable. + bit_offset: 17 + bit_size: 1 + - name: PE2IE + description: PHY Error 2 Interrupt Enable. + bit_offset: 18 + bit_size: 1 + - name: PE3IE + description: PHY Error 3 Interrupt Enable. + bit_offset: 19 + bit_size: 1 + - name: PE4IE + description: PHY Error 4 Interrupt Enable. + bit_offset: 20 + bit_size: 1 +fieldset/IER1: + description: DSI Host Interrupt Enable Register 1. + fields: + - name: TOHSTXIE + description: Timeout High-Speed Transmission Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: TOLPRXIE + description: Timeout Low-Power Reception Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: ECCSEIE + description: ECC Single-bit Error Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: ECCMEIE + description: ECC Multi-bit Error Interrupt Enable. + bit_offset: 3 + bit_size: 1 + - name: CRCEIE + description: CRC Error Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: PSEIE + description: Packet Size Error Interrupt Enable. + bit_offset: 5 + bit_size: 1 + - name: EOTPEIE + description: EoTp Error Interrupt Enable. + bit_offset: 6 + bit_size: 1 + - name: LPWREIE + description: LTDC Payload Write Error Interrupt Enable. + bit_offset: 7 + bit_size: 1 + - name: GCWREIE + description: Generic Command Write Error Interrupt Enable. + bit_offset: 8 + bit_size: 1 + - name: GPWREIE + description: Generic Payload Write Error Interrupt Enable. + bit_offset: 9 + bit_size: 1 + - name: GPTXEIE + description: Generic Payload Transmit Error Interrupt Enable. + bit_offset: 10 + bit_size: 1 + - name: GPRDEIE + description: Generic Payload Read Error Interrupt Enable. + bit_offset: 11 + bit_size: 1 + - name: GPRXEIE + description: Generic Payload Receive Error Interrupt Enable. + bit_offset: 12 + bit_size: 1 +fieldset/ISR0: + description: DSI Host Interrupt & Status Register 0. + fields: + - name: AE0 + description: Acknowledge Error 0. + bit_offset: 0 + bit_size: 1 + - name: AE1 + description: Acknowledge Error 1. + bit_offset: 1 + bit_size: 1 + - name: AE2 + description: Acknowledge Error 2. + bit_offset: 2 + bit_size: 1 + - name: AE3 + description: Acknowledge Error 3. + bit_offset: 3 + bit_size: 1 + - name: AE4 + description: Acknowledge Error 4. + bit_offset: 4 + bit_size: 1 + - name: AE5 + description: Acknowledge Error 5. + bit_offset: 5 + bit_size: 1 + - name: AE6 + description: Acknowledge Error 6. + bit_offset: 6 + bit_size: 1 + - name: AE7 + description: Acknowledge Error 7. + bit_offset: 7 + bit_size: 1 + - name: AE8 + description: Acknowledge Error 8. + bit_offset: 8 + bit_size: 1 + - name: AE9 + description: Acknowledge Error 9. + bit_offset: 9 + bit_size: 1 + - name: AE10 + description: Acknowledge Error 10. + bit_offset: 10 + bit_size: 1 + - name: AE11 + description: Acknowledge Error 11. + bit_offset: 11 + bit_size: 1 + - name: AE12 + description: Acknowledge Error 12. + bit_offset: 12 + bit_size: 1 + - name: AE13 + description: Acknowledge Error 13. + bit_offset: 13 + bit_size: 1 + - name: AE14 + description: Acknowledge Error 14. + bit_offset: 14 + bit_size: 1 + - name: AE15 + description: Acknowledge Error 15. + bit_offset: 15 + bit_size: 1 + - name: PE0 + description: PHY Error 0. + bit_offset: 16 + bit_size: 1 + - name: PE1 + description: PHY Error 1. + bit_offset: 17 + bit_size: 1 + - name: PE2 + description: PHY Error 2. + bit_offset: 18 + bit_size: 1 + - name: PE3 + description: PHY Error 3. + bit_offset: 19 + bit_size: 1 + - name: PE4 + description: PHY Error 4. + bit_offset: 20 + bit_size: 1 +fieldset/ISR1: + description: DSI Host Interrupt & Status Register 1. + fields: + - name: TOHSTX + description: Timeout High-Speed Transmission. + bit_offset: 0 + bit_size: 1 + - name: TOLPRX + description: Timeout Low-Power Reception. + bit_offset: 1 + bit_size: 1 + - name: ECCSE + description: ECC Single-bit Error. + bit_offset: 2 + bit_size: 1 + - name: ECCME + description: ECC Multi-bit Error. + bit_offset: 3 + bit_size: 1 + - name: CRCE + description: CRC Error. + bit_offset: 4 + bit_size: 1 + - name: PSE + description: Packet Size Error. + bit_offset: 5 + bit_size: 1 + - name: EOTPE + description: EoTp Error. + bit_offset: 6 + bit_size: 1 + - name: LPWRE + description: LTDC Payload Write Error. + bit_offset: 7 + bit_size: 1 + - name: GCWRE + description: Generic Command Write Error. + bit_offset: 8 + bit_size: 1 + - name: GPWRE + description: Generic Payload Write Error. + bit_offset: 9 + bit_size: 1 + - name: GPTXE + description: Generic Payload Transmit Error. + bit_offset: 10 + bit_size: 1 + - name: GPRDE + description: Generic Payload Read Error. + bit_offset: 11 + bit_size: 1 + - name: GPRXE + description: Generic Payload Receive Error. + bit_offset: 12 + bit_size: 1 +fieldset/LCCCR: + description: DSI Host LTDC Current Color Coding Register. + fields: + - name: COLC + description: Color Coding. + bit_offset: 0 + bit_size: 4 + - name: LPE + description: Loosely Packed Enable. + bit_offset: 8 + bit_size: 1 +fieldset/LCCR: + description: DSI Host LTDC Command Configuration Register. + fields: + - name: CMDSIZE + description: Command Size. + bit_offset: 0 + bit_size: 16 +fieldset/LCOLCR: + description: DSI Host LTDC Color Coding Register. + fields: + - name: COLC + description: Color Coding. + bit_offset: 0 + bit_size: 4 + - name: LPE + description: Loosely Packet Enable. + bit_offset: 8 + bit_size: 1 +fieldset/LCVCIDR: + description: DSI Host LTDC Current VCID Register. + fields: + - name: VCID + description: Virtual Channel ID. + bit_offset: 0 + bit_size: 2 +fieldset/LPCR: + description: DSI Host LTDC Polarity Configuration Register. + fields: + - name: DEP + description: Data Enable Polarity. + bit_offset: 0 + bit_size: 1 + - name: VSP + description: VSYNC Polarity. + bit_offset: 1 + bit_size: 1 + - name: HSP + description: HSYNC Polarity. + bit_offset: 2 + bit_size: 1 +fieldset/LPMCCR: + description: DSI Host Low-Power mode Current Configuration Register. + fields: + - name: VLPSIZE + description: VACT Largest Packet Size. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: Largest Packet Size. + bit_offset: 16 + bit_size: 8 +fieldset/LPMCR: + description: DSI Host Low-Power mode Configuration Register. + fields: + - name: VLPSIZE + description: VACT Largest Packet Size. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: Largest Packet Size. + bit_offset: 16 + bit_size: 8 +fieldset/LVCIDR: + description: DSI Host LTDC VCID Register. + fields: + - name: VCID + description: Virtual Channel ID. + bit_offset: 0 + bit_size: 2 +fieldset/MCR: + description: DSI Host mode Configuration Register. + fields: + - name: CMDM + description: Command mode. + bit_offset: 0 + bit_size: 1 +fieldset/PCONFR: + description: DSI Host PHY Configuration Register. + fields: + - name: NL + description: Number of Lanes. + bit_offset: 0 + bit_size: 2 + - name: SW_TIME + description: Stop Wait Time. + bit_offset: 8 + bit_size: 8 +fieldset/PCR: + description: DSI Host Protocol Configuration Register. + fields: + - name: ETTXE + description: EoTp Transmission Enable. + bit_offset: 0 + bit_size: 1 + - name: ETRXE + description: EoTp Reception Enable. + bit_offset: 1 + bit_size: 1 + - name: BTAE + description: Bus Turn Around Enable. + bit_offset: 2 + bit_size: 1 + - name: ECCRXE + description: ECC Reception Enable. + bit_offset: 3 + bit_size: 1 + - name: CRCRXE + description: CRC Reception Enable. + bit_offset: 4 + bit_size: 1 +fieldset/PCTLR: + description: DSI Host PHY Control Register. + fields: + - name: DEN + description: Digital Enable. + bit_offset: 1 + bit_size: 1 + - name: CKE + description: Clock Enable. + bit_offset: 2 + bit_size: 1 +fieldset/PSR: + description: DSI Host PHY Status Register. + fields: + - name: PD + description: PHY Direction. + bit_offset: 1 + bit_size: 1 + - name: PSSC + description: PHY Stop State Clock lane. + bit_offset: 2 + bit_size: 1 + - name: UANC + description: ULPS Active Not Clock lane. + bit_offset: 3 + bit_size: 1 + - name: PSS0 + description: PHY Stop State lane 0. + bit_offset: 4 + bit_size: 1 + - name: UAN0 + description: ULPS Active Not lane 1. + bit_offset: 5 + bit_size: 1 + - name: RUE0 + description: RX ULPS Escape lane 0. + bit_offset: 6 + bit_size: 1 + - name: PSS1 + description: PHY Stop State lane 1. + bit_offset: 7 + bit_size: 1 + - name: UAN1 + description: ULPS Active Not lane 1. + bit_offset: 8 + bit_size: 1 +fieldset/PTTCR: + description: DSI Host PHY TX Triggers Configuration Register. + fields: + - name: TX_TRIG + description: Transmission Trigger. + bit_offset: 0 + bit_size: 4 +fieldset/PUCR: + description: DSI Host PHY ULPS Control Register. + fields: + - name: URCL + description: ULPS Request on Clock Lane. + bit_offset: 0 + bit_size: 1 + - name: UECL + description: ULPS Exit on Clock Lane. + bit_offset: 1 + bit_size: 1 + - name: URDL + description: ULPS Request on Data Lane. + bit_offset: 2 + bit_size: 1 + - name: UEDL + description: ULPS Exit on Data Lane. + bit_offset: 3 + bit_size: 1 +fieldset/TCCR0: + description: DSI Host Timeout Counter Configuration Register 0. + fields: + - name: LPRX_TOCNT + description: Low-power Reception Timeout Counter. + bit_offset: 0 + bit_size: 16 + - name: HSTX_TOCNT + description: High-Speed Transmission Timeout Counter. + bit_offset: 16 + bit_size: 16 +fieldset/TCCR1: + description: DSI Host Timeout Counter Configuration Register 1. + fields: + - name: HSRD_TOCNT + description: High-Speed Read Timeout Counter. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR2: + description: DSI Host Timeout Counter Configuration Register 2. + fields: + - name: LPRD_TOCNT + description: Low-Power Read Timeout Counter. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR3: + description: DSI Host Timeout Counter Configuration Register 3. + fields: + - name: HSWR_TOCNT + description: High-Speed Write Timeout Counter. + bit_offset: 0 + bit_size: 16 + - name: PM + description: Presp mode. + bit_offset: 24 + bit_size: 1 +fieldset/TCCR4: + description: DSI Host Timeout Counter Configuration Register 4. + fields: + - name: LSWR_TOCNT + description: Low-Power Write Timeout Counter. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR5: + description: DSI Host Timeout Counter Configuration Register 5. + fields: + - name: BTA_TOCNT + description: Bus-Turn-Around Timeout Counter. + bit_offset: 0 + bit_size: 16 +fieldset/VCCCR: + description: DSI Host Video Chunks Current Configuration Register. + fields: + - name: NUMC + description: Number of Chunks. + bit_offset: 0 + bit_size: 13 +fieldset/VCCR: + description: DSI Host Video Chunks Configuration Register. + fields: + - name: NUMC + description: Number of Chunks. + bit_offset: 0 + bit_size: 13 +fieldset/VHBPCCR: + description: DSI Host Video HBP Current Configuration Register. + fields: + - name: HBP + description: Horizontal Back-Porch duration. + bit_offset: 0 + bit_size: 12 +fieldset/VHBPCR: + description: DSI Host Video HBP Configuration Register. + fields: + - name: HBP + description: Horizontal Back-Porch duration. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACCR: + description: DSI Host Video HSA Current Configuration Register. + fields: + - name: HSA + description: Horizontal Synchronism Active duration. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACR: + description: DSI Host Video HSA Configuration Register. + fields: + - name: HSA + description: Horizontal Synchronism Active duration. + bit_offset: 0 + bit_size: 12 +fieldset/VLCCR: + description: DSI Host Video Line Current Configuration Register. + fields: + - name: HLINE + description: Horizontal Line duration. + bit_offset: 0 + bit_size: 15 +fieldset/VLCR: + description: DSI Host Video Line Configuration Register. + fields: + - name: HLINE + description: Horizontal Line duration. + bit_offset: 0 + bit_size: 15 +fieldset/VMCCR: + description: DSI Host Video mode Current Configuration Register. + fields: + - name: VMT + description: Video mode Type. + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: Low-Power Vertical Sync time Enable. + bit_offset: 2 + bit_size: 1 + - name: LPVBPE + description: Low-power Vertical Back-Porch Enable. + bit_offset: 3 + bit_size: 1 + - name: LPVFPE + description: Low-power Vertical Front-Porch Enable. + bit_offset: 4 + bit_size: 1 + - name: LPVAE + description: Low-Power Vertical Active Enable. + bit_offset: 5 + bit_size: 1 + - name: LPHBPE + description: Low-power Horizontal Back-Porch Enable. + bit_offset: 6 + bit_size: 1 + - name: LPHFE + description: Low-Power Horizontal Front-Porch Enable. + bit_offset: 7 + bit_size: 1 + - name: FBTAAE + description: Frame BTA Acknowledge Enable. + bit_offset: 8 + bit_size: 1 + - name: LPCE + description: Low-Power Command Enable. + bit_offset: 9 + bit_size: 1 +fieldset/VMCR: + description: DSI Host Video mode Configuration Register. + fields: + - name: VMT + description: Video mode Type. + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: Low-Power Vertical Sync Active Enable. + bit_offset: 8 + bit_size: 1 + - name: LPVBPE + description: Low-power Vertical Back-Porch Enable. + bit_offset: 9 + bit_size: 1 + - name: LPVFPE + description: Low-power Vertical Front-porch Enable. + bit_offset: 10 + bit_size: 1 + - name: LPVAE + description: Low-Power Vertical Active Enable. + bit_offset: 11 + bit_size: 1 + - name: LPHBPE + description: Low-Power Horizontal Back-Porch Enable. + bit_offset: 12 + bit_size: 1 + - name: LPHFPE + description: Low-Power Horizontal Front-Porch Enable. + bit_offset: 13 + bit_size: 1 + - name: FBTAAE + description: Frame Bus-Turn-Around Acknowledge Enable. + bit_offset: 14 + bit_size: 1 + - name: LPCE + description: Low-Power Command Enable. + bit_offset: 15 + bit_size: 1 + - name: PGE + description: Pattern Generator Enable. + bit_offset: 16 + bit_size: 1 + - name: PGM + description: Pattern Generator mode. + bit_offset: 20 + bit_size: 1 + - name: PGO + description: Pattern Generator Orientation. + bit_offset: 24 + bit_size: 1 +fieldset/VNPCCR: + description: DSI Host Video Null Packet Current Configuration Register. + fields: + - name: NPSIZE + description: Null Packet Size. + bit_offset: 0 + bit_size: 13 +fieldset/VNPCR: + description: DSI Host Video Null Packet Configuration Register. + fields: + - name: NPSIZE + description: Null Packet Size. + bit_offset: 0 + bit_size: 13 +fieldset/VPCCR: + description: DSI Host Video Packet Current Configuration Register. + fields: + - name: VPSIZE + description: Video Packet Size. + bit_offset: 0 + bit_size: 14 +fieldset/VPCR: + description: DSI Host Video Packet Configuration Register. + fields: + - name: VPSIZE + description: Video Packet Size. + bit_offset: 0 + bit_size: 14 +fieldset/VR: + description: DSI Host Version Register. + fields: + - name: VERSION + description: Version of the DSI Host. + bit_offset: 0 + bit_size: 32 +fieldset/VSCR: + description: DSI Host Video Shadow Control Register. + fields: + - name: EN + description: Enable. + bit_offset: 0 + bit_size: 1 + - name: UR + description: Update Register. + bit_offset: 8 + bit_size: 1 +fieldset/VVACCR: + description: DSI Host Video VA Current Configuration Register. + fields: + - name: VA + description: Vertical Active duration. + bit_offset: 0 + bit_size: 14 +fieldset/VVACR: + description: DSI Host Video VA Configuration Register. + fields: + - name: VA + description: Vertical Active duration. + bit_offset: 0 + bit_size: 14 +fieldset/VVBPCCR: + description: DSI Host Video VBP Current Configuration Register. + fields: + - name: VBP + description: Vertical Back-Porch duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVBPCR: + description: DSI Host Video VBP Configuration Register. + fields: + - name: VBP + description: Vertical Back-Porch duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCCR: + description: DSI Host Video VFP Current Configuration Register. + fields: + - name: VFP + description: Vertical Front-Porch duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCR: + description: DSI Host Video VFP Configuration Register. + fields: + - name: VFP + description: Vertical Front-Porch duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACCR: + description: DSI Host Video VSA Current Configuration Register. + fields: + - name: VSA + description: Vertical Synchronism Active duration. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACR: + description: DSI Host Video VSA Configuration Register. + fields: + - name: VSA + description: Vertical Synchronism Active duration. + bit_offset: 0 + bit_size: 10 +fieldset/WCFGR: + description: DSI Wrapper Configuration Register. + fields: + - name: DSIM + description: DSI Mode. + bit_offset: 0 + bit_size: 1 + - name: COLMUX + description: Color Multiplexing. + bit_offset: 1 + bit_size: 3 + - name: TESRC + description: TE Source. + bit_offset: 4 + bit_size: 1 + - name: TEPOL + description: TE Polarity. + bit_offset: 5 + bit_size: 1 + - name: AR + description: Automatic Refresh. + bit_offset: 6 + bit_size: 1 + - name: VSPOL + description: VSync Polarity. + bit_offset: 7 + bit_size: 1 +fieldset/WCR: + description: DSI Wrapper Control Register. + fields: + - name: COLM + description: Color Mode. + bit_offset: 0 + bit_size: 1 + - name: SHTDN + description: Shutdown. + bit_offset: 1 + bit_size: 1 + - name: LTDCEN + description: LTDC Enable. + bit_offset: 2 + bit_size: 1 + - name: DSIEN + description: DSI Enable. + bit_offset: 3 + bit_size: 1 +fieldset/WIER: + description: DSI Wrapper Interrupt Enable Register. + fields: + - name: TEIE + description: Tearing Effect Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: ERIE + description: End of Refresh Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: PLLLIE + description: PLL Lock Interrupt Enable. + bit_offset: 9 + bit_size: 1 + - name: PLLUIE + description: PLL Unlock Interrupt Enable. + bit_offset: 10 + bit_size: 1 + - name: RRIE + description: Regulator Ready Interrupt Enable. + bit_offset: 13 + bit_size: 1 +fieldset/WIFCR: + description: DSI Wrapper Interrupt Flag Clear Register. + fields: + - name: CTEIF + description: Clear Tearing Effect Interrupt Flag. + bit_offset: 0 + bit_size: 1 + - name: CERIF + description: Clear End of Refresh Interrupt Flag. + bit_offset: 1 + bit_size: 1 + - name: CPLLLIF + description: Clear PLL Lock Interrupt Flag. + bit_offset: 9 + bit_size: 1 + - name: CPLLUIF + description: Clear PLL Unlock Interrupt Flag. + bit_offset: 10 + bit_size: 1 + - name: CRRIF + description: Clear Regulator Ready Interrupt Flag. + bit_offset: 13 + bit_size: 1 +fieldset/WISR: + description: DSI Wrapper Interrupt & Status Register. + fields: + - name: TEIF + description: Tearing Effect Interrupt Flag. + bit_offset: 0 + bit_size: 1 + - name: ERIF + description: End of Refresh Interrupt Flag. + bit_offset: 1 + bit_size: 1 + - name: BUSY + description: Busy Flag. + bit_offset: 2 + bit_size: 1 + - name: PLLLS + description: PLL Lock Status. + bit_offset: 8 + bit_size: 1 + - name: PLLLIF + description: PLL Lock Interrupt Flag. + bit_offset: 9 + bit_size: 1 + - name: PLLUIF + description: PLL Unlock Interrupt Flag. + bit_offset: 10 + bit_size: 1 + - name: RRS + description: Regulator Ready Status. + bit_offset: 12 + bit_size: 1 + - name: RRIF + description: Regulator Ready Interrupt Flag. + bit_offset: 13 + bit_size: 1 +fieldset/WPCR0: + description: DSI Wrapper PHY Configuration Register 0. + fields: + - name: UIX4 + description: Unit Interval multiplied by 4. + bit_offset: 0 + bit_size: 6 + - name: SWCL + description: Swap Clock Lane pins. + bit_offset: 6 + bit_size: 1 + - name: SWDL0 + description: Swap Data Lane 0 pins. + bit_offset: 7 + bit_size: 1 + - name: SWDL1 + description: Swap Data Lane 1 pins. + bit_offset: 8 + bit_size: 1 + - name: HSICL + description: Invert Hight-Speed data signal on Clock Lane. + bit_offset: 9 + bit_size: 1 + - name: HSIDL0 + description: Invert the Hight-Speed data signal on Data Lane 0. + bit_offset: 10 + bit_size: 1 + - name: HSIDL1 + description: Invert the High-Speed data signal on Data Lane 1. + bit_offset: 11 + bit_size: 1 + - name: FTXSMCL + description: Force in TX Stop Mode the Clock Lane. + bit_offset: 12 + bit_size: 1 + - name: FTXSMDL + description: Force in TX Stop Mode the Data Lanes. + bit_offset: 13 + bit_size: 1 + - name: CDOFFDL + description: Contention Detection OFF on Data Lanes. + bit_offset: 14 + bit_size: 1 + - name: TDDL + description: Turn Disable Data Lanes. + bit_offset: 16 + bit_size: 1 + - name: PDEN + description: Pull-Down Enable. + bit_offset: 18 + bit_size: 1 + - name: TCLKPREPEN + description: custom time for tCLK-PREPARE Enable. + bit_offset: 19 + bit_size: 1 + - name: TCLKZEROEN + description: custom time for tCLK-ZERO Enable. + bit_offset: 20 + bit_size: 1 + - name: THSPREPEN + description: custom time for tHS-PREPARE Enable. + bit_offset: 21 + bit_size: 1 + - name: THSTRAILEN + description: custom time for tHS-TRAIL Enable. + bit_offset: 22 + bit_size: 1 + - name: THSZEROEN + description: custom time for tHS-ZERO Enable. + bit_offset: 23 + bit_size: 1 + - name: TLPXDEN + description: custom time for tLPX for Data lanes Enable. + bit_offset: 24 + bit_size: 1 + - name: THSEXITEN + description: custom time for tHS-EXIT Enable. + bit_offset: 25 + bit_size: 1 + - name: TLPXCEN + description: custom time for tLPX for Clock lane Enable. + bit_offset: 26 + bit_size: 1 + - name: TCLKPOSTEN + description: custom time for tCLK-POST Enable. + bit_offset: 27 + bit_size: 1 +fieldset/WPCR1: + description: DSI Wrapper PHY Configuration Register 1. + fields: + - name: HSTXDCL + description: High-Speed Transmission Delay on Clock Lane. + bit_offset: 0 + bit_size: 2 + - name: HSTXDLL + description: High-Speed Transmission Delay on Data Lanes. + bit_offset: 2 + bit_size: 2 + - name: LPSRCL + description: Low-Power transmission Slew Rate Compensation on Clock Lane. + bit_offset: 6 + bit_size: 2 + - name: LPSRDL + description: Low-Power transmission Slew Rate Compensation on Data Lanes. + bit_offset: 8 + bit_size: 2 + - name: SDCC + description: SDD Control. + bit_offset: 12 + bit_size: 1 + - name: HSTXSRCCL + description: High-Speed Transmission Slew Rate Control on Clock Lane. + bit_offset: 16 + bit_size: 2 + - name: HSTXSRCDL + description: High-Speed Transmission Slew Rate Control on Data Lanes. + bit_offset: 18 + bit_size: 2 + - name: FLPRXLPM + description: Forces LP Receiver in Low-Power Mode. + bit_offset: 22 + bit_size: 1 + - name: LPRXFT + description: Low-Power RX low-pass Filtering Tuning. + bit_offset: 25 + bit_size: 2 +fieldset/WPCR2: + description: DSI Wrapper PHY Configuration Register 2. + fields: + - name: TCLKPREP + description: tCLK-PREPARE. + bit_offset: 0 + bit_size: 8 + - name: TCLKZEO + description: tCLK-ZERO. + bit_offset: 8 + bit_size: 8 + - name: THSPREP + description: tHS-PREPARE. + bit_offset: 16 + bit_size: 8 + - name: THSTRAIL + description: tHSTRAIL. + bit_offset: 24 + bit_size: 8 +fieldset/WPCR3: + description: DSI Wrapper PHY Configuration Register 3. + fields: + - name: THSZERO + description: tHS-ZERO. + bit_offset: 0 + bit_size: 8 + - name: TLPXD + description: tLPX for Data lanes. + bit_offset: 8 + bit_size: 8 + - name: THSEXIT + description: tHSEXIT. + bit_offset: 16 + bit_size: 8 + - name: TLPXC + description: tLPXC for Clock lane. + bit_offset: 24 + bit_size: 8 +fieldset/WPCR4: + description: DSI Wrapper PHY Configuration Register 4. + fields: + - name: TCLKPOST + description: tCLK-POST. + bit_offset: 0 + bit_size: 8 +fieldset/WRPCR: + description: DSI Wrapper Regulator and PLL Control Register. + fields: + - name: PLLEN + description: PLL Enable. + bit_offset: 0 + bit_size: 1 + - name: NDIV + description: PLL Loop Division Factor. + bit_offset: 2 + bit_size: 7 + - name: IDF + description: PLL Input Division Factor. + bit_offset: 11 + bit_size: 4 + - name: ODF + description: PLL Output Division Factor. + bit_offset: 16 + bit_size: 2 + - name: REGEN + description: Regulator Enable. + bit_offset: 24 + bit_size: 1 diff --git a/data/registers/dsihost_v2.yaml b/data/registers/dsihost_v2.yaml new file mode 100644 index 0000000..47a31de --- /dev/null +++ b/data/registers/dsihost_v2.yaml @@ -0,0 +1,1716 @@ +block/DSIHOST: + description: DSIHOST1. + items: + - name: VR + description: DSI Host version register. + byte_offset: 0 + access: Read + fieldset: VR + - name: CR + description: DSI Host control register. + byte_offset: 4 + fieldset: CR + - name: CCR + description: DSI Host clock control register. + byte_offset: 8 + fieldset: CCR + - name: LVCIDR + description: DSI Host LTDC VCID register. + byte_offset: 12 + fieldset: LVCIDR + - name: LCOLCR + description: DSI Host LTDC color coding register. + byte_offset: 16 + fieldset: LCOLCR + - name: LPCR + description: DSI Host LTDC polarity configuration register. + byte_offset: 20 + fieldset: LPCR + - name: LPMCR + description: DSI Host low-power mode configuration register. + byte_offset: 24 + fieldset: LPMCR + - name: PCR + description: DSI Host protocol configuration register. + byte_offset: 44 + fieldset: PCR + - name: GVCIDR + description: DSI Host generic VCID register. + byte_offset: 48 + access: Read + fieldset: GVCIDR + - name: MCR + description: DSI Host mode configuration register. + byte_offset: 52 + fieldset: MCR + - name: VMCR + description: DSI Host video mode configuration register. + byte_offset: 56 + fieldset: VMCR + - name: VPCR + description: DSI Host video packet configuration register. + byte_offset: 60 + fieldset: VPCR + - name: VCCR + description: DSI Host video chunks configuration register. + byte_offset: 64 + fieldset: VCCR + - name: VNPCR + description: DSI Host video null packet configuration register. + byte_offset: 68 + fieldset: VNPCR + - name: VHSACR + description: DSI Host video HSA configuration register. + byte_offset: 72 + fieldset: VHSACR + - name: VHBPCR + description: DSI Host video HBP configuration register. + byte_offset: 76 + fieldset: VHBPCR + - name: VLCR + description: DSI Host video line configuration register. + byte_offset: 80 + fieldset: VLCR + - name: VVSACR + description: DSI Host video VSA configuration register. + byte_offset: 84 + fieldset: VVSACR + - name: VVBPCR + description: DSI Host video VBP configuration register. + byte_offset: 88 + fieldset: VVBPCR + - name: VVFPCR + description: DSI Host video VFP configuration register. + byte_offset: 92 + fieldset: VVFPCR + - name: VVACR + description: DSI Host video VA configuration register. + byte_offset: 96 + fieldset: VVACR + - name: LCCR + description: DSI Host LTDC command configuration register. + byte_offset: 100 + fieldset: LCCR + - name: CMCR + description: DSI Host command mode configuration register. + byte_offset: 104 + fieldset: CMCR + - name: GHCR + description: DSI Host generic header configuration register. + byte_offset: 108 + fieldset: GHCR + - name: GPDR + description: DSI Host generic payload data register. + byte_offset: 112 + fieldset: GPDR + - name: GPSR + description: DSI Host generic packet status register. + byte_offset: 116 + access: Read + fieldset: GPSR + - name: TCCR0 + description: DSI Host timeout counter configuration register 0. + byte_offset: 120 + fieldset: TCCR0 + - name: TCCR1 + description: DSI Host timeout counter configuration register 1. + byte_offset: 124 + fieldset: TCCR1 + - name: TCCR2 + description: DSI Host timeout counter configuration register 2. + byte_offset: 128 + fieldset: TCCR2 + - name: TCCR3 + description: DSI Host timeout counter configuration register 3. + byte_offset: 132 + fieldset: TCCR3 + - name: TCCR4 + description: DSI Host timeout counter configuration register 4. + byte_offset: 136 + fieldset: TCCR4 + - name: TCCR5 + description: DSI Host timeout counter configuration register 5. + byte_offset: 140 + fieldset: TCCR5 + - name: CLCR + description: DSI Host clock lane configuration register. + byte_offset: 148 + fieldset: CLCR + - name: CLTCR + description: DSI Host clock lane timer configuration register. + byte_offset: 152 + fieldset: CLTCR + - name: DLTCR + description: DSI Host data lane timer configuration register. + byte_offset: 156 + fieldset: DLTCR + - name: PCTLR + description: DSI Host PHY control register. + byte_offset: 160 + fieldset: PCTLR + - name: PCONFR + description: DSI Host PHY configuration register. + byte_offset: 164 + fieldset: PCONFR + - name: PUCR + description: DSI Host PHY ULPS control register. + byte_offset: 168 + fieldset: PUCR + - name: PTTCR + description: DSI Host PHY TX triggers configuration register. + byte_offset: 172 + fieldset: PTTCR + - name: PSR + description: DSI Host PHY status register. + byte_offset: 176 + access: Read + fieldset: PSR + - name: ISR0 + description: DSI Host interrupt and status register 0. + byte_offset: 188 + access: Read + fieldset: ISR0 + - name: ISR1 + description: DSI Host interrupt and status register 1. + byte_offset: 192 + access: Read + fieldset: ISR1 + - name: IER0 + description: DSI Host interrupt enable register 0. + byte_offset: 196 + fieldset: IER0 + - name: IER1 + description: DSI Host interrupt enable register 1. + byte_offset: 200 + fieldset: IER1 + - name: FIR0 + description: DSI Host force interrupt register 0. + byte_offset: 216 + access: Write + fieldset: FIR0 + - name: FIR1 + description: DSI Host force interrupt register 1. + byte_offset: 220 + access: Write + fieldset: FIR1 + - name: DLTRCR + description: DSI Host data lane timer read configuration register. + byte_offset: 244 + fieldset: DLTRCR + - name: VSCR + description: DSI Host video shadow control register. + byte_offset: 256 + fieldset: VSCR + - name: LCVCIDR + description: DSI Host LTDC current VCID register. + byte_offset: 268 + fieldset: LCVCIDR + - name: LCCCR + description: DSI Host LTDC current color coding register. + byte_offset: 272 + access: Read + fieldset: LCCCR + - name: LPMCCR + description: DSI Host low-power mode current configuration register. + byte_offset: 280 + access: Read + fieldset: LPMCCR + - name: VMCCR + description: DSI Host video mode current configuration register. + byte_offset: 312 + access: Read + fieldset: VMCCR + - name: VPCCR + description: DSI Host video packet current configuration register. + byte_offset: 316 + access: Read + fieldset: VPCCR + - name: VCCCR + description: DSI Host video chunks current configuration register. + byte_offset: 320 + access: Read + fieldset: VCCCR + - name: VNPCCR + description: DSI Host video null packet current configuration register. + byte_offset: 324 + access: Read + fieldset: VNPCCR + - name: VHSACCR + description: DSI Host video HSA current configuration register. + byte_offset: 328 + access: Read + fieldset: VHSACCR + - name: VHBPCCR + description: DSI Host video HBP current configuration register. + byte_offset: 332 + access: Read + fieldset: VHBPCCR + - name: VLCCR + description: DSI Host video line current configuration register. + byte_offset: 336 + access: Read + fieldset: VLCCR + - name: VVSACCR + description: DSI Host video VSA current configuration register. + byte_offset: 340 + access: Read + fieldset: VVSACCR + - name: VVBPCCR + description: DSI Host video VBP current configuration register. + byte_offset: 344 + access: Read + fieldset: VVBPCCR + - name: VVFPCCR + description: DSI Host video VFP current configuration register. + byte_offset: 348 + access: Read + fieldset: VVFPCCR + - name: VVACCR + description: DSI Host video VA current configuration register. + byte_offset: 352 + access: Read + fieldset: VVACCR + - name: WCFGR + description: DSI wrapper configuration register. + byte_offset: 1024 + fieldset: WCFGR + - name: WCR + description: DSI wrapper control register. + byte_offset: 1028 + fieldset: WCR + - name: WIER + description: DSI wrapper interrupt enable register. + byte_offset: 1032 + fieldset: WIER + - name: WISR + description: DSI wrapper interrupt and status register. + byte_offset: 1036 + access: Read + fieldset: WISR + - name: WIFCR + description: DSI wrapper interrupt flag clear register. + byte_offset: 1040 + access: Write + fieldset: WIFCR + - name: WPCR0 + description: DSI wrapper PHY configuration register 0. + byte_offset: 1048 + fieldset: WPCR0 + - name: WPCR1 + description: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). + byte_offset: 1052 + fieldset: WPCR1 + - name: WRPCR + description: DSI wrapper regulator and PLL control register. + byte_offset: 1072 + fieldset: WRPCR + - name: HWCFGR + description: DSI Host hardware configuration register. + byte_offset: 2032 + access: Read + fieldset: HWCFGR + - name: VERR + description: DSI Host version register. + byte_offset: 2036 + access: Read + fieldset: VERR + - name: IPIDR + description: DSI Host identification register. + byte_offset: 2040 + access: Read + fieldset: IPIDR + - name: SIDR + description: DSI Host size identification register. + byte_offset: 2044 + access: Read + fieldset: SIDR +fieldset/CCR: + description: DSI Host clock control register. + fields: + - name: TXECKDIV + description: TXECKDIV. + bit_offset: 0 + bit_size: 8 + - name: TOCKDIV + description: TOCKDIV. + bit_offset: 8 + bit_size: 8 +fieldset/CLCR: + description: DSI Host clock lane configuration register. + fields: + - name: DPCC + description: DPCC. + bit_offset: 0 + bit_size: 1 + - name: ACR + description: ACR. + bit_offset: 1 + bit_size: 1 +fieldset/CLTCR: + description: DSI Host clock lane timer configuration register. + fields: + - name: LP2HS_TIME + description: LP2HS_TIME. + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: HS2LP_TIME. + bit_offset: 16 + bit_size: 10 +fieldset/CMCR: + description: DSI Host command mode configuration register. + fields: + - name: TEARE + description: TEARE. + bit_offset: 0 + bit_size: 1 + - name: ARE + description: ARE. + bit_offset: 1 + bit_size: 1 + - name: GSW0TX + description: GSW0TX. + bit_offset: 8 + bit_size: 1 + - name: GSW1TX + description: GSW1TX. + bit_offset: 9 + bit_size: 1 + - name: GSW2TX + description: GSW2TX. + bit_offset: 10 + bit_size: 1 + - name: GSR0TX + description: GSR0TX. + bit_offset: 11 + bit_size: 1 + - name: GSR1TX + description: GSR1TX. + bit_offset: 12 + bit_size: 1 + - name: GSR2TX + description: GSR2TX. + bit_offset: 13 + bit_size: 1 + - name: GLWTX + description: GLWTX. + bit_offset: 14 + bit_size: 1 + - name: DSW0TX + description: DSW0TX. + bit_offset: 16 + bit_size: 1 + - name: DSW1TX + description: DSW1TX. + bit_offset: 17 + bit_size: 1 + - name: DSR0TX + description: DSR0TX. + bit_offset: 18 + bit_size: 1 + - name: DLWTX + description: DLWTX. + bit_offset: 19 + bit_size: 1 + - name: MRDPS + description: MRDPS. + bit_offset: 24 + bit_size: 1 +fieldset/CR: + description: DSI Host control register. + fields: + - name: EN + description: EN. + bit_offset: 0 + bit_size: 1 +fieldset/DLTCR: + description: DSI Host data lane timer configuration register. + fields: + - name: LP2HS_TIME + description: LP2HS_TIME. + bit_offset: 0 + bit_size: 10 + - name: HS2LP_TIME + description: HS2LP_TIME. + bit_offset: 16 + bit_size: 10 +fieldset/DLTRCR: + description: DSI Host data lane timer read configuration register. + fields: + - name: MRD_TIME + description: MRD_TIME. + bit_offset: 0 + bit_size: 15 +fieldset/FIR0: + description: DSI Host force interrupt register 0. + fields: + - name: FAE0 + description: FAE0. + bit_offset: 0 + bit_size: 1 + - name: FAE1 + description: FAE1. + bit_offset: 1 + bit_size: 1 + - name: FAE2 + description: FAE2. + bit_offset: 2 + bit_size: 1 + - name: FAE3 + description: FAE3. + bit_offset: 3 + bit_size: 1 + - name: FAE4 + description: FAE4. + bit_offset: 4 + bit_size: 1 + - name: FAE5 + description: FAE5. + bit_offset: 5 + bit_size: 1 + - name: FAE6 + description: FAE6. + bit_offset: 6 + bit_size: 1 + - name: FAE7 + description: FAE7. + bit_offset: 7 + bit_size: 1 + - name: FAE8 + description: FAE8. + bit_offset: 8 + bit_size: 1 + - name: FAE9 + description: FAE9. + bit_offset: 9 + bit_size: 1 + - name: FAE10 + description: FAE10. + bit_offset: 10 + bit_size: 1 + - name: FAE11 + description: FAE11. + bit_offset: 11 + bit_size: 1 + - name: FAE12 + description: FAE12. + bit_offset: 12 + bit_size: 1 + - name: FAE13 + description: FAE13. + bit_offset: 13 + bit_size: 1 + - name: FAE14 + description: FAE14. + bit_offset: 14 + bit_size: 1 + - name: FAE15 + description: FAE15. + bit_offset: 15 + bit_size: 1 + - name: FPE0 + description: FPE0. + bit_offset: 16 + bit_size: 1 + - name: FPE1 + description: FPE1. + bit_offset: 17 + bit_size: 1 + - name: FPE2 + description: FPE2. + bit_offset: 18 + bit_size: 1 + - name: FPE3 + description: FPE3. + bit_offset: 19 + bit_size: 1 + - name: FPE4 + description: FPE4. + bit_offset: 20 + bit_size: 1 +fieldset/FIR1: + description: DSI Host force interrupt register 1. + fields: + - name: FTOHSTX + description: FTOHSTX. + bit_offset: 0 + bit_size: 1 + - name: FTOLPRX + description: FTOLPRX. + bit_offset: 1 + bit_size: 1 + - name: FECCSE + description: FECCSE. + bit_offset: 2 + bit_size: 1 + - name: FECCME + description: FECCME. + bit_offset: 3 + bit_size: 1 + - name: FCRCE + description: FCRCE. + bit_offset: 4 + bit_size: 1 + - name: FPSE + description: FPSE. + bit_offset: 5 + bit_size: 1 + - name: FEOTPE + description: FEOTPE. + bit_offset: 6 + bit_size: 1 + - name: FLPWRE + description: FLPWRE. + bit_offset: 7 + bit_size: 1 + - name: FGCWRE + description: FGCWRE. + bit_offset: 8 + bit_size: 1 + - name: FGPWRE + description: FGPWRE. + bit_offset: 9 + bit_size: 1 + - name: FGPTXE + description: FGPTXE. + bit_offset: 10 + bit_size: 1 + - name: FGPRDE + description: FGPRDE. + bit_offset: 11 + bit_size: 1 + - name: FGPRXE + description: FGPRXE. + bit_offset: 12 + bit_size: 1 +fieldset/GHCR: + description: DSI Host generic header configuration register. + fields: + - name: DT + description: DT. + bit_offset: 0 + bit_size: 6 + - name: VCID + description: VCID. + bit_offset: 6 + bit_size: 2 + - name: WCLSB + description: WCLSB. + bit_offset: 8 + bit_size: 8 + - name: WCMSB + description: WCMSB. + bit_offset: 16 + bit_size: 8 +fieldset/GPDR: + description: DSI Host generic payload data register. + fields: + - name: DATA1 + description: DATA1. + bit_offset: 0 + bit_size: 8 + - name: DATA2 + description: DATA2. + bit_offset: 8 + bit_size: 8 + - name: DATA3 + description: DATA3. + bit_offset: 16 + bit_size: 8 + - name: DATA4 + description: DATA4. + bit_offset: 24 + bit_size: 8 +fieldset/GPSR: + description: DSI Host generic packet status register. + fields: + - name: CMDFE + description: CMDFE. + bit_offset: 0 + bit_size: 1 + - name: CMDFF + description: CMDFF. + bit_offset: 1 + bit_size: 1 + - name: PWRFE + description: PWRFE. + bit_offset: 2 + bit_size: 1 + - name: PWRFF + description: PWRFF. + bit_offset: 3 + bit_size: 1 + - name: PRDFE + description: PRDFE. + bit_offset: 4 + bit_size: 1 + - name: PRDFF + description: PRDFF. + bit_offset: 5 + bit_size: 1 + - name: RCB + description: RCB. + bit_offset: 6 + bit_size: 1 +fieldset/GVCIDR: + description: DSI Host generic VCID register. + fields: + - name: VCID + description: VCID. + bit_offset: 0 + bit_size: 2 +fieldset/HWCFGR: + description: DSI Host hardware configuration register. + fields: + - name: TECHNO + description: TECHNO. + bit_offset: 0 + bit_size: 4 + - name: FIFOSIZE + description: FIFOSIZE. + bit_offset: 4 + bit_size: 12 +fieldset/IER0: + description: DSI Host interrupt enable register 0. + fields: + - name: AE0IE + description: AE0IE. + bit_offset: 0 + bit_size: 1 + - name: AE1IE + description: AE1IE. + bit_offset: 1 + bit_size: 1 + - name: AE2IE + description: AE2IE. + bit_offset: 2 + bit_size: 1 + - name: AE3IE + description: AE3IE. + bit_offset: 3 + bit_size: 1 + - name: AE4IE + description: AE4IE. + bit_offset: 4 + bit_size: 1 + - name: AE5IE + description: AE5IE. + bit_offset: 5 + bit_size: 1 + - name: AE6IE + description: AE6IE. + bit_offset: 6 + bit_size: 1 + - name: AE7IE + description: AE7IE. + bit_offset: 7 + bit_size: 1 + - name: AE8IE + description: AE8IE. + bit_offset: 8 + bit_size: 1 + - name: AE9IE + description: AE9IE. + bit_offset: 9 + bit_size: 1 + - name: AE10IE + description: AE10IE. + bit_offset: 10 + bit_size: 1 + - name: AE11IE + description: AE11IE. + bit_offset: 11 + bit_size: 1 + - name: AE12IE + description: AE12IE. + bit_offset: 12 + bit_size: 1 + - name: AE13IE + description: AE13IE. + bit_offset: 13 + bit_size: 1 + - name: AE14IE + description: AE14IE. + bit_offset: 14 + bit_size: 1 + - name: AE15IE + description: AE15IE. + bit_offset: 15 + bit_size: 1 + - name: PE0IE + description: PE0IE. + bit_offset: 16 + bit_size: 1 + - name: PE1IE + description: PE1IE. + bit_offset: 17 + bit_size: 1 + - name: PE2IE + description: PE2IE. + bit_offset: 18 + bit_size: 1 + - name: PE3IE + description: PE3IE. + bit_offset: 19 + bit_size: 1 + - name: PE4IE + description: PE4IE. + bit_offset: 20 + bit_size: 1 +fieldset/IER1: + description: DSI Host interrupt enable register 1. + fields: + - name: TOHSTXIE + description: TOHSTXIE. + bit_offset: 0 + bit_size: 1 + - name: TOLPRXIE + description: TOLPRXIE. + bit_offset: 1 + bit_size: 1 + - name: ECCSEIE + description: ECCSEIE. + bit_offset: 2 + bit_size: 1 + - name: ECCMEIE + description: ECCMEIE. + bit_offset: 3 + bit_size: 1 + - name: CRCEIE + description: CRCEIE. + bit_offset: 4 + bit_size: 1 + - name: PSEIE + description: PSEIE. + bit_offset: 5 + bit_size: 1 + - name: EOTPEIE + description: EOTPEIE. + bit_offset: 6 + bit_size: 1 + - name: LPWREIE + description: LPWREIE. + bit_offset: 7 + bit_size: 1 + - name: GCWREIE + description: GCWREIE. + bit_offset: 8 + bit_size: 1 + - name: GPWREIE + description: GPWREIE. + bit_offset: 9 + bit_size: 1 + - name: GPTXEIE + description: GPTXEIE. + bit_offset: 10 + bit_size: 1 + - name: GPRDEIE + description: GPRDEIE. + bit_offset: 11 + bit_size: 1 + - name: GPRXEIE + description: GPRXEIE. + bit_offset: 12 + bit_size: 1 +fieldset/IPIDR: + description: DSI Host identification register. + fields: + - name: ID + description: ID. + bit_offset: 0 + bit_size: 32 +fieldset/ISR0: + description: DSI Host interrupt and status register 0. + fields: + - name: AE0 + description: AE0. + bit_offset: 0 + bit_size: 1 + - name: AE1 + description: AE1. + bit_offset: 1 + bit_size: 1 + - name: AE2 + description: AE2. + bit_offset: 2 + bit_size: 1 + - name: AE3 + description: AE3. + bit_offset: 3 + bit_size: 1 + - name: AE4 + description: AE4. + bit_offset: 4 + bit_size: 1 + - name: AE5 + description: AE5. + bit_offset: 5 + bit_size: 1 + - name: AE6 + description: AE6. + bit_offset: 6 + bit_size: 1 + - name: AE7 + description: AE7. + bit_offset: 7 + bit_size: 1 + - name: AE8 + description: AE8. + bit_offset: 8 + bit_size: 1 + - name: AE9 + description: AE9. + bit_offset: 9 + bit_size: 1 + - name: AE10 + description: AE10. + bit_offset: 10 + bit_size: 1 + - name: AE11 + description: AE11. + bit_offset: 11 + bit_size: 1 + - name: AE12 + description: AE12. + bit_offset: 12 + bit_size: 1 + - name: AE13 + description: AE13. + bit_offset: 13 + bit_size: 1 + - name: AE14 + description: AE14. + bit_offset: 14 + bit_size: 1 + - name: AE15 + description: AE15. + bit_offset: 15 + bit_size: 1 + - name: PE0 + description: PE0. + bit_offset: 16 + bit_size: 1 + - name: PE1 + description: PE1. + bit_offset: 17 + bit_size: 1 + - name: PE2 + description: PE2. + bit_offset: 18 + bit_size: 1 + - name: PE3 + description: PE3. + bit_offset: 19 + bit_size: 1 + - name: PE4 + description: PE4. + bit_offset: 20 + bit_size: 1 +fieldset/ISR1: + description: DSI Host interrupt and status register 1. + fields: + - name: TOHSTX + description: TOHSTX. + bit_offset: 0 + bit_size: 1 + - name: TOLPRX + description: TOLPRX. + bit_offset: 1 + bit_size: 1 + - name: ECCSE + description: ECCSE. + bit_offset: 2 + bit_size: 1 + - name: ECCME + description: ECCME. + bit_offset: 3 + bit_size: 1 + - name: CRCE + description: CRCE. + bit_offset: 4 + bit_size: 1 + - name: PSE + description: PSE. + bit_offset: 5 + bit_size: 1 + - name: EOTPE + description: EOTPE. + bit_offset: 6 + bit_size: 1 + - name: LPWRE + description: LPWRE. + bit_offset: 7 + bit_size: 1 + - name: GCWRE + description: GCWRE. + bit_offset: 8 + bit_size: 1 + - name: GPWRE + description: GPWRE. + bit_offset: 9 + bit_size: 1 + - name: GPTXE + description: GPTXE. + bit_offset: 10 + bit_size: 1 + - name: GPRDE + description: GPRDE. + bit_offset: 11 + bit_size: 1 + - name: GPRXE + description: GPRXE. + bit_offset: 12 + bit_size: 1 +fieldset/LCCCR: + description: DSI Host LTDC current color coding register. + fields: + - name: COLC + description: COLC. + bit_offset: 0 + bit_size: 4 + - name: LPE + description: LPE. + bit_offset: 8 + bit_size: 1 +fieldset/LCCR: + description: DSI Host LTDC command configuration register. + fields: + - name: CMDSIZE + description: CMDSIZE. + bit_offset: 0 + bit_size: 16 +fieldset/LCOLCR: + description: DSI Host LTDC color coding register. + fields: + - name: COLC + description: COLC. + bit_offset: 0 + bit_size: 4 + - name: LPE + description: LPE. + bit_offset: 8 + bit_size: 1 +fieldset/LCVCIDR: + description: DSI Host LTDC current VCID register. + fields: + - name: VCID + description: VCID. + bit_offset: 0 + bit_size: 2 +fieldset/LPCR: + description: DSI Host LTDC polarity configuration register. + fields: + - name: DEP + description: DEP. + bit_offset: 0 + bit_size: 1 + - name: VSP + description: VSP. + bit_offset: 1 + bit_size: 1 + - name: HSP + description: HSP. + bit_offset: 2 + bit_size: 1 +fieldset/LPMCCR: + description: DSI Host low-power mode current configuration register. + fields: + - name: VLPSIZE + description: VLPSIZE. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: LPSIZE. + bit_offset: 16 + bit_size: 8 +fieldset/LPMCR: + description: DSI Host low-power mode configuration register. + fields: + - name: VLPSIZE + description: VLPSIZE. + bit_offset: 0 + bit_size: 8 + - name: LPSIZE + description: LPSIZE. + bit_offset: 16 + bit_size: 8 +fieldset/LVCIDR: + description: DSI Host LTDC VCID register. + fields: + - name: VCID + description: VCID. + bit_offset: 0 + bit_size: 2 +fieldset/MCR: + description: DSI Host mode configuration register. + fields: + - name: CMDM + description: CMDM. + bit_offset: 0 + bit_size: 1 +fieldset/PCONFR: + description: DSI Host PHY configuration register. + fields: + - name: NL + description: NL. + bit_offset: 0 + bit_size: 2 + - name: SW_TIME + description: SW_TIME. + bit_offset: 8 + bit_size: 8 +fieldset/PCR: + description: DSI Host protocol configuration register. + fields: + - name: ETTXE + description: ETTXE. + bit_offset: 0 + bit_size: 1 + - name: ETRXE + description: ETRXE. + bit_offset: 1 + bit_size: 1 + - name: BTAE + description: BTAE. + bit_offset: 2 + bit_size: 1 + - name: ECCRXE + description: ECCRXE. + bit_offset: 3 + bit_size: 1 + - name: CRCRXE + description: CRCRXE. + bit_offset: 4 + bit_size: 1 +fieldset/PCTLR: + description: DSI Host PHY control register. + fields: + - name: DEN + description: DEN. + bit_offset: 1 + bit_size: 1 + - name: CKE + description: CKE. + bit_offset: 2 + bit_size: 1 +fieldset/PSR: + description: DSI Host PHY status register. + fields: + - name: PD + description: PD. + bit_offset: 1 + bit_size: 1 + - name: PSSC + description: PSSC. + bit_offset: 2 + bit_size: 1 + - name: UANC + description: UANC. + bit_offset: 3 + bit_size: 1 + - name: PSS0 + description: PSS0. + bit_offset: 4 + bit_size: 1 + - name: UAN0 + description: UAN0. + bit_offset: 5 + bit_size: 1 + - name: RUE0 + description: RUE0. + bit_offset: 6 + bit_size: 1 + - name: PSS1 + description: PSS1. + bit_offset: 7 + bit_size: 1 + - name: UAN1 + description: UAN1. + bit_offset: 8 + bit_size: 1 +fieldset/PTTCR: + description: DSI Host PHY TX triggers configuration register. + fields: + - name: TX_TRIG + description: TX_TRIG. + bit_offset: 0 + bit_size: 4 +fieldset/PUCR: + description: DSI Host PHY ULPS control register. + fields: + - name: URCL + description: URCL. + bit_offset: 0 + bit_size: 1 + - name: UECL + description: UECL. + bit_offset: 1 + bit_size: 1 + - name: URDL + description: URDL. + bit_offset: 2 + bit_size: 1 + - name: UEDL + description: UEDL. + bit_offset: 3 + bit_size: 1 +fieldset/SIDR: + description: DSI Host size identification register. + fields: + - name: SID + description: SID. + bit_offset: 0 + bit_size: 32 +fieldset/TCCR0: + description: DSI Host timeout counter configuration register 0. + fields: + - name: LPRX_TOCNT + description: LPRX_TOCNT. + bit_offset: 0 + bit_size: 16 + - name: HSTX_TOCNT + description: HSTX_TOCNT. + bit_offset: 16 + bit_size: 16 +fieldset/TCCR1: + description: DSI Host timeout counter configuration register 1. + fields: + - name: HSRD_TOCNT + description: HSRD_TOCNT. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR2: + description: DSI Host timeout counter configuration register 2. + fields: + - name: LPRD_TOCNT + description: LPRD_TOCNT. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR3: + description: DSI Host timeout counter configuration register 3. + fields: + - name: HSWR_TOCNT + description: HSWR_TOCNT. + bit_offset: 0 + bit_size: 16 + - name: PM + description: PM. + bit_offset: 24 + bit_size: 1 +fieldset/TCCR4: + description: DSI Host timeout counter configuration register 4. + fields: + - name: LPWR_TOCNT + description: LPWR_TOCNT. + bit_offset: 0 + bit_size: 16 +fieldset/TCCR5: + description: DSI Host timeout counter configuration register 5. + fields: + - name: BTA_TOCNT + description: BTA_TOCNT. + bit_offset: 0 + bit_size: 16 +fieldset/VCCCR: + description: DSI Host video chunks current configuration register. + fields: + - name: NUMC + description: NUMC. + bit_offset: 0 + bit_size: 13 +fieldset/VCCR: + description: DSI Host video chunks configuration register. + fields: + - name: NUMC + description: NUMC. + bit_offset: 0 + bit_size: 13 +fieldset/VERR: + description: DSI Host version register. + fields: + - name: MINREV + description: MINREV. + bit_offset: 0 + bit_size: 4 + - name: MAJREV + description: MAJREV. + bit_offset: 4 + bit_size: 4 +fieldset/VHBPCCR: + description: DSI Host video HBP current configuration register. + fields: + - name: HBP + description: HBP. + bit_offset: 0 + bit_size: 12 +fieldset/VHBPCR: + description: DSI Host video HBP configuration register. + fields: + - name: HBP + description: HBP. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACCR: + description: DSI Host video HSA current configuration register. + fields: + - name: HSA + description: HSA. + bit_offset: 0 + bit_size: 12 +fieldset/VHSACR: + description: DSI Host video HSA configuration register. + fields: + - name: HSA + description: HSA. + bit_offset: 0 + bit_size: 12 +fieldset/VLCCR: + description: DSI Host video line current configuration register. + fields: + - name: HLINE + description: HLINE. + bit_offset: 0 + bit_size: 15 +fieldset/VLCR: + description: DSI Host video line configuration register. + fields: + - name: HLINE + description: HLINE. + bit_offset: 0 + bit_size: 15 +fieldset/VMCCR: + description: DSI Host video mode current configuration register. + fields: + - name: VMT + description: VMT. + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: LPVSAE. + bit_offset: 2 + bit_size: 1 + - name: LPVBPE + description: LPVBPE. + bit_offset: 3 + bit_size: 1 + - name: LPVFPE + description: LPVFPE. + bit_offset: 4 + bit_size: 1 + - name: LPVAE + description: LPVAE. + bit_offset: 5 + bit_size: 1 + - name: LPHBPE + description: LPHBPE. + bit_offset: 6 + bit_size: 1 + - name: LPHFE + description: LPHFE. + bit_offset: 7 + bit_size: 1 + - name: FBTAAE + description: FBTAAE. + bit_offset: 8 + bit_size: 1 + - name: LPCE + description: LPCE. + bit_offset: 9 + bit_size: 1 +fieldset/VMCR: + description: DSI Host video mode configuration register. + fields: + - name: VMT + description: VMT. + bit_offset: 0 + bit_size: 2 + - name: LPVSAE + description: LPVSAE. + bit_offset: 8 + bit_size: 1 + - name: LPVBPE + description: LPVBPE. + bit_offset: 9 + bit_size: 1 + - name: LPVFPE + description: LPVFPE. + bit_offset: 10 + bit_size: 1 + - name: LPVAE + description: LPVAE. + bit_offset: 11 + bit_size: 1 + - name: LPHBPE + description: LPHBPE. + bit_offset: 12 + bit_size: 1 + - name: LPHFPE + description: LPHFPE. + bit_offset: 13 + bit_size: 1 + - name: FBTAAE + description: FBTAAE. + bit_offset: 14 + bit_size: 1 + - name: LPCE + description: LPCE. + bit_offset: 15 + bit_size: 1 + - name: PGE + description: PGE. + bit_offset: 16 + bit_size: 1 + - name: PGM + description: PGM. + bit_offset: 20 + bit_size: 1 + - name: PGO + description: PGO. + bit_offset: 24 + bit_size: 1 +fieldset/VNPCCR: + description: DSI Host video null packet current configuration register. + fields: + - name: NPSIZE + description: NPSIZE. + bit_offset: 0 + bit_size: 13 +fieldset/VNPCR: + description: DSI Host video null packet configuration register. + fields: + - name: NPSIZE + description: NPSIZE. + bit_offset: 0 + bit_size: 13 +fieldset/VPCCR: + description: DSI Host video packet current configuration register. + fields: + - name: VPSIZE + description: VPSIZE. + bit_offset: 0 + bit_size: 14 +fieldset/VPCR: + description: DSI Host video packet configuration register. + fields: + - name: VPSIZE + description: VPSIZE. + bit_offset: 0 + bit_size: 14 +fieldset/VR: + description: DSI Host version register. + fields: + - name: VERSION + description: VERSION. + bit_offset: 0 + bit_size: 32 +fieldset/VSCR: + description: DSI Host video shadow control register. + fields: + - name: EN + description: EN. + bit_offset: 0 + bit_size: 1 + - name: UR + description: UR. + bit_offset: 8 + bit_size: 1 +fieldset/VVACCR: + description: DSI Host video VA current configuration register. + fields: + - name: VA + description: VA. + bit_offset: 0 + bit_size: 14 +fieldset/VVACR: + description: DSI Host video VA configuration register. + fields: + - name: VA + description: VA. + bit_offset: 0 + bit_size: 14 +fieldset/VVBPCCR: + description: DSI Host video VBP current configuration register. + fields: + - name: VBP + description: VBP. + bit_offset: 0 + bit_size: 10 +fieldset/VVBPCR: + description: DSI Host video VBP configuration register. + fields: + - name: VBP + description: VBP. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCCR: + description: DSI Host video VFP current configuration register. + fields: + - name: VFP + description: VFP. + bit_offset: 0 + bit_size: 10 +fieldset/VVFPCR: + description: DSI Host video VFP configuration register. + fields: + - name: VFP + description: VFP. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACCR: + description: DSI Host video VSA current configuration register. + fields: + - name: VSA + description: VSA. + bit_offset: 0 + bit_size: 10 +fieldset/VVSACR: + description: DSI Host video VSA configuration register. + fields: + - name: VSA + description: VSA. + bit_offset: 0 + bit_size: 10 +fieldset/WCFGR: + description: DSI wrapper configuration register. + fields: + - name: DSIM + description: DSIM. + bit_offset: 0 + bit_size: 1 + - name: COLMUX + description: COLMUX. + bit_offset: 1 + bit_size: 3 + - name: TESRC + description: TESRC. + bit_offset: 4 + bit_size: 1 + - name: TEPOL + description: TEPOL. + bit_offset: 5 + bit_size: 1 + - name: AR + description: AR. + bit_offset: 6 + bit_size: 1 + - name: VSPOL + description: VSPOL. + bit_offset: 7 + bit_size: 1 +fieldset/WCR: + description: DSI wrapper control register. + fields: + - name: COLM + description: COLM. + bit_offset: 0 + bit_size: 1 + - name: SHTDN + description: SHTDN. + bit_offset: 1 + bit_size: 1 + - name: LTDCEN + description: LTDCEN. + bit_offset: 2 + bit_size: 1 + - name: DSIEN + description: DSIEN. + bit_offset: 3 + bit_size: 1 +fieldset/WIER: + description: DSI wrapper interrupt enable register. + fields: + - name: TEIE + description: TEIE. + bit_offset: 0 + bit_size: 1 + - name: ERIE + description: ERIE. + bit_offset: 1 + bit_size: 1 + - name: PLLLIE + description: PLLLIE. + bit_offset: 9 + bit_size: 1 + - name: PLLUIE + description: PLLUIE. + bit_offset: 10 + bit_size: 1 + - name: RRIE + description: RRIE. + bit_offset: 13 + bit_size: 1 +fieldset/WIFCR: + description: DSI wrapper interrupt flag clear register. + fields: + - name: CTEIF + description: CTEIF. + bit_offset: 0 + bit_size: 1 + - name: CERIF + description: CERIF. + bit_offset: 1 + bit_size: 1 + - name: CPLLLIF + description: CPLLLIF. + bit_offset: 9 + bit_size: 1 + - name: CPLLUIF + description: CPLLUIF. + bit_offset: 10 + bit_size: 1 + - name: CRRIF + description: CRRIF. + bit_offset: 13 + bit_size: 1 +fieldset/WISR: + description: DSI wrapper interrupt and status register. + fields: + - name: TEIF + description: TEIF. + bit_offset: 0 + bit_size: 1 + - name: ERIF + description: ERIF. + bit_offset: 1 + bit_size: 1 + - name: BUSY + description: BUSY. + bit_offset: 2 + bit_size: 1 + - name: PLLLS + description: PLLLS. + bit_offset: 8 + bit_size: 1 + - name: PLLLIF + description: PLLLIF. + bit_offset: 9 + bit_size: 1 + - name: PLLUIF + description: PLLUIF. + bit_offset: 10 + bit_size: 1 + - name: RRS + description: RRS. + bit_offset: 12 + bit_size: 1 + - name: RRIF + description: RRIF. + bit_offset: 13 + bit_size: 1 +fieldset/WPCR0: + description: DSI wrapper PHY configuration register 0. + fields: + - name: UIX4 + description: UIX4. + bit_offset: 0 + bit_size: 6 + - name: SWCL + description: SWCL. + bit_offset: 6 + bit_size: 1 + - name: SWDL0 + description: SWDL0. + bit_offset: 7 + bit_size: 1 + - name: SWDL1 + description: SWDL1. + bit_offset: 8 + bit_size: 1 + - name: HSICL + description: HSICL. + bit_offset: 9 + bit_size: 1 + - name: HSIDL0 + description: HSIDL0. + bit_offset: 10 + bit_size: 1 + - name: HSIDL1 + description: HSIDL1. + bit_offset: 11 + bit_size: 1 + - name: FTXSMCL + description: FTXSMCL. + bit_offset: 12 + bit_size: 1 + - name: FTXSMDL + description: FTXSMDL. + bit_offset: 13 + bit_size: 1 + - name: CDOFFDL + description: CDOFFDL. + bit_offset: 14 + bit_size: 1 + - name: TDDL + description: TDDL. + bit_offset: 16 + bit_size: 1 +fieldset/WPCR1: + description: This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0). + fields: + - name: SKEWCL + description: SKEWCL. + bit_offset: 0 + bit_size: 2 + - name: SKEWDL + description: SKEWDL. + bit_offset: 2 + bit_size: 2 + - name: LPTXSRCL + description: LPTXSRCL. + bit_offset: 6 + bit_size: 2 + - name: LPTXSRDL + description: LPTXSRDL. + bit_offset: 8 + bit_size: 2 + - name: SDDCCL + description: SDDCCL. + bit_offset: 12 + bit_size: 1 + - name: SDDCDL + description: SDDCDL. + bit_offset: 13 + bit_size: 1 + - name: HSTXSRUCL + description: HSTXSRUCL. + bit_offset: 16 + bit_size: 1 + - name: HSTXSRDCL + description: HSTXSRDCL. + bit_offset: 17 + bit_size: 1 + - name: HSTXSRUDL + description: HSTXSRUDL. + bit_offset: 18 + bit_size: 1 + - name: HSTXSRDDL + description: HSTXSRDDL. + bit_offset: 19 + bit_size: 1 +fieldset/WRPCR: + description: DSI wrapper regulator and PLL control register. + fields: + - name: PLLEN + description: PLLEN. + bit_offset: 0 + bit_size: 1 + - name: NDIV + description: NDIV. + bit_offset: 2 + bit_size: 7 + - name: IDF + description: IDF. + bit_offset: 11 + bit_size: 4 + - name: ODF + description: ODF. + bit_offset: 16 + bit_size: 2 + - name: REGEN + description: REGEN. + bit_offset: 24 + bit_size: 1 + - name: BGREN + description: BGREN. + bit_offset: 28 + bit_size: 1 diff --git a/data/registers/flash_h50.yaml b/data/registers/flash_h50.yaml index 85177d3..713dce2 100644 --- a/data/registers/flash_h50.yaml +++ b/data/registers/flash_h50.yaml @@ -713,27 +713,6 @@ enum/OPTSR_NRST_STDBY: - name: B_0x1 description: no reset generated when entering Standby mode on core domain. value: 1 -enum/PRODUCT_STATE: - bit_size: 8 - variants: - - name: OPEN - description: Open - value: 0xED - - name: PROVISIONING - description: Provisioning - value: 0x17 - - name: IROT_PROVISIONED - description: iROT-Provisioned - value: 0x2E - - name: CLOSED - description: Closed - value: 0x72 - - name: LOCKED - description: Locked - value: 0x5C - - name: REGRESSION - description: Regression - value: 0x9A enum/OPTSR_NRST_STOP: bit_size: 1 variants: @@ -770,3 +749,24 @@ enum/PRIVBB: - name: B_0x1 description: sector y in bank 1 is privileged value: 1 +enum/PRODUCT_STATE: + bit_size: 8 + variants: + - name: PROVISIONING + description: Provisioning + value: 23 + - name: IROT_PROVISIONED + description: iROT-Provisioned + value: 46 + - name: LOCKED + description: Locked + value: 92 + - name: CLOSED + description: Closed + value: 114 + - name: REGRESSION + description: Regression + value: 154 + - name: OPEN + description: Open + value: 237 diff --git a/data/registers/flash_h7rs.yaml b/data/registers/flash_h7rs.yaml new file mode 100644 index 0000000..ffa2410 --- /dev/null +++ b/data/registers/flash_h7rs.yaml @@ -0,0 +1,882 @@ +block/FLASH: + description: Embedded Flash memory. + items: + - name: ACR + description: Access control register. + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: FLASH control key register. + byte_offset: 4 + fieldset: KEYR + - name: CR + description: FLASH control register. + byte_offset: 16 + fieldset: CR + - name: SR + description: FLASH status register. + byte_offset: 20 + fieldset: SR + - name: FCR + description: FLASH status register. + byte_offset: 24 + fieldset: FCR + - name: IER + description: FLASH interrupt enable register. + byte_offset: 32 + fieldset: IER + - name: ISR + description: FLASH interrupt status register. + byte_offset: 36 + fieldset: ISR + - name: ICR + description: FLASH interrupt clear register. + byte_offset: 40 + fieldset: ICR + - name: CRCCR + description: FLASH CRC control register. + byte_offset: 48 + fieldset: CRCCR + - name: CRCSADDR + description: FLASH CRC start address register. + byte_offset: 52 + fieldset: CRCSADDR + - name: CRCEADDR + description: FLASH CRC end address register. + byte_offset: 56 + fieldset: CRCEADDR + - name: CRCDATAR + description: FLASH CRC data register. + byte_offset: 60 + fieldset: CRCDATAR + - name: ECCSFADDR + description: FLASH ECC single error fail address. + byte_offset: 64 + fieldset: ECCSFADDR + - name: ECCDFADDR + description: FLASH ECC double error fail address. + byte_offset: 68 + fieldset: ECCDFADDR + - name: OPTKEYR + description: FLASH options key register. + byte_offset: 256 + fieldset: OPTKEYR + - name: OPTCR + description: FLASH options control register. + byte_offset: 260 + fieldset: OPTCR + - name: OPTISR + description: FLASH options interrupt status register. + byte_offset: 264 + fieldset: OPTISR + - name: OPTICR + description: FLASH options interrupt clear register. + byte_offset: 268 + fieldset: OPTICR + - name: OBKCR + description: FLASH option byte key control register. + byte_offset: 272 + fieldset: OBKCR + - name: OBKDR + description: FLASH option bytes key data register 0. + array: + len: 8 + stride: 4 + byte_offset: 280 + - name: NVSR + description: FLASH non-volatile status register. + byte_offset: 512 + fieldset: NVSR + - name: NVSRP + description: FLASH security status register programming. + byte_offset: 516 + fieldset: NVSRP + - name: ROTSR + description: FLASH RoT status register. + byte_offset: 520 + fieldset: ROTSR + - name: ROTSRP + description: FLASH RoT status register programming. + byte_offset: 524 + fieldset: ROTSRP + - name: OTPLSR + description: FLASH OTP lock status register. + byte_offset: 528 + fieldset: OTPLSR + - name: OTPLSRP + description: FLASH OTP lock status register programming. + byte_offset: 532 + fieldset: OTPLSRP + - name: WRPSR + description: FLASH write protection status register. + byte_offset: 536 + fieldset: WRPSR + - name: WRPSRP + description: FLASH write protection status register programming. + byte_offset: 540 + fieldset: WRPSRP + - name: HDPSR + description: FLASH hide protection status register. + byte_offset: 560 + fieldset: HDPSR + - name: HDPSRP + description: FLASH hide protection status register programming. + byte_offset: 564 + fieldset: HDPSRP + - name: EPOCHSR + description: FLASH epoch status register. + byte_offset: 592 + fieldset: EPOCHSR + - name: EPOCHSRP + description: FLASH RoT status register programming. + byte_offset: 596 + fieldset: EPOCHSRP + - name: OBW1SR + description: FLASH option byte word 1 status register. + byte_offset: 608 + fieldset: OBW1SR + - name: OBW1SRP + description: FLASH option byte word 1 status register programming. + byte_offset: 612 + fieldset: OBW1SRP + - name: OBW2SR + description: FLASH option byte word 2 status register. + byte_offset: 616 + fieldset: OBW2SR + - name: OBW2SRP + description: FLASH option byte word 2 status register programming. + byte_offset: 620 + fieldset: OBW2SRP +fieldset/ACR: + description: Access control register. + fields: + - name: LATENCY + description: 'Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. Please refer to Table 27 for details. ... Note: Embedded Flash does not verify that the configuration is correct.' + bit_offset: 0 + bit_size: 4 + - name: WRHIGHFREQ + description: 'Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to Table 27 for details. Note: Embedded Flash does not verify that the configuration is correct.' + bit_offset: 4 + bit_size: 2 +fieldset/CR: + description: FLASH control register. + fields: + - name: LOCK + description: Configuration lock bit When this bit is set write to all other bits in this register, and to FLASH_IER register, are ignored. Clearing this bit requires the correct write sequence to FLASH_KEYR register (see this register for details). If a wrong sequence is executed, or if the unlock sequence is performed twice, this bit remains locked until the next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register. + bit_offset: 0 + bit_size: 1 + - name: PG + description: Internal buffer control bit Setting this bit enables internal buffer for write operations. This allows preparing program operations even if a sector or bank erase is ongoing. When PG is cleared, the internal buffer is disabled for write operations, and all the data stored in the buffer but not sent to the operation queue are lost. + bit_offset: 1 + bit_size: 1 + - name: SER + description: 'Sector erase request Setting this bit requests a sector erase. Write protection error is triggered when a sector erase is required on at least one protected sector. BER has a higher priority than SER: if both bits are set, the embedded Flash memory executes a bank erase.' + bit_offset: 2 + bit_size: 1 + - name: BER + description: 'Bank erase request Setting this bit requests a bank erase operation (user Flash memory only). Write protection error is triggered when a bank erase is required and some sectors are protected. BER has a higher priority than SER: if both are set, the embedded Flash memory executes a bank erase.' + bit_offset: 3 + bit_size: 1 + - name: FW + description: 'Force write This bit forces a write operation even if the write buffer is not full. In this case all bits not written are set by hardware. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively).' + bit_offset: 4 + bit_size: 1 + - name: START + description: Erase start control bit This bit is used to start a sector erase or a bank erase operation. The embedded Flash memory resets START when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged. + bit_offset: 5 + bit_size: 1 + - name: SSN + description: Sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). ... + bit_offset: 6 + bit_size: 2 + - name: PG_OTP + description: Program Enable for OTP Area Set this bit to enable write operations to OTP area. + bit_offset: 16 + bit_size: 1 + - name: CRC_EN + description: CRC enable Setting this bit enables the CRC calculation. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR register. When CRC calculation is performed it can be disabled by clearing CRC_EN bit. Doing so sets CRCDATA to 0x0, clears CRC configuration and resets the content of FLASH_CRCDATAR register. + bit_offset: 17 + bit_size: 1 + - name: ALL_BANKS + description: All banks select bit When this bit is set the erase is done on all Flash Memory sectors. ALL_BANKS is used only if a bank erase is required (BER=1). In all others operations, this control bit is ignored. + bit_offset: 24 + bit_size: 1 +fieldset/CRCCR: + description: FLASH CRC control register. + fields: + - name: CRC_SECT + description: CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADDR and FLASH_CRCEADDR) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting ADD_SECT bit. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. ... + bit_offset: 0 + bit_size: 2 + - name: CRC_BY_SECT + description: CRC sector mode select bit When this bit is set the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is cleared the CRC calculation is performed on all addresses defined between start and end addresses defined in FLASH_CRCSADDR and FLASH_CRCEADDR registers. + bit_offset: 9 + bit_size: 1 + - name: ADD_SECT + description: CRC sector select bit When this bit is set the sector whose number is written in CRC_SECT is added to the list of sectors on which the CRC is calculated. + bit_offset: 10 + bit_size: 1 + - name: CLEAN_SECT + description: CRC sector list clear bit When this bit is set the list of sectors on which the CRC is calculated is cleared. + bit_offset: 11 + bit_size: 1 + - name: START_CRC + description: CRC start bit START_CRC bit triggers a CRC calculation using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all read accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed. This bit is cleared when CRC computation starts. + bit_offset: 16 + bit_size: 1 + - name: CLEAN_CRC + description: CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register. + bit_offset: 17 + bit_size: 1 + - name: CRC_BURST + description: CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. A Flash word is 128-bit. + bit_offset: 20 + bit_size: 2 + enum: CRC_BURST + - name: ALL_SECT + description: All sectors selection When this bit is set all the sectors in user Flash are added to list of sectors on which the CRC shall be calculated. This bit is cleared when CRC computation starts. + bit_offset: 24 + bit_size: 1 +fieldset/CRCDATAR: + description: FLASH CRC data register. + fields: + - name: CRC_DATA + description: CRC result This bitfield contains the result of the last CRC calculation. The value is valid only when CRC calculation completed (CRCENDF is set in FLASH_ISR register). CRC_DATA is cleared when CRC_EN is cleared in FLASH_CR register (CRC disabled), or when CLEAN_CRC bit is set in FLASH_CRCCR register. + bit_offset: 0 + bit_size: 32 +fieldset/CRCEADDR: + description: FLASH CRC end address register. + fields: + - name: CRC_END_ADDR + description: CRC end address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the Flash word starting the last burst of the CRC calculation. The burst size is defined in CRC_BURST of FLASH_CRCCR register. The least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. + bit_offset: 6 + bit_size: 11 +fieldset/CRCSADDR: + description: FLASH CRC start address register. + fields: + - name: CRC_START_ADDR + description: CRC start address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the first Flash word to use for the CRC calculation, done burst by burst. CRC computation starts at an address aligned to the burst size defined in CRC_BURST of FLASH_CRCCR register. Hence least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. + bit_offset: 6 + bit_size: 11 +fieldset/ECCDFADDR: + description: FLASH ECC double error fail address. + fields: + - name: DED_FADD + description: ECC double error detection fail address When a double ECC detection occurs during a read operation, the DED_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when the DBECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC double error detection error is saved in this register. + bit_offset: 0 + bit_size: 32 +fieldset/ECCSFADDR: + description: FLASH ECC single error fail address. + fields: + - name: SEC_FADD + description: ECC single error correction fail address When a single ECC error correction occurs during a read operation, the SEC_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when SNECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC single error correction error is saved in this register. + bit_offset: 0 + bit_size: 32 +fieldset/EPOCHSR: + description: FLASH epoch status register. + fields: + - name: EPOCH + description: Epoch This value is distributed by hardware to the SAES peripheral. + bit_offset: 0 + bit_size: 24 +fieldset/EPOCHSRP: + description: FLASH RoT status register programming. + fields: + - name: EPOCH + description: Epoch programming Write to change corresponding bits in FLASH_EPOCHSR register. + bit_offset: 0 + bit_size: 24 +fieldset/FCR: + description: FLASH status register. + fields: + - name: RCHECKF + description: Root code check flag clear Set this bit to clear RCHECKF bit in FLASH_SR. + bit_offset: 25 + bit_size: 1 +fieldset/HDPSR: + description: FLASH hide protection status register. + fields: + - name: HDP_AREA_START + description: Hide protection user Flash area start This option sets the start address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:' bit_offset: 11 bit_size: 2 - enum: CH_TR1_PAM + enum: PAM - name: SBX description: source byte exchange within the unaligned half-word of each source word. If set, the two consecutive bytes within the unaligned half-word of each source word are exchanged. If the source data width is shorter than a word, this bit is ignored. bit_offset: 13 @@ -320,7 +320,7 @@ fieldset/CH_TR1: description: 'source allocated port. This bit is used to allocate the master port for the source transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.' bit_offset: 14 bit_size: 1 - enum: CH_TR1_AP + enum: AP - name: SSEC description: 'security attribute of the GPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer from the source is non-secure.' bit_offset: 15 @@ -329,7 +329,7 @@ fieldset/CH_TR1: description: 'binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued.' bit_offset: 16 bit_size: 2 - enum: CH_TR1_DW + enum: DW - name: DINC description: destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. bit_offset: 19 @@ -350,7 +350,7 @@ fieldset/CH_TR1: description: 'destination allocated port. This bit is used to allocate the master port for the destination transfer. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.' bit_offset: 30 bit_size: 1 - enum: CH_TR1_AP + enum: AP - name: DSEC description: 'security attribute of the GPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the GPDMA transfer to the destination is non-secure.' bit_offset: 31 @@ -366,22 +366,22 @@ fieldset/CH_TR2: description: software request. This bit is internally taken into account when CH[x].CR.EN is asserted. bit_offset: 9 bit_size: 1 - enum: CH_TR2_SWREQ + enum: SWREQ - name: DREQ description: 'destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:' bit_offset: 10 bit_size: 1 - enum: CH_TR2_DREQ + enum: DREQ - name: BREQ description: 'Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:' bit_offset: 11 bit_size: 1 - enum: CH_TR2_BREQ + enum: BREQ - name: TRIGM description: 'trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a GPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The GPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.' bit_offset: 14 bit_size: 2 - enum: CH_TR2_TRIGM + enum: TRIGM - name: TRIGSEL description: trigger event input selection. These bits select the trigger event input of the GPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00. bit_offset: 16 @@ -390,12 +390,12 @@ fieldset/CH_TR2: description: trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. bit_offset: 24 bit_size: 2 - enum: CH_TR2_TRIGPOL + enum: TRIGPOL - name: TCEM description: 'transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.' bit_offset: 30 bit_size: 2 - enum: CH_TR2_TCEM + enum: TCEM fieldset/CH_TR3: description: GPDMA channel 14 transfer register 3 fields: @@ -447,7 +447,25 @@ fieldset/SECCFGR: array: len: 16 stride: 1 -enum/CH_BR1_DEC: +enum/AP: + bit_size: 1 + variants: + - name: Port0 + description: port 0 (AHB) allocated + value: 0 + - name: Port1 + description: port 1 (AHB) allocated + value: 1 +enum/BREQ: + bit_size: 1 + variants: + - name: Burst + description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + value: 0 + - name: Block + description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). + value: 1 +enum/DEC: bit_size: 1 variants: - name: Add @@ -456,49 +474,16 @@ enum/CH_BR1_DEC: - name: Subtract description: The address is decremented by the programmed offset. value: 1 -enum/CH_CR_LAP: +enum/DREQ: bit_size: 1 variants: - - name: Port0 - description: port 0 (AHB) allocated + - name: SourcePeripheral + description: selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) value: 0 - - name: Port1 - description: port 1 (AHB) allocated + - name: DestinationPeripheral + description: selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) value: 1 -enum/CH_CR_LSM: - bit_size: 1 - variants: - - name: RunToCompletion - description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. - value: 0 - - name: LinkStep - description: channel executed once for the current LLI - value: 1 -enum/CH_CR_PRIO: - bit_size: 2 - variants: - - name: LowWithLowhWeight - description: low priority, low weight - value: 0 - - name: LowWithMidWeight - description: low priority, mid weight - value: 1 - - name: LowWithHighWeight - description: low priority, high weight - value: 2 - - name: High - description: high priority - value: 3 -enum/CH_TR1_AP: - bit_size: 1 - variants: - - name: Port0 - description: port 0 (AHB) allocated - value: 0 - - name: Port1 - description: port 1 (AHB) allocated - value: 1 -enum/CH_TR1_DW: +enum/DW: bit_size: 2 variants: - name: Byte @@ -510,7 +495,16 @@ enum/CH_TR1_DW: - name: Word description: word (4 bytes) value: 2 -enum/CH_TR1_PAM: +enum/LSM: + bit_size: 1 + variants: + - name: RunToCompletion + description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. + value: 0 + - name: LinkStep + description: channel executed once for the current LLI + value: 1 +enum/PAM: bit_size: 2 variants: - name: ZeroExtendOrLeftTruncate @@ -526,25 +520,22 @@ enum/CH_TR1_PAM: - name: Pack description: source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination value: 2 -enum/CH_TR2_BREQ: - bit_size: 1 +enum/PRIO: + bit_size: 2 variants: - - name: Burst - description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + - name: LowWithLowhWeight + description: low priority, low weight value: 0 - - name: Block - description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). + - name: LowWithMidWeight + description: low priority, mid weight value: 1 -enum/CH_TR2_DREQ: - bit_size: 1 - variants: - - name: SourcePeripheral - description: selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) - value: 0 - - name: DestinationPeripheral - description: selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) - value: 1 -enum/CH_TR2_SWREQ: + - name: LowWithHighWeight + description: low priority, high weight + value: 2 + - name: High + description: high priority + value: 3 +enum/SWREQ: bit_size: 1 variants: - name: Hardware @@ -553,7 +544,7 @@ enum/CH_TR2_SWREQ: - name: Software description: software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored. value: 1 -enum/CH_TR2_TCEM: +enum/TCEM: bit_size: 2 variants: - name: EachBlock @@ -568,7 +559,7 @@ enum/CH_TR2_TCEM: - name: LastLinkedListItem description: 'at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated.' value: 3 -enum/CH_TR2_TRIGM: +enum/TRIGM: bit_size: 2 variants: - name: Block @@ -583,7 +574,7 @@ enum/CH_TR2_TRIGM: - name: Burst description: 'at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger.' value: 3 -enum/CH_TR2_TRIGPOL: +enum/TRIGPOL: bit_size: 2 variants: - name: None diff --git a/data/registers/hsem_v1.yaml b/data/registers/hsem_v1.yaml index 0089381..2bbaa38 100644 --- a/data/registers/hsem_v1.yaml +++ b/data/registers/hsem_v1.yaml @@ -18,34 +18,34 @@ block/HSEM: fieldset: RLR - name: IER description: HSEM Interrupt enable register. + array: + len: 2 + stride: 16 byte_offset: 256 fieldset: IER - array: - len: 2 - stride: 16 - name: ICR description: HSEM Interrupt clear register. - byte_offset: 260 - fieldset: ICR array: len: 2 stride: 16 + byte_offset: 260 + fieldset: ICR - name: ISR description: HSEM Interrupt status register. + array: + len: 2 + stride: 16 byte_offset: 264 access: Read fieldset: ISR + - name: MISR + description: HSEM Masked interrupt status register. array: len: 2 stride: 16 - - name: MISR - description: HSEM Masked interrupt status register. byte_offset: 268 access: Read fieldset: MISR - array: - len: 2 - stride: 16 - name: CR description: HSEM Clear register. byte_offset: 320 @@ -65,6 +65,36 @@ fieldset/CR: description: Semaphore clear Key. bit_offset: 16 bit_size: 16 +fieldset/ICR: + description: HSEM Interrupt clear register. + fields: + - name: ISC + description: Interrupt semaphore x clear bit. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/IER: + description: HSEM Interrupt enable register. + fields: + - name: ISE + description: Interrupt semaphore x enable bit. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/ISR: + description: HSEM Interrupt status register. + fields: + - name: ISF + description: Interrupt semaphore x status bit before enable (mask). + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 fieldset/KEYR: description: HSEM Interrupt clear register. fields: @@ -72,6 +102,16 @@ fieldset/KEYR: description: Semaphore Clear Key. bit_offset: 16 bit_size: 16 +fieldset/MISR: + description: HSEM Masked interrupt status register. + fields: + - name: MISF + description: masked interrupt semaphore x status bit after enable (mask). + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 fieldset/R: description: HSEM register HSEM_R%s HSEM_R31. fields: @@ -102,43 +142,3 @@ fieldset/RLR: description: Lock indication. bit_offset: 31 bit_size: 1 -fieldset/IER: - description: HSEM Interrupt enable register. - fields: - - name: ISE - description: Interrupt semaphore x enable bit. - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/ICR: - description: HSEM Interrupt clear register. - fields: - - name: ISC - description: Interrupt semaphore x clear bit. - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/ISR: - description: HSEM Interrupt status register. - fields: - - name: ISF - description: Interrupt semaphore x status bit before enable (mask). - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/MISR: - description: HSEM Masked interrupt status register. - fields: - - name: MISF - description: masked interrupt semaphore x status bit after enable (mask). - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 diff --git a/data/registers/hsem_v2.yaml b/data/registers/hsem_v2.yaml index 3ec588e..c9d8990 100644 --- a/data/registers/hsem_v2.yaml +++ b/data/registers/hsem_v2.yaml @@ -18,35 +18,35 @@ block/HSEM: fieldset: RLR - name: IER description: HSEM Interrupt enable register. - byte_offset: 256 - fieldset: IER array: len: 1 stride: 16 + byte_offset: 256 + fieldset: IER - name: ICR description: HSEM Interrupt clear register. + array: + len: 1 + stride: 16 byte_offset: 260 access: Read fieldset: ICR + - name: ISR + description: HSEM Interrupt status register. array: len: 1 stride: 16 - - name: ISR - description: HSEM Interrupt status register. byte_offset: 264 access: Read fieldset: ISR + - name: MISR + description: HSEM Masked interrupt status register. array: len: 1 stride: 16 - - name: MISR - description: HSEM Masked interrupt status register. byte_offset: 268 access: Read fieldset: MISR - array: - len: 1 - stride: 16 - name: CR description: HSEM Clear register. byte_offset: 320 @@ -66,6 +66,36 @@ fieldset/CR: description: Semaphore clear Key. bit_offset: 16 bit_size: 16 +fieldset/ICR: + description: HSEM Interrupt clear register. + fields: + - name: ISC + description: Interrupt semaphore x clear bit. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/IER: + description: HSEM Interrupt enable register. + fields: + - name: ISE + description: Interrupt semaphore x enable bit. + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 +fieldset/ISR: + description: HSEM Interrupt status register. + fields: + - name: ISF + description: Interrupt semaphore x status bit before enable (mask). + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 fieldset/KEYR: description: HSEM Interrupt clear register. fields: @@ -73,6 +103,16 @@ fieldset/KEYR: description: Semaphore Clear Key. bit_offset: 16 bit_size: 16 +fieldset/MISR: + description: HSEM Masked interrupt status register. + fields: + - name: MISF + description: masked interrupt semaphore x status bit after enable (mask). + bit_offset: 0 + bit_size: 1 + array: + len: 32 + stride: 1 fieldset/R: description: HSEM register HSEM_R%s HSEM_R31. fields: @@ -103,43 +143,3 @@ fieldset/RLR: description: Lock indication. bit_offset: 31 bit_size: 1 -fieldset/IER: - description: HSEM Interrupt enable register. - fields: - - name: ISE - description: Interrupt semaphore x enable bit. - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/ICR: - description: HSEM Interrupt clear register. - fields: - - name: ISC - description: Interrupt semaphore x clear bit. - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/ISR: - description: HSEM Interrupt status register. - fields: - - name: ISF - description: Interrupt semaphore x status bit before enable (mask). - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 -fieldset/MISR: - description: HSEM Masked interrupt status register. - fields: - - name: MISF - description: masked interrupt semaphore x status bit after enable (mask). - bit_offset: 0 - bit_size: 1 - array: - len: 32 - stride: 1 diff --git a/data/registers/hsem_v3.yaml b/data/registers/hsem_v3.yaml index f754a68..80c06ab 100644 --- a/data/registers/hsem_v3.yaml +++ b/data/registers/hsem_v3.yaml @@ -18,34 +18,34 @@ block/HSEM: fieldset: RLR - name: IER description: HSEM Interrupt enable register. + array: + len: 2 + stride: 16 byte_offset: 256 fieldset: IER - array: - len: 2 - stride: 16 - name: ICR description: HSEM Interrupt clear register. - byte_offset: 260 - fieldset: ICR array: len: 2 stride: 16 + byte_offset: 260 + fieldset: ICR - name: ISR description: HSEM Interrupt status register. + array: + len: 2 + stride: 16 byte_offset: 264 access: Read fieldset: ISR + - name: MISR + description: HSEM Masked interrupt status register. array: len: 2 stride: 16 - - name: MISR - description: HSEM Masked interrupt status register. byte_offset: 268 access: Read fieldset: MISR - array: - len: 2 - stride: 16 - name: CR description: HSEM Clear register. byte_offset: 320 @@ -66,6 +66,36 @@ fieldset/CR: description: Semaphore clear Key. bit_offset: 16 bit_size: 16 +fieldset/ICR: + description: HSEM Interrupt clear register. + fields: + - name: ISC + description: Interrupt semaphore x clear bit. + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/IER: + description: HSEM Interrupt enable register. + fields: + - name: ISE + description: Interrupt semaphore x enable bit. + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/ISR: + description: HSEM Interrupt status register. + fields: + - name: ISF + description: Interrupt semaphore x status bit before enable (mask). + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/KEYR: description: HSEM Interrupt clear register. fields: @@ -73,6 +103,16 @@ fieldset/KEYR: description: Semaphore Clear Key. bit_offset: 16 bit_size: 16 +fieldset/MISR: + description: HSEM Masked interrupt status register. + fields: + - name: MISF + description: masked interrupt semaphore x status bit after enable (mask). + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 fieldset/R: description: HSEM register HSEM_R%s HSEM_R31. fields: @@ -103,43 +143,3 @@ fieldset/RLR: description: Lock indication. bit_offset: 31 bit_size: 1 -fieldset/IER: - description: HSEM Interrupt enable register. - fields: - - name: ISE - description: Interrupt semaphore x enable bit. - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 -fieldset/ICR: - description: HSEM Interrupt clear register. - fields: - - name: ISC - description: Interrupt semaphore x clear bit. - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 -fieldset/ISR: - description: HSEM Interrupt status register. - fields: - - name: ISF - description: Interrupt semaphore x status bit before enable (mask). - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 -fieldset/MISR: - description: HSEM Masked interrupt status register. - fields: - - name: MISF - description: masked interrupt semaphore x status bit after enable (mask). - bit_offset: 0 - bit_size: 1 - array: - len: 16 - stride: 1 diff --git a/data/registers/hsem_v4.yaml b/data/registers/hsem_v4.yaml index 1c0794a..dd1f31a 100644 --- a/data/registers/hsem_v4.yaml +++ b/data/registers/hsem_v4.yaml @@ -18,34 +18,34 @@ block/HSEM: fieldset: RLR - name: IER description: HSEM Interrupt enable register. + array: + len: 1 + stride: 16 byte_offset: 256 fieldset: IER - array: - len: 1 - stride: 16 - name: ICR description: HSEM Interrupt clear register. - byte_offset: 260 - fieldset: ICR array: len: 1 stride: 16 + byte_offset: 260 + fieldset: ICR - name: ISR description: HSEM Interrupt status register. + array: + len: 1 + stride: 16 byte_offset: 264 access: Read fieldset: ISR + - name: MISR + description: HSEM Masked interrupt status register. array: len: 1 stride: 16 - - name: MISR - description: HSEM Masked interrupt status register. byte_offset: 268 access: Read fieldset: MISR - array: - len: 1 - stride: 16 - name: CR description: HSEM Clear register. byte_offset: 320 @@ -55,6 +55,17 @@ block/HSEM: description: HSEM Interrupt clear register. byte_offset: 324 fieldset: KEYR +fieldset/CR: + description: HSEM Clear register. + fields: + - name: COREID + description: COREID. + bit_offset: 8 + bit_size: 4 + - name: KEY + description: Semaphore clear Key. + bit_offset: 16 + bit_size: 16 fieldset/ICR: description: HSEM Interrupt clear register. fields: @@ -85,6 +96,13 @@ fieldset/ISR: array: len: 16 stride: 1 +fieldset/KEYR: + description: HSEM Interrupt clear register. + fields: + - name: KEY + description: Semaphore Clear Key. + bit_offset: 16 + bit_size: 16 fieldset/MISR: description: HSEM Masked interrupt status register. fields: @@ -95,24 +113,6 @@ fieldset/MISR: array: len: 16 stride: 1 -fieldset/CR: - description: HSEM Clear register. - fields: - - name: COREID - description: COREID. - bit_offset: 8 - bit_size: 4 - - name: KEY - description: Semaphore clear Key. - bit_offset: 16 - bit_size: 16 -fieldset/KEYR: - description: HSEM Interrupt clear register. - fields: - - name: KEY - description: Semaphore Clear Key. - bit_offset: 16 - bit_size: 16 fieldset/R: description: HSEM register HSEM_R%s HSEM_R31. fields: diff --git a/data/registers/i2c_v3.yaml b/data/registers/i2c_v3.yaml new file mode 100644 index 0000000..5e875be --- /dev/null +++ b/data/registers/i2c_v3.yaml @@ -0,0 +1,524 @@ +block/I2C: + description: Inter-integrated circuit + items: + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: OAR1 + description: Own address register 1 + byte_offset: 8 + fieldset: OAR1 + - name: OAR2 + description: Own address register 2 + byte_offset: 12 + fieldset: OAR2 + - name: TIMINGR + description: Timing register + byte_offset: 16 + fieldset: TIMINGR + - name: TIMEOUTR + description: Timeout register + byte_offset: 20 + fieldset: TIMEOUTR + - name: ISR + description: Interrupt and Status register + byte_offset: 24 + fieldset: ISR + - name: ICR + description: Interrupt clear register + byte_offset: 28 + fieldset: ICR + - name: PECR + description: PEC register + byte_offset: 32 + fieldset: PECR + - name: RXDR + description: Receive data register + byte_offset: 36 + fieldset: RXDR + - name: TXDR + description: Transmit data register + byte_offset: 40 + fieldset: TXDR +fieldset/CR1: + description: Control register 1 + fields: + - name: PE + description: Peripheral enable + bit_offset: 0 + bit_size: 1 + - name: TXIE + description: TX Interrupt enable + bit_offset: 1 + bit_size: 1 + - name: RXIE + description: RX Interrupt enable + bit_offset: 2 + bit_size: 1 + - name: ADDRIE + description: Address match interrupt enable (slave only) + bit_offset: 3 + bit_size: 1 + - name: NACKIE + description: Not acknowledge received interrupt enable + bit_offset: 4 + bit_size: 1 + - name: STOPIE + description: STOP detection Interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TCIE + description: Transfer Complete interrupt enable + bit_offset: 6 + bit_size: 1 + - name: ERRIE + description: Error interrupts enable + bit_offset: 7 + bit_size: 1 + - name: DNF + description: Digital noise filter + bit_offset: 8 + bit_size: 4 + enum: DNF + - name: ANFOFF + description: Analog noise filter OFF + bit_offset: 12 + bit_size: 1 + - name: TXDMAEN + description: DMA transmission requests enable + bit_offset: 14 + bit_size: 1 + - name: RXDMAEN + description: DMA reception requests enable + bit_offset: 15 + bit_size: 1 + - name: SBC + description: Slave byte control + bit_offset: 16 + bit_size: 1 + - name: NOSTRETCH + description: Clock stretching disable + bit_offset: 17 + bit_size: 1 + - name: GCEN + description: General call enable + bit_offset: 19 + bit_size: 1 + - name: SMBHEN + description: SMBus Host address enable + bit_offset: 20 + bit_size: 1 + - name: SMBDEN + description: SMBus Device Default address enable + bit_offset: 21 + bit_size: 1 + - name: ALERTEN + description: SMBUS alert enable + bit_offset: 22 + bit_size: 1 + - name: PECEN + description: PEC enable + bit_offset: 23 + bit_size: 1 + - name: FMP + description: Fast-mode Plus 20 mA drive enable. + bit_offset: 24 + bit_size: 1 + - name: ADDRACLR + description: Address match flag (ADDR) automatic clear. + bit_offset: 30 + bit_size: 1 + - name: STOPFACLR + description: STOP detection flag (STOPF) automatic clear. + bit_offset: 31 + bit_size: 1 +fieldset/CR2: + description: Control register 2 + fields: + - name: SADD + description: Slave address bit (master mode) + bit_offset: 0 + bit_size: 10 + - name: DIR + description: Transfer direction (master mode) + bit_offset: 10 + bit_size: 1 + enum: DIR + - name: ADD10 + description: 10-bit addressing mode (master mode) + bit_offset: 11 + bit_size: 1 + enum: ADDMODE + - name: HEAD10R + description: 10-bit address header only read direction (master receiver mode) + bit_offset: 12 + bit_size: 1 + enum: HEADR + - name: START + description: Start generation + bit_offset: 13 + bit_size: 1 + - name: STOP + description: Stop generation (master mode) + bit_offset: 14 + bit_size: 1 + - name: NACK + description: NACK generation (slave mode) + bit_offset: 15 + bit_size: 1 + - name: NBYTES + description: Number of bytes + bit_offset: 16 + bit_size: 8 + - name: RELOAD + description: NBYTES reload mode + bit_offset: 24 + bit_size: 1 + enum: RELOAD + - name: AUTOEND + description: Automatic end mode (master mode) + bit_offset: 25 + bit_size: 1 + enum: AUTOEND + - name: PECBYTE + description: Packet error checking byte + bit_offset: 26 + bit_size: 1 +fieldset/ICR: + description: Interrupt clear register + fields: + - name: ADDRCF + description: Address Matched flag clear + bit_offset: 3 + bit_size: 1 + - name: NACKCF + description: Not Acknowledge flag clear + bit_offset: 4 + bit_size: 1 + - name: STOPCF + description: Stop detection flag clear + bit_offset: 5 + bit_size: 1 + - name: BERRCF + description: Bus error flag clear + bit_offset: 8 + bit_size: 1 + - name: ARLOCF + description: Arbitration lost flag clear + bit_offset: 9 + bit_size: 1 + - name: OVRCF + description: Overrun/Underrun flag clear + bit_offset: 10 + bit_size: 1 + - name: PECCF + description: PEC Error flag clear + bit_offset: 11 + bit_size: 1 + - name: TIMOUTCF + description: Timeout detection flag clear + bit_offset: 12 + bit_size: 1 + - name: ALERTCF + description: Alert flag clear + bit_offset: 13 + bit_size: 1 +fieldset/ISR: + description: Interrupt and Status register + fields: + - name: TXE + description: Transmit data register empty (transmitters) + bit_offset: 0 + bit_size: 1 + - name: TXIS + description: Transmit interrupt status (transmitters) + bit_offset: 1 + bit_size: 1 + - name: RXNE + description: Receive data register not empty (receivers) + bit_offset: 2 + bit_size: 1 + - name: ADDR + description: Address matched (slave mode) + bit_offset: 3 + bit_size: 1 + - name: NACKF + description: Not acknowledge received flag + bit_offset: 4 + bit_size: 1 + - name: STOPF + description: Stop detection flag + bit_offset: 5 + bit_size: 1 + - name: TC + description: Transfer Complete (master mode) + bit_offset: 6 + bit_size: 1 + - name: TCR + description: Transfer Complete Reload + bit_offset: 7 + bit_size: 1 + - name: BERR + description: Bus error + bit_offset: 8 + bit_size: 1 + - name: ARLO + description: Arbitration lost + bit_offset: 9 + bit_size: 1 + - name: OVR + description: Overrun/Underrun (slave mode) + bit_offset: 10 + bit_size: 1 + - name: PECERR + description: PEC Error in reception + bit_offset: 11 + bit_size: 1 + - name: TIMEOUT + description: Timeout or t_low detection flag + bit_offset: 12 + bit_size: 1 + - name: ALERT + description: SMBus alert + bit_offset: 13 + bit_size: 1 + - name: BUSY + description: Bus busy + bit_offset: 15 + bit_size: 1 + - name: DIR + description: Transfer direction (Slave mode) + bit_offset: 16 + bit_size: 1 + enum: DIR + - name: ADDCODE + description: Address match code (Slave mode) + bit_offset: 17 + bit_size: 7 +fieldset/OAR1: + description: Own address register 1 + fields: + - name: OA1 + description: Interface address + bit_offset: 0 + bit_size: 10 + - name: OA1MODE + description: Own Address 1 10-bit mode + bit_offset: 10 + bit_size: 1 + enum: ADDMODE + - name: OA1EN + description: Own Address 1 enable + bit_offset: 15 + bit_size: 1 +fieldset/OAR2: + description: Own address register 2 + fields: + - name: OA2 + description: Interface address + bit_offset: 1 + bit_size: 7 + - name: OA2MSK + description: Own Address 2 masks + bit_offset: 8 + bit_size: 3 + enum: OAMSK + - name: OA2EN + description: Own Address 2 enable + bit_offset: 15 + bit_size: 1 +fieldset/PECR: + description: PEC register + fields: + - name: PEC + description: Packet error checking register + bit_offset: 0 + bit_size: 8 +fieldset/RXDR: + description: Receive data register + fields: + - name: RXDATA + description: 8-bit receive data + bit_offset: 0 + bit_size: 8 +fieldset/TIMEOUTR: + description: Timeout register + fields: + - name: TIMEOUTA + description: Bus timeout A + bit_offset: 0 + bit_size: 12 + - name: TIDLE + description: Idle clock timeout detection + bit_offset: 12 + bit_size: 1 + - name: TIMOUTEN + description: Clock timeout enable + bit_offset: 15 + bit_size: 1 + - name: TIMEOUTB + description: Bus timeout B + bit_offset: 16 + bit_size: 12 + - name: TEXTEN + description: Extended clock timeout enable + bit_offset: 31 + bit_size: 1 +fieldset/TIMINGR: + description: Timing register + fields: + - name: SCLL + description: SCL low period (master mode) + bit_offset: 0 + bit_size: 8 + - name: SCLH + description: SCL high period (master mode) + bit_offset: 8 + bit_size: 8 + - name: SDADEL + description: Data hold time + bit_offset: 16 + bit_size: 4 + - name: SCLDEL + description: Data setup time + bit_offset: 20 + bit_size: 4 + - name: PRESC + description: Timing prescaler + bit_offset: 28 + bit_size: 4 +fieldset/TXDR: + description: Transmit data register + fields: + - name: TXDATA + description: 8-bit transmit data + bit_offset: 0 + bit_size: 8 +enum/ADDMODE: + bit_size: 1 + variants: + - name: Bit7 + description: 7-bit addressing mode + value: 0 + - name: Bit10 + description: 10-bit addressing mode + value: 1 +enum/AUTOEND: + bit_size: 1 + variants: + - name: Software + description: 'Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low' + value: 0 + - name: Automatic + description: 'Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred' + value: 1 +enum/DIR: + bit_size: 1 + variants: + - name: Write + description: Write transfer, slave enters receiver mode + value: 0 + - name: Read + description: Read transfer, slave enters transmitter mode + value: 1 +enum/DNF: + bit_size: 4 + variants: + - name: NoFilter + description: Digital filter disabled + value: 0 + - name: Filter1 + description: Digital filter enabled and filtering capability up to 1 tI2CCLK + value: 1 + - name: Filter2 + description: Digital filter enabled and filtering capability up to 2 tI2CCLK + value: 2 + - name: Filter3 + description: Digital filter enabled and filtering capability up to 3 tI2CCLK + value: 3 + - name: Filter4 + description: Digital filter enabled and filtering capability up to 4 tI2CCLK + value: 4 + - name: Filter5 + description: Digital filter enabled and filtering capability up to 5 tI2CCLK + value: 5 + - name: Filter6 + description: Digital filter enabled and filtering capability up to 6 tI2CCLK + value: 6 + - name: Filter7 + description: Digital filter enabled and filtering capability up to 7 tI2CCLK + value: 7 + - name: Filter8 + description: Digital filter enabled and filtering capability up to 8 tI2CCLK + value: 8 + - name: Filter9 + description: Digital filter enabled and filtering capability up to 9 tI2CCLK + value: 9 + - name: Filter10 + description: Digital filter enabled and filtering capability up to 10 tI2CCLK + value: 10 + - name: Filter11 + description: Digital filter enabled and filtering capability up to 11 tI2CCLK + value: 11 + - name: Filter12 + description: Digital filter enabled and filtering capability up to 12 tI2CCLK + value: 12 + - name: Filter13 + description: Digital filter enabled and filtering capability up to 13 tI2CCLK + value: 13 + - name: Filter14 + description: Digital filter enabled and filtering capability up to 14 tI2CCLK + value: 14 + - name: Filter15 + description: Digital filter enabled and filtering capability up to 15 tI2CCLK + value: 15 +enum/HEADR: + bit_size: 1 + variants: + - name: Complete + description: The master sends the complete 10 bit slave address read sequence + value: 0 + - name: Partial + description: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction + value: 1 +enum/OAMSK: + bit_size: 3 + variants: + - name: NoMask + description: No mask + value: 0 + - name: Mask1 + description: OA2[1] is masked and don’t care. Only OA2[7:2] are compared + value: 1 + - name: Mask2 + description: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared + value: 2 + - name: Mask3 + description: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared + value: 3 + - name: Mask4 + description: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared + value: 4 + - name: Mask5 + description: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared + value: 5 + - name: Mask6 + description: OA2[6:1] are masked and don’t care. Only OA2[7] is compared. + value: 6 + - name: Mask7 + description: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged + value: 7 +enum/RELOAD: + bit_size: 1 + variants: + - name: Completed + description: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow) + value: 0 + - name: NotCompleted + description: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded) + value: 1 diff --git a/data/registers/lpdma_v1.yaml b/data/registers/lpdma_v1.yaml new file mode 100644 index 0000000..ecfc8ed --- /dev/null +++ b/data/registers/lpdma_v1.yaml @@ -0,0 +1,543 @@ +block/Channel: + items: + - name: LBAR + description: LPDMA channel 15 linked-list base address register + byte_offset: 0 + fieldset: CH_LBAR + - name: FCR + description: LPDMA channel 15 flag clear register + byte_offset: 12 + fieldset: CH_FCR + - name: SR + description: LPDMA channel 15 status register + byte_offset: 16 + fieldset: CH_SR + - name: CR + description: LPDMA channel 15 control register + byte_offset: 20 + fieldset: CH_CR + - name: TR1 + description: LPDMA channel 15 transfer register 1 + byte_offset: 64 + fieldset: CH_TR1 + - name: TR2 + description: LPDMA channel 15 transfer register 2 + byte_offset: 68 + fieldset: CH_TR2 + - name: BR1 + description: LPDMA channel 15 alternate block register 1 + byte_offset: 72 + fieldset: CH_BR1 + - name: SAR + description: LPDMA channel 15 source address register + byte_offset: 76 + - name: DAR + description: LPDMA channel 15 destination address register + byte_offset: 80 + - name: TR3 + description: LPDMA channel 15 transfer register 3 + byte_offset: 84 + fieldset: CH_TR3 + - name: BR2 + description: LPDMA channel 15 block register 2 + byte_offset: 88 + fieldset: CH_BR2 + - name: LLR + description: LPDMA channel 15 alternate linked-list address register + byte_offset: 124 + fieldset: CH_LLR +block/LPDMA: + description: LPDMA + items: + - name: SECCFGR + description: LPDMA secure configuration register + byte_offset: 0 + fieldset: SECCFGR + - name: PRIVCFGR + description: LPDMA privileged configuration register + byte_offset: 4 + fieldset: PRIVCFGR + - name: RCFGLOCKR + description: LPDMA configuration lock register + byte_offset: 8 + fieldset: RCFGLOCKR + - name: MISR + description: LPDMA non-secure masked interrupt status register + byte_offset: 12 + fieldset: MISR + - name: SMISR + description: LPDMA secure masked interrupt status register + byte_offset: 16 + fieldset: MISR + - name: CH + array: + len: 4 + stride: 128 + byte_offset: 80 + block: Channel +fieldset/CH_BR1: + description: LPDMA channel 15 alternate block register 1 + fields: + - name: BNDT + description: 'block number of data bytes to transfer from the source. Block size transferred from the source. When the channel is enabled, this field becomes read-only and is decremented, indicating the remaining number of data items in the current source block to be transferred. BNDT[15:0] is programmed in number of bytes, maximum source block size is 64 Kbytes -1. Once the last data transfer is completed (BNDT[15:0] = 0): - if CH[x].LLR.UB1 = 1, this field is updated by the LLI in the memory. - if CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. - if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). - if CH[x].LLR = 0, this field is kept as zero following the last LLI data transfer. Note: A non-null source block size must be a multiple of the source data width (BNDT[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued. When configured in packing mode (CH[x].TR1.PAM[1]=1 and destination data width different from source data width), a non-null source block size must be a multiple of the destination data width (BNDT[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.' + bit_offset: 0 + bit_size: 16 + - name: BRC + description: 'Block repeat counter. This field contains the number of repetitions of the current block (0 to 2047). When the channel is enabled, this field becomes read-only. After decrements, this field indicates the remaining number of blocks, excluding the current one. This counter is hardware decremented for each completed block transfer. Once the last block transfer is completed (BRC[10:0] = BNDT[15:0] = 0): If CH[x].LLR.UB1 = 1, all CH[x].BR1 fields are updated by the next LLI in the memory. If CH[x].LLR.UB1 = 0 and if there is at least one not null Uxx update bit, this field is internally restored to the programmed value. if all CH[x].LLR.Uxx = 0 and if CH[x].LLR.LA[15:0] ≠ 0, this field is internally restored to the programmed value (infinite/continuous last LLI). if CH[x].LLR = 0, this field is kept as zero following the last LLI and data transfer.' + bit_offset: 16 + bit_size: 11 + - name: SDEC + description: source address decrement + bit_offset: 28 + bit_size: 1 + enum: DEC + - name: DDEC + description: destination address decrement + bit_offset: 29 + bit_size: 1 + enum: DEC + - name: BRSDEC + description: 'Block repeat source address decrement. Note: On top of this increment/decrement (depending on BRSDEC), CH[x].SAR is in the same time also updated by the increment/decrement (depending on SDEC) of the CH[x].TR3.SAO value, as it is done after any programmed burst transfer.' + bit_offset: 30 + bit_size: 1 + enum: DEC + - name: BRDDEC + description: 'Block repeat destination address decrement. Note: On top of this increment/decrement (depending on BRDDEC), CH[x].DAR is in the same time also updated by the increment/decrement (depending on DDEC) of the CH[x].TR3.DAO value, as it is usually done at the end of each programmed burst transfer.' + bit_offset: 31 + bit_size: 1 + enum: DEC +fieldset/CH_BR2: + description: LPDMA channel 12 block register 2 + fields: + - name: BRSAO + description: 'Block repeated source address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRSDEC) the current source address (CH[x].SAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (BRSAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and no transfer is issued.' + bit_offset: 0 + bit_size: 16 + - name: BRDAO + description: 'Block repeated destination address offset. For a channel with 2D addressing capability, this field is used to update (by addition or subtraction depending on CH[x].BR1.BRDDEC) the current destination address (CH[x].DAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (BRDAO[2:0] versus CH[x].TR1.DDW[1:0]). Else a user setting error is reported and no transfer is issued.' + bit_offset: 16 + bit_size: 16 +fieldset/CH_CR: + description: LPDMA channel 11 control register + fields: + - name: EN + description: 'enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.' + bit_offset: 0 + bit_size: 1 + - name: RESET + description: 'reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ).' + bit_offset: 1 + bit_size: 1 + - name: SUSP + description: 'suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going LPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .' + bit_offset: 2 + bit_size: 1 + - name: TCIE + description: transfer complete interrupt enable + bit_offset: 8 + bit_size: 1 + - name: HTIE + description: half transfer complete interrupt enable + bit_offset: 9 + bit_size: 1 + - name: DTEIE + description: data transfer error interrupt enable + bit_offset: 10 + bit_size: 1 + - name: ULEIE + description: update link transfer error interrupt enable + bit_offset: 11 + bit_size: 1 + - name: USEIE + description: user setting error interrupt enable + bit_offset: 12 + bit_size: 1 + - name: SUSPIE + description: completed suspension interrupt enable + bit_offset: 13 + bit_size: 1 + - name: TOIE + description: trigger overrun interrupt enable + bit_offset: 14 + bit_size: 1 + - name: LSM + description: 'Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.' + bit_offset: 16 + bit_size: 1 + enum: LSM + - name: PRIO + description: 'priority level of the channel x LPDMA transfer versus others. Note: This bit must be written when EN = 0. This bit is read-only when EN = 1.' + bit_offset: 22 + bit_size: 2 + enum: PRIO +fieldset/CH_FCR: + description: LPDMA channel 7 flag clear register + fields: + - name: TCF + description: transfer complete flag clear + bit_offset: 8 + bit_size: 1 + - name: HTF + description: half transfer flag clear + bit_offset: 9 + bit_size: 1 + - name: DTEF + description: data transfer error flag clear + bit_offset: 10 + bit_size: 1 + - name: ULEF + description: update link transfer error flag clear + bit_offset: 11 + bit_size: 1 + - name: USEF + description: user setting error flag clear + bit_offset: 12 + bit_size: 1 + - name: SUSPF + description: completed suspension flag clear + bit_offset: 13 + bit_size: 1 + - name: TOF + description: trigger overrun flag clear + bit_offset: 14 + bit_size: 1 +fieldset/CH_LBAR: + description: LPDMA channel 14 linked-list base address register + fields: + - name: LBA + description: linked-list base address of LPDMA channel x + bit_offset: 16 + bit_size: 16 +fieldset/CH_LLR: + description: LPDMA channel 15 alternate linked-list address register + fields: + - name: LA + description: 'pointer (16-bit low-significant address) to the next linked-list data structure. If UT1 = UT2 = UB1 = USA = UDA = ULL = 0 and if LA[15:20] = 0, the current LLI is the last one. The channel transfer is completed without any update of the linked-list LPDMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure is automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list LPDMA internal register file (CH[x].CTR1, CH[x].TR2, CH[x].BR1, CH[x].SAR, CH[x].DAR and CH[x].LLR). Note: The user must program the pointer to be 32-bit aligned. The two low-significant bits are write ignored.' + bit_offset: 2 + bit_size: 14 + - name: ULL + description: Update CH[x].LLR register from memory. This bit is used to control the update of CH[x].LLR from the memory during the link transfer. + bit_offset: 16 + bit_size: 1 + - name: UB2 + description: Update CH[x].BR2 from memory. This bit controls the update of CH[x].BR2 from the memory during the link transfer. + bit_offset: 25 + bit_size: 1 + - name: UT3 + description: Update CH[x].TR3 from memory. This bit controls the update of CH[x].TR3 from the memory during the link transfer. + bit_offset: 26 + bit_size: 1 + - name: UDA + description: Update CH[x].DAR register from memory. This bit is used to control the update of CH[x].DAR from the memory during the link transfer. + bit_offset: 27 + bit_size: 1 + - name: USA + description: update CH[x].SAR from memory. This bit controls the update of CH[x].SAR from the memory during the link transfer. + bit_offset: 28 + bit_size: 1 + - name: UB1 + description: Update CH[x].BR1 from memory. This bit controls the update of CH[x].BR1 from the memory during the link transfer. If UB1 = 0 and if CH[x].LLR ≠ 0, the linked-list is not completed. CH[x].BR1.BNDT[15:0] is then restored to the programmed value after data transfer is completed and before the link transfer. + bit_offset: 29 + bit_size: 1 + - name: UT2 + description: Update CH[x].TR2 from memory. This bit controls the update of CH[x].TR2 from the memory during the link transfer. + bit_offset: 30 + bit_size: 1 + - name: UT1 + description: Update CH[x].TR1 from memory. This bit controls the update of CH[x].TR1 from the memory during the link transfer. + bit_offset: 31 + bit_size: 1 +fieldset/CH_SR: + description: LPDMA channel 15 status register + fields: + - name: IDLEF + description: idle flag. This idle flag is de-asserted by hardware when the channel is enabled (CH[x].CR.EN = 1) with a valid channel configuration (no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (in suspended or disabled state). + bit_offset: 0 + bit_size: 1 + - name: TCF + description: transfer complete flag. A transfer complete event is either a block transfer complete, a 2D/repeated block transfer complete, a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). + bit_offset: 8 + bit_size: 1 + - name: HTF + description: half transfer flag. An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode (CH[x].TR2.TCEM[1:0]). An half block transfer occurs when half of the bytes of the source block size (rounded up integer of CH[x].BR1.BNDT[15:0]/2) has been transferred to the destination. An half 2D/repeated block transfer occurs when half of the repeated blocks (rounded up integer of (CH[x].BR1.BRC[10:0]+1)/2)) has been transferred to the destination. + bit_offset: 9 + bit_size: 1 + - name: DTEF + description: data transfer error flag + bit_offset: 10 + bit_size: 1 + - name: ULEF + description: update link transfer error flag + bit_offset: 11 + bit_size: 1 + - name: USEF + description: user setting error flag + bit_offset: 12 + bit_size: 1 + - name: SUSPF + description: completed suspension flag + bit_offset: 13 + bit_size: 1 + - name: TOF + description: trigger overrun flag + bit_offset: 14 + bit_size: 1 +fieldset/CH_TR1: + description: LPDMA channel 8 transfer register 1 + fields: + - name: SDW + description: 'binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.' + bit_offset: 0 + bit_size: 2 + enum: DW + - name: SINC + description: source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + bit_offset: 3 + bit_size: 1 + - name: PAM + description: 'padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:' + bit_offset: 11 + bit_size: 2 + enum: PAM + - name: SSEC + description: 'security attribute of the LPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.' + bit_offset: 15 + bit_size: 1 + - name: DDW + description: 'binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued.' + bit_offset: 16 + bit_size: 2 + enum: DW + - name: DINC + description: destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. + bit_offset: 19 + bit_size: 1 + - name: DSEC + description: 'security attribute of the LPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.' + bit_offset: 31 + bit_size: 1 +fieldset/CH_TR2: + description: LPDMA channel 10 transfer register 2 + fields: + - name: REQSEL + description: LPDMA hardware request selection. These bits are ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else, the selected hardware request is internally taken into account as per . The user must not assign a same input hardware request (same REQSEL[6:0] value) to different active LPDMA channels (CH[x].CR.EN = 1 and CH[x].TR2.SWREQ = 0 for these channels). LPDMA is not intended to hardware support the case of simultaneous enabled channels incorrectly configured with a same hardware peripheral request signal, and there is no user setting error reporting. + bit_offset: 0 + bit_size: 7 + - name: SWREQ + description: software request. This bit is internally taken into account when CH[x].CR.EN is asserted. + bit_offset: 9 + bit_size: 1 + enum: SWREQ + - name: DREQ + description: 'destination hardware request. This bit is ignored if channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer). Else: Note:' + bit_offset: 10 + bit_size: 1 + enum: DREQ + - name: BREQ + description: 'Block hardware request. If the channel x is activated (CH[x].CR.EN asserted) with SWREQ = 1 (software request for a memory-to-memory transfer), this bit is ignored. Else:' + bit_offset: 11 + bit_size: 1 + enum: BREQ + - name: TRIGM + description: 'trigger mode. These bits define the transfer granularity for its conditioning by the trigger. If the channel x is enabled (CH[x].CR.EN asserted) with TRIGPOL[1:0] = 00 or 11, these TRIGM[1:0] bits are ignored. Else, a LPDMA transfer is conditioned by at least one trigger hit: first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. – If the peripheral is programmed as a source (DREQ = 0) of the LLI data transfer, each programmed burst read is conditioned. – If the peripheral is programmed as a destination (DREQ = 1) of the LLI data transfer, each programmed burst write is conditioned. The first memory burst read of a (possibly 2D/repeated) block, also named as the first ready FIFO-based source burst, is gated by the occurrence of both the hardware request and the first trigger hit. The LPDMA monitoring of a trigger for channel x is started when the channel is enabled/loaded with a new active trigger configuration: rising or falling edge on a selected trigger (TRIGPOL[1:0] = 01 or respectively TRIGPOL[1:0] = 10). The monitoring of this trigger is kept active during the triggered and uncompleted (data or link) transfer; and if a new trigger is detected then, this hit is internally memorized to grant the next transfer, as long as the defined rising or falling edge is not modified, and the TRIGSEL[5:0] is not modified, and the channel is enabled. Transferring a next LLIn+1 that updates the CH[x].TR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0], resets the monitoring, trashing the memorized hit of the formerly defined LLIn trigger. After a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, hitn+2 is lost and not memorized.memorized. A trigger overrun flag is reported (CH[x].SR.TOF =1 ), and an interrupt is generated if enabled (CH[x].CR.TOIE = 1). The channel is not automatically disabled by hardware due to a trigger overrun. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0] = 11 and (SWREQ =1 or (SWREQ = 0 and DREQ =0 )), the shortened burst transfer (by singles or/and by bursts of lower length) is conditioned once by the trigger. When the programmed destination burst is internally shortened by singles or/and by bursts of lower length (versus FIFO size, versus block size, 1-Kbyte boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0] = 11 and SWREQ = 0 and DREQ = 1), this shortened destination burst transfer is conditioned once by the trigger.' + bit_offset: 14 + bit_size: 2 + enum: TRIGM + - name: TRIGSEL + description: trigger event input selection. These bits select the trigger event input of the LPDMA transfer (as per ), with an active trigger event if TRIGPOL[1:0] ≠ 00. + bit_offset: 16 + bit_size: 6 + - name: TRIGPOL + description: trigger event polarity. These bits define the polarity of the selected trigger event input defined by TRIGSEL[5:0]. + bit_offset: 24 + bit_size: 2 + enum: TRIGPOL + - name: TCEM + description: 'transfer complete event mode. These bits define the transfer granularity for the transfer complete and half transfer complete events generation. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] = 0), then neither the complete transfer event nor the half transfer event is generated. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with CH[x].BR1.BNDT[15:0] =0 ), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1.' + bit_offset: 30 + bit_size: 2 + enum: TCEM +fieldset/CH_TR3: + description: LPDMA channel 14 transfer register 3 + fields: + - name: SAO + description: 'source address offset increment. The source address, pointed by CH[x].SAR, is incremented or decremented (depending on CH[x].BR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.SINC = 1). Note: A source address offset must be aligned with the programmed data width of a source burst (SAO[2:0] versus CH[x].TR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional CH[x].TR3.SAO[12:0] is not applied.' + bit_offset: 0 + bit_size: 13 + - name: DAO + description: 'destination address offset increment. The destination address, pointed by CH[x].DAR, is incremented or decremented (depending on CH[x].BR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode (CH[x].TR1.DINC = 1). Note: A destination address offset must be aligned with the programmed data width of a destination burst (DAO[2:0] versus CH[x].TR1.DDW[1:0]). Else, a user setting error is reported and no transfer is issued.' + bit_offset: 16 + bit_size: 13 +fieldset/MISR: + description: LPDMA secure masked interrupt status register + fields: + - name: MIS + description: MIS0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/PRIVCFGR: + description: LPDMA privileged configuration register + fields: + - name: PRIV + description: PRIV0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/RCFGLOCKR: + description: LPDMA configuration lock register + fields: + - name: LOCK + description: LOCK0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/SECCFGR: + description: LPDMA secure configuration register + fields: + - name: SEC + description: SEC0 + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +enum/BREQ: + bit_size: 1 + variants: + - name: Burst + description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. + value: 0 + - name: Block + description: the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see ). + value: 1 +enum/DEC: + bit_size: 1 + variants: + - name: Add + description: The address is incremented by the programmed offset. + value: 0 + - name: Subtract + description: The address is decremented by the programmed offset. + value: 1 +enum/DREQ: + bit_size: 1 + variants: + - name: SourcePeripheral + description: selected hardware request driven by a source peripheral (request signal taken into account by the LPDMA transfer scheduler over the source/read port) + value: 0 + - name: DestinationPeripheral + description: selected hardware request driven by a destination peripheral (request signal taken into account by the LPDMA transfer scheduler over the destination/write port) + value: 1 +enum/DW: + bit_size: 2 + variants: + - name: Byte + description: byte + value: 0 + - name: HalfWord + description: half-word (2 bytes) + value: 1 + - name: Word + description: word (4 bytes) + value: 2 +enum/LSM: + bit_size: 1 + variants: + - name: RunToCompletion + description: channel executed for the full linked-list and completed at the end of the last LLI (CH[x].LLR = 0). The 16 low-significant bits of the link address are null (LA[15:0] = 0) and all the update bits are null (UT1 =UB1 = UT2 = USA = UDA = ULL = 0 and UT3 = UB2 = 0 if present). Then CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. + value: 0 + - name: LinkStep + description: channel executed once for the current LLI + value: 1 +enum/PAM: + bit_size: 2 + variants: + - name: ZeroExtendOrLeftTruncate + description: |- + If destination is wider: source data is transferred as right aligned, padded with 0s up to the destination data width + If source is wider: source data is transferred as right aligned, left-truncated down to the destination data width + value: 0 + - name: SignExtendOrRightTruncate + description: |- + If destination is wider: source data is transferred as right aligned, sign extended up to the destination data width + If source is wider: source data is transferred as left-aligned, right-truncated down to the destination data width + value: 1 + - name: Pack + description: source data is FIFO queued and packed/unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination + value: 2 +enum/PRIO: + bit_size: 2 + variants: + - name: LowWithLowhWeight + description: low priority, low weight + value: 0 + - name: LowWithMidWeight + description: low priority, mid weight + value: 1 + - name: LowWithHighWeight + description: low priority, high weight + value: 2 + - name: High + description: high priority + value: 3 +enum/SWREQ: + bit_size: 1 + variants: + - name: Hardware + description: no software request. The selected hardware request REQSEL[6:0] is taken into account. + value: 0 + - name: Software + description: software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[6:0] is ignored. + value: 1 +enum/TCEM: + bit_size: 2 + variants: + - name: EachBlock + description: 'at block level (when CH[x].BR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block.' + value: 0 + - name: Each2DBlock + description: channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when CH[x].BR1.BRC[10:0] = 0 and CH[x].BR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block. + value: 1 + - name: EachLinkedListItem + description: 'at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer.' + value: 2 + - name: LastLinkedListItem + description: 'at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address CH[x].LLR.LA[15:2] to zero and clears all the CH[x].LLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated.' + value: 3 +enum/TRIGM: + bit_size: 2 + variants: + - name: Block + description: 'at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with CH[x].BR1.BRC[10:0] ≠ 0).' + value: 0 + - name: 2DBlock + description: channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the + value: 1 + - name: LinkedListItem + description: 'at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned.' + value: 2 + - name: Burst + description: 'at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger.' + value: 3 +enum/TRIGPOL: + bit_size: 2 + variants: + - name: None + description: no trigger (masked trigger event) + value: 0 + - name: RisingEdge + description: trigger on the rising edge + value: 1 + - name: FallingEdge + description: trigger on the falling edge + value: 2 + - name: NoneAlt + description: same as 00 + value: 3 diff --git a/data/registers/lptim_v1.yaml b/data/registers/lptim_v1.yaml index 7a85c84..f38b5bb 100644 --- a/data/registers/lptim_v1.yaml +++ b/data/registers/lptim_v1.yaml @@ -1,222 +1,320 @@ block/LPTIM: - description: Low power timer + description: Low power timer with Output Compare items: - name: ISR - description: Interrupt and Status Register + description: LPTIM interrupt and status register. byte_offset: 0 - access: Read fieldset: ISR - name: ICR - description: Interrupt Clear Register + description: LPTIM interrupt clear register. byte_offset: 4 - access: Write fieldset: ICR - name: IER - description: Interrupt Enable Register + description: LPTIM interrupt enable register. byte_offset: 8 fieldset: IER - name: CFGR - description: Configuration Register + description: LPTIM configuration register. byte_offset: 12 fieldset: CFGR - name: CR - description: Control Register + description: LPTIM control register. byte_offset: 16 fieldset: CR - name: CMP - description: Compare Register + description: LPTIM compare register 1. byte_offset: 20 fieldset: CMP - name: ARR - description: Autoreload Register + description: LPTIM autoreload register. byte_offset: 24 fieldset: ARR - name: CNT - description: Counter Register + description: LPTIM counter register. byte_offset: 28 - access: Read fieldset: CNT fieldset/ARR: - description: Autoreload Register + description: LPTIM autoreload register. fields: - name: ARR - description: Auto reload value + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. bit_offset: 0 bit_size: 16 fieldset/CFGR: - description: Configuration Register + description: LPTIM configuration register. fields: - name: CKSEL - description: Clock selector + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. bit_offset: 0 bit_size: 1 + enum: ClockSource - name: CKPOL - description: Clock Polarity + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' bit_offset: 1 bit_size: 2 + enum: CKPOL - name: CKFLT - description: Configurable digital filter for external clock + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. bit_offset: 3 bit_size: 2 + enum: Filter - name: TRGFLT - description: Configurable digital filter for trigger + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. bit_offset: 6 bit_size: 2 + enum: Filter - name: PRESC - description: Clock prescaler + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. bit_offset: 9 bit_size: 3 + enum: PRESC - name: TRIGSEL - description: Trigger selector + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' bit_offset: 13 bit_size: 3 - name: TRIGEN - description: Trigger enable and polarity + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. bit_offset: 17 bit_size: 2 + enum: TRIGEN - name: TIMOUT - description: Timeout enable + description: Timeout enable The TIMOUT bit controls the Timeout feature. bit_offset: 19 bit_size: 1 - name: WAVE - description: Waveform shape + description: Waveform shape The WAVE bit controls the output shape. bit_offset: 20 bit_size: 1 - name: WAVPOL - description: Waveform shape polarity + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' bit_offset: 21 bit_size: 1 + enum: WAVPOL - name: PRELOAD - description: Registers update mode + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. bit_offset: 22 bit_size: 1 - name: COUNTMODE - description: counter mode enabled + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. bit_offset: 23 bit_size: 1 + enum: ClockSource - name: ENC - description: Encoder mode enable + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 24 bit_size: 1 fieldset/CMP: - description: Compare Register + description: LPTIM compare register 1. fields: - name: CMP - description: Compare value + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' bit_offset: 0 bit_size: 16 fieldset/CNT: - description: Counter Register + description: LPTIM counter register. fields: - name: CNT - description: Counter value + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. bit_offset: 0 bit_size: 16 fieldset/CR: - description: Control Register + description: LPTIM control register. fields: - name: ENABLE - description: LPTIM Enable + description: LPTIM enable The ENABLE bit is set and cleared by software. bit_offset: 0 bit_size: 1 - name: SNGSTRT - description: LPTIM start in single mode + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. bit_offset: 1 bit_size: 1 - name: CNTSTRT - description: Timer start in continuous mode + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. bit_offset: 2 bit_size: 1 fieldset/ICR: - description: Interrupt Clear Register + description: LPTIM interrupt clear register. fields: - - name: CMPMCF - description: compare match Clear Flag + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. bit_offset: 0 bit_size: 1 + array: + len: 1 + stride: 9 - name: ARRMCF - description: Autoreload match Clear Flag + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. bit_offset: 1 bit_size: 1 - name: EXTTRIGCF - description: External trigger valid edge Clear Flag + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. bit_offset: 2 bit_size: 1 - name: CMPOKCF - description: Compare register update OK Clear Flag + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. bit_offset: 3 bit_size: 1 + array: + len: 1 + stride: 16 - name: ARROKCF - description: Autoreload register update OK Clear Flag + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. bit_offset: 4 bit_size: 1 - name: UPCF - description: Direction change to UP Clear Flag + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 5 bit_size: 1 - name: DOWNCF - description: Direction change to down Clear Flag + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 6 bit_size: 1 fieldset/IER: - description: Interrupt Enable Register + description: LPTIM interrupt enable register. fields: - - name: CMPMIE - description: Compare match Interrupt Enable + - name: CCIE + description: Capture/compare 1 interrupt enable. bit_offset: 0 bit_size: 1 + array: + len: 1 + stride: 9 - name: ARRMIE - description: Autoreload match Interrupt Enable + description: Autoreload match Interrupt Enable. bit_offset: 1 bit_size: 1 - name: EXTTRIGIE - description: External trigger valid edge Interrupt Enable + description: External trigger valid edge Interrupt Enable. bit_offset: 2 bit_size: 1 - name: CMPOKIE - description: Compare register update OK Interrupt Enable + description: Compare register 1 update OK interrupt enable. bit_offset: 3 bit_size: 1 + array: + len: 1 + stride: 16 - name: ARROKIE - description: Autoreload register update OK Interrupt Enable + description: Autoreload register update OK Interrupt Enable. bit_offset: 4 bit_size: 1 - name: UPIE - description: Direction change to UP Interrupt Enable + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 5 bit_size: 1 - name: DOWNIE - description: Direction change to down Interrupt Enable + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 6 bit_size: 1 fieldset/ISR: - description: Interrupt and Status Register + description: LPTIM interrupt and status register. fields: - - name: CMPM - description: Compare match + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. bit_offset: 0 bit_size: 1 + array: + len: 1 + stride: 9 - name: ARRM - description: Autoreload match + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. bit_offset: 1 bit_size: 1 - name: EXTTRIG - description: External trigger edge event + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. bit_offset: 2 bit_size: 1 - name: CMPOK - description: Compare register update OK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. bit_offset: 3 bit_size: 1 + array: + len: 1 + stride: 16 - name: ARROK - description: Autoreload register update OK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. bit_offset: 4 bit_size: 1 - name: UP - description: Counter direction change down to up + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 5 bit_size: 1 - name: DOWN - description: Counter direction change up to down + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 6 bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/data/registers/lptim_v1a.yaml b/data/registers/lptim_v1a.yaml new file mode 100644 index 0000000..b822348 --- /dev/null +++ b/data/registers/lptim_v1a.yaml @@ -0,0 +1,323 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/data/registers/lptim_v1b.yaml b/data/registers/lptim_v1b.yaml new file mode 100644 index 0000000..5574889 --- /dev/null +++ b/data/registers/lptim_v1b.yaml @@ -0,0 +1,331 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/data/registers/lptim_v1b_g4.yaml b/data/registers/lptim_v1b_g4.yaml new file mode 100644 index 0000000..3aaf7fa --- /dev/null +++ b/data/registers/lptim_v1b_g4.yaml @@ -0,0 +1,335 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: + - start: 13 + end: 15 + - start: 29 + end: 29 + bit_size: 4 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/data/registers/lptim_v1b_h7.yaml b/data/registers/lptim_v1b_h7.yaml new file mode 100644 index 0000000..503f17e --- /dev/null +++ b/data/registers/lptim_v1b_h7.yaml @@ -0,0 +1,342 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: CFGR2 + description: LPTIM configuration register 2. + byte_offset: 36 + fieldset: CFGR2 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CFGR2: + description: LPTIM configuration register 2. + fields: + - name: INSEL + description: LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 4 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/data/registers/lptim_v1c.yaml b/data/registers/lptim_v1c.yaml new file mode 100644 index 0000000..5c9717d --- /dev/null +++ b/data/registers/lptim_v1c.yaml @@ -0,0 +1,366 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 + - name: RCR + description: LPTIM repetition register. + byte_offset: 40 + fieldset: RCR +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UECF + description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + bit_offset: 7 + bit_size: 1 + - name: REPOKCF + description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + bit_offset: 8 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UEIE + description: Update event interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: REPOKIE + description: Repetition register update OK interrupt Enable. + bit_offset: 8 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UE + description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + bit_offset: 7 + bit_size: 1 + - name: REPOK + description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + bit_offset: 8 + bit_size: 1 +fieldset/RCR: + description: LPTIM repetition register. + fields: + - name: REP + description: Repetition register value REP is the repetition value for the LPTIM. + bit_offset: 0 + bit_size: 8 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/data/registers/lptim_v2a.yaml b/data/registers/lptim_v2a.yaml index 614eb21..e19ed1c 100644 --- a/data/registers/lptim_v2a.yaml +++ b/data/registers/lptim_v2a.yaml @@ -1,198 +1,292 @@ -block/LPTIM: - description: Low power timer. +block/LPTIM_ADV: + extends: LPTIM_BASIC + description: Low power timer with Output Compare items: - name: ISR - description: Interrupt and Status Register. + description: LPTIM interrupt and status register. byte_offset: 0 - access: Read - fieldset: ISR + fieldset: ISR_ADV - name: ICR - description: Interrupt Clear Register. + description: LPTIM interrupt clear register. byte_offset: 4 - access: Write - fieldset: ICR - - name: IER - description: Interrupt Enable Register. + fieldset: ICR_ADV + - name: DIER + description: LPTIM interrupt enable register. byte_offset: 8 - fieldset: IER + fieldset: DIER_ADV + - name: CCR + description: LPTIM compare register 1. + array: + len: 2 + stride: 32 + byte_offset: 20 + fieldset: CCR + - name: CCMR + description: LPTIM capture/compare mode register 1. + byte_offset: 44 + fieldset: CCMR +block/LPTIM_BASIC: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR_BASIC + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR_BASIC + - name: DIER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER_BASIC - name: CFGR - description: Configuration Register. + description: LPTIM configuration register. byte_offset: 12 fieldset: CFGR - name: CR - description: Control Register. + description: LPTIM control register. byte_offset: 16 fieldset: CR - - name: CMP - description: Compare Register. + - name: CCR + description: LPTIM compare register 1. + array: + len: 1 + stride: 32 byte_offset: 20 - fieldset: CMP + fieldset: CCR - name: ARR - description: Autoreload Register. + description: LPTIM autoreload register. byte_offset: 24 fieldset: ARR - name: CNT - description: Counter Register. + description: LPTIM counter register. byte_offset: 28 - access: Read fieldset: CNT - - name: OR - description: LPTIM option register. - byte_offset: 32 + - name: CFGR2 + description: LPTIM configuration register 2. + byte_offset: 36 + fieldset: CFGR2 - name: RCR description: LPTIM repetition register. byte_offset: 40 fieldset: RCR fieldset/ARR: - description: Autoreload Register. + description: LPTIM autoreload register. fields: - name: ARR - description: Auto reload value. + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CCMR: + description: LPTIM capture/compare mode register 1. + fields: + - name: CCSEL + description: Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 16 + enum: CCSEL + - name: CCE + description: Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CCP_Input + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: CCP_Input + - name: CCP_Output + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: CCP_Output + - name: ICPSC + description: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + bit_offset: 8 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: Filter + - name: ICF + description: Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 12 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: Filter +fieldset/CCR: + description: LPTIM compare register 1. + fields: + - name: CCR + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' bit_offset: 0 bit_size: 16 fieldset/CFGR: - description: Configuration Register. + description: LPTIM configuration register. fields: - name: CKSEL - description: Clock selector. + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. bit_offset: 0 bit_size: 1 - enum: CKSEL + enum: ClockSource - name: CKPOL - description: Clock Polarity. + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' bit_offset: 1 bit_size: 2 enum: CKPOL - name: CKFLT - description: Configurable digital filter for external clock. + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. bit_offset: 3 bit_size: 2 enum: Filter - name: TRGFLT - description: Configurable digital filter for trigger. + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. bit_offset: 6 bit_size: 2 enum: Filter - name: PRESC - description: Clock prescaler. + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. bit_offset: 9 bit_size: 3 enum: PRESC - name: TRIGSEL - description: Trigger selector. + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' bit_offset: 13 bit_size: 3 - name: TRIGEN - description: Trigger enable and polarity. + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. bit_offset: 17 bit_size: 2 + enum: TRIGEN - name: TIMOUT - description: Timeout enable. + description: Timeout enable The TIMOUT bit controls the Timeout feature. bit_offset: 19 bit_size: 1 - name: WAVE - description: Waveform shape. + description: Waveform shape The WAVE bit controls the output shape. bit_offset: 20 bit_size: 1 - name: WAVPOL - description: Waveform shape polarity. + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' bit_offset: 21 bit_size: 1 + enum: WAVPOL - name: PRELOAD - description: Registers update mode. + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. bit_offset: 22 bit_size: 1 - name: COUNTMODE - description: counter mode enabled. + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. bit_offset: 23 bit_size: 1 + enum: ClockSource - name: ENC - description: Encoder mode enable. + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 24 bit_size: 1 -fieldset/CMP: - description: Compare Register. +fieldset/CFGR2: + description: LPTIM configuration register 2. fields: - - name: CMP - description: Compare value. + - name: INSEL + description: LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. bit_offset: 0 - bit_size: 16 + bit_size: 2 + array: + len: 2 + stride: 4 + - name: ICSEL + description: LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + bit_offset: 16 + bit_size: 2 + array: + len: 2 + stride: 4 fieldset/CNT: - description: Counter Register. + description: LPTIM counter register. fields: - name: CNT - description: Counter value. + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. bit_offset: 0 bit_size: 16 fieldset/CR: - description: Control Register. + description: LPTIM control register. fields: - name: ENABLE - description: LPTIM Enable. + description: LPTIM enable The ENABLE bit is set and cleared by software. bit_offset: 0 bit_size: 1 - name: SNGSTRT - description: LPTIM start in single mode. + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. bit_offset: 1 bit_size: 1 - name: CNTSTRT - description: Timer start in continuous mode. + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. bit_offset: 2 bit_size: 1 - - name: RSTARE - description: Reset after read enable. - bit_offset: 3 - bit_size: 1 - name: COUNTRST - description: Counter reset. - bit_offset: 4 - bit_size: 1 -fieldset/ICR: - description: Interrupt Clear Register. - fields: - - name: CMPMCF - description: compare match Clear Flag. - bit_offset: 0 - bit_size: 1 - - name: ARRMCF - description: Autoreload match Clear Flag. - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGCF - description: External trigger valid edge Clear Flag. - bit_offset: 2 - bit_size: 1 - - name: CMPOKCF - description: Compare register update OK Clear Flag. + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. bit_offset: 3 bit_size: 1 - - name: ARROKCF - description: Autoreload register update OK Clear Flag. + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. bit_offset: 4 bit_size: 1 - - name: UPCF - description: Direction change to UP Clear Flag. - bit_offset: 5 - bit_size: 1 - - name: DOWNCF - description: Direction change to down Clear Flag. - bit_offset: 6 - bit_size: 1 - - name: UECF - description: Update event clear flag. - bit_offset: 7 - bit_size: 1 - - name: REPOKCF - description: Repetition register update OK clear flag. - bit_offset: 8 - bit_size: 1 -fieldset/IER: - description: Interrupt Enable Register. +fieldset/DIER_ADV: + extends: DIER_BASIC + description: LPTIM interrupt enable register. fields: - - name: CMPMIE - description: Compare match Interrupt Enable. + - name: CCIE + description: Capture/compare 1 interrupt enable. bit_offset: 0 bit_size: 1 + array: + len: 2 + stride: 9 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CCOIE + description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CCDE + description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 16 + bit_size: 1 + array: + len: 2 + stride: 9 +fieldset/DIER_BASIC: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 - name: ARRMIE description: Autoreload match Interrupt Enable. bit_offset: 1 @@ -202,19 +296,22 @@ fieldset/IER: bit_offset: 2 bit_size: 1 - name: CMPOKIE - description: Compare register update OK Interrupt Enable. + description: Compare register 1 update OK interrupt enable. bit_offset: 3 bit_size: 1 + array: + len: 1 + stride: 16 - name: ARROKIE description: Autoreload register update OK Interrupt Enable. bit_offset: 4 bit_size: 1 - name: UPIE - description: Direction change to UP Interrupt Enable. + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 5 bit_size: 1 - name: DOWNIE - description: Direction change to down Interrupt Enable. + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 6 bit_size: 1 - name: UEIE @@ -222,55 +319,189 @@ fieldset/IER: bit_offset: 7 bit_size: 1 - name: REPOKIE - description: REPOKIE. + description: Repetition register update OK interrupt Enable. bit_offset: 8 bit_size: 1 -fieldset/ISR: - description: Interrupt and Status Register. +fieldset/ICR_ADV: + extends: ICR_BASIC + description: LPTIM interrupt clear register. fields: - - name: CMPM - description: Compare match. + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. bit_offset: 0 bit_size: 1 + array: + len: 2 + stride: 9 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CCOCF + description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/ICR_BASIC: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UECF + description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + bit_offset: 7 + bit_size: 1 + - name: REPOKCF + description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + bit_offset: 8 + bit_size: 1 + - name: DIEROKCF + description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + bit_offset: 24 + bit_size: 1 +fieldset/ISR_ADV: + extends: ISR_BASIC + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 9 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CCOF + description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/ISR_BASIC: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 - name: ARRM - description: Autoreload match. + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. bit_offset: 1 bit_size: 1 - name: EXTTRIG - description: External trigger edge event. + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. bit_offset: 2 bit_size: 1 - name: CMPOK - description: Compare register update OK. + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. bit_offset: 3 bit_size: 1 + array: + len: 1 + stride: 16 - name: ARROK - description: Autoreload register update OK. + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. bit_offset: 4 bit_size: 1 - name: UP - description: Counter direction change down to up. + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 5 bit_size: 1 - name: DOWN - description: Counter direction change up to down. + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 6 bit_size: 1 - name: UE - description: LPTIM update event occurred. + description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. bit_offset: 7 bit_size: 1 - name: REPOK - description: Repetition register update Ok. + description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. bit_offset: 8 bit_size: 1 + - name: DIEROK + description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + bit_offset: 24 + bit_size: 1 fieldset/RCR: description: LPTIM repetition register. fields: - name: REP - description: Repetition register value. + description: Repetition register value REP is the repetition value for the LPTIM. bit_offset: 0 bit_size: 8 +enum/CCP_Input: + bit_size: 2 + variants: + - name: Rising + value: 0 + - name: Falling + value: 1 + - name: Both + value: 3 +enum/CCP_Output: + bit_size: 2 + variants: + - name: ActiveHigh + value: 0 + - name: ActiveLow + value: 1 +enum/CCSEL: + bit_size: 1 + variants: + - name: OutputCompare + description: channel is configured in output PWM mode + value: 0 + - name: InputCapture + description: channel is configured in input capture mode + value: 1 enum/CKPOL: bit_size: 2 variants: @@ -283,14 +514,14 @@ enum/CKPOL: - name: Both description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. value: 2 -enum/CKSEL: +enum/ClockSource: bit_size: 1 variants: - name: Internal - description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + description: clocked by internal clock source (APB clock or any of the embedded oscillators) value: 0 - name: External - description: LPTIM is clocked by an external clock source through the LPTIM external Input1 + description: clocked by an external clock source through the LPTIM external Input1 value: 1 enum/Filter: bit_size: 2 @@ -322,3 +553,27 @@ enum/PRESC: value: 6 - name: Div128 value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/data/registers/lptim_v2b.yaml b/data/registers/lptim_v2b.yaml index de86cb0..b42976c 100644 --- a/data/registers/lptim_v2b.yaml +++ b/data/registers/lptim_v2b.yaml @@ -1,45 +1,18 @@ -block/LPTIM_ADV: - extends: LPTIM_BASIC +block/LPTIM: description: Low power timer with Output Compare items: - name: ISR description: LPTIM interrupt and status register. byte_offset: 0 - fieldset: ISR_ADV + fieldset: ISR - name: ICR description: LPTIM interrupt clear register. byte_offset: 4 - fieldset: ICR_ADV + fieldset: ICR - name: DIER description: LPTIM interrupt enable register. byte_offset: 8 - fieldset: DIER_ADV - - name: CCR - description: LPTIM compare register 1. - array: - len: 2 - stride: 32 - byte_offset: 20 - fieldset: CCR - - name: CCMR - description: LPTIM capture/compare mode register 1. - byte_offset: 44 - fieldset: CCMR -block/LPTIM_BASIC: - description: Low power timer with Output Compare - items: - - name: ISR - description: LPTIM interrupt and status register. - byte_offset: 0 - fieldset: ISR_BASIC - - name: ICR - description: LPTIM interrupt clear register. - byte_offset: 4 - fieldset: ICR_BASIC - - name: DIER - description: LPTIM interrupt enable register. - byte_offset: 8 - fieldset: DIER_BASIC + fieldset: DIER - name: CFGR description: LPTIM configuration register. byte_offset: 12 @@ -51,8 +24,11 @@ block/LPTIM_BASIC: - name: CCR description: LPTIM compare register 1. array: - len: 1 - stride: 32 + offsets: + - 0 + - 32 + - 36 + - 40 byte_offset: 20 fieldset: CCR - name: ARR @@ -71,6 +47,13 @@ block/LPTIM_BASIC: description: LPTIM repetition register. byte_offset: 40 fieldset: RCR + - name: CCMR + description: LPTIM capture/compare mode register 1. + array: + len: 2 + stride: 1 + byte_offset: 44 + fieldset: CCMR fieldset/ARR: description: LPTIM autoreload register. fields: @@ -142,7 +125,7 @@ fieldset/CFGR: description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. bit_offset: 0 bit_size: 1 - enum: CKSEL + enum: ClockSource - name: CKPOL description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' bit_offset: 1 @@ -180,10 +163,6 @@ fieldset/CFGR: description: Waveform shape The WAVE bit controls the output shape. bit_offset: 20 bit_size: 1 - - name: WAVPOL - description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' - bit_offset: 21 - bit_size: 1 - name: PRELOAD description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. bit_offset: 22 @@ -192,6 +171,7 @@ fieldset/CFGR: description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. bit_offset: 23 bit_size: 1 + enum: ClockSource - name: ENC description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 24 @@ -243,8 +223,7 @@ fieldset/CR: description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. bit_offset: 4 bit_size: 1 -fieldset/DIER_ADV: - extends: DIER_BASIC +fieldset/DIER: description: LPTIM interrupt enable register. fields: - name: CCIE @@ -252,39 +231,11 @@ fieldset/DIER_ADV: bit_offset: 0 bit_size: 1 array: - len: 2 - stride: 9 - - name: CMPOKIE - description: Compare register 1 update OK interrupt enable. - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 16 - - name: CCOIE - description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: CCDE - description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' - bit_offset: 16 - bit_size: 1 - array: - len: 2 - stride: 9 -fieldset/DIER_BASIC: - description: LPTIM interrupt enable register. - fields: - - name: CCIE - description: Capture/compare 1 interrupt enable. - bit_offset: 0 - bit_size: 1 - array: - len: 1 - stride: 9 + offsets: + - 0 + - 9 + - 10 + - 11 - name: ARRMIE description: Autoreload match Interrupt Enable. bit_offset: 1 @@ -298,8 +249,11 @@ fieldset/DIER_BASIC: bit_offset: 3 bit_size: 1 array: - len: 1 - stride: 16 + offsets: + - 0 + - 16 + - 17 + - 18 - name: ARROKIE description: Autoreload register update OK Interrupt Enable. bit_offset: 4 @@ -320,32 +274,24 @@ fieldset/DIER_BASIC: description: Repetition register update OK interrupt Enable. bit_offset: 8 bit_size: 1 -fieldset/ICR_ADV: - extends: ICR_BASIC - description: LPTIM interrupt clear register. - fields: - - name: CCCF - description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 9 - - name: CMPOKCF - description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 16 - - name: CCOCF - description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + - name: CCOIE + description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' bit_offset: 12 bit_size: 1 array: - len: 2 + len: 4 stride: 1 -fieldset/ICR_BASIC: + - name: CCDE + description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 16 + bit_size: 1 + array: + offsets: + - 0 + - 9 + - 10 + - 11 +fieldset/ICR: description: LPTIM interrupt clear register. fields: - name: CCCF @@ -353,8 +299,11 @@ fieldset/ICR_BASIC: bit_offset: 0 bit_size: 1 array: - len: 1 - stride: 9 + offsets: + - 0 + - 9 + - 10 + - 11 - name: ARRMCF description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. bit_offset: 1 @@ -368,8 +317,11 @@ fieldset/ICR_BASIC: bit_offset: 3 bit_size: 1 array: - len: 1 - stride: 16 + offsets: + - 0 + - 16 + - 17 + - 18 - name: ARROKCF description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. bit_offset: 4 @@ -390,12 +342,18 @@ fieldset/ICR_BASIC: description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. bit_offset: 8 bit_size: 1 + - name: CCOCF + description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 4 + stride: 1 - name: DIEROKCF description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. bit_offset: 24 bit_size: 1 -fieldset/ISR_ADV: - extends: ISR_BASIC +fieldset/ISR: description: LPTIM interrupt and status register. fields: - name: CCIF @@ -403,32 +361,11 @@ fieldset/ISR_ADV: bit_offset: 0 bit_size: 1 array: - len: 2 - stride: 9 - - name: CMPOK - description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 16 - - name: CCOF - description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 -fieldset/ISR_BASIC: - description: LPTIM interrupt and status register. - fields: - - name: CCIF - description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - bit_offset: 0 - bit_size: 1 - array: - len: 1 - stride: 9 + offsets: + - 0 + - 9 + - 10 + - 11 - name: ARRM description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. bit_offset: 1 @@ -442,8 +379,11 @@ fieldset/ISR_BASIC: bit_offset: 3 bit_size: 1 array: - len: 1 - stride: 16 + offsets: + - 0 + - 16 + - 17 + - 18 - name: ARROK description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. bit_offset: 4 @@ -464,6 +404,13 @@ fieldset/ISR_BASIC: description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. bit_offset: 8 bit_size: 1 + - name: CCOF + description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 4 + stride: 1 - name: DIEROK description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. bit_offset: 24 @@ -512,14 +459,14 @@ enum/CKPOL: - name: Both description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. value: 2 -enum/CKSEL: +enum/ClockSource: bit_size: 1 variants: - name: Internal - description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + description: clocked by internal clock source (APB clock or any of the embedded oscillators) value: 0 - name: External - description: LPTIM is clocked by an external clock source through the LPTIM external Input1 + description: clocked by an external clock source through the LPTIM external Input1 value: 1 enum/Filter: bit_size: 2 diff --git a/data/registers/ltdc_v1.yaml b/data/registers/ltdc_v1.yaml index 19186aa..dd40b3d 100644 --- a/data/registers/ltdc_v1.yaml +++ b/data/registers/ltdc_v1.yaml @@ -145,14 +145,16 @@ fieldset/BCCR: fieldset/BFCR: description: Layerx Blending Factors Configuration Register fields: - - name: BF + - name: BF2 description: Blending Factor 2 bit_offset: 0 bit_size: 3 - array: - len: 2 - stride: 8 enum: BF2 + - name: BF1 + description: Blending Factor 1 + bit_offset: 8 + bit_size: 3 + enum: BF1 fieldset/BPCR: description: Back Porch Configuration Register fields: @@ -470,6 +472,15 @@ fieldset/WVPCR: description: Window Vertical Stop Position bit_offset: 16 bit_size: 11 +enum/BF1: + bit_size: 3 + variants: + - name: Constant + description: BF1 = constant alpha + value: 4 + - name: Pixel + description: BF1 = pixel alpha * constant alpha + value: 7 enum/BF2: bit_size: 3 variants: diff --git a/data/registers/opamp_u0.yaml b/data/registers/opamp_u0.yaml new file mode 100644 index 0000000..b7d267c --- /dev/null +++ b/data/registers/opamp_u0.yaml @@ -0,0 +1,186 @@ +block/OPAMP: + description: OPAMP address block description. + items: + - name: CSR + description: OPAMP control/status register. + byte_offset: 0 + fieldset: CSR + - name: OTR + description: OPAMP offset trimming register in normal mode. + byte_offset: 4 + fieldset: OTR + - name: LPOTR + description: OPAMP offset trimming register in low-power mode. + byte_offset: 8 + fieldset: LPOTR +fieldset/CSR: + description: OPAMP control/status register. + fields: + - name: OPAMPEN + description: Operational amplifier Enable. + bit_offset: 0 + bit_size: 1 + - name: OPALPM + description: Operational amplifier Low Power Mode. The operational amplifier must be disable to change this configuration. + bit_offset: 1 + bit_size: 1 + enum: OPALPM + - name: OPAMODE + description: Operational amplifier PGA mode. + bit_offset: 2 + bit_size: 2 + enum: OPAMODE + - name: PGA_GAIN + description: Operational amplifier Programmable amplifier gain value. + bit_offset: 4 + bit_size: 2 + enum: PGA_GAIN + - name: VM_SEL + description: 'Inverting input selection. These bits are used only when OPAMODE = 00, 01 or 10. 1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode).' + bit_offset: 8 + bit_size: 2 + enum: VM_SEL + - name: VP_SEL + description: Non inverted input selection. + bit_offset: 10 + bit_size: 1 + enum: VP_SEL + - name: CALON + description: Calibration mode enabled. + bit_offset: 12 + bit_size: 1 + enum: CALON + - name: CALSEL + description: Calibration selection. + bit_offset: 13 + bit_size: 1 + enum: CALSEL + - name: USERTRIM + description: allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values This bit is active for both mode normal and low-power. + bit_offset: 14 + bit_size: 1 + enum: USERTRIM + - name: CALOUT + description: Operational amplifier calibration output During calibration mode offset is trimmed when this signal toggle. + bit_offset: 15 + bit_size: 1 + - name: OPA_RANGE + description: Operational amplifier power supply range for stability All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP embedded in the product. + bit_offset: 31 + bit_size: 1 + enum: OPA_RANGE +fieldset/LPOTR: + description: OPAMP offset trimming register in low-power mode. + fields: + - name: TRIMLPOFFSETN + description: Low-power mode trim for NMOS differential pairs. + bit_offset: 0 + bit_size: 5 + - name: TRIMLPOFFSETP + description: Low-power mode trim for PMOS differential pairs. + bit_offset: 8 + bit_size: 5 +fieldset/OTR: + description: OPAMP offset trimming register in normal mode. + fields: + - name: TRIMOFFSETN + description: Trim for NMOS differential pairs. + bit_offset: 0 + bit_size: 5 + - name: TRIMOFFSETP + description: Trim for PMOS differential pairs. + bit_offset: 8 + bit_size: 5 +enum/CALON: + bit_size: 1 + variants: + - name: Normal + description: Normal mode. + value: 0 + - name: Calibration + description: Calibration mode (all switches opened by HW). + value: 1 +enum/CALSEL: + bit_size: 1 + variants: + - name: NMOS + description: NMOS calibration (200mV applied on OPAMP inputs). + value: 0 + - name: PMOS + description: PMOS calibration (VDDA-200mV applied on OPAMP inputs). + value: 1 +enum/OPALPM: + bit_size: 1 + variants: + - name: Normal + description: operational amplifier in normal mode. + value: 0 + - name: LowPower + description: operational amplifier in low-power mode. + value: 1 +enum/OPAMODE: + bit_size: 2 + variants: + - name: Disable + description: internal PGA disable. + value: 0 + - name: Disable2 + description: internal PGA disable. (Duplicate) + value: 1 + - name: Enable + description: internal PGA enable, gain programmed in PGA_GAIN. + value: 2 + - name: Follower + description: internal follower. + value: 3 +enum/OPA_RANGE: + bit_size: 1 + variants: + - name: Low + description: Low range (VDDA < 2.4V). + value: 0 + - name: High + description: High range (VDDA > 2.4V). + value: 1 +enum/PGA_GAIN: + bit_size: 2 + variants: + - name: Gain2 + description: internal PGA Gain 2. + value: 0 + - name: Gain4 + description: internal PGA Gain 4. + value: 1 + - name: Gain8 + description: internal PGA Gain 8. + value: 2 + - name: Gain16 + description: internal PGA Gain 16. + value: 3 +enum/USERTRIM: + bit_size: 1 + variants: + - name: Factory + description: Factory trim code used. + value: 0 + - name: User + description: User trim code used. + value: 1 +enum/VM_SEL: + bit_size: 2 + variants: + - name: VINM + description: GPIO connected to VINM (valid also in PGA mode for filtering). + value: 0 + - name: NotConnected + description: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) + value: 2 +enum/VP_SEL: + bit_size: 1 + variants: + - name: VINP + description: GPIO connected to VINP. + value: 0 + - name: DAC + description: DAC connected to VINP. + value: 1 diff --git a/data/registers/pwr_h50.yaml b/data/registers/pwr_h50.yaml index 9b3949c..0142ab7 100644 --- a/data/registers/pwr_h50.yaml +++ b/data/registers/pwr_h50.yaml @@ -1,267 +1,269 @@ block/PWR: - description: Power control + description: Power control. items: - name: PMCR - description: PWR power mode control register + description: PWR power mode control register. byte_offset: 0 fieldset: PMCR - name: PMSR - description: PWR status register + description: PWR status register. byte_offset: 4 fieldset: PMSR - name: VOSCR - description: PWR voltage scaling control register + description: PWR voltage scaling control register. byte_offset: 16 fieldset: VOSCR - name: VOSSR - description: PWR voltage scaling status register + description: PWR voltage scaling status register. byte_offset: 20 fieldset: VOSSR - name: BDCR - description: PWR Backup domain control register + description: PWR Backup domain control register. byte_offset: 32 fieldset: BDCR - name: DBPCR - description: PWR disable backup protection control register + description: PWR Backup domain control register. byte_offset: 36 fieldset: DBPCR - name: BDSR - description: PWR Backup domain status register + description: PWR Backup domain status register. byte_offset: 40 fieldset: BDSR - name: SCCR - description: PWR supply configuration control register + description: PWR supply configuration control register. byte_offset: 48 fieldset: SCCR - name: VMCR - description: PWR voltage monitor control register + description: PWR voltage monitor control register. byte_offset: 52 fieldset: VMCR - name: VMSR - description: PWR voltage monitor status register + description: PWR voltage monitor status register. byte_offset: 60 fieldset: VMSR - name: WUSCR - description: PWR wakeup status clear register + description: PWR wakeup status clear register. byte_offset: 64 fieldset: WUSCR - name: WUSR - description: PWR wakeup status register + description: PWR wakeup status register. byte_offset: 68 fieldset: WUSR - name: WUCR - description: PWR wakeup configuration register + description: PWR wakeup configuration register. byte_offset: 72 fieldset: WUCR - name: IORETR - description: PWR I/O retention register + description: PWR I/O retention register. byte_offset: 80 fieldset: IORETR - name: PRIVCFGR - description: PWR privilege configuration register + description: PWR privilege configuration register. byte_offset: 260 fieldset: PRIVCFGR fieldset/BDCR: - description: PWR Backup domain control register + description: PWR Backup domain control register. fields: - name: BREN - description: "Backup RAM retention in Standby and VBAT modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and VBAT modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and VBAT modes." + description: Backup RAM retention in Standby and V_BAT modes When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V_BAT modes) is enabled. If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in. Run and Stop modes. However its content is lost in Standby and V_BAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V_BAT modes. bit_offset: 0 bit_size: 1 + enum: Retention - name: MONEN - description: Backup domain voltage and temperature monitoring enable + description: Backup domain voltage and temperature monitoring enable. bit_offset: 1 bit_size: 1 - name: VBE - description: "VBAT charging enable\r Note: Reset only by POR,." + description: 'V_BAT charging enable Note: Reset only by POR,.' bit_offset: 8 bit_size: 1 - name: VBRS - description: VBAT charging resistor selection + description: V_BAT charging resistor selection. bit_offset: 9 bit_size: 1 enum: VBRS fieldset/BDSR: - description: PWR Backup domain status register + description: PWR Backup domain status register. fields: - name: BRRDY - description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." + description: backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. bit_offset: 16 bit_size: 1 - name: VBATL - description: VBAT level monitoring versus low threshold + description: V_BAT level monitoring versus low threshold. bit_offset: 20 bit_size: 1 - name: VBATH - description: VBAT level monitoring versus high threshold + description: V_BAT level monitoring versus high threshold. bit_offset: 21 bit_size: 1 - name: TEMPL - description: temperature level monitoring versus low threshold + description: temperature level monitoring versus low threshold. bit_offset: 22 bit_size: 1 - name: TEMPH - description: temperature level monitoring versus high threshold + description: temperature level monitoring versus high threshold. bit_offset: 23 bit_size: 1 fieldset/DBPCR: - description: PWR disable backup protection control register + description: PWR Backup domain control register. fields: - name: DBP - description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." + description: Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write. access. This bit must be set to enable write access to these registers. bit_offset: 0 bit_size: 1 fieldset/IORETR: - description: PWR I/O retention register + description: PWR I/O retention register. fields: - name: IORETEN - description: "IO retention enable:\r When entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." + description: 'IO retention enable: When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register.' bit_offset: 0 bit_size: 1 - name: JTAGIORETEN - description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode" + description: IO retention enable for JTAG IOs when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. bit_offset: 16 bit_size: 1 fieldset/PMCR: - description: PWR power mode control register + description: PWR power mode control register. fields: - name: LPMS - description: "low-power mode selection\r This bit defines the Deepsleep mode." + description: low-power mode selection This bit defines the Deepsleep mode. bit_offset: 0 bit_size: 1 + enum: LPMS - name: SVOS - description: "system Stop mode voltage scaling selection\r These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." + description: system Stop mode voltage scaling selection These bits control the V_CORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance. bit_offset: 2 bit_size: 2 enum: SVOS - name: CSSF - description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." + description: clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. bit_offset: 7 bit_size: 1 - name: FLPS - description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." + description: 'Flash memory low-power mode in Stop mode This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode. Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode.' bit_offset: 9 bit_size: 1 + enum: PowerModeInStopMode - name: BOOSTE - description: "analog switch VBOOST control\r This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits." + description: analog switch V_BOOST control This bit enables the booster to guarantee the analog switch AC performance when the V_DD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V_DD supply voltage can be monitored through the PVD and the PLS bits. bit_offset: 12 bit_size: 1 - name: AVD_READY - description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected VDDA analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." + description: analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected V_DDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored. (ALS bits). bit_offset: 13 bit_size: 1 - name: SRAM2SO description: AHB SRAM2 shut-off in Stop mode. bit_offset: 25 bit_size: 1 + enum: ShutOff - name: SRAM1SO - description: AHB SRAM1 shut-off in Stop mode + description: AHB SRAM1 shut-off in Stop mode. bit_offset: 26 bit_size: 1 + enum: ShutOff fieldset/PMSR: - description: PWR status register + description: PWR status register. fields: - name: STOPF - description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." + description: Stop flag This bit is set by hardware and cleared only by any reset or by setting the CSSF bit. bit_offset: 5 bit_size: 1 - name: SBF - description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." + description: System standby flag This bit is set by hardware and cleared only by a POR or by setting the CSSF bit. bit_offset: 6 bit_size: 1 fieldset/PRIVCFGR: - description: PWR privilege configuration register + description: PWR privilege configuration register. fields: - name: NSPRIV - description: "PWR functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access." + description: PWR non-secure functions privilege configuration Set and reset by software. This bit can be written only by privileged access, secure or non-secure. bit_offset: 1 bit_size: 1 - enum: PRIV fieldset/SCCR: - description: PWR supply configuration control register + description: PWR supply configuration control register. fields: - name: BYPASS - description: power management unit bypass + description: power management unit bypass. bit_offset: 0 bit_size: 1 - name: LDOEN - description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." + description: LDO enable The value is set by hardware when the package uses the LDO regulator. bit_offset: 8 bit_size: 1 fieldset/VMCR: - description: PWR voltage monitor control register + description: PWR voltage monitor control register. fields: - name: PVDE - description: PVD enable + description: PVD enable. bit_offset: 0 bit_size: 1 - name: PLS - description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." + description: programmable voltage detector (PVD) level selection These bits select the voltage threshold detected by the PVD. bit_offset: 1 bit_size: 3 enum: PLS - name: AVDEN - description: peripheral voltage monitor on VDDA enable + description: peripheral voltage monitor on V_DDA enable. bit_offset: 8 bit_size: 1 - name: ALS - description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." + description: analog voltage detector (AVD) level selection These bits select the voltage threshold detected by the AVD. bit_offset: 9 bit_size: 2 enum: ALS fieldset/VMSR: - description: PWR voltage monitor status register + description: PWR voltage monitor status register. fields: - name: AVDO - description: "analog voltage detector output on VDDA\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." + description: 'analog voltage detector output on V_DDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set.' bit_offset: 19 bit_size: 1 - enum: AVDO - name: VDDIO2RDY - description: "voltage detector output on VDDIO2\r This bit is set and cleared by hardware." + description: voltage detector output on V_DDIO2 This bit is set and cleared by hardware. bit_offset: 20 bit_size: 1 - name: PVDO - description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." + description: 'programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.' bit_offset: 22 bit_size: 1 - enum: PVDO fieldset/VOSCR: - description: PWR voltage scaling control register + description: PWR voltage scaling control register. fields: - name: VOS - description: "voltage scaling selection according to performance\r These bits control the VCORE voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." + description: 'voltage scaling selection according to performance These bits control the V_CORE voltage level and allow to obtain the best trade-off between power consumption and performance: - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance. - When increasing the performance, the voltage scaling must be changed before increasing the system frequency. - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling.' bit_offset: 4 bit_size: 2 enum: VOS fieldset/VOSSR: - description: PWR voltage scaling status register + description: PWR voltage scaling status register. fields: - name: VOSRDY - description: Ready bit for VCORE voltage scaling output selection. + description: Ready bit for V_CORE voltage scaling output selection. bit_offset: 3 bit_size: 1 - name: ACTVOSRDY - description: Voltage level ready for currently used VOS + description: Voltage level ready for currently used VOS. bit_offset: 13 bit_size: 1 - name: ACTVOS - description: "voltage output scaling currently applied to VCORE\r This field provides the last VOS value." + description: voltage output scaling currently applied to V_CORE This field provides the last VOS value. bit_offset: 14 bit_size: 2 - enum: ACTVOS + enum: VOS fieldset/WUCR: - description: PWR wakeup configuration register + description: PWR wakeup configuration register. fields: - name: WUPEN - description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." + description: 'enable wakeup pin WUPx These bits are set and cleared by software. Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge.' bit_offset: 0 bit_size: 1 array: len: 5 stride: 1 - name: WUPP - description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." + description: wakeup pin polarity bit for WUPx These bits define the polarity used for event detection on WUPx external wakeup pin. bit_offset: 8 bit_size: 1 array: @@ -269,7 +271,7 @@ fieldset/WUCR: stride: 1 enum: WUPP - name: WUPPUPD - description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." + description: wakeup pin pull configuration for WKUPx These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode. bit_offset: 16 bit_size: 2 array: @@ -277,169 +279,150 @@ fieldset/WUCR: stride: 2 enum: WUPPUPD fieldset/WUSCR: - description: PWR wakeup status clear register + description: PWR wakeup status clear register. fields: - name: CWUF - description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." + description: clear wakeup pin flag for WUFx These bits are always read as 0. bit_offset: 0 bit_size: 1 array: len: 5 stride: 1 fieldset/WUSR: - description: PWR wakeup status register + description: PWR wakeup status register. fields: - name: WUF - description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." + description: wakeup pin WUFx flag This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register. bit_offset: 0 bit_size: 1 array: len: 5 stride: 1 -enum/ACTVOS: - bit_size: 2 - variants: - - name: B_0x0 - description: VOS3 (lowest power) - value: 0 - - name: B_0x1 - description: VOS2 - value: 1 - - name: B_0x2 - description: VOS1 - value: 2 - - name: B_0x3 - description: VOS0 (highest frequency) - value: 3 enum/ALS: bit_size: 2 variants: - - name: B_0x0 - description: 1.7 V + - name: Level0 + description: AVD level0 (VAVD0 ~ 1.7 V) value: 0 - - name: B_0x1 - description: 2.1 V + - name: Level1 + description: AVD level1 (VAVD1 ~ 2.1 V) value: 1 - - name: B_0x2 - description: 2.5 V + - name: Level2 + description: AVD level2 (VAVD2 ~ 2.5 V) value: 2 - - name: B_0x3 - description: 2.8 V + - name: Level3 + description: AVD level3 (VAVD3 ~ 2.8 V) value: 3 -enum/AVDO: +enum/LPMS: bit_size: 1 variants: - - name: B_0x0 - description: VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits. + - name: Stop + description: Keeps Stop mode when entering DeepSleep. value: 0 - - name: B_0x1 - description: VDDA is lower than the AVD threshold selected with the ALS[2:0] bits. + - name: Standby + description: Allows Standby mode when entering DeepSleep. value: 1 enum/PLS: bit_size: 3 variants: - - name: B_0x0 - description: 1.95 V + - name: Level0 + description: PVD level0 (VPVD0 ~ 1.95 V) value: 0 - - name: B_0x1 - description: 2.1 V + - name: Level1 + description: PVD level1 (VPVD1 ~ 2.10 V) value: 1 - - name: B_0x2 - description: 2.25 V + - name: Level2 + description: PVD level2 (VPVD2 ~ 2.25 V) value: 2 - - name: B_0x3 - description: 2.4 V + - name: Level3 + description: PVD level3 (VPVD3 ~ 2.40 V) value: 3 - - name: B_0x4 - description: 2.55 V + - name: Level4 + description: PVD level4 (VPVD4 ~ 2.55 V) value: 4 - - name: B_0x5 - description: 2.7 V + - name: Level5 + description: PVD level5 (VPVD5 ~ 2.70 V) value: 5 - - name: B_0x6 - description: 2.85 V + - name: Level6 + description: PVD level6 (VPVD6 ~ 2.85 V) value: 6 - - name: B_0x7 + - name: PVDInPin description: PVD_IN pin value: 7 -enum/PRIV: +enum/PowerModeInStopMode: bit_size: 1 variants: - - name: B_0x0 - description: Read and write to PWR functions can be done by privileged or unprivileged access. + - name: Normal + description: Remains in normal mode when the system enters Stop mode (quick restart time). value: 0 - - name: B_0x1 - description: Read and write to PWR functions can be done by privileged access only. + - name: LowPower + description: Enters low-power mode when the system enters Stop mode (low-power consumption). value: 1 -enum/PVDO: +enum/Retention: bit_size: 1 variants: - - name: B_0x0 - description: VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits. + - name: Lost + description: Content is lost. value: 0 - - name: B_0x1 - description: VDD is lower than the PVD threshold selected through the PLS[2:0] bits. + - name: Preserved + description: Content is preserved. value: 1 enum/SVOS: bit_size: 2 variants: - - name: B_0x0 - description: reserved - value: 0 - - name: B_0x1 + - name: Scale5 description: SVOS5 scale 5 value: 1 - - name: B_0x2 + - name: Scale4 description: SVOS4 scale 4 value: 2 - - name: B_0x3 - description: SVOS3 scale 3 (default). + - name: Scale3 + description: SVOS3 scale 3 (default) value: 3 +enum/ShutOff: + bit_size: 1 + variants: + - name: Kept + description: Content is kept. + value: 0 + - name: Lost + description: Content is lost. + value: 1 enum/VBRS: bit_size: 1 variants: - - name: B_0x0 - description: Charge VBAT through a 5 kΩ resistor. + - name: R5kOhm + description: Charge VBAT through a 5 kΩ resistor. value: 0 - - name: B_0x1 - description: Charge VBAT through a 1.5 kΩ resistor. + - name: R1_5kOhm + description: Charge VBAT through a 1.5 kΩ resistor. value: 1 enum/VOS: bit_size: 2 variants: - name: Scale3 - description: scale 3 (default) value: 0 - name: Scale2 - description: scale 2 value: 1 - name: Scale1 - description: scale 1 value: 2 - name: Scale0 - description: scale 0 value: 3 enum/WUPP: bit_size: 1 variants: - - name: B_0x0 + - name: High description: detection on high level (rising edge) value: 0 - - name: B_0x1 + - name: Low description: detection on low level (falling edge) value: 1 enum/WUPPUPD: bit_size: 2 variants: - - name: B_0x0 - description: no pull-up + - name: NoPullUp value: 0 - - name: B_0x1 - description: pull-up + - name: PullUp value: 1 - - name: B_0x2 - description: pull-down + - name: PullDown value: 2 - - name: B_0x3 - description: reserved - value: 3 diff --git a/data/registers/pwr_h7rm0399.yaml b/data/registers/pwr_h7rm0399.yaml index 9e7c628..3b044f7 100644 --- a/data/registers/pwr_h7rm0399.yaml +++ b/data/registers/pwr_h7rm0399.yaml @@ -253,6 +253,7 @@ fieldset/WKUPEPR: array: len: 6 stride: 2 + enum: WKUPPUPD fieldset/WKUPFR: description: reset only by system reset, not reset by wakeup from Standby mode fields: @@ -283,3 +284,15 @@ enum/VOS: value: 2 - name: Scale1 value: 3 +enum/WKUPPUPD: + bit_size: 2 + variants: + - name: NoPull + description: No pull-up. + value: 0 + - name: PullUp + description: Pull-up. + value: 1 + - name: PullDown + description: Pull-down. + value: 2 diff --git a/data/registers/pwr_h7rm0433.yaml b/data/registers/pwr_h7rm0433.yaml index e7eb3e0..f89e6fc 100644 --- a/data/registers/pwr_h7rm0433.yaml +++ b/data/registers/pwr_h7rm0433.yaml @@ -240,6 +240,7 @@ fieldset/WKUPEPR: array: len: 6 stride: 2 + enum: WKUPPUPD fieldset/WKUPFR: description: reset only by system reset, not reset by wakeup from Standby mode fields: @@ -259,3 +260,15 @@ enum/VOS: value: 2 - name: Scale1 value: 3 +enum/WKUPPUPD: + bit_size: 2 + variants: + - name: NoPull + description: No pull-up. + value: 0 + - name: PullUp + description: Pull-up. + value: 1 + - name: PullDown + description: Pull-down. + value: 2 diff --git a/data/registers/pwr_h7rm0455.yaml b/data/registers/pwr_h7rm0455.yaml index 54a0f77..7c9916a 100644 --- a/data/registers/pwr_h7rm0455.yaml +++ b/data/registers/pwr_h7rm0455.yaml @@ -253,6 +253,7 @@ fieldset/WKUPEPR: array: len: 6 stride: 2 + enum: WKUPPUPD fieldset/WKUPFR: description: reset only by system reset, not reset by wakeup from Standby mode fields: @@ -285,3 +286,15 @@ enum/VOS: value: 2 - name: Scale0 value: 3 +enum/WKUPPUPD: + bit_size: 2 + variants: + - name: NoPull + description: No pull-up. + value: 0 + - name: PullUp + description: Pull-up. + value: 1 + - name: PullDown + description: Pull-down. + value: 2 diff --git a/data/registers/pwr_h7rm0468.yaml b/data/registers/pwr_h7rm0468.yaml index d48059d..fdc0fcb 100644 --- a/data/registers/pwr_h7rm0468.yaml +++ b/data/registers/pwr_h7rm0468.yaml @@ -253,6 +253,7 @@ fieldset/WKUPEPR: array: len: 6 stride: 2 + enum: WKUPPUPD fieldset/WKUPFR: description: reset only by system reset, not reset by wakeup from Standby mode fields: @@ -285,3 +286,15 @@ enum/VOS: value: 2 - name: Scale1 value: 3 +enum/WKUPPUPD: + bit_size: 2 + variants: + - name: NoPull + description: No pull-up. + value: 0 + - name: PullUp + description: Pull-up. + value: 1 + - name: PullDown + description: Pull-down. + value: 2 diff --git a/data/registers/pwr_h7rs.yaml b/data/registers/pwr_h7rs.yaml new file mode 100644 index 0000000..e8d6276 --- /dev/null +++ b/data/registers/pwr_h7rs.yaml @@ -0,0 +1,643 @@ +block/PWR: + description: Power control. + items: + - name: CR1 + description: PWR control register 1. + byte_offset: 0 + fieldset: CR1 + - name: SR1 + description: PWR control status register 1. + byte_offset: 4 + fieldset: SR1 + - name: CSR1 + description: PWR control status register 1. + byte_offset: 8 + fieldset: CSR1 + - name: CSR2 + description: PWR control register 2. + byte_offset: 12 + fieldset: CSR2 + - name: CSR3 + description: PWR CPU control register 3. + byte_offset: 16 + fieldset: CSR3 + - name: CSR4 + description: PWR control status register 4. + byte_offset: 20 + fieldset: CSR4 + - name: WKUPCR + description: PWR wakeup clear register. + byte_offset: 32 + fieldset: WKUPCR + - name: WKUPFR + description: PWR wakeup flag register. + byte_offset: 36 + fieldset: WKUPFR + - name: WKUPEPR + description: PWR wakeup enable and polarity register. + byte_offset: 40 + fieldset: WKUPEPR + - name: UCPDR + description: PWR USB Type-C and Power Delivery register. + byte_offset: 44 + fieldset: UCPDR + - name: APCR + description: PWR apply pull configuration register. + byte_offset: 48 + fieldset: APCR + - name: PUCRN + description: PWR port N pull-up control register. + byte_offset: 52 + fieldset: PUCRN + - name: PDCRN + description: PWR port N pull-down control register. + byte_offset: 56 + fieldset: PDCRN + - name: PUCRO + description: PWR port O pull-up control register. + byte_offset: 60 + fieldset: PUCRO + - name: PDCRO + description: PWR port O pull-down control register. + byte_offset: 64 + fieldset: PDCRO + - name: PDCRP + description: PWR port P pull-down control register. + byte_offset: 68 + fieldset: PDCRP + - name: PDR1 + description: PWR debug register 1. + byte_offset: 80 + fieldset: PDR1 +fieldset/APCR: + description: PWR apply pull configuration register. + fields: + - name: APC + description: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx, PDCRx registers are applied in Standby mode even after wakeup until APC bit is reset to 0. When this bit is cleared, the I/O pull-up or pull-down configurations defined in PO5_PUPD, PN7_PUPD bits and PUCRx and PDCRx registers are not applied in Standby mode and IO becomes Hi-Z. + bit_offset: 0 + bit_size: 1 + - name: PN7_PUPD + description: Port N bit 7 pull-up/down configuration When this bit is set, a weak pull-up or pull-down resistor is applied on PN7 following inverse logic applied on PN6. If the PUN6 bit in PWR_PUCRN register is set and APC bit is set the week pull-down is applied on PN7. If the PDN6 bit in PWR_PDCRN register is set and APC bit is set the week pull-up is applied on PN7. + bit_offset: 16 + bit_size: 1 + - name: PO5_PUPD + description: Port O bit 5 pull-up/down configuration When this bit is set, a weak pull-up or pull down resistor is applied on PO5 following inverse logic applied on PO4. If the PUO4 bit in PWR_PUCRO register is set and APC bit is set the week pull-down is applied on PO5. If the PDO4 bit in PWR_PDCRO register is set and APC bit is set the week pull-up is applied on PO5.. + bit_offset: 17 + bit_size: 1 + - name: I3CPB6_PU + description: Port PB6 I3C pull-up bit When I3C is used on PB6, when set, this bit activates the pull-up on I3C1_SCL (PB6) in standby mode. + bit_offset: 28 + bit_size: 1 + - name: I3CPB7_PU + description: Port PB7 I3C pull-up bit When I3C is used on PB7, when set, this bit activates the pull-up on I3C1_SDA (PB7) in standby mode. + bit_offset: 29 + bit_size: 1 + - name: I3CPB8_PU + description: Port PB8 I3C pull-up bit When I3C is used on PB8, when set, this bit activates the pull-up on I3C1_SCL (PB8) in standby mode. + bit_offset: 30 + bit_size: 1 + - name: I3CPB9_PU + description: Port PB9 I3C pull-up bit When I3C is used on PB9, when set, this bit activates the pull-up on I3C1_SDA (PB9) in standby mode. + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: PWR control register 1. + fields: + - name: SVOS + description: System Stop mode voltage scaling selection. + bit_offset: 0 + bit_size: 1 + enum: SVOS + - name: PVDE + description: Programmable voltage detector enable. + bit_offset: 4 + bit_size: 1 + - name: PLS + description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.' + bit_offset: 5 + bit_size: 3 + enum: PLS + - name: DBP + description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in the PWR_CSR1 register, are protected against parasitic write access. This bit must be set to enable write access to these registers. + bit_offset: 8 + bit_size: 1 + - name: FLPS + description: Flash low-power mode in Stop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode. When it is set, the Flash memory enters low-power mode when device is in Stop mode. consumption). + bit_offset: 9 + bit_size: 1 + - name: RLPSN + description: RAM low power mode disable in STOP. When set the RAMs will not enter to low power mode when the system enters to STOP. + bit_offset: 10 + bit_size: 1 + enum: RLPSN + - name: BOOSTE + description: analog switch VBoost control This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits. + bit_offset: 11 + bit_size: 1 + - name: AVDREADY + description: analog voltage ready This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit). It must be set by software when the expected VDDA analog supply level is available. The correct analog supply level is indicated by the AVDO bit (PWR_CSR1 register) after setting the AVDEN bit and selecting the supply level to be monitored (ALS bits). + bit_offset: 12 + bit_size: 1 + - name: AVDEN + description: Peripheral voltage monitor on VDDA enable. + bit_offset: 13 + bit_size: 1 + - name: ALS + description: 'Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.' + bit_offset: 14 + bit_size: 2 + enum: ALS +fieldset/CSR1: + description: PWR control status register 1. + fields: + - name: BREN + description: Backup regulator enable When set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes. + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: 'VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled. Note: VBAT and temperature monitoring are only available when the backup regulator is enabled (BREN bit set to 1).' + bit_offset: 4 + bit_size: 1 + - name: BRRDY + description: Backup regulator ready This bit is set by hardware to indicate that the backup regulator is ready. + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold. + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold. + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: Temperature level monitoring versus low threshold. + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: Temperature level monitoring versus high threshold. + bit_offset: 23 + bit_size: 1 +fieldset/CSR2: + description: PWR control register 2. + fields: + - name: BYPASS + description: 'Power management unit bypass Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.' + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: 'Low drop-out regulator enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.' + bit_offset: 1 + bit_size: 1 + - name: SDEN + description: 'SMPS step-down converter enable Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.' + bit_offset: 2 + bit_size: 1 + - name: SDEXTHP + description: 'SMPS external power delivery selection Note: Illegal combinations of SDHILEVEL, SMPSEXTHP, SDEN, LDOEN and BYPASS are described in Table 41.' + bit_offset: 3 + bit_size: 1 + - name: SDLEVEL + description: SMPS step-down converter voltage output for LDO or external supply This bit is used when both the LDO and SMPS step-down converter are enabled with SDEN and LDOEN enabled or when SMPSEXTHP is enabled. In this case SDHILEVEL has to be set to 1 to confirm the regulator settings. + bit_offset: 4 + bit_size: 1 + enum: SDLEVEL + - name: VBE + description: VBAT charging enable. + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection. + bit_offset: 9 + bit_size: 1 + enum: VBRS + - name: XSPICAP1 + description: XSPI port 1 capacitor control bits see the product datasheet for more details. + bit_offset: 10 + bit_size: 2 + enum: XSPICAP + - name: XSPICAP2 + description: XSPI port 2 capacitor control bits see the product datasheet for more details. + bit_offset: 12 + bit_size: 2 + enum: XSPICAP + - name: EN_XSPIM1 + description: 'EN_XSPIM1: this bit allow the SW to enable the XSPI interface. The XSPIM_P1 supply must be stable prior to setting this bit.' + bit_offset: 14 + bit_size: 1 + - name: EN_XSPIM2 + description: 'EN_XSPIM2: this bit allows the SW to enable the XSPI interface, when available. The XSPIM_P2 supply must be stable prior to setting this bit. It should also be set when FMC is used.' + bit_offset: 15 + bit_size: 1 + - name: SDEXTRDY + description: SMPS step-down converter external supply ready This bit is set by hardware to indicate that the external supply from the SMPS step-down converter is ready. + bit_offset: 16 + bit_size: 1 + - name: USB33DEN + description: VDD33_USB voltage level detector enable. + bit_offset: 24 + bit_size: 1 + - name: USBREGEN + description: USB regulator enable. + bit_offset: 25 + bit_size: 1 + - name: USB33RDY + description: USB supply ready. + bit_offset: 26 + bit_size: 1 + - name: USBHSREGEN + description: USB HS regulator enable. + bit_offset: 27 + bit_size: 1 +fieldset/CSR3: + description: PWR CPU control register 3. + fields: + - name: PDDS + description: Power Down Deepsleep. This bit allows CPU to define the Deepsleep mode. + bit_offset: 0 + bit_size: 1 + enum: PDDS + - name: CSSF + description: Clear Standby and Stop flags (always read as 0) This bit is cleared to 0 by hardware. + bit_offset: 1 + bit_size: 1 + - name: STOPF + description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU CSSF bit. + bit_offset: 8 + bit_size: 1 + - name: SBF + description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU CSSF bit. + bit_offset: 9 + bit_size: 1 +fieldset/CSR4: + description: PWR control status register 4. + fields: + - name: VOS + description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling must be changed before increasing the system frequency. When decreasing performance, the system frequency must first be decreased before changing the voltage scaling. Note: Refer to Section Electrical characteristics of the product datasheet for more details.' + bit_offset: 0 + bit_size: 1 + enum: VOS + - name: VOSRDY + description: VOS Ready bit. + bit_offset: 1 + bit_size: 1 +fieldset/PDCRN: + description: PWR port N pull-down control register. + fields: + - name: PDN0 + description: Port N pull-down bit 0 When set activates the pull-down on PN0 when the APC bit is set in PWR_APCR. + bit_offset: 0 + bit_size: 1 + - name: PDN1 + description: Port N pull-down bit 1 When set activates the pull-down on PN1 when the APC bit is set in PWR_APCR. + bit_offset: 1 + bit_size: 1 + - name: PDN2N5 + description: Port N PN2 to PN5 pull-down activation When set, four pull-down resistors are activated on PN2 to PN5 when the APC bit is set in PWR_APCR. + bit_offset: 2 + bit_size: 1 + - name: PDN6 + description: Port N pull-down bit 6 When set activates the pull-down on PN6 when the APC bit is set in PWR_APCR. + bit_offset: 6 + bit_size: 1 + - name: PDN8N11 + description: Port N - PN8 to PN11 pull-down activation When set, four pull-down resistors are activated on PN8 to PN11 when the APC bit is set in PWR_APCR. + bit_offset: 8 + bit_size: 1 + - name: PDN12 + description: Port N pull-down bit 12 When set activates the pull-down on PN12 when the APC bit is set in PWR_APCR. + bit_offset: 12 + bit_size: 1 +fieldset/PDCRO: + description: PWR port O pull-down control register. + fields: + - name: PDO0 + description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + bit_offset: 0 + bit_size: 1 + - name: PDO1 + description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + bit_offset: 1 + bit_size: 1 + - name: PDO2 + description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + bit_offset: 2 + bit_size: 1 + - name: PDO3 + description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + bit_offset: 3 + bit_size: 1 + - name: PDO4 + description: Port O pull-down bit y When set, each bit activates the pull-down on POy when the APC bit is set in PWR_APCR. + bit_offset: 4 + bit_size: 1 +fieldset/PDCRP: + description: PWR port P pull-down control register. + fields: + - name: PDP0P3 + description: Port P0-P3 pull-down activation When set, four pull-down resistors are activated on P0 to P3 when the APC bit is set in PWR_APCR. + bit_offset: 0 + bit_size: 1 + - name: PDP4P7 + description: Port P4-P7 pull-down activation When set, four pull-down resitors are activated on P4 to P7 when the APC bit is set in PWR_APCR. + bit_offset: 4 + bit_size: 1 + - name: PDP8P11 + description: Port P8-P11 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR. + bit_offset: 8 + bit_size: 1 + - name: PDP12P15 + description: Port P12-P15 pull-down activation When set, four pull-down resistors are activated on P8 to P11 when the APC bit is set in PWR_APCR. + bit_offset: 12 + bit_size: 1 +fieldset/PDR1: + description: PWR debug register 1. + fields: + - name: UNLOCKED + description: Debug Register Unlocked. + bit_offset: 0 + bit_size: 1 + enum: UNLOCKED + - name: SDFPWMEN + description: Step down converter force PWM mode. + bit_offset: 3 + bit_size: 1 + - name: SYNC_ADC + description: (Non-User bit). + bit_offset: 16 + bit_size: 1 + enum: SYNC_ADC +fieldset/PUCRN: + description: PWR port N pull-up control register. + fields: + - name: PUN1 + description: Port N pull-up bit 1 When set, each bit activates the pull-up on PN1 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD1 bit is also set. + bit_offset: 1 + bit_size: 1 + - name: PUN6 + description: Port N pull-up bit 6 When set activates the pull-up on PN6 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PDN6 bit is also set. + bit_offset: 6 + bit_size: 1 + - name: PUN12 + description: Port N pull-up bit 12 When set, each bit activates the pull-up on PN12 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD12 bit is also set. + bit_offset: 12 + bit_size: 1 +fieldset/PUCRO: + description: PWR port O pull-up control register. + fields: + - name: PUO0 + description: (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set. + bit_offset: 0 + bit_size: 1 + - name: PUO1 + description: (n = 1 to 0) Port O pull-up bits When set, each bit activates the pull-up on POy when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits in PWR_PDCRO is also set. + bit_offset: 1 + bit_size: 1 + - name: PUO4 + description: Port O pull-up bit 4 When set activates the pull-up on PO4 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding bits PDO4 in PWR_PDCRO is also set. + bit_offset: 4 + bit_size: 1 +fieldset/SR1: + description: PWR control status register 1. + fields: + - name: ACTVOS + description: VOS currently applied for VCORE voltage scaling selection. These bit reflect the last VOS value applied to the PMU. + bit_offset: 0 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2). + bit_offset: 1 + bit_size: 1 + - name: PVDO + description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.' + bit_offset: 4 + bit_size: 1 + enum: PVDO + - name: AVDO + description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.' + bit_offset: 13 + bit_size: 1 + enum: AVDO +fieldset/UCPDR: + description: PWR USB Type-C and Power Delivery register. + fields: + - name: UCPD_DBDIS + description: UCPD dead battery disable. + bit_offset: 0 + bit_size: 1 + - name: UCPD_STBY + description: UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. + bit_offset: 1 + bit_size: 1 +fieldset/WKUPCR: + description: PWR wakeup clear register. + fields: + - name: WKUPC + description: Clear Wakeup pin flag for WKUP1 These bits are always read as 0. + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 +fieldset/WKUPEPR: + description: PWR wakeup enable and polarity register. + fields: + - name: WKUPEN + description: 'Enable Wakeup Pin WKUPn, (n = 4, 3, 2, 1) Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn bit) when WKUPn pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn selects falling edge.' + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: WKUPP + description: Wakeup pin polarity bit for WKUPn, (n = 4, 3, 2, 1) These bits define the polarity used for event detection on WKUPn external wakeup pin. + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: WKUPP + - name: WKUPPUPD + description: Wakeup pin pull configuration + bit_offset: 16 + bit_size: 2 + array: + len: 4 + stride: 2 + enum: WKUPPUPD +fieldset/WKUPFR: + description: PWR wakeup flag register. + fields: + - name: WKUPF + description: Wakeup pin WKUP flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPC1 bit in the PWR wakeup clear register (PWR_WKUPCR). + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 1 +enum/ALS: + bit_size: 2 + variants: + - name: Level1 + description: AVD level 1. + value: 0 + - name: Level2 + description: AVD level 2. + value: 1 + - name: Level3 + description: AVD level 3. + value: 2 + - name: Level4 + description: AVD level 4. + value: 3 +enum/AVDO: + bit_size: 1 + variants: + - name: AboveOrEqual + description: VDDA is equal or higher than the AVD threshold selected with the ALS[1:0] bits. + value: 0 + - name: Below + description: VDDA is lower than the AVD threshold selected with the ALS[1:0] bits. + value: 1 +enum/PDDS: + bit_size: 1 + variants: + - name: Stop + description: Stop mode when device enters Deepsleep. + value: 0 + - name: Standby + description: Standby mode when device enters Deepsleep. + value: 1 +enum/PLS: + bit_size: 3 + variants: + - name: Level1 + description: PVD level 1. + value: 0 + - name: Level2 + description: PVD level 2. + value: 1 + - name: Level3 + description: PVD level 3. + value: 2 + - name: Level4 + description: PVD level 4. + value: 3 + - name: Level5 + description: PVD level 5. + value: 4 + - name: Level6 + description: PVD level 6. + value: 5 + - name: Level7 + description: PVD level 7. + value: 6 + - name: External + description: External voltage level on PVD_IN pin, compared to internal VREFINT level. + value: 7 +enum/PVDO: + bit_size: 1 + variants: + - name: AboveOrEqual + description: VDD or PVD_IN voltage is equal or higher than the PVD threshold selected through the. + value: 0 + - name: Below + description: VDD or PVD_IN voltage is lower than the PVD threshold selected through the PLS[2:0]. + value: 1 +enum/RLPSN: + bit_size: 1 + variants: + - name: LowPower + description: RAM enters to low power mode when system enters to STOP. + value: 0 + - name: Normal + description: RAM remains in normal mode when system enters to STOP. + value: 1 +enum/SDLEVEL: + bit_size: 1 + variants: + - name: Reset + value: 0 + - name: V1_8 + value: 1 +enum/SVOS: + bit_size: 1 + variants: + - name: Low + description: SVOS Low. + value: 0 + - name: High + description: SVOS High (default). + value: 1 +enum/SYNC_ADC: + bit_size: 1 + variants: + - name: FreeRunning + description: SD_Converter clock free running. + value: 0 + - name: Synchronized + description: SD_Converter clock synchronised to ADC. + value: 1 +enum/UNLOCKED: + bit_size: 1 + variants: + - name: Locked + description: 'accessed locked: key was not written and after each register write access.' + value: 0 + - name: Unlocked + description: after key 0xCAFECAFE was written in this register. + value: 1 +enum/VBRS: + bit_size: 1 + variants: + - name: Ohm5k + description: Charge VBAT through a 5 k resistor. + value: 0 + - name: Ohm1_5k + description: Charge VBAT through a 1.5 k resistor. + value: 1 +enum/VOS: + bit_size: 1 + variants: + - name: Low + description: VOS Low level (default). + value: 0 + - name: High + description: VOS High level. + value: 1 +enum/WKUPP: + bit_size: 1 + variants: + - name: High + description: Detection on high level (rising edge). + value: 0 + - name: Low + description: Detection on low level (falling edge). + value: 1 +enum/WKUPPUPD: + bit_size: 2 + variants: + - name: NoPull + description: No pull-up. + value: 0 + - name: PullUp + description: Pull-up. + value: 1 + - name: PullDown + description: Pull-down. + value: 2 +enum/XSPICAP: + bit_size: 2 + variants: + - name: Disabled + description: 'XSPI Capacitor OFF (default) note: to confirm with analog design.' + value: 0 + - name: OneThird + description: XSPI Capacitor set to 1/3. + value: 1 + - name: TwoThirds + description: XSPI Capacitor set to 2/3. + value: 2 + - name: Full + description: XSPI Capacitor set to full capacitance. + value: 3 diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml index 17041c7..b9333bc 100644 --- a/data/registers/rcc_h5.yaml +++ b/data/registers/rcc_h5.yaml @@ -328,7 +328,7 @@ fieldset/AHB1RSTR: bit_offset: 17 bit_size: 1 - name: ETHRST - description: "ETHRST block reset\r Set and reset by software" + description: "ETH1 block reset\r Set and reset by software" bit_offset: 19 bit_size: 1 - name: TZSC1RST @@ -1187,7 +1187,7 @@ fieldset/APB2RSTR: fieldset/APB3ENR: description: RCC APB3 peripheral clock register fields: - - name: SBSEN + - name: SYSCFGEN description: "SBS clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 @@ -1238,7 +1238,7 @@ fieldset/APB3ENR: fieldset/APB3LPENR: description: RCC APB3 sleep clock register fields: - - name: SBSLPEN + - name: SYSCFGLPEN description: "SBS clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 @@ -1289,7 +1289,7 @@ fieldset/APB3LPENR: fieldset/APB3RSTR: description: RCC APB3 peripheral reset register fields: - - name: SBSRST + - name: SYSCFGRST description: "SBS block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index 4309016..2f03361 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -658,7 +658,7 @@ fieldset/APB2RSTR: fieldset/APB3ENR: description: RCC APB3 peripheral clock register fields: - - name: SBSEN + - name: SYSCFGEN description: "SBS clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 @@ -685,7 +685,7 @@ fieldset/APB3ENR: fieldset/APB3LPENR: description: RCC APB3 sleep clock register fields: - - name: SBSLPEN + - name: SYSCFGLPEN description: "SBS clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 @@ -712,7 +712,7 @@ fieldset/APB3LPENR: fieldset/APB3RSTR: description: RCC APB3 peripheral reset register fields: - - name: SBSRST + - name: SYSCFGRST description: "SBS block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index d3d5b62..0520366 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -312,15 +312,15 @@ fieldset/AHB1ENR: description: ART Clock Enable bit_offset: 14 bit_size: 1 - - name: ETH1MACEN + - name: ETHEN description: Ethernet MAC bus interface Clock Enable bit_offset: 15 bit_size: 1 - - name: ETH1TXEN + - name: ETHTXEN description: Ethernet Transmission Clock Enable bit_offset: 16 bit_size: 1 - - name: ETH1RXEN + - name: ETHRXEN description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 @@ -359,15 +359,15 @@ fieldset/AHB1LPENR: description: ART Clock Enable During CSleep Mode bit_offset: 14 bit_size: 1 - - name: ETH1MACLPEN + - name: ETHLPEN description: Ethernet MAC bus interface Clock Enable During CSleep Mode bit_offset: 15 bit_size: 1 - - name: ETH1TXLPEN + - name: ETHTXLPEN description: Ethernet Transmission Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - - name: ETH1RXLPEN + - name: ETHRXLPEN description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 @@ -406,8 +406,8 @@ fieldset/AHB1RSTR: description: ART block reset bit_offset: 14 bit_size: 1 - - name: ETH1MACRST - description: ETH1MAC block reset + - name: ETHRST + description: ETH block reset bit_offset: 15 bit_size: 1 - name: USB_OTG_HSRST @@ -1802,15 +1802,15 @@ fieldset/C1_AHB1ENR: description: ART Clock Enable bit_offset: 14 bit_size: 1 - - name: ETH1MACEN + - name: ETHEN description: Ethernet MAC bus interface Clock Enable bit_offset: 15 bit_size: 1 - - name: ETH1TXEN + - name: ETHTXEN description: Ethernet Transmission Clock Enable bit_offset: 16 bit_size: 1 - - name: ETH1RXEN + - name: ETHRXEN description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 @@ -1849,15 +1849,15 @@ fieldset/C1_AHB1LPENR: description: ART Clock Enable During CSleep Mode bit_offset: 14 bit_size: 1 - - name: ETH1MACLPEN + - name: ETHLPEN description: Ethernet MAC bus interface Clock Enable During CSleep Mode bit_offset: 15 bit_size: 1 - - name: ETH1TXLPEN + - name: ETHTXLPEN description: Ethernet Transmission Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - - name: ETH1RXLPEN + - name: ETHRXLPEN description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 @@ -3073,9 +3073,10 @@ fieldset/D1CCIPR: bit_size: 2 enum: FMCSEL - name: DSISEL - description: kernel clock source selection + description: DSI clock source selection (not available on all chips) bit_offset: 8 bit_size: 1 + enum: DSISEL - name: SDMMCSEL description: SDMMC kernel clock source selection bit_offset: 16 @@ -3550,6 +3551,15 @@ enum/DFSDMSEL: - name: SYS description: System clock selected as peripheral clock value: 1 +enum/DSISEL: + bit_size: 1 + variants: + - name: DSI_PHY + description: DSI-PHY used as DSI byte lane clock source (usual case) + value: 0 + - name: PLL2_Q + description: PLL2_Q used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode) + value: 1 enum/FDCANSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index 554992a..fbd1732 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -232,15 +232,15 @@ fieldset/AHB1ENR: description: ART Clock Enable bit_offset: 14 bit_size: 1 - - name: ETH1MACEN + - name: ETHEN description: Ethernet MAC bus interface Clock Enable bit_offset: 15 bit_size: 1 - - name: ETH1TXEN + - name: ETHTXEN description: Ethernet Transmission Clock Enable bit_offset: 16 bit_size: 1 - - name: ETH1RXEN + - name: ETHRXEN description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 @@ -279,15 +279,15 @@ fieldset/AHB1LPENR: description: ART Clock Enable During CSleep Mode bit_offset: 14 bit_size: 1 - - name: ETH1MACLPEN + - name: ETHLPEN description: Ethernet MAC bus interface Clock Enable During CSleep Mode bit_offset: 15 bit_size: 1 - - name: ETH1TXLPEN + - name: ETHTXLPEN description: Ethernet Transmission Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - - name: ETH1RXLPEN + - name: ETHRXLPEN description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 @@ -326,8 +326,8 @@ fieldset/AHB1RSTR: description: ART block reset bit_offset: 14 bit_size: 1 - - name: ETH1MACRST - description: ETH1MAC block reset + - name: ETHRST + description: ETH block reset bit_offset: 15 bit_size: 1 - name: USB_OTG_HSRST @@ -1871,7 +1871,7 @@ fieldset/CIFR: description: HSE ready Interrupt Flag bit_offset: 3 bit_size: 1 - - name: CSIRDY + - name: CSIRDYF description: CSI ready Interrupt Flag bit_offset: 4 bit_size: 1 @@ -2018,10 +2018,6 @@ fieldset/D1CCIPR: bit_offset: 4 bit_size: 2 enum: FMCSEL - - name: DSISEL - description: kernel clock source selection - bit_offset: 8 - bit_size: 1 - name: SDMMCSEL description: SDMMC kernel clock source selection bit_offset: 16 diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index 90549fa..aa0103b 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -312,15 +312,15 @@ fieldset/AHB1ENR: description: ART Clock Enable bit_offset: 14 bit_size: 1 - - name: ETH1MACEN + - name: ETHEN description: Ethernet MAC bus interface Clock Enable bit_offset: 15 bit_size: 1 - - name: ETH1TXEN + - name: ETHTXEN description: Ethernet Transmission Clock Enable bit_offset: 16 bit_size: 1 - - name: ETH1RXEN + - name: ETHRXEN description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 @@ -359,15 +359,15 @@ fieldset/AHB1LPENR: description: ART Clock Enable During CSleep Mode bit_offset: 14 bit_size: 1 - - name: ETH1MACLPEN + - name: ETHLPEN description: Ethernet MAC bus interface Clock Enable During CSleep Mode bit_offset: 15 bit_size: 1 - - name: ETH1TXLPEN + - name: ETHTXLPEN description: Ethernet Transmission Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - - name: ETH1RXLPEN + - name: ETHRXLPEN description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 @@ -406,8 +406,8 @@ fieldset/AHB1RSTR: description: ART block reset bit_offset: 14 bit_size: 1 - - name: ETH1MACRST - description: ETH1MAC block reset + - name: ETHRST + description: ETH block reset bit_offset: 15 bit_size: 1 - name: USB_OTG_HSRST @@ -1790,15 +1790,15 @@ fieldset/C1_AHB1ENR: description: ART Clock Enable bit_offset: 14 bit_size: 1 - - name: ETH1MACEN + - name: ETHEN description: Ethernet MAC bus interface Clock Enable bit_offset: 15 bit_size: 1 - - name: ETH1TXEN + - name: ETHTXEN description: Ethernet Transmission Clock Enable bit_offset: 16 bit_size: 1 - - name: ETH1RXEN + - name: ETHRXEN description: Ethernet Reception Clock Enable bit_offset: 17 bit_size: 1 @@ -1837,15 +1837,15 @@ fieldset/C1_AHB1LPENR: description: ART Clock Enable During CSleep Mode bit_offset: 14 bit_size: 1 - - name: ETH1MACLPEN + - name: ETHLPEN description: Ethernet MAC bus interface Clock Enable During CSleep Mode bit_offset: 15 bit_size: 1 - - name: ETH1TXLPEN + - name: ETHTXLPEN description: Ethernet Transmission Clock Enable During CSleep Mode bit_offset: 16 bit_size: 1 - - name: ETH1RXLPEN + - name: ETHRXLPEN description: Ethernet Reception Clock Enable During CSleep Mode bit_offset: 17 bit_size: 1 @@ -3055,10 +3055,6 @@ fieldset/D1CCIPR: bit_offset: 4 bit_size: 2 enum: FMCSEL - - name: DSISEL - description: kernel clock source selection - bit_offset: 8 - bit_size: 1 - name: SDMMCSEL description: SDMMC kernel clock source selection bit_offset: 16 diff --git a/data/registers/rcc_h7rs.yaml b/data/registers/rcc_h7rs.yaml new file mode 100644 index 0000000..dbcf0b2 --- /dev/null +++ b/data/registers/rcc_h7rs.yaml @@ -0,0 +1,4295 @@ +block/RCC: + description: Reset and clock control. + items: + - name: CR + description: RCC source control register. + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI calibration register. + byte_offset: 4 + fieldset: HSICFGR + - name: CRRCR + description: RCC clock recovery RC register. + byte_offset: 8 + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI calibration register. + byte_offset: 12 + fieldset: CSICFGR + - name: CFGR + description: RCC clock configuration register. + byte_offset: 16 + fieldset: CFGR + - name: CDCFGR + description: RCC CPU domain clock configuration register. + byte_offset: 24 + fieldset: CDCFGR + - name: BMCFGR + description: RCC AHB clock configuration register. + byte_offset: 28 + fieldset: BMCFGR + - name: APBCFGR + description: RCC APB clocks configuration register. + byte_offset: 32 + fieldset: APBCFGR + - name: PLLCKSELR + description: RCC PLLs clock source selection register. + byte_offset: 40 + fieldset: PLLCKSELR + - name: PLLCFGR + description: RCC PLLs configuration register. + byte_offset: 44 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL dividers configuration register 1. + array: + len: 3 + stride: 8 + byte_offset: 48 + fieldset: PLLDIVR + - name: PLLFRACR + description: RCC PLL fractional divider register. + array: + len: 3 + stride: 8 + byte_offset: 52 + fieldset: PLLFRACR + - name: AHBPERCKSELR + description: RCC AHB peripheral kernel clock selection register. + byte_offset: 76 + fieldset: AHBPERCKSELR + - name: APB1PERCKSELR + description: RCC APB1 peripherals kernel clock selection register. + byte_offset: 80 + fieldset: APB1PERCKSELR + - name: APB2PERCKSELR + description: RCC APB2 peripherals kernel clock selection register. + byte_offset: 84 + fieldset: APB2PERCKSELR + - name: APB45PERCKSELR + description: RCC APB4,5 peripherals kernel clock selection register. + byte_offset: 88 + fieldset: APB45PERCKSELR + - name: CIER + description: RCC clock source interrupt enable register. + byte_offset: 96 + fieldset: CIER + - name: CIFR + description: RCC clock source interrupt flag register. + byte_offset: 100 + fieldset: CIFR + - name: CICR + description: RCC clock source interrupt clear register. + byte_offset: 104 + fieldset: CICR + - name: BDCR + description: RCC Backup domain control register. + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: RCC clock control and status register. + byte_offset: 116 + fieldset: CSR + - name: AHB5RSTR + description: RCC AHB5 peripheral reset register. + byte_offset: 124 + fieldset: AHB5RSTR + - name: AHB1RSTR + description: RCC AHB1 peripheral reset register. + byte_offset: 128 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 peripheral reset register. + byte_offset: 132 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 peripheral reset register. + byte_offset: 136 + fieldset: AHB4RSTR + - name: APB5RSTR + description: RCC APB5 peripheral reset register. + byte_offset: 140 + fieldset: APB5RSTR + - name: APB1RSTR1 + description: RCC APB1 peripheral reset register 1. + byte_offset: 144 + fieldset: APB1RSTR1 + - name: APB1RSTR2 + description: RCC APB1 peripheral reset register 2. + byte_offset: 148 + fieldset: APB1RSTR2 + - name: APB2RSTR + description: RCC APB2 peripheral reset register. + byte_offset: 152 + fieldset: APB2RSTR + - name: APB4RSTR + description: RCC APB4 peripheral reset register. + byte_offset: 156 + fieldset: APB4RSTR + - name: AHB3RSTR + description: RCC AHB3 peripheral reset register. + byte_offset: 164 + fieldset: AHB3RSTR + - name: CKGDISR + description: RCC AXI clocks gating disable register. + byte_offset: 176 + fieldset: CKGDISR + - name: PLLDIVR2 + description: RCC PLL dividers configuration register 2. + array: + len: 3 + stride: 4 + byte_offset: 192 + fieldset: PLLDIVR2 + - name: PLLSSCGR + description: RCC PLL Spread Spectrum Clock Generator register. + array: + len: 3 + stride: 4 + byte_offset: 204 + fieldset: PLLSSCGR + - name: CKPROTR + description: RCC clock protection register. + byte_offset: 256 + fieldset: CKPROTR + - name: RSR + description: RCC Reset status register. + byte_offset: 304 + fieldset: RSR + - name: AHB5ENR + description: RCC AHB5 clock enable register. + byte_offset: 308 + fieldset: AHB5ENR + - name: AHB1ENR + description: RCC AHB1 clock enable register. + byte_offset: 312 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 clock enable register. + byte_offset: 316 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 clock enable register. + byte_offset: 320 + fieldset: AHB4ENR + - name: APB5ENR + description: RCC APB5 clock enable register. + byte_offset: 324 + fieldset: APB5ENR + - name: APB1ENR1 + description: RCC APB1 clock enable register 1. + byte_offset: 328 + fieldset: APB1ENR1 + - name: APB1ENR2 + description: RCC APB1 clock enable register 2. + byte_offset: 332 + fieldset: APB1ENR2 + - name: APB2ENR + description: RCC APB2 clock enable register. + byte_offset: 336 + fieldset: APB2ENR + - name: APB4ENR + description: RCC APB4 clock enable register. + byte_offset: 340 + fieldset: APB4ENR + - name: AHB3ENR + description: RCC AHB3 clock enable register. + byte_offset: 344 + fieldset: AHB3ENR + - name: AHB5LPENR + description: RCC AHB5 low-power clock enable register. + byte_offset: 348 + fieldset: AHB5LPENR + - name: AHB1LPENR + description: RCC AHB1 low-power clock enable register. + byte_offset: 352 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 low-power clock enable register. + byte_offset: 356 + fieldset: AHB2LPENR + - name: AHB4LPENR + description: RCC AHB4 low-power clock enable register. + byte_offset: 360 + fieldset: AHB4LPENR + - name: AHB3LPENR + description: RCC AHB3 low-power clock enable register. + byte_offset: 364 + fieldset: AHB3LPENR + - name: APB1LPENR1 + description: RCC APB1 low-power clock enable register 1. + byte_offset: 368 + fieldset: APB1LPENR1 + - name: APB1LPENR2 + description: RCC APB1 low-power clock enable register 2. + byte_offset: 372 + fieldset: APB1LPENR2 + - name: APB2LPENR + description: RCC APB2 low-power clock enable register. + byte_offset: 376 + fieldset: APB2LPENR + - name: APB4LPENR + description: RCC APB4 low-power clock enable register. + byte_offset: 380 + fieldset: APB4LPENR + - name: APB5LPENR + description: RCC APB5 sleep clock register. + byte_offset: 384 + fieldset: APB5LPENR +fieldset/AHB1ENR: + description: RCC AHB1 clock enable register. + fields: + - name: GPDMA1EN + description: GPDMA1 clock enable Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: ADC12EN + description: ADC1 and 2 peripheral clocks enable Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the hclk1 bus interface clock. + bit_offset: 5 + bit_size: 1 + - name: ETHEN + description: ETH1 MAC peripheral clock enable Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: ETHTXEN + description: ETH1 transmission clock enable Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: ETHRXEN + description: ETH1 reception clock enable Set and reset by software. + bit_offset: 17 + bit_size: 1 + - name: USB_OTG_HSEN + description: OTGHS clocks enable Set and reset by software. + bit_offset: 25 + bit_size: 1 + - name: USBPHYCEN + description: USBPHYC clocks enable Set and reset by software. + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSEN + description: OTGFS peripheral clocks enable Set and reset by software. + bit_offset: 27 + bit_size: 1 + - name: ADFEN + description: ADF clocks enable Set and reset by software. + bit_offset: 31 + bit_size: 1 +fieldset/AHB1LPENR: + description: RCC AHB1 low-power clock enable register. + fields: + - name: GPDMA1LPEN + description: GPDMA1 clock enable in low-power mode Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: ADC12LPEN + description: ADC1 and 2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the ADC1 and 2 are the kernel clock selected by ADCSEL and provided to ADCx_CK input, and the rcc_hclk1 bus interface clock. + bit_offset: 5 + bit_size: 1 + - name: ETHLPEN + description: ETH1 MAC peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: ETHTXLPEN + description: ETH1 transmission peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: ETHRXLPEN + description: ETH1 reception peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 17 + bit_size: 1 + - name: USBPDCTRL + description: USBPHYC common block power-down control Set and reset by software. + bit_offset: 24 + bit_size: 1 + enum: USBPDCTRL + - name: USB_OTG_HSLPEN + description: OTGHS peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 25 + bit_size: 1 + - name: USBPHYCLPEN + description: USBPHYC peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSLPEN + description: OTGFS clock enable in low-power mode Set and reset by software. + bit_offset: 27 + bit_size: 1 + - name: ADFLPEN + description: ADF clock enable in low-power mode Set and reset by software. + bit_offset: 31 + bit_size: 1 +fieldset/AHB1RSTR: + description: RCC AHB1 peripheral reset register. + fields: + - name: GPDMA1RST + description: GPDMA1 blocks reset Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: ADC12RST + description: ADC1 and 2 blocks reset Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: ETHRST + description: ETH1 block reset Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: USB_OTG_HSRST + description: OTGHS block reset Set and reset by software. + bit_offset: 25 + bit_size: 1 + - name: USBPHYCRST + description: USBPHYC block reset Set and reset by software. + bit_offset: 26 + bit_size: 1 + - name: USB_OTG_FSRST + description: OTGFS block reset Set and reset by software. + bit_offset: 27 + bit_size: 1 + - name: ADFRST + description: ADF block reset Set and reset by software. + bit_offset: 31 + bit_size: 1 +fieldset/AHB2ENR: + description: RCC AHB2 clock enable register. + fields: + - name: PSSIEN + description: PSSI peripheral clocks enable Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: SDMMC2EN + description: SDMMC2 and SDMMC2 delay clock enable Set and reset by software. + bit_offset: 9 + bit_size: 1 + - name: CORDICEN + description: CORDIC clock enable Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: SRAM1EN + description: SRAM1 clock enable Set and reset by software. + bit_offset: 29 + bit_size: 1 + - name: SRAM2EN + description: SRAM2 clock enable Set and reset by software. + bit_offset: 30 + bit_size: 1 +fieldset/AHB2LPENR: + description: RCC AHB2 low-power clock enable register. + fields: + - name: PSSILPEN + description: PSSI peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: SDMMC2LPEN + description: SDMMC2 and SDMMC2 delay clock enable in low-power mode Set and reset by software. + bit_offset: 9 + bit_size: 1 + - name: CORDICLPEN + description: CORDIC clock enable in low-power mode Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: SRAM1LPEN + description: SRAM1 clock enable in low-power mode Set and reset by software. + bit_offset: 29 + bit_size: 1 + - name: SRAM2LPEN + description: SRAM2 clock enable in low-power mode Set and reset by software. + bit_offset: 30 + bit_size: 1 +fieldset/AHB2RSTR: + description: RCC AHB2 peripheral reset register. + fields: + - name: PSSIRST + description: PSSI block reset Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: SDMMC2RST + description: SDMMC2 and SDMMC2 delay blocks reset Set and reset by software. + bit_offset: 9 + bit_size: 1 + - name: CORDICRST + description: CORDIC reset Set and reset by software. + bit_offset: 14 + bit_size: 1 +fieldset/AHB3ENR: + description: RCC AHB3 clock enable register. + fields: + - name: RNGEN + description: RNG peripheral clocks enable Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: HASHEN + description: HASH peripheral clock enable Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: CRYPEN + description: CRYP peripheral clock enable Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: SAESEN + description: SAES peripheral clock enable Set and reset by software. This bit controls the enable of the clock delivered to the SAES. + bit_offset: 4 + bit_size: 1 + - name: PKAEN + description: PKA peripheral clock enable Set and reset by software. + bit_offset: 6 + bit_size: 1 +fieldset/AHB3LPENR: + description: RCC AHB3 low-power clock enable register. + fields: + - name: RNGLPEN + description: RNG peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: HASHLPEN + description: HASH peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: CRYPLPEN + description: CRYP peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: SAESLPEN + description: SAES peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: PKALPEN + description: PKA peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 6 + bit_size: 1 +fieldset/AHB3RSTR: + description: RCC AHB3 peripheral reset register. + fields: + - name: RNGRST + description: random number generator block reset Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: HASHRST + description: HASH block reset Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: CRYPRST + description: CRYP block reset Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: SAESRST + description: SAES block reset Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: PKARST + description: PKA block reset Set and reset by software. + bit_offset: 6 + bit_size: 1 +fieldset/AHB4ENR: + description: RCC AHB4 clock enable register. + fields: + - name: GPIOAEN + description: GPIOA peripheral clock enable Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: GPIOBEN + description: GPIOB peripheral clock enable Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: GPIOCEN + description: GPIOC peripheral clock enable Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: GPIODEN + description: GPIOD peripheral clock enable Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: GPIOEEN + description: GPIOE peripheral clock enable Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: GPIOFEN + description: GPIOF peripheral clock enable Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: GPIOGEN + description: GPIOG peripheral clock enable Set and reset by software. + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: GPIOH peripheral clock enable Set and reset by software. + bit_offset: 7 + bit_size: 1 + - name: GPIOMEN + description: GPIOM peripheral clock enable Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: GPIONEN + description: GPION peripheral clock enable Set and reset by software. + bit_offset: 13 + bit_size: 1 + - name: GPIOOEN + description: GPIOO peripheral clock enable Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: GPIOPEN + description: GPIOP peripheral clock enable Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: CRCEN + description: CRC clock enable Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: BKPRAMEN + description: Backup RAM clock enable Set and reset by software. + bit_offset: 28 + bit_size: 1 +fieldset/AHB4LPENR: + description: RCC AHB4 low-power clock enable register. + fields: + - name: GPIOALPEN + description: GPIOA peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: GPIOBLPEN + description: GPIOB peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: GPIOCLPEN + description: GPIOC peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: GPIODLPEN + description: GPIOD peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: GPIOELPEN + description: GPIOE peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: GPIOFLPEN + description: GPIOF peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: GPIOGLPEN + description: GPIOG peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 6 + bit_size: 1 + - name: GPIOHLPEN + description: GPIOH peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 7 + bit_size: 1 + - name: GPIOMLPEN + description: GPIOM peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: GPIONLPEN + description: GPION peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 13 + bit_size: 1 + - name: GPIOOLPEN + description: GPIOO peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: GPIOPLPEN + description: GPIOP peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: CRCLPEN + description: CRC clock enable in low-power mode Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: BKPRAMLPEN + description: Backup RAM clock enable in low-power mode Set and reset by software. + bit_offset: 28 + bit_size: 1 +fieldset/AHB4RSTR: + description: RCC AHB4 peripheral reset register. + fields: + - name: GPIOARST + description: GPIOA block reset Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: GPIOBRST + description: GPIOB block reset Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: GPIOCRST + description: GPIOC block reset Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: GPIODRST + description: GPIOD block reset Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: GPIOERST + description: GPIOE block reset Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: GPIOFRST + description: GPIOF block reset Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: GPIOGRST + description: GPIOG block reset Set and reset by software. + bit_offset: 6 + bit_size: 1 + - name: GPIOHRST + description: GPIOH block reset Set and reset by software. + bit_offset: 7 + bit_size: 1 + - name: GPIOMRST + description: GPIOM block reset Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: GPIONRST + description: GPION block reset Set and reset by software. + bit_offset: 13 + bit_size: 1 + - name: GPIOORST + description: GPIOO block reset Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: GPIOPRST + description: GPIOP block reset Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: CRCRST + description: CRC block reset Set and reset by software. + bit_offset: 19 + bit_size: 1 +fieldset/AHB5ENR: + description: RCC AHB5 clock enable register. + fields: + - name: HPDMA1EN + description: HPDMA1 peripheral clock enable Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: DMA2DEN + description: DMA2D peripheral clock enable Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: JPEGEN + description: JPEG peripheral clock enable Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: FMCEN + description: FMC and MCE3 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. + bit_offset: 4 + bit_size: 1 + - name: XSPI1EN + description: XSPI1 and MCE1 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + bit_offset: 5 + bit_size: 1 + - name: SDMMC1EN + description: SDMMC1 and DB_SDMMC1 peripheral clocks enable Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: XSPI2EN + description: XSPI2 and MCE2 peripheral clocks enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + bit_offset: 12 + bit_size: 1 + - name: IOMNGREN + description: XSPIM peripheral clock enable Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: GFXMMUEN + description: GFXMMU peripheral clock enable Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: GPUEN + description: GPU peripheral clock enable Set and reset by software. + bit_offset: 20 + bit_size: 1 +fieldset/AHB5LPENR: + description: RCC AHB5 low-power clock enable register. + fields: + - name: HPDMA1LPEN + description: HPDMA1 low-power peripheral clock enable Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: DMA2DLPEN + description: DMA2D low-power peripheral clock enable Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: FLITFLPEN + description: FLITF low-power peripheral clock enable Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: JPEGLPEN + description: JPEG clock enable during Sleep mode Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: FMCLPEN + description: FMC and MCE3 peripheral clocks enable during Sleep mode Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. The peripheral clocks of the FMC are the kernel clock selected by FMCSEL, and the hclk5 bus interface clock. + bit_offset: 4 + bit_size: 1 + - name: XSPI1LPEN + description: XSPI1 and MCE1 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + bit_offset: 5 + bit_size: 1 + - name: SDMMC1LPEN + description: SDMMC1 and SDMMC1 delay low-power peripheral clock enable Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: XSPI2LPEN + description: XSPI2 and MCE2 low-power peripheral clock enable Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + bit_offset: 12 + bit_size: 1 + - name: XSPIMLPEN + description: XSPIM low-power peripheral clock enable Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: GFXMMULPEN + description: GFXMMU low-power peripheral clock enable Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: GPULPEN + description: GPU low-power peripheral clock enable Set and reset by software. + bit_offset: 20 + bit_size: 1 + - name: DTCM1LPEN + description: DTCM1 low-power peripheral clock enable Set and reset by software. + bit_offset: 28 + bit_size: 1 + - name: DTCM2LPEN + description: DTCM2 low-power peripheral clock enable Set and reset by software. + bit_offset: 29 + bit_size: 1 + - name: ITCMLPEN + description: ITCM low-power peripheral clock enable Set and reset by software. + bit_offset: 30 + bit_size: 1 + - name: AXISRAMLPEN + description: AXISRAM[4:1] low-power peripheral clock enable Set and reset by software. + bit_offset: 31 + bit_size: 1 +fieldset/AHB5RSTR: + description: RCC AHB5 peripheral reset register. + fields: + - name: HPDMA1RST + description: HPDMA1 block reset Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: DMA2DRST + description: DMA2D block reset Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: JPEGRST + description: JPEG block reset Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: FMCRST + description: FMC and MCE3 blocks reset Set and reset by software. The hardware prevents writing this bit if FMCCKP = 1. + bit_offset: 4 + bit_size: 1 + - name: XSPI1RST + description: XSPI1 and MCE1 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + bit_offset: 5 + bit_size: 1 + - name: SDMMC1RST + description: SDMMC1 and DB_SDMMC1 blocks reset Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: XSPI2RST + description: XSPI2 and MCE2 blocks reset Set and reset by software. The hardware prevents writing this bit if XSPICKP = 1. + bit_offset: 12 + bit_size: 1 + - name: IOMNGRRST + description: XSPIM reset Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: GFXMMURST + description: GFXMMU block reset Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: GPURST + description: GPU block reset Set and reset by software. + bit_offset: 20 + bit_size: 1 +fieldset/AHBPERCKSELR: + description: RCC AHB peripheral kernel clock selection register. + fields: + - name: FMCSEL + description: FMC kernel clock source selection Set and reset by software. + bit_offset: 0 + bit_size: 2 + enum: FMCSEL + - name: SDMMCSEL + description: SDMMC1 and SDMMC2 kernel clock source selection Set and reset by software. + bit_offset: 2 + bit_size: 1 + enum: SDMMCSEL + - name: OCTOSPI1SEL + description: 'XSPI1 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock.' + bit_offset: 4 + bit_size: 2 + enum: OCTOSPISEL + - name: OCTOSPI2SEL + description: 'XSPI2 kernel clock source selection Set and reset by software. 1x: pll2_t_ck selected as kernel peripheral clock.' + bit_offset: 6 + bit_size: 2 + enum: OCTOSPISEL + - name: USBREFCKSEL + description: 'USBPHYC kernel clock frequency selection Set and reset by software. This field is used to indicate to the USBPHYC, the frequency of the reference kernel clock provided to the USBPHYC. others: reserved.' + bit_offset: 8 + bit_size: 4 + enum: USBREFCKSEL + - name: USBPHYCSEL + description: USBPHYC kernel clock source selection Set and reset by software. + bit_offset: 12 + bit_size: 2 + enum: USBPHYCSEL + - name: USB_OTG_FSSEL + description: OTGFS kernel clock source selection Set and reset by software. + bit_offset: 14 + bit_size: 2 + enum: USB_OTG_FSSEL + - name: ETH_REF_CLK_SEL + description: 'Ethernet reference clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 16 + bit_size: 2 + enum: ETH_REF_CLK_SEL + - name: ETHPHY_CLK_SEL + description: Clock source selection for external Ethernet PHY Set and reset by software. + bit_offset: 18 + bit_size: 1 + enum: ETHPHY_CLK_SEL + - name: ADFSEL + description: 'ADF kernel clock source selection Set and reset by software. Note: I2S_CKIN is an external clock taken from a pin.' + bit_offset: 20 + bit_size: 3 + enum: ADFSEL + - name: ADCSEL + description: 'SAR ADC kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 24 + bit_size: 2 + enum: ADCSEL + - name: PSSISEL + description: PSSI kernel clock source selection Set and reset by software. + bit_offset: 27 + bit_size: 1 + enum: PSSISEL + - name: PERSEL + description: per_ck clock source selection. + bit_offset: 28 + bit_size: 2 + enum: PERSEL +fieldset/APB1ENR1: + description: RCC APB1 clock enable register 1. + fields: + - name: TIM2EN + description: TIM2 peripheral clock enable Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: TIM3 peripheral clock enable Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: TIM4 peripheral clock enable Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: TIM5EN + description: TIM5 peripheral clock enable Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: TIM6EN + description: TIM6 peripheral clock enable Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: TIM7 peripheral clock enable Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: TIM12EN + description: TIM12 peripheral clock enable Set and reset by software. + bit_offset: 6 + bit_size: 1 + - name: TIM13EN + description: TIM13 peripheral clock enable Set and reset by software. + bit_offset: 7 + bit_size: 1 + - name: TIM14EN + description: TIM14 peripheral clock enable Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: LPTIM1EN + description: LPTIM1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPTIM1 are the kernel clock selected by LPTIM1SEL and provided to clk_lpt input, and the rcc_pclk1 bus interface clock. + bit_offset: 9 + bit_size: 1 + - name: WWDGEN + description: WWDG clock enable Set by software, and reset by hardware when a system reset occurs. + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI2 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI3 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI3 are the kernel clock selected by I2S123SRC and provided to com_clk input, and the rcc_pclk1 bus interface clock. + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXEN + description: SPDIFRX peripheral clocks enable Set and reset by software. The peripheral clocks of the SPDIFRX are the kernel clock selected by SPDIFRXSEL and provided to SPDIFRX_CLK input, and the rcc_pclk1 bus interface clock. + bit_offset: 16 + bit_size: 1 + - name: USART2EN + description: USART2peripheral clocks enable Set and reset by software. The peripheral clocks of the USART2 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART3 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART3 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART4 are the kernel clock selected by USART234578SEL and provided to UCLK input, and the rcc_pclk1 bus interface clock. + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 peripheral clocks enable Set and reset by software. + bit_offset: 20 + bit_size: 1 + - name: I2C1_I3C1EN + description: I2C1/I3C1 peripheral clocks enable Set and reset by software. + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C2 peripheral clocks enable Set and reset by software. + bit_offset: 22 + bit_size: 1 + - name: I2C3EN + description: I2C3 peripheral clocks enable Set and reset by software. + bit_offset: 23 + bit_size: 1 + - name: CECEN + description: HDMI-CEC peripheral clock enable Set and reset by software. + bit_offset: 27 + bit_size: 1 + - name: UART7EN + description: UART7 peripheral clocks enable Set and reset by software. + bit_offset: 30 + bit_size: 1 + - name: UART8EN + description: UART8 peripheral clocks enable Set and reset by software. + bit_offset: 31 + bit_size: 1 +fieldset/APB1ENR2: + description: RCC APB1 clock enable register 2. + fields: + - name: CRSEN + description: clock recovery system peripheral clock enable Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: MDIOSEN + description: MDIOS peripheral clock enable Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: FDCANEN + description: FDCAN peripheral clock enable Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: UCPDEN + description: UCPD peripheral clock enable Set and reset by software. + bit_offset: 27 + bit_size: 1 +fieldset/APB1LPENR1: + description: RCC APB1 low-power clock enable register 1. + fields: + - name: TIM2LPEN + description: TIM2 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: TIM3LPEN + description: TIM3 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: TIM4LPEN + description: TIM4 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: TIM5LPEN + description: TIM5 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: TIM6LPEN + description: TIM6 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: TIM7LPEN + description: TIM7 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: TIM12LPEN + description: TIM12 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 6 + bit_size: 1 + - name: TIM13LPEN + description: TIM13 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 7 + bit_size: 1 + - name: TIM14LPEN + description: TIM14 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: LPTIM1LPEN + description: LPTIM1 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 9 + bit_size: 1 + - name: WWDGLPEN + description: WWDG clock enable in low-power mode Set and reset by software. + bit_offset: 11 + bit_size: 1 + - name: SPI2LPEN + description: SPI2 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: SPI3LPEN + description: SPI3 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXLPEN + description: SPDIFRX peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: USART2LPEN + description: USART2 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 17 + bit_size: 1 + - name: USART3LPEN + description: USART3 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 18 + bit_size: 1 + - name: UART4LPEN + description: UART4 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: UART5LPEN + description: UART5 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 20 + bit_size: 1 + - name: I2C1_I3C1LPEN + description: I2C1/I3C1 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 21 + bit_size: 1 + - name: I2C2LPEN + description: I2C2 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 22 + bit_size: 1 + - name: I2C3LPEN + description: I2C3 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 23 + bit_size: 1 + - name: CECLPEN + description: HDMI-CEC peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 27 + bit_size: 1 + - name: UART7LPEN + description: UART7 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 30 + bit_size: 1 + - name: UART8LPEN + description: UART8 peripheral clocks enable in low-power mode Set and reset by software. + bit_offset: 31 + bit_size: 1 +fieldset/APB1LPENR2: + description: RCC APB1 low-power clock enable register 2. + fields: + - name: CRSLPEN + description: clock recovery system peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: MDIOSLPEN + description: MDIOS peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: FDCANLPEN + description: FDCAN peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: UCPDLPEN + description: UCPD peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 27 + bit_size: 1 +fieldset/APB1PERCKSELR: + description: RCC APB1 peripherals kernel clock selection register. + fields: + - name: USART234578SEL + description: 'USART2,3, UART4,5,7,8 (APB1) kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 0 + bit_size: 3 + enum: USART234578SEL + - name: SPI23SEL + description: 'SPI/I2S2 and SPI/I2S3 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.' + bit_offset: 4 + bit_size: 3 + enum: SPI123SEL + - name: I2C23SEL + description: I2C2, I2C3 kernel clock source selection Set and reset by software. + bit_offset: 8 + bit_size: 2 + enum: I2CSEL + - name: I2C1_I3C1SEL + description: I2C1 or I3C1 kernel clock source selection Set and reset by software. + bit_offset: 12 + bit_size: 2 + enum: I2C1_I3C1SEL + - name: LPTIM1SEL + description: 'LPTIM1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 16 + bit_size: 3 + enum: LPTIM1SEL + - name: FDCANSEL + description: FDCAN kernel clock source selection. + bit_offset: 22 + bit_size: 2 + enum: FDCANSEL + - name: SPDIFRXSEL + description: SPDIFRX kernel clock source selection. + bit_offset: 24 + bit_size: 2 + enum: SPDIFRXSEL + - name: CECSEL + description: HDMI-CEC kernel clock source selection Set and reset by software. + bit_offset: 28 + bit_size: 2 + enum: CECSEL +fieldset/APB1RSTR1: + description: RCC APB1 peripheral reset register 1. + fields: + - name: TIM2RST + description: TIM2 block reset Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: TIM3 block reset Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: TIM4 block reset Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: TIM5RST + description: TIM5 block reset Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: TIM6RST + description: TIM6 block reset Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: TIM7 block reset Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: TIM12RST + description: TIM12 block reset Set and reset by software. + bit_offset: 6 + bit_size: 1 + - name: TIM13RST + description: TIM13 block reset Set and reset by software. + bit_offset: 7 + bit_size: 1 + - name: TIM14RST + description: TIM14 block reset Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: LPTIM1RST + description: LPTIM1 block reset Set and reset by software. + bit_offset: 9 + bit_size: 1 + - name: SPI2RST + description: SPI2S2 block reset Set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI2S3 block reset Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: SPDIFRXRST + description: SPDIFRX block reset Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: USART2RST + description: USART2 block reset Set and reset by software. + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 block reset Set and reset by software. + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART4 block reset Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART5 block reset Set and reset by software. + bit_offset: 20 + bit_size: 1 + - name: I2C1_I3C1RST + description: I2C1/I3C1 block reset Set and reset by software. + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 block reset Set and reset by software. + bit_offset: 22 + bit_size: 1 + - name: I2C3RST + description: I2C3 block reset Set and reset by software. + bit_offset: 23 + bit_size: 1 + - name: CECRST + description: HDMI-CEC block reset Set and reset by software. + bit_offset: 27 + bit_size: 1 + - name: UART7RST + description: UART7 block reset Set and reset by software. + bit_offset: 30 + bit_size: 1 + - name: UART8RST + description: UART8 block reset Set and reset by software. + bit_offset: 31 + bit_size: 1 +fieldset/APB1RSTR2: + description: RCC APB1 peripheral reset register 2. + fields: + - name: CRSRST + description: clock recovery system reset Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: MDIOSRST + description: MDIOS block reset Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: FDCANRST + description: FDCAN block reset Set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: UCPDRST + description: UCPD block reset Set and reset by software. + bit_offset: 27 + bit_size: 1 +fieldset/APB2ENR: + description: RCC APB2 clock enable register. + fields: + - name: TIM1EN + description: TIM1 peripheral clock enable Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: USART1EN + description: USART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART1SEL, and the pclk2 bus interface clock. + bit_offset: 4 + bit_size: 1 + - name: SPI1EN + description: 'SPI2S1 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by SPI1SEL, and the pclk2 bus interface clock.' + bit_offset: 12 + bit_size: 1 + - name: SPI4EN + description: 'SPI4 Peripheral Clocks Enable Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock.' + bit_offset: 13 + bit_size: 1 + - name: TIM15EN + description: TIM15 peripheral clock enable Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 peripheral clock enable Set and reset by software. + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 peripheral clock enable Set and reset by software. + bit_offset: 18 + bit_size: 1 + - name: TIM9EN + description: TIM9 peripheral clock enable Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: SPI5EN + description: SPI5 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL, and the pclk2 bus interface clock. + bit_offset: 20 + bit_size: 1 + - name: SAI1EN + description: SAI1 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI1 are the kernel clock selected by SAI1SEL, and the pclk2 bus interface clock. + bit_offset: 22 + bit_size: 1 + - name: SAI2EN + description: SAI2 peripheral clocks enable Set and reset by software. The peripheral clocks of the SAI2 are the kernel clock selected by SAI2SEL, and the pclk2 bus interface clock. + bit_offset: 23 + bit_size: 1 +fieldset/APB2LPENR: + description: RCC APB2 low-power clock enable register. + fields: + - name: TIM1LPEN + description: TIM1 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: USART1LPEN + description: USART1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the USART1 are the kernel clock selected by USART169SEL and provided to UCLK inputs, and the pclk2 bus interface clock. + bit_offset: 4 + bit_size: 1 + - name: SPI1LPEN + description: 'SPI2S1 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI2S1 are: the kernel clock selected by I2S1SEL and provided to spi_ker_ck input, and the pclk2 bus interface clock.' + bit_offset: 12 + bit_size: 1 + - name: SPI4LPEN + description: 'SPI4 peripheral clock enable in low-power mode Set and reset by software. The peripheral clocks of the SPI4 are: the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock.' + bit_offset: 13 + bit_size: 1 + - name: TIM15LPEN + description: TIM15 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: TIM16LPEN + description: TIM16 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 17 + bit_size: 1 + - name: TIM17LPEN + description: TIM17 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 18 + bit_size: 1 + - name: TIM9LPEN + description: TIM9 peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: SPI5LPEN + description: SPI5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI5 are the kernel clock selected by SPI45SEL and provided to com_clk input, and the pclk2 bus interface clock. + bit_offset: 20 + bit_size: 1 + - name: SAI1LPEN + description: 'SAI1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI1 are: the kernel clock selected by SAI1SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock.' + bit_offset: 22 + bit_size: 1 + - name: SAI2LPEN + description: 'SAI2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SAI2 are: the kernel clock selected by SAI2SEL and provided to SAI_CK_A and SAI_CK_B inputs, and the pclk2 bus interface clock.' + bit_offset: 23 + bit_size: 1 +fieldset/APB2PERCKSELR: + description: RCC APB2 peripherals kernel clock selection register. + fields: + - name: USART1SEL + description: 'USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 0 + bit_size: 3 + enum: USART1SEL + - name: SPI45SEL + description: 'SPI4 and 5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 4 + bit_size: 3 + enum: SPI45SEL + - name: SPI1SEL + description: 'SPI/I2S1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not be possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.' + bit_offset: 8 + bit_size: 3 + enum: SPI123SEL + - name: SAI1SEL + description: 'SAI1 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin.' + bit_offset: 16 + bit_size: 3 + enum: SAI1SEL + - name: SAI2SEL + description: 'SAI2 kernel clock source selection Set and reset by software. If the selected clock is the external clock and this clock is stopped, it is not possible to switch to another clock. Refer to Clock switches and gating on page 437 for additional information. others: reserved, the kernel clock is disabled Note: I2S_CKIN is an external clock taken from a pin. spdifrx_symb_ck is the symbol clock generated by the spdifrx (see Figure 51).' + bit_offset: 20 + bit_size: 3 + enum: SAI2SEL +fieldset/APB2RSTR: + description: RCC APB2 peripheral reset register. + fields: + - name: TIM1RST + description: TIM1 block reset Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: USART1RST + description: USART1 block reset Set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: SPI1RST + description: SPI2S1 block reset Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: SPI4RST + description: SPI4 block reset Set and reset by software. + bit_offset: 13 + bit_size: 1 + - name: TIM15RST + description: TIM15 block reset Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 block reset Set and reset by software. + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 block reset Set and reset by software. + bit_offset: 18 + bit_size: 1 + - name: TIM9RST + description: TIM9 block reset Set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: SPI5RST + description: SPI5 block reset Set and reset by software. + bit_offset: 20 + bit_size: 1 + - name: SAI1RST + description: SAI1 block reset Set and reset by software. + bit_offset: 22 + bit_size: 1 + - name: SAI2RST + description: SAI2 block reset Set and reset by software. + bit_offset: 23 + bit_size: 1 +fieldset/APB45PERCKSELR: + description: RCC APB4,5 peripherals kernel clock selection register. + fields: + - name: LPUART1SEL + description: 'LPUART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 0 + bit_size: 3 + enum: LPUARTSEL + - name: SPI6SEL + description: 'SPI/I2S6 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 4 + bit_size: 3 + enum: SPI6SEL + - name: LPTIM23SEL + description: 'LPTIM2 and LPTIM3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 8 + bit_size: 3 + enum: LPTIMSEL + - name: LPTIM45SEL + description: 'LPTIM4, and LPTIM5 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled.' + bit_offset: 12 + bit_size: 3 + enum: LPTIMSEL +fieldset/APB4ENR: + description: RCC APB4 clock enable register. + fields: + - name: SYSCFGEN + description: SBS peripheral clock enable Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: LPUART1EN + description: LPUART1 peripheral clocks enable Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the pclk4 bus interface clock. + bit_offset: 3 + bit_size: 1 + - name: SPI6EN + description: SPI/I2S6 peripheral clocks enable Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_clk input, and the pclk4 bus interface clock. + bit_offset: 5 + bit_size: 1 + - name: LPTIM2EN + description: LPTIM2 peripheral clocks enable Set and reset by software. The LPTIM2 kernel clock can be selected by LPTIM23SEL. + bit_offset: 9 + bit_size: 1 + - name: LPTIM3EN + description: LPTIM3 peripheral clocks enable Set and reset by software. The LPTIM3 kernel clock can be selected by LPTIM23SEL. + bit_offset: 10 + bit_size: 1 + - name: LPTIM4EN + description: LPTIM4 peripheral clocks enable Set and reset by software. The LPTIM4 kernel clock can be selected by LPTIM45SEL. + bit_offset: 11 + bit_size: 1 + - name: LPTIM5EN + description: LPTIM5 peripheral clocks enable Set and reset by software. The LPTIM5 kernel clock can be selected by LPTIM45SEL. + bit_offset: 12 + bit_size: 1 + - name: VREFEN + description: VREF peripheral clock enable Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: RTCAPBEN + description: RTC APB clock enable Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: TMPSENSEN + description: Temperature Sensor peripheral clock enable Set and reset by software. + bit_offset: 26 + bit_size: 1 +fieldset/APB4LPENR: + description: RCC APB4 low-power clock enable register. + fields: + - name: SYSCFGLPEN + description: SBS peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: LPUART1LPEN + description: LPUART1 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPUART1 are the kernel clock selected by LPUART1SEL and provided to UCLK input, and the rcc_pclk4 bus interface clock. + bit_offset: 3 + bit_size: 1 + - name: SPI6LPEN + description: SPI/I2S6 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the SPI/I2S6 are the kernel clock selected by SPI6SEL and provided to com_ck input, and the rcc_pclk4 bus interface clock. + bit_offset: 5 + bit_size: 1 + - name: LPTIM2LPEN + description: LPTIM2 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM2 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock. + bit_offset: 9 + bit_size: 1 + - name: LPTIM3LPEN + description: LPTIM3 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM3 are the kernel clock selected by LPTIM23SEL and provided to clk_lpt input, and the pclk4 bus interface clock. + bit_offset: 10 + bit_size: 1 + - name: LPTIM4LPEN + description: LPTIM4 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM4 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock. + bit_offset: 11 + bit_size: 1 + - name: LPTIM5LPEN + description: LPTIM5 peripheral clocks enable in low-power mode Set and reset by software. The peripheral clocks of the LPTIM5 are the kernel clock selected by LPTIM45SEL and provided to clk_lpt input, and the pclk4 bus interface clock. + bit_offset: 12 + bit_size: 1 + - name: VREFLPEN + description: VREF peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: RTCAPBLPEN + description: RTC APB clock enable in low-power mode Set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: TMPSENSLPEN + description: temperature sensor peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 26 + bit_size: 1 +fieldset/APB4RSTR: + description: RCC APB4 peripheral reset register. + fields: + - name: SYSCFGRST + description: SBS block reset Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: LPUART1RST + description: LPUART1 block reset Set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: SPI6RST + description: SPI/I2S6 block reset Set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: LPTIM2RST + description: LPTIM2 block reset Set and reset by software. + bit_offset: 9 + bit_size: 1 + - name: LPTIM3RST + description: LPTIM3 block reset Set and reset by software. + bit_offset: 10 + bit_size: 1 + - name: LPTIM4RST + description: LPTIM4 block reset Set and reset by software. + bit_offset: 11 + bit_size: 1 + - name: LPTIM5RST + description: LPTIM5 block reset Set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: VREFRST + description: VREF block reset Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: TMPSENSRST + description: TMPSENS block reset Set and reset by software. + bit_offset: 26 + bit_size: 1 +fieldset/APB5ENR: + description: RCC APB5 clock enable register. + fields: + - name: LTDCEN + description: LTDC peripheral clock enable Provides the pixel clock (ltdc_clk) to the LTDC block. Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: DCMIPPEN + description: DCMIPP peripheral clock enable Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: GFXTIMEN + description: GFXTIM peripheral clock enable Set and reset by software. + bit_offset: 4 + bit_size: 1 +fieldset/APB5LPENR: + description: RCC APB5 sleep clock register. + fields: + - name: LTDCLPEN + description: LTDC peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: DCMIPPLPEN + description: DCMIPP peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: GFXTIMLPEN + description: GFXTIM peripheral clock enable in low-power mode Set and reset by software. + bit_offset: 4 + bit_size: 1 +fieldset/APB5RSTR: + description: RCC APB5 peripheral reset register. + fields: + - name: LTDCRST + description: LTDC block reset Set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: DCMIPPRST + description: DCMIPP block reset Set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: GFXTIMRST + description: GFXTIM block reset Set and reset by software. + bit_offset: 4 + bit_size: 1 +fieldset/APBCFGR: + description: RCC APB clocks configuration register. + fields: + - name: PPRE1 + description: 'CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset).' + bit_offset: 0 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: 'CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset).' + bit_offset: 4 + bit_size: 3 + enum: PPRE + - name: PPRE4 + description: 'CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset).' + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE5 + description: 'CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset).' + bit_offset: 12 + bit_size: 3 + enum: PPRE +fieldset/BDCR: + description: RCC Backup domain control register. + fields: + - name: LSEON + description: LSE oscillator enabled Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0. + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1). + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit can only be disabled, After a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON. After a back-up domain reset. + bit_offset: 5 + bit_size: 1 + - name: LSECSSD + description: LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator. + bit_offset: 6 + bit_size: 1 + - name: LSEEXT + description: low-speed external clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled. + bit_offset: 7 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST). + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: LSECSSRA + description: 'Re-Arm the LSECSS function Set by software. After a LSE failure detection, the software application can re-enable the LSECSS by writing this bit to 1. Reading this bit returns the written value. Prior to set this bit to 1, LSECSSON must be set to 0. Please refer to Section : CSS on LSE for details.' + bit_offset: 12 + bit_size: 1 + - name: RTCEN + description: RTC clock enable Set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: VSWRST + description: VSwitch domain software reset Set and reset by software. To generate a VSW reset, it is recommended to write this bit to 1, then back to 0. + bit_offset: 16 + bit_size: 1 +fieldset/BMCFGR: + description: RCC AHB clock configuration register. + fields: + - name: BMPRE + description: 'Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck.' + bit_offset: 0 + bit_size: 4 + enum: HPRE +fieldset/CDCFGR: + description: RCC CPU domain clock configuration register. + fields: + - name: CPRE + description: 'CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset).' + bit_offset: 0 + bit_size: 4 + enum: HPRE +fieldset/CFGR: + description: RCC clock configuration register. + fields: + - name: SW + description: 'system clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock. others: reserved.' + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: 'system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved.' + bit_offset: 3 + bit_size: 3 + enum: SW + - name: STOPWUCK + description: 'system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).' + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: 'kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details.' + bit_offset: 7 + bit_size: 1 + enum: STOPKERWUCK + - name: RTCPRE + description: 'HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. ...' + bit_offset: 8 + bit_size: 6 + - name: TIMPRE + description: 'timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. or 4, else it is equal to 4 x Frcc_pclkx_d2 Refer to Table 64: Ratio between clock timer and pclk for more details.' + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... + bit_offset: 18 + bit_size: 4 + enum: MCOPRE + - name: MCO1SEL + description: 'Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.' + bit_offset: 22 + bit_size: 3 + enum: MCO1SEL + - name: MCO2PRE + description: MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. ... + bit_offset: 25 + bit_size: 4 + enum: MCOPRE + - name: MCO2SEL + description: 'microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.' + bit_offset: 29 + bit_size: 3 + enum: MCO2SEL +fieldset/CICR: + description: RCC clock source interrupt clear register. + fields: + - name: LSIRDYC + description: LSI ready interrupt clear Set by software to clear LSIRDYF. Reset by hardware when clear done. + bit_offset: 0 + bit_size: 1 + - name: LSERDYC + description: LSE ready interrupt clear Set by software to clear LSERDYF. Reset by hardware when clear done. + bit_offset: 1 + bit_size: 1 + - name: HSIRDYC + description: HSI ready interrupt clear Set by software to clear HSIRDYF. Reset by hardware when clear done. + bit_offset: 2 + bit_size: 1 + - name: HSERDYC + description: HSE ready interrupt clear Set by software to clear HSERDYF. Reset by hardware when clear done. + bit_offset: 3 + bit_size: 1 + - name: CSIRDYC + description: CSI ready interrupt clear Set by software to clear CSIRDYF. Reset by hardware when clear done. + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: HSI48 ready interrupt clear Set by software to clear HSI48RDYF. Reset by hardware when clear done. + bit_offset: 5 + bit_size: 1 + - name: PLLRDYC + description: PLL1 ready interrupt clear Set by software to clear PLL1RDYF. Reset by hardware when clear done. + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSC + description: LSE clock security system interrupt clear Set by software to clear LSECSSF. Reset by hardware when clear done. + bit_offset: 9 + bit_size: 1 + - name: HSECSSC + description: HSE clock security system interrupt clear Set by software to clear HSECSSF. Reset by hardware when clear done. + bit_offset: 10 + bit_size: 1 +fieldset/CIER: + description: RCC clock source interrupt enable register. + fields: + - name: LSIRDYIE + description: LSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization. + bit_offset: 0 + bit_size: 1 + - name: LSERDYIE + description: LSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization. + bit_offset: 1 + bit_size: 1 + - name: HSIRDYIE + description: HSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization. + bit_offset: 2 + bit_size: 1 + - name: HSERDYIE + description: HSE ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization. + bit_offset: 3 + bit_size: 1 + - name: CSIRDYIE + description: CSI ready interrupt enable Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization. + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYIE + description: HSI48 ready interrupt enable Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. + bit_offset: 5 + bit_size: 1 + - name: PLLRDYIE + description: PLL1 ready interrupt enable Set and reset by software to enable/disable interrupt caused by PLL1 lock. + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSIE + description: LSE clock security system interrupt enable Set and reset by software to enable/disable interrupt caused by the clock security system (CSS) on external 32 kHz oscillator. + bit_offset: 9 + bit_size: 1 +fieldset/CIFR: + description: RCC clock source interrupt flag register. + fields: + - name: LSIRDYF + description: LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set. + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set. + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set. + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set. + bit_offset: 3 + bit_size: 1 + - name: CSIRDYF + description: CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set. + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set. + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSF + description: LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set. + bit_offset: 9 + bit_size: 1 + - name: HSECSSF + description: HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure. + bit_offset: 10 + bit_size: 1 +fieldset/CKGDISR: + description: RCC AXI clocks gating disable register. + fields: + - name: AXICKG + description: AXI interconnect matrix clock gating disable This bit is set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: AHBMCKG + description: AXI master AHB clock gating disable This bit is set and reset by software. + bit_offset: 1 + bit_size: 1 + - name: SDMMC1CKG + description: AXI master SDMMC1 clock gating disable This bit is set and reset by software. + bit_offset: 2 + bit_size: 1 + - name: HPDMA1CKG + description: AXI master HPDMA1 clock gating disable This bit is set and reset by software. + bit_offset: 3 + bit_size: 1 + - name: CPUCKG + description: AXI master CPU clock gating disable This bit is set and reset by software. + bit_offset: 4 + bit_size: 1 + - name: GPUS0CKG + description: AXI master 0 GPU clock gating disable This bit is set and reset by software. + bit_offset: 5 + bit_size: 1 + - name: GPUS1CKG + description: AXI master 1 GPU clock gating disable This bit is set and reset by software. + bit_offset: 6 + bit_size: 1 + - name: GPUCLCKG + description: AXI master cache GPU clock gating disable This bit is set and reset by software. + bit_offset: 7 + bit_size: 1 + - name: DCMIPPCKG + description: AXI master DCMIPP clock gating disable This bit is set and reset by software. + bit_offset: 8 + bit_size: 1 + - name: DMA2DCKG + description: AXI master DMA2D clock gating disable This bit is set and reset by software. + bit_offset: 9 + bit_size: 1 + - name: GFXMMUSCKG + description: AXI matrix slave GFXMMU clock gating disable This bit is set and reset by software. + bit_offset: 10 + bit_size: 1 + - name: LTDCCKG + description: AXI master LTDC clock gating disable This bit is set and reset by software. + bit_offset: 11 + bit_size: 1 + - name: GFXMMUMCKG + description: AXI master GFXMMU clock gating disable This bit is set and reset by software. + bit_offset: 12 + bit_size: 1 + - name: AHBSCKG + description: AXI slave AHB clock gating disable This bit is set and reset by software. + bit_offset: 13 + bit_size: 1 + - name: FMCCKG + description: AXI slave FMC and MCE3 clock gating disable This bit is set and reset by software. + bit_offset: 14 + bit_size: 1 + - name: XSPI1CKG + description: AXI slave XSPI1 and MCE1 clock gating disable This bit is set and reset by software. + bit_offset: 15 + bit_size: 1 + - name: XSPI2CKG + description: AXI slave XSPI2 and MCE2 clock gating disable This bit is set and reset by software. + bit_offset: 16 + bit_size: 1 + - name: AXIRAM4CKG + description: AXI matrix slave SRAM4 clock gating disable This bit is set and reset by software. + bit_offset: 17 + bit_size: 1 + - name: AXIRAM3CKG + description: AXI matrix slave SRAM3 clock gating disable This bit is set and reset by software. + bit_offset: 18 + bit_size: 1 + - name: AXIRAM2CKG + description: AXI slave SRAM2 clock gating disable This bit is set and reset by software. + bit_offset: 19 + bit_size: 1 + - name: AXIRAM1CKG + description: AXI slave SRAM1 / error code correction (ECC) clock gating disable This bit is set and reset by software. + bit_offset: 20 + bit_size: 1 + - name: FLITFCKG + description: AXI slave Flash interface (FLIFT) clock gating disable This bit is set and reset by software. + bit_offset: 21 + bit_size: 1 + - name: EXTICKG + description: EXTI clock gating disable This bit is set and reset by software. + bit_offset: 30 + bit_size: 1 + - name: JTAGCKG + description: JTAG automatic clock gating disabling This bit is set and reset by software. + bit_offset: 31 + bit_size: 1 +fieldset/CKPROTR: + description: RCC clock protection register. + fields: + - name: XSPICKP + description: 'XSPI clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the XSPIs. The following fields cannot be modified when this bit is set to 1: PLL2ON, PLL2DIVSEN, PLL2DIVTEN, HSEON, HSION, CSION, XSPIxEN, OCTOSPIxLPEN, OCTOSPIxRST.' + bit_offset: 0 + bit_size: 1 + - name: FMCCKP + description: 'FMC clock protection Set and cleared by software. When set to 1, this bit prevents disabling accidentally the FMC. The following fields cannot be modified when this bit is set to 1: PLL1ON, PLL2ON, PLL1DIVQEN, PLL2DIVREN, HSEON, HSION, CSION, FMCEN, FMCLPEN, FMCRST.' + bit_offset: 1 + bit_size: 1 + - name: XSPI1SWP + description: XSPI1 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector. + bit_offset: 4 + bit_size: 3 + enum: XSPISWP + - name: XSPI2SWP + description: XSPI2 kernel clock switch position Set by hardware. This field can be used to verify the real position of XSPI2 kernel switch selector. + bit_offset: 8 + bit_size: 3 + enum: XSPISWP + - name: FMCSWP + description: FMC kernel clock switch position Set by hardware. This field can be used to verify the real position of FMC kernel switch selector. + bit_offset: 12 + bit_size: 3 + enum: FMCSWP +fieldset/CR: + description: RCC source control register. + fields: + - name: HSION + description: HSI clock enable Set and cleared by software. Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 0 or STOPKERWUCK = 0. Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source. This bit cannot be cleared if the HSI is used directly (via SW switch) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. + bit_offset: 0 + bit_size: 1 + - name: HSIKERON + description: HSI clock enable in Stop mode Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION. + bit_offset: 1 + bit_size: 1 + - name: HSIRDY + description: HSI clock ready flag Set by hardware to indicate that the HSI oscillator is stable. + bit_offset: 2 + bit_size: 1 + - name: HSIDIV + description: HSI clock divider Set and reset by software. These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored. + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: HSI divider flag Set and reset by hardware. As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV. clock setting is completed). + bit_offset: 5 + bit_size: 1 + - name: CSION + description: CSI clock enable Set and reset by software to enable/disable CSI clock for system and/or peripheral. Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1. This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. + bit_offset: 7 + bit_size: 1 + - name: CSIRDY + description: CSI clock ready flag Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request). + bit_offset: 8 + bit_size: 1 + - name: CSIKERON + description: CSI clock enable in Stop mode Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION. + bit_offset: 9 + bit_size: 1 + - name: HSI48ON + description: HSI48 clock enable Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode. + bit_offset: 12 + bit_size: 1 + - name: HSI48RDY + description: HSI48 clock ready flag Set by hardware to indicate that the HSI48 oscillator is stable. + bit_offset: 13 + bit_size: 1 + - name: HSEON + description: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE when entering Stop or Standby mode. This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1) or if FMCCKP = 1, or if XSPICKP = 1. + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: HSE clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. + bit_offset: 18 + bit_size: 1 + - name: HSEEXT + description: external high speed clock type in Bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled. + bit_offset: 19 + bit_size: 1 + enum: HSEEXT + - name: HSECSSON + description: HSE clock security system enable Set by software to enable clock security system on HSE. This bit is set only (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected. + bit_offset: 20 + bit_size: 1 + - name: PLLON + description: PLL1 enable Set and cleared by software to enable PLL1. Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3) or if FMCCKP = 1, or if XSPICKP = 1. + bit_offset: 24 + bit_size: 1 + array: + len: 3 + stride: 2 + - name: PLLRDY + description: PLL1 clock ready flag Set by hardware to indicate that the PLL1 is locked. + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 2 +fieldset/CRRCR: + description: RCC clock recovery RC register. + fields: + - name: HSI48CAL + description: Internal RC 48 MHz clock calibration Set by hardware by option byte loading. Read-only. + bit_offset: 0 + bit_size: 10 +fieldset/CSICFGR: + description: RCC CSI calibration register. + fields: + - name: CSICAL + description: CSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits CSITRIM. This field represents the sum of engineering option byte calibration value and CSITRIM bits value. + bit_offset: 0 + bit_size: 8 + - name: CSITRIM + description: 'CSI clock trimming Set by software to adjust calibration. CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_opt) in order to form the calibration trimming value. CSICAL = CSITRIM + FLASH_CSI_opt. Note: The reset value of the field is 0x20.' + bit_offset: 24 + bit_size: 6 +fieldset/CSR: + description: RCC clock control and status register. + fields: + - name: LSION + description: LSI oscillator enable Set and reset by software. + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: LSI oscillator ready Set and reset by hardware to indicate when the low-speed internal RC oscillator is stable. This bit needs 3 cycles of lsi_ck clock to fall down after LSION has been set to 0. This bit can be set even when LSION is not enabled if there is a request for LSI clock by the clock security system on LSE or by the low-speed watchdog or by the RTC. + bit_offset: 1 + bit_size: 1 +fieldset/HSICFGR: + description: RCC HSI calibration register. + fields: + - name: HSICAL + description: HSI clock calibration Set by hardware by option byte loading. Adjusted by software through trimming bits HSITRIM. This field represents the sum of engineering option byte calibration value and HSITRIM bits value. + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: 'HSI clock trimming Set by software to adjust calibration. HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value. HSICAL = HSITRIM + FLASH_HSI_opt. Note: The reset value of the field is 0x40.' + bit_offset: 24 + bit_size: 7 +fieldset/PLLCFGR: + description: RCC PLLs configuration register. + fields: + - name: PLLFRACEN + description: PLL1 fractional latch enable Set and reset by software to latch the content of FRACN into the sigma-delta modulator. In order to latch the FRACN value into the sigma-delta modulator, PLL1FRACLE must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN into the modulator. Refer to PLL initialization procedure on page 444 for additional information. + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 11 + - name: PLLVCOSEL + description: 'PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. It allows the application to select the VCO range: VCOH: working from 400 to 1600 MHz (Fref1_ck must be between 2 and 16 MHz) VCOL: working from 150 to 420 MHz (Fref1_ck must be between 1 and 2 MHz).' + bit_offset: 1 + bit_size: 1 + array: + len: 3 + stride: 11 + enum: PLLVCOSEL + - name: PLLSSCGEN + description: PLL1 SSCG enable Set and reset by software to enable the Spread Spectrum Clock Generator of PLL1, in order to reduce the amount of EMI peaks. + bit_offset: 2 + bit_size: 1 + array: + len: 3 + stride: 11 + - name: PLLRGE + description: PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. + bit_offset: 3 + bit_size: 2 + array: + len: 3 + stride: 11 + enum: PLLRGE + - name: DIVPEN + description: PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. The hardware prevents writing this bit to 0, if the PLL1 output is used as the system clock (SW=3). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. + bit_offset: 5 + bit_size: 1 + array: + len: 3 + stride: 11 + - name: DIVQEN + description: PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. The hardware prevents writing this bit if FMCCKP = 1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 11 + - name: DIVREN + description: PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1DIVREN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 11 + - name: DIVSEN + description: PLL1 DIVS divider output enable Set and reset by software to enable the pll1_s_ck output of the PLL1. To save power, PLL1DIVSEN must be set to 0 when the pll1_s_ck is not used. + bit_offset: 8 + bit_size: 1 + array: + len: 3 + stride: 11 + - name: DIVTEN + description: PLL1 DIVT divider output enable Set and reset by software to enable the pll1_t_ck output of the PLL1. To save power, PLL1DIVTEN must be set to 0 when the pll1_t_ck is not used. + bit_offset: 9 + bit_size: 1 + array: + len: 3 + stride: 11 +fieldset/PLLCKSELR: + description: RCC PLLs clock source selection register. + fields: + - name: PLLSRC + description: DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11. + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: DIVM + description: prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. ... ... + bit_offset: 4 + bit_size: 6 + array: + len: 3 + stride: 8 + enum: PLLM +fieldset/PLLDIVR: + description: RCC PLL1 dividers configuration register 1. + fields: + - name: PLLN + description: 'multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = PLL1RDY = 0). ..........: not used ... ... Others: wrong configurations The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x DIVN1, when fractional value 0 has been loaded into FRACN, with: DIVN1 between 8 and 420 The input frequency Fref1_ck must be between 1 and 16 MHz.' + bit_offset: 0 + bit_size: 9 + enum: PLLN + - name: PLLP + description: PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1DIVPEN = 0. ... + bit_offset: 9 + bit_size: 7 + enum: PLLDIV + - name: PLLQ + description: PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1DIVQEN = 0. ... + bit_offset: 16 + bit_size: 7 + enum: PLLDIV + - name: PLLR + description: PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1_r_ck clock. These bits can be written only when the PLL1DIVREN = 0. ... + bit_offset: 24 + bit_size: 7 + enum: PLLDIV +fieldset/PLLDIVR2: + description: RCC PLL1 dividers configuration register 2. + fields: + - name: PLLS + description: 'PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0.' + bit_offset: 0 + bit_size: 3 + enum: PLLDIVST + - name: PLLT + description: 'PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0.' + bit_offset: 8 + bit_size: 3 + enum: PLLDIVST +fieldset/PLLFRACR: + description: RCC PLL1 fractional divider register. + fields: + - name: FRACN + description: 'fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is: 128 to 544 MHz if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (DIVN1 + (FRACN / 213)), with DIVN1 between 8 and 420 FRACN can be between 0 and 213- 1 The input frequency Fref1_ck must be between 1 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL1FRACLE to 0. Write the new fractional value into FRACN. Set the bit PLL1FRACLE to 1.' + bit_offset: 3 + bit_size: 13 +fieldset/PLLSSCGR: + description: RCC PLL1 Spread Spectrum Clock Generator register. + fields: + - name: MOD_PER + description: Modulation Period Adjustment for PLL1 Set and reset by software to adjust the modulation period of the clock spreading generator. + bit_offset: 0 + bit_size: 13 + - name: TPDFN_DIS1 + description: Dithering TPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a triangular probability density function. + bit_offset: 13 + bit_size: 1 + - name: RPDFN_DIS1 + description: Dithering RPDF noise control for PLL1 Set and reset by software. This bit is used to enable or disable the injection of a dithering noise into the SSCG modulator. This dithering noise is generated using a rectangular probability density function. + bit_offset: 14 + bit_size: 1 + - name: DWNSPREAD1 + description: Spread spectrum clock generator mode for PLL1 Set and reset by software to select the clock spreading mode. + bit_offset: 15 + bit_size: 1 + enum: DWNSPREAD + - name: INC_STEP + description: Modulation Depth Adjustment for PLL1 Set and reset by software to adjust the modulation depth of the clock spreading generator. + bit_offset: 16 + bit_size: 15 +fieldset/RSR: + description: RCC Reset status register. + fields: + - name: RMVF + description: remove reset flag Set and reset by software to reset the value of the reset flags. + bit_offset: 16 + bit_size: 1 + - name: OBLRSTF + description: Option byte loading reset flag (1) Reset by software by the RMVF bit. Set by hardware when a reset from the option byte loading occurs. + bit_offset: 17 + bit_size: 1 + - name: BORRSTF + description: BOR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a BOR reset occurs (pwr_bor_rst). + bit_offset: 21 + bit_size: 1 + - name: PINRSTF + description: pin reset flag (NRST) (1) Reset by software by writing the RMVF bit. Set by hardware when a reset from pin occurs. + bit_offset: 22 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a POR/PDR reset occurs. + bit_offset: 23 + bit_size: 1 + - name: SFTRSTF + description: system reset from CPU reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M7. + bit_offset: 24 + bit_size: 1 + - name: IWDGRSTF + description: independent watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when an independent watchdog reset occurs. + bit_offset: 26 + bit_size: 1 + - name: WWDGRSTF + description: window watchdog reset flag (1) Reset by software by writing the RMVF bit. Set by hardware when a window watchdog reset occurs. + bit_offset: 28 + bit_size: 1 + - name: LPWRRSTF + description: reset due to illegal Stop or Standby flag Reset by software by writing the RMVF bit. Set by hardware when the CPU goes erroneously in Stop or Standby mode,. + bit_offset: 30 + bit_size: 1 +enum/ADCSEL: + bit_size: 2 + variants: + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: PER + description: PER selected as peripheral clock + value: 2 +enum/ADFSEL: + bit_size: 3 + variants: + - name: HCLK1 + description: hclk1 selected as ADF kernel clock (default after reset). + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as ADF kernel clock. + value: 1 +enum/CECSEL: + bit_size: 2 + variants: + - name: LSE + description: LSE selected as peripheral clock + value: 0 + - name: LSI + description: LSI selected as peripheral clock + value: 1 + - name: CSI + description: csi_ker selected as peripheral clock + value: 2 +enum/DWNSPREAD: + bit_size: 1 + variants: + - name: CenterSpread + description: Center-spread modulation selected (default after reset). + value: 0 + - name: DownSpread + description: Down-spread modulation selected. + value: 1 +enum/ETHPHY_CLK_SEL: + bit_size: 1 + variants: + - name: HSE + description: hse_ker_ck selected as clock source (default after reset). + value: 0 + - name: PLL3_S + description: pll3_s_ck selected clock source. + value: 1 +enum/ETH_REF_CLK_SEL: + bit_size: 2 + variants: + - name: ETH_RMII_REF + description: PAD ETH_RMII_REF_CLK selected as kernel peripheral clock (default after reset). + value: 0 + - name: HSE + description: hse_ker_ck selected as kernel peripheral clock. + value: 1 + - name: ETH + description: eth_clk_fb selected as kernel peripheral clock. + value: 2 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: HSE + description: HSE selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 2 +enum/FMCSEL: + bit_size: 2 + variants: + - name: HCLK5 + description: hclk5 selected as kernel peripheral clock (default after reset). + value: 0 + - name: PLL1_Q + description: pll1_q_ck selected as kernel peripheral clock. + value: 1 + - name: PLL2_R + description: pll2_r_ck selected as kernel peripheral clock. + value: 2 + - name: HSI + description: hsi_ker_ck selected as kernel peripheral clock. + value: 3 +enum/FMCSWP: + bit_size: 3 + variants: + - name: B_0x0 + description: The switch is in neutral mode and output clock is gated (default after reset). + value: 0 + - name: B_0x1 + description: The switch is selecting hclk5. + value: 1 + - name: B_0x2 + description: The switch is selecting pll1_q_ck. + value: 2 + - name: B_0x3 + description: The switch is selecting pll2_r_ck. + value: 3 + - name: B_0x4 + description: The switch is selecting hsi_ker_ck. + value: 4 + - name: B_0x5 + description: The switch is in recovery position (hclk5/4). + value: 5 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 8 + - name: Div4 + value: 9 + - name: Div8 + value: 10 + - name: Div16 + value: 11 + - name: Div64 + value: 12 + - name: Div128 + value: 13 + - name: Div256 + value: 14 + - name: Div512 + value: 15 +enum/HSEEXT: + bit_size: 1 + variants: + - name: Analog + description: HSE in analog mode (default after reset) + value: 0 + - name: Digital + description: HSE in digital mode + value: 1 +enum/HSIDIV: + bit_size: 2 + variants: + - name: Div1 + description: division by 1, hsi(_ker)_ck = 64 MHz (default after reset). + value: 0 + - name: Div2 + description: division by 2, hsi(_ker)_ck = 32 MHz. + value: 1 + - name: Div4 + description: division by 4, hsi(_ker)_ck = 16 MHz. + value: 2 + - name: Div8 + description: division by 8, hsi(_ker)_ck = 8 MHz. + value: 3 +enum/I2C1_I3C1SEL: + bit_size: 2 + variants: + - name: PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI + description: csi_ker selected as peripheral clock + value: 3 +enum/I2CSEL: + bit_size: 2 + variants: + - name: PCLK1 + description: pclk1 selected as kernel clock (default after reset). + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI + description: csi_ker selected as peripheral clock + value: 3 +enum/LPTIM1SEL: + bit_size: 3 + variants: + - name: PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 +enum/LPTIMSEL: + bit_size: 3 + variants: + - name: PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 +enum/LPUARTSEL: + bit_size: 3 + variants: + - name: PCLK4 + description: rcc_pclk_d4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low driving capability + value: 0 + - name: MediumLow + description: Medium low driving capability + value: 1 + - name: MediumHigh + description: Medium high driving capability + value: 2 + - name: High + description: High driving capability + value: 3 +enum/MCO1SEL: + bit_size: 3 + variants: + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 +enum/MCO2SEL: + bit_size: 3 + variants: + - name: SYS + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 +enum/MCOPRE: + bit_size: 4 + variants: + - name: Div1 + description: Divide by 1 + value: 1 + - name: Div2 + description: Divide by 2 + value: 2 + - name: Div3 + description: Divide by 3 + value: 3 + - name: Div4 + description: Divide by 4 + value: 4 + - name: Div5 + description: Divide by 5 + value: 5 + - name: Div6 + description: Divide by 6 + value: 6 + - name: Div7 + description: Divide by 7 + value: 7 + - name: Div8 + description: Divide by 8 + value: 8 + - name: Div9 + description: Divide by 9 + value: 9 + - name: Div10 + description: Divide by 10 + value: 10 + - name: Div11 + description: Divide by 11 + value: 11 + - name: Div12 + description: Divide by 12 + value: 12 + - name: Div13 + description: Divide by 13 + value: 13 + - name: Div14 + description: Divide by 14 + value: 14 + - name: Div15 + description: Divide by 15 + value: 15 +enum/OCTOSPISEL: + bit_size: 2 + variants: + - name: HCLK5 + description: hclk5 selected as kernel peripheral clock (default after reset). + value: 0 + - name: PLL2_S + description: pll2_s_ck selected as kernel peripheral clock. + value: 1 +enum/PERSEL: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as peripheral clock + value: 0 + - name: CSI + description: CSI selected as peripheral clock + value: 1 + - name: HSE + description: HSE selected as peripheral clock + value: 2 +enum/PLLDIV: + bit_size: 7 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div3 + value: 2 + - name: Div4 + value: 3 + - name: Div5 + value: 4 + - name: Div6 + value: 5 + - name: Div7 + value: 6 + - name: Div8 + value: 7 + - name: Div9 + value: 8 + - name: Div10 + value: 9 + - name: Div11 + value: 10 + - name: Div12 + value: 11 + - name: Div13 + value: 12 + - name: Div14 + value: 13 + - name: Div15 + value: 14 + - name: Div16 + value: 15 + - name: Div17 + value: 16 + - name: Div18 + value: 17 + - name: Div19 + value: 18 + - name: Div20 + value: 19 + - name: Div21 + value: 20 + - name: Div22 + value: 21 + - name: Div23 + value: 22 + - name: Div24 + value: 23 + - name: Div25 + value: 24 + - name: Div26 + value: 25 + - name: Div27 + value: 26 + - name: Div28 + value: 27 + - name: Div29 + value: 28 + - name: Div30 + value: 29 + - name: Div31 + value: 30 + - name: Div32 + value: 31 + - name: Div33 + value: 32 + - name: Div34 + value: 33 + - name: Div35 + value: 34 + - name: Div36 + value: 35 + - name: Div37 + value: 36 + - name: Div38 + value: 37 + - name: Div39 + value: 38 + - name: Div40 + value: 39 + - name: Div41 + value: 40 + - name: Div42 + value: 41 + - name: Div43 + value: 42 + - name: Div44 + value: 43 + - name: Div45 + value: 44 + - name: Div46 + value: 45 + - name: Div47 + value: 46 + - name: Div48 + value: 47 + - name: Div49 + value: 48 + - name: Div50 + value: 49 + - name: Div51 + value: 50 + - name: Div52 + value: 51 + - name: Div53 + value: 52 + - name: Div54 + value: 53 + - name: Div55 + value: 54 + - name: Div56 + value: 55 + - name: Div57 + value: 56 + - name: Div58 + value: 57 + - name: Div59 + value: 58 + - name: Div60 + value: 59 + - name: Div61 + value: 60 + - name: Div62 + value: 61 + - name: Div63 + value: 62 + - name: Div64 + value: 63 + - name: Div65 + value: 64 + - name: Div66 + value: 65 + - name: Div67 + value: 66 + - name: Div68 + value: 67 + - name: Div69 + value: 68 + - name: Div70 + value: 69 + - name: Div71 + value: 70 + - name: Div72 + value: 71 + - name: Div73 + value: 72 + - name: Div74 + value: 73 + - name: Div75 + value: 74 + - name: Div76 + value: 75 + - name: Div77 + value: 76 + - name: Div78 + value: 77 + - name: Div79 + value: 78 + - name: Div80 + value: 79 + - name: Div81 + value: 80 + - name: Div82 + value: 81 + - name: Div83 + value: 82 + - name: Div84 + value: 83 + - name: Div85 + value: 84 + - name: Div86 + value: 85 + - name: Div87 + value: 86 + - name: Div88 + value: 87 + - name: Div89 + value: 88 + - name: Div90 + value: 89 + - name: Div91 + value: 90 + - name: Div92 + value: 91 + - name: Div93 + value: 92 + - name: Div94 + value: 93 + - name: Div95 + value: 94 + - name: Div96 + value: 95 + - name: Div97 + value: 96 + - name: Div98 + value: 97 + - name: Div99 + value: 98 + - name: Div100 + value: 99 + - name: Div101 + value: 100 + - name: Div102 + value: 101 + - name: Div103 + value: 102 + - name: Div104 + value: 103 + - name: Div105 + value: 104 + - name: Div106 + value: 105 + - name: Div107 + value: 106 + - name: Div108 + value: 107 + - name: Div109 + value: 108 + - name: Div110 + value: 109 + - name: Div111 + value: 110 + - name: Div112 + value: 111 + - name: Div113 + value: 112 + - name: Div114 + value: 113 + - name: Div115 + value: 114 + - name: Div116 + value: 115 + - name: Div117 + value: 116 + - name: Div118 + value: 117 + - name: Div119 + value: 118 + - name: Div120 + value: 119 + - name: Div121 + value: 120 + - name: Div122 + value: 121 + - name: Div123 + value: 122 + - name: Div124 + value: 123 + - name: Div125 + value: 124 + - name: Div126 + value: 125 + - name: Div127 + value: 126 + - name: Div128 + value: 127 +enum/PLLDIVST: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div3 + value: 2 + - name: Div4 + value: 3 + - name: Div5 + value: 4 + - name: Div6 + value: 5 + - name: Div7 + value: 6 + - name: Div8 + value: 7 +enum/PLLM: + bit_size: 6 + variants: + - name: Div1 + value: 1 + - name: Div2 + value: 2 + - name: Div3 + value: 3 + - name: Div4 + value: 4 + - name: Div5 + value: 5 + - name: Div6 + value: 6 + - name: Div7 + value: 7 + - name: Div8 + value: 8 + - name: Div9 + value: 9 + - name: Div10 + value: 10 + - name: Div11 + value: 11 + - name: Div12 + value: 12 + - name: Div13 + value: 13 + - name: Div14 + value: 14 + - name: Div15 + value: 15 + - name: Div16 + value: 16 + - name: Div17 + value: 17 + - name: Div18 + value: 18 + - name: Div19 + value: 19 + - name: Div20 + value: 20 + - name: Div21 + value: 21 + - name: Div22 + value: 22 + - name: Div23 + value: 23 + - name: Div24 + value: 24 + - name: Div25 + value: 25 + - name: Div26 + value: 26 + - name: Div27 + value: 27 + - name: Div28 + value: 28 + - name: Div29 + value: 29 + - name: Div30 + value: 30 + - name: Div31 + value: 31 + - name: Div32 + value: 32 + - name: Div33 + value: 33 + - name: Div34 + value: 34 + - name: Div35 + value: 35 + - name: Div36 + value: 36 + - name: Div37 + value: 37 + - name: Div38 + value: 38 + - name: Div39 + value: 39 + - name: Div40 + value: 40 + - name: Div41 + value: 41 + - name: Div42 + value: 42 + - name: Div43 + value: 43 + - name: Div44 + value: 44 + - name: Div45 + value: 45 + - name: Div46 + value: 46 + - name: Div47 + value: 47 + - name: Div48 + value: 48 + - name: Div49 + value: 49 + - name: Div50 + value: 50 + - name: Div51 + value: 51 + - name: Div52 + value: 52 + - name: Div53 + value: 53 + - name: Div54 + value: 54 + - name: Div55 + value: 55 + - name: Div56 + value: 56 + - name: Div57 + value: 57 + - name: Div58 + value: 58 + - name: Div59 + value: 59 + - name: Div60 + value: 60 + - name: Div61 + value: 61 + - name: Div62 + value: 62 + - name: Div63 + value: 63 +enum/PLLN: + bit_size: 9 + variants: + - name: Mul8 + value: 7 + - name: Mul9 + value: 8 + - name: Mul10 + value: 9 + - name: Mul11 + value: 10 + - name: Mul12 + value: 11 + - name: Mul13 + value: 12 + - name: Mul14 + value: 13 + - name: Mul15 + value: 14 + - name: Mul16 + value: 15 + - name: Mul17 + value: 16 + - name: Mul18 + value: 17 + - name: Mul19 + value: 18 + - name: Mul20 + value: 19 + - name: Mul21 + value: 20 + - name: Mul22 + value: 21 + - name: Mul23 + value: 22 + - name: Mul24 + value: 23 + - name: Mul25 + value: 24 + - name: Mul26 + value: 25 + - name: Mul27 + value: 26 + - name: Mul28 + value: 27 + - name: Mul29 + value: 28 + - name: Mul30 + value: 29 + - name: Mul31 + value: 30 + - name: Mul32 + value: 31 + - name: Mul33 + value: 32 + - name: Mul34 + value: 33 + - name: Mul35 + value: 34 + - name: Mul36 + value: 35 + - name: Mul37 + value: 36 + - name: Mul38 + value: 37 + - name: Mul39 + value: 38 + - name: Mul40 + value: 39 + - name: Mul41 + value: 40 + - name: Mul42 + value: 41 + - name: Mul43 + value: 42 + - name: Mul44 + value: 43 + - name: Mul45 + value: 44 + - name: Mul46 + value: 45 + - name: Mul47 + value: 46 + - name: Mul48 + value: 47 + - name: Mul49 + value: 48 + - name: Mul50 + value: 49 + - name: Mul51 + value: 50 + - name: Mul52 + value: 51 + - name: Mul53 + value: 52 + - name: Mul54 + value: 53 + - name: Mul55 + value: 54 + - name: Mul56 + value: 55 + - name: Mul57 + value: 56 + - name: Mul58 + value: 57 + - name: Mul59 + value: 58 + - name: Mul60 + value: 59 + - name: Mul61 + value: 60 + - name: Mul62 + value: 61 + - name: Mul63 + value: 62 + - name: Mul64 + value: 63 + - name: Mul65 + value: 64 + - name: Mul66 + value: 65 + - name: Mul67 + value: 66 + - name: Mul68 + value: 67 + - name: Mul69 + value: 68 + - name: Mul70 + value: 69 + - name: Mul71 + value: 70 + - name: Mul72 + value: 71 + - name: Mul73 + value: 72 + - name: Mul74 + value: 73 + - name: Mul75 + value: 74 + - name: Mul76 + value: 75 + - name: Mul77 + value: 76 + - name: Mul78 + value: 77 + - name: Mul79 + value: 78 + - name: Mul80 + value: 79 + - name: Mul81 + value: 80 + - name: Mul82 + value: 81 + - name: Mul83 + value: 82 + - name: Mul84 + value: 83 + - name: Mul85 + value: 84 + - name: Mul86 + value: 85 + - name: Mul87 + value: 86 + - name: Mul88 + value: 87 + - name: Mul89 + value: 88 + - name: Mul90 + value: 89 + - name: Mul91 + value: 90 + - name: Mul92 + value: 91 + - name: Mul93 + value: 92 + - name: Mul94 + value: 93 + - name: Mul95 + value: 94 + - name: Mul96 + value: 95 + - name: Mul97 + value: 96 + - name: Mul98 + value: 97 + - name: Mul99 + value: 98 + - name: Mul100 + value: 99 + - name: Mul101 + value: 100 + - name: Mul102 + value: 101 + - name: Mul103 + value: 102 + - name: Mul104 + value: 103 + - name: Mul105 + value: 104 + - name: Mul106 + value: 105 + - name: Mul107 + value: 106 + - name: Mul108 + value: 107 + - name: Mul109 + value: 108 + - name: Mul110 + value: 109 + - name: Mul111 + value: 110 + - name: Mul112 + value: 111 + - name: Mul113 + value: 112 + - name: Mul114 + value: 113 + - name: Mul115 + value: 114 + - name: Mul116 + value: 115 + - name: Mul117 + value: 116 + - name: Mul118 + value: 117 + - name: Mul119 + value: 118 + - name: Mul120 + value: 119 + - name: Mul121 + value: 120 + - name: Mul122 + value: 121 + - name: Mul123 + value: 122 + - name: Mul124 + value: 123 + - name: Mul125 + value: 124 + - name: Mul126 + value: 125 + - name: Mul127 + value: 126 + - name: Mul128 + value: 127 + - name: Mul129 + value: 128 + - name: Mul130 + value: 129 + - name: Mul131 + value: 130 + - name: Mul132 + value: 131 + - name: Mul133 + value: 132 + - name: Mul134 + value: 133 + - name: Mul135 + value: 134 + - name: Mul136 + value: 135 + - name: Mul137 + value: 136 + - name: Mul138 + value: 137 + - name: Mul139 + value: 138 + - name: Mul140 + value: 139 + - name: Mul141 + value: 140 + - name: Mul142 + value: 141 + - name: Mul143 + value: 142 + - name: Mul144 + value: 143 + - name: Mul145 + value: 144 + - name: Mul146 + value: 145 + - name: Mul147 + value: 146 + - name: Mul148 + value: 147 + - name: Mul149 + value: 148 + - name: Mul150 + value: 149 + - name: Mul151 + value: 150 + - name: Mul152 + value: 151 + - name: Mul153 + value: 152 + - name: Mul154 + value: 153 + - name: Mul155 + value: 154 + - name: Mul156 + value: 155 + - name: Mul157 + value: 156 + - name: Mul158 + value: 157 + - name: Mul159 + value: 158 + - name: Mul160 + value: 159 + - name: Mul161 + value: 160 + - name: Mul162 + value: 161 + - name: Mul163 + value: 162 + - name: Mul164 + value: 163 + - name: Mul165 + value: 164 + - name: Mul166 + value: 165 + - name: Mul167 + value: 166 + - name: Mul168 + value: 167 + - name: Mul169 + value: 168 + - name: Mul170 + value: 169 + - name: Mul171 + value: 170 + - name: Mul172 + value: 171 + - name: Mul173 + value: 172 + - name: Mul174 + value: 173 + - name: Mul175 + value: 174 + - name: Mul176 + value: 175 + - name: Mul177 + value: 176 + - name: Mul178 + value: 177 + - name: Mul179 + value: 178 + - name: Mul180 + value: 179 + - name: Mul181 + value: 180 + - name: Mul182 + value: 181 + - name: Mul183 + value: 182 + - name: Mul184 + value: 183 + - name: Mul185 + value: 184 + - name: Mul186 + value: 185 + - name: Mul187 + value: 186 + - name: Mul188 + value: 187 + - name: Mul189 + value: 188 + - name: Mul190 + value: 189 + - name: Mul191 + value: 190 + - name: Mul192 + value: 191 + - name: Mul193 + value: 192 + - name: Mul194 + value: 193 + - name: Mul195 + value: 194 + - name: Mul196 + value: 195 + - name: Mul197 + value: 196 + - name: Mul198 + value: 197 + - name: Mul199 + value: 198 + - name: Mul200 + value: 199 + - name: Mul201 + value: 200 + - name: Mul202 + value: 201 + - name: Mul203 + value: 202 + - name: Mul204 + value: 203 + - name: Mul205 + value: 204 + - name: Mul206 + value: 205 + - name: Mul207 + value: 206 + - name: Mul208 + value: 207 + - name: Mul209 + value: 208 + - name: Mul210 + value: 209 + - name: Mul211 + value: 210 + - name: Mul212 + value: 211 + - name: Mul213 + value: 212 + - name: Mul214 + value: 213 + - name: Mul215 + value: 214 + - name: Mul216 + value: 215 + - name: Mul217 + value: 216 + - name: Mul218 + value: 217 + - name: Mul219 + value: 218 + - name: Mul220 + value: 219 + - name: Mul221 + value: 220 + - name: Mul222 + value: 221 + - name: Mul223 + value: 222 + - name: Mul224 + value: 223 + - name: Mul225 + value: 224 + - name: Mul226 + value: 225 + - name: Mul227 + value: 226 + - name: Mul228 + value: 227 + - name: Mul229 + value: 228 + - name: Mul230 + value: 229 + - name: Mul231 + value: 230 + - name: Mul232 + value: 231 + - name: Mul233 + value: 232 + - name: Mul234 + value: 233 + - name: Mul235 + value: 234 + - name: Mul236 + value: 235 + - name: Mul237 + value: 236 + - name: Mul238 + value: 237 + - name: Mul239 + value: 238 + - name: Mul240 + value: 239 + - name: Mul241 + value: 240 + - name: Mul242 + value: 241 + - name: Mul243 + value: 242 + - name: Mul244 + value: 243 + - name: Mul245 + value: 244 + - name: Mul246 + value: 245 + - name: Mul247 + value: 246 + - name: Mul248 + value: 247 + - name: Mul249 + value: 248 + - name: Mul250 + value: 249 + - name: Mul251 + value: 250 + - name: Mul252 + value: 251 + - name: Mul253 + value: 252 + - name: Mul254 + value: 253 + - name: Mul255 + value: 254 + - name: Mul256 + value: 255 + - name: Mul257 + value: 256 + - name: Mul258 + value: 257 + - name: Mul259 + value: 258 + - name: Mul260 + value: 259 + - name: Mul261 + value: 260 + - name: Mul262 + value: 261 + - name: Mul263 + value: 262 + - name: Mul264 + value: 263 + - name: Mul265 + value: 264 + - name: Mul266 + value: 265 + - name: Mul267 + value: 266 + - name: Mul268 + value: 267 + - name: Mul269 + value: 268 + - name: Mul270 + value: 269 + - name: Mul271 + value: 270 + - name: Mul272 + value: 271 + - name: Mul273 + value: 272 + - name: Mul274 + value: 273 + - name: Mul275 + value: 274 + - name: Mul276 + value: 275 + - name: Mul277 + value: 276 + - name: Mul278 + value: 277 + - name: Mul279 + value: 278 + - name: Mul280 + value: 279 + - name: Mul281 + value: 280 + - name: Mul282 + value: 281 + - name: Mul283 + value: 282 + - name: Mul284 + value: 283 + - name: Mul285 + value: 284 + - name: Mul286 + value: 285 + - name: Mul287 + value: 286 + - name: Mul288 + value: 287 + - name: Mul289 + value: 288 + - name: Mul290 + value: 289 + - name: Mul291 + value: 290 + - name: Mul292 + value: 291 + - name: Mul293 + value: 292 + - name: Mul294 + value: 293 + - name: Mul295 + value: 294 + - name: Mul296 + value: 295 + - name: Mul297 + value: 296 + - name: Mul298 + value: 297 + - name: Mul299 + value: 298 + - name: Mul300 + value: 299 + - name: Mul301 + value: 300 + - name: Mul302 + value: 301 + - name: Mul303 + value: 302 + - name: Mul304 + value: 303 + - name: Mul305 + value: 304 + - name: Mul306 + value: 305 + - name: Mul307 + value: 306 + - name: Mul308 + value: 307 + - name: Mul309 + value: 308 + - name: Mul310 + value: 309 + - name: Mul311 + value: 310 + - name: Mul312 + value: 311 + - name: Mul313 + value: 312 + - name: Mul314 + value: 313 + - name: Mul315 + value: 314 + - name: Mul316 + value: 315 + - name: Mul317 + value: 316 + - name: Mul318 + value: 317 + - name: Mul319 + value: 318 + - name: Mul320 + value: 319 + - name: Mul321 + value: 320 + - name: Mul322 + value: 321 + - name: Mul323 + value: 322 + - name: Mul324 + value: 323 + - name: Mul325 + value: 324 + - name: Mul326 + value: 325 + - name: Mul327 + value: 326 + - name: Mul328 + value: 327 + - name: Mul329 + value: 328 + - name: Mul330 + value: 329 + - name: Mul331 + value: 330 + - name: Mul332 + value: 331 + - name: Mul333 + value: 332 + - name: Mul334 + value: 333 + - name: Mul335 + value: 334 + - name: Mul336 + value: 335 + - name: Mul337 + value: 336 + - name: Mul338 + value: 337 + - name: Mul339 + value: 338 + - name: Mul340 + value: 339 + - name: Mul341 + value: 340 + - name: Mul342 + value: 341 + - name: Mul343 + value: 342 + - name: Mul344 + value: 343 + - name: Mul345 + value: 344 + - name: Mul346 + value: 345 + - name: Mul347 + value: 346 + - name: Mul348 + value: 347 + - name: Mul349 + value: 348 + - name: Mul350 + value: 349 + - name: Mul351 + value: 350 + - name: Mul352 + value: 351 + - name: Mul353 + value: 352 + - name: Mul354 + value: 353 + - name: Mul355 + value: 354 + - name: Mul356 + value: 355 + - name: Mul357 + value: 356 + - name: Mul358 + value: 357 + - name: Mul359 + value: 358 + - name: Mul360 + value: 359 + - name: Mul361 + value: 360 + - name: Mul362 + value: 361 + - name: Mul363 + value: 362 + - name: Mul364 + value: 363 + - name: Mul365 + value: 364 + - name: Mul366 + value: 365 + - name: Mul367 + value: 366 + - name: Mul368 + value: 367 + - name: Mul369 + value: 368 + - name: Mul370 + value: 369 + - name: Mul371 + value: 370 + - name: Mul372 + value: 371 + - name: Mul373 + value: 372 + - name: Mul374 + value: 373 + - name: Mul375 + value: 374 + - name: Mul376 + value: 375 + - name: Mul377 + value: 376 + - name: Mul378 + value: 377 + - name: Mul379 + value: 378 + - name: Mul380 + value: 379 + - name: Mul381 + value: 380 + - name: Mul382 + value: 381 + - name: Mul383 + value: 382 + - name: Mul384 + value: 383 + - name: Mul385 + value: 384 + - name: Mul386 + value: 385 + - name: Mul387 + value: 386 + - name: Mul388 + value: 387 + - name: Mul389 + value: 388 + - name: Mul390 + value: 389 + - name: Mul391 + value: 390 + - name: Mul392 + value: 391 + - name: Mul393 + value: 392 + - name: Mul394 + value: 393 + - name: Mul395 + value: 394 + - name: Mul396 + value: 395 + - name: Mul397 + value: 396 + - name: Mul398 + value: 397 + - name: Mul399 + value: 398 + - name: Mul400 + value: 399 + - name: Mul401 + value: 400 + - name: Mul402 + value: 401 + - name: Mul403 + value: 402 + - name: Mul404 + value: 403 + - name: Mul405 + value: 404 + - name: Mul406 + value: 405 + - name: Mul407 + value: 406 + - name: Mul408 + value: 407 + - name: Mul409 + value: 408 + - name: Mul410 + value: 409 + - name: Mul411 + value: 410 + - name: Mul412 + value: 411 + - name: Mul413 + value: 412 + - name: Mul414 + value: 413 + - name: Mul415 + value: 414 + - name: Mul416 + value: 415 + - name: Mul417 + value: 416 + - name: Mul418 + value: 417 + - name: Mul419 + value: 418 + - name: Mul420 + value: 419 +enum/PLLRGE: + bit_size: 2 + variants: + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 +enum/PLLSRC: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as PLL clock + value: 0 + - name: CSI + description: CSI selected as PLL clock + value: 1 + - name: HSE + description: HSE selected as PLL clock + value: 2 + - name: DISABLE + description: No clock sent to DIVMx dividers and PLLs + value: 3 +enum/PLLVCOSEL: + bit_size: 1 + variants: + - name: WideVCO + description: VCOH selected (default after reset). + value: 0 + - name: MediumVCO + description: VCOL selected. + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: rcc_hclk not divided + value: 0 + - name: Div2 + description: rcc_hclk divided by 2 + value: 4 + - name: Div4 + description: rcc_hclk divided by 4 + value: 5 + - name: Div8 + description: rcc_hclk divided by 8 + value: 6 + - name: Div16 + description: rcc_hclk divided by 16 + value: 7 +enum/PSSISEL: + bit_size: 1 + variants: + - name: PLL3_R + description: pll3_r_ck selected as kernel peripheral clock (default after reset). + value: 0 + - name: PER + description: per_ck selected as kernel peripheral clock. + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: DISABLE + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SAI1SEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: I2S_CKIN selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 +enum/SAI2SEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: I2S_CKIN selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 + - name: SPDIFRX_SYMB + description: spdifrx_symb_ck selected as SAI2 kernel clock. + value: 5 +enum/SDMMCSEL: + bit_size: 1 + variants: + - name: PLL2_S + description: pll2_s_ck selected as kernel peripheral clock (default after reset). + value: 0 + - name: PLL2_T + description: pll2_t_ck selected as kernel peripheral clock. + value: 1 +enum/SPDIFRXSEL: + bit_size: 2 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: HSI + description: hsi_ker selected as peripheral clock + value: 3 +enum/SPI123SEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q_ck selected as SPI/I2S1 and 7 kernel clock (default after reset). + value: 0 + - name: PLL2_P + description: pll2_p_ck selected as SPI/I2S1 and 7 kernel clock. + value: 1 + - name: PLL3_P + description: pll3_p_ck selected as SPI/I2S1 and 7 kernel clock. + value: 2 + - name: I2S_CKIN + description: I2S_CKIN selected as SPI/I2S1 and 7 kernel clock. + value: 3 + - name: PER + description: per_ck selected as SPI/I2S1,and 7 kernel clock. + value: 4 +enum/SPI45SEL: + bit_size: 3 + variants: + - name: HCLK2 + description: APB2 clock selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/SPI6SEL: + bit_size: 3 + variants: + - name: PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/STOPKERWUCK: + bit_size: 1 + variants: + - name: HSI + description: HSI selected as wake up clock from system Stop (default after reset). + value: 0 + - name: CSI + description: CSI selected as wake up clock from system Stop. + value: 1 +enum/STOPWUCK: + bit_size: 1 + variants: + - name: HSI + description: HSI selected as wake up clock from system Stop + value: 0 + - name: CSI + description: CSI selected as wake up clock from system Stop + value: 1 +enum/SW: + bit_size: 3 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1_P + description: PLL1 selected as system clock + value: 3 +enum/TIMPRE: + bit_size: 1 + variants: + - name: DefaultX2 + description: Timer kernel clock equal to 2x pclk by default + value: 0 + - name: DefaultX4 + description: Timer kernel clock equal to 4x pclk by default + value: 1 +enum/USART1SEL: + bit_size: 3 + variants: + - name: PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USART234578SEL: + bit_size: 3 + variants: + - name: PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USBPDCTRL: + bit_size: 1 + variants: + - name: RemainPowered + description: In SUSPEND, PHY state machine, bias and USBPHYC PLL remain powered (default after reset). + value: 0 + - name: PowerDown + description: In SUSPEND, PHY state machine, bias and USBPHYC PLL are powered down. + value: 1 +enum/USBPHYCSEL: + bit_size: 2 + variants: + - name: HSE + description: hse_ker_ck (default after reset). + value: 0 + - name: HSE_DIV_2 + description: hse_ker_ck / 2. + value: 1 + - name: PLL3_Q + description: pll3_q_ck. + value: 2 +enum/USBREFCKSEL: + bit_size: 4 + variants: + - name: Mhz16 + description: The kernel clock frequency provided to the USBPHYC is 16 MHz. + value: 3 + - name: Mhz19_2 + description: The kernel clock frequency provided to the USBPHYC is 19.2 MHz. + value: 8 + - name: Mhz20 + description: The kernel clock frequency provided to the USBPHYC is 20MHz. + value: 9 + - name: Mhz24 + description: The kernel clock frequency provided to the USBPHYC is 24 MHz (default after reset). + value: 10 + - name: Mhz32 + description: The kernel clock frequency provided to the USBPHYC is 32 MHz. + value: 11 + - name: Mhz26 + description: The kernel clock frequency provided to the USBPHYC is 26 MHz. + value: 14 +enum/USB_OTG_FSSEL: + bit_size: 2 + variants: + - name: HSI48 + description: hsi48_ker_ck (default after reset). + value: 0 + - name: PLL3_Q + description: pll3_q_ck. + value: 1 + - name: HSE + description: hse_ker_ck. + value: 2 + - name: CLK48MOHCI + description: clk48mohci. + value: 3 +enum/XSPISWP: + bit_size: 3 + variants: + - name: B_0x0 + description: The switch is in neutral mode and output clock is gated (default after reset). + value: 0 + - name: B_0x1 + description: The switch is selecting hclk5. + value: 1 + - name: B_0x2 + description: The switch is selecting pll2_s_ck. + value: 2 + - name: B_0x3 + description: The switch is selecting pll2_t_ck. + value: 3 + - name: B_0x4 + description: The switch is in recovery position (hclk5/4). + value: 4 diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index b761f37..bbf9b48 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -99,7 +99,7 @@ fieldset/AHBENR: description: CRC clock enable bit_offset: 12 bit_size: 1 - - name: TOUCHEN + - name: TSCEN description: Touch Sensing clock enable bit_offset: 16 bit_size: 1 @@ -126,7 +126,7 @@ fieldset/AHBRSTR: description: Test integration module reset bit_offset: 12 bit_size: 1 - - name: TOUCHRST + - name: TSCRST description: Touch Sensing reset bit_offset: 16 bit_size: 1 @@ -157,7 +157,7 @@ fieldset/AHBSMENR: description: CRC clock enable during sleep mode bit_offset: 12 bit_size: 1 - - name: TOUCHSMEN + - name: TSCSMEN description: Touch Sensing clock enable during sleep mode bit_offset: 16 bit_size: 1 diff --git a/data/registers/rcc_l0_v2.yaml b/data/registers/rcc_l0_v2.yaml index 333cde2..fde5a47 100644 --- a/data/registers/rcc_l0_v2.yaml +++ b/data/registers/rcc_l0_v2.yaml @@ -103,7 +103,7 @@ fieldset/AHBENR: description: CRC clock enable bit_offset: 12 bit_size: 1 - - name: TOUCHEN + - name: TSCEN description: Touch Sensing clock enable bit_offset: 16 bit_size: 1 @@ -130,7 +130,7 @@ fieldset/AHBRSTR: description: Test integration module reset bit_offset: 12 bit_size: 1 - - name: TOUCHRST + - name: TSCRST description: Touch Sensing reset bit_offset: 16 bit_size: 1 @@ -161,7 +161,7 @@ fieldset/AHBSMENR: description: CRC clock enable during sleep mode bit_offset: 12 bit_size: 1 - - name: TOUCHSMEN + - name: TSCSMEN description: Touch Sensing clock enable during sleep mode bit_offset: 16 bit_size: 1 diff --git a/data/registers/rcc_l4plus.yaml b/data/registers/rcc_l4plus.yaml index 17e9f27..9db03de 100644 --- a/data/registers/rcc_l4plus.yaml +++ b/data/registers/rcc_l4plus.yaml @@ -1713,7 +1713,7 @@ enum/DFSDMSEL: enum/DSISEL: bit_size: 1 variants: - - name: DSIPHY + - name: DSI_PHY description: DSI-PHY is selected as DSI byte lane clock source (usual case) value: 0 - name: PLLSAI2_Q diff --git a/data/registers/rcc_u0.yaml b/data/registers/rcc_u0.yaml index c1dbd8e..a03e71b 100644 --- a/data/registers/rcc_u0.yaml +++ b/data/registers/rcc_u0.yaml @@ -1047,25 +1047,6 @@ fieldset/DBGCFGR: description: Debug support reset Set and cleared by software. bit_offset: 1 bit_size: 1 -fieldset/ICSCR: - description: Internal clock sources calibration register. - fields: - - name: MSICAL - description: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. - bit_offset: 0 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. - bit_offset: 8 - bit_size: 8 - - name: HSICAL - description: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. - bit_offset: 16 - bit_size: 8 - - name: HSITRIM - description: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%. - bit_offset: 24 - bit_size: 7 fieldset/GPIOENR: description: I/O port clock enable register. fields: @@ -1147,6 +1128,25 @@ fieldset/GPIOSMENR: description: I/O port F clock enable during Sleep mode Set and cleared by software. bit_offset: 5 bit_size: 1 +fieldset/ICSCR: + description: Internal clock sources calibration register. + fields: + - name: MSICAL + description: MSI clock calibration These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value. + bit_offset: 0 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI. + bit_offset: 8 + bit_size: 8 + - name: HSICAL + description: HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. + bit_offset: 16 + bit_size: 8 + - name: HSITRIM + description: HSI clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI. The default value is 64 when added to the HSICAL value, trim the HSI to 161MHz 1 11%. + bit_offset: 24 + bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register. fields: diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index d345691..9a226d7 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -2499,8 +2499,8 @@ enum/DSISEL: - name: PLL3_P description: PLL3 “P” (pll3_p_ck) selected value: 0 - - name: DCLK - description: DSI PHY PLL output selected + - name: DSI_PHY + description: DSI PHY PLL output selected (formerly called DCLK, renamed to DSI_PHY to match other chip families) value: 1 enum/FDCANSEL: bit_size: 2 diff --git a/data/registers/spi_v3.yaml b/data/registers/spi_v3.yaml index 4afed99..6eea179 100644 --- a/data/registers/spi_v3.yaml +++ b/data/registers/spi_v3.yaml @@ -31,34 +31,34 @@ block/SPI: byte_offset: 24 access: Write fieldset: IFCR + - name: TXDR16 + description: Transmit Data Register - half-word sized + byte_offset: 32 + access: Write + bit_size: 16 - name: TXDR32 description: Transmit Data Register byte_offset: 32 access: Write - - name: TXDR16 - description: Transmit Data Register - half-word sized - byte_offset: 32 - bit_size: 16 - access: Write - name: TXDR8 description: Transmit Data Register - byte sized byte_offset: 32 - bit_size: 8 access: Write + bit_size: 8 + - name: RXDR16 + description: Receive Data Register - half-word sized + byte_offset: 48 + access: Read + bit_size: 16 - name: RXDR32 description: Receive Data Register byte_offset: 48 access: Read - - name: RXDR16 - description: Receive Data Register - half-word sized - byte_offset: 48 - bit_size: 16 - access: Read - name: RXDR8 description: Receive Data Register - byte sized byte_offset: 48 - bit_size: 8 access: Read + bit_size: 8 - name: CRCPOLY description: Polynomial Register byte_offset: 64 diff --git a/data/registers/spi_v4.yaml b/data/registers/spi_v4.yaml index 78a74eb..26abc59 100644 --- a/data/registers/spi_v4.yaml +++ b/data/registers/spi_v4.yaml @@ -31,34 +31,34 @@ block/SPI: byte_offset: 24 access: Write fieldset: IFCR + - name: TXDR16 + description: Transmit Data Register - half-word sized + byte_offset: 32 + access: Write + bit_size: 16 - name: TXDR32 description: Transmit Data Register byte_offset: 32 access: Write - - name: TXDR16 - description: Transmit Data Register - half-word sized - byte_offset: 32 - bit_size: 16 - access: Write - name: TXDR8 description: Transmit Data Register - byte sized byte_offset: 32 - bit_size: 8 access: Write + bit_size: 8 + - name: RXDR16 + description: Receive Data Register - half-word sized + byte_offset: 48 + access: Read + bit_size: 16 - name: RXDR32 description: Receive Data Register byte_offset: 48 access: Read - - name: RXDR16 - description: Receive Data Register - half-word sized - byte_offset: 48 - bit_size: 16 - access: Read - name: RXDR8 description: Receive Data Register - byte sized byte_offset: 48 - bit_size: 8 access: Read + bit_size: 8 - name: CRCPOLY description: Polynomial Register byte_offset: 64 diff --git a/data/registers/spi_v5.yaml b/data/registers/spi_v5.yaml index 8155eca..acb0592 100644 --- a/data/registers/spi_v5.yaml +++ b/data/registers/spi_v5.yaml @@ -34,34 +34,34 @@ block/SPI: - name: AUTOCR byte_offset: 28 fieldset: AUTOCR + - name: TXDR16 + description: Transmit Data Register - half-word sized + byte_offset: 32 + access: Write + bit_size: 16 - name: TXDR32 description: Transmit Data Register byte_offset: 32 access: Write - - name: TXDR16 - description: Transmit Data Register - half-word sized - byte_offset: 32 - bit_size: 16 - access: Write - name: TXDR8 description: Transmit Data Register - byte sized byte_offset: 32 - bit_size: 8 access: Write + bit_size: 8 + - name: RXDR16 + description: Receive Data Register - half-word sized + byte_offset: 48 + access: Read + bit_size: 16 - name: RXDR32 description: Receive Data Register byte_offset: 48 access: Read - - name: RXDR16 - description: Receive Data Register - half-word sized - byte_offset: 48 - bit_size: 16 - access: Read - name: RXDR8 description: Receive Data Register - byte sized byte_offset: 48 - bit_size: 8 access: Read + bit_size: 8 - name: CRCPOLY description: Polynomial Register byte_offset: 64 diff --git a/data/registers/syscfg_h5.yaml b/data/registers/syscfg_h5.yaml index 3094aeb..6e354dc 100644 --- a/data/registers/syscfg_h5.yaml +++ b/data/registers/syscfg_h5.yaml @@ -365,13 +365,13 @@ enum/EPOCH_SEL: enum/ETH_SEL_PHY: bit_size: 3 variants: - - name: B_0x0 + - name: MII_GMII description: GMII or MII value: 0 - - name: B_0x1 + - name: ReservedRGMII description: reserved (RGMII) value: 1 - - name: B_0x4 + - name: RMII description: RMII value: 4 enum/HDPL: diff --git a/data/registers/syscfg_h7.yaml b/data/registers/syscfg_h7.yaml index b1d79f6..721d2bc 100644 --- a/data/registers/syscfg_h7.yaml +++ b/data/registers/syscfg_h7.yaml @@ -139,7 +139,7 @@ fieldset/CCCSR: description: Code selection bit_offset: 1 bit_size: 1 - - name: READY + - name: RDY description: Compensation cell ready flag bit_offset: 8 bit_size: 1 @@ -218,10 +218,11 @@ fieldset/PMCR: description: Analog switch supply voltage selection bit_offset: 9 bit_size: 1 - - name: EPIS - description: Ethernet PHY Interface Selection + - name: ETH_SEL_PHY + description: Ethernet PHY interface selection. bit_offset: 21 bit_size: 3 + enum: ETH_SEL_PHY - name: PA0SO description: PA0 Switch Open bit_offset: 24 @@ -413,6 +414,15 @@ fieldset/UR9: description: Protected area start address for bank 2 bit_offset: 16 bit_size: 12 +enum/ETH_SEL_PHY: + bit_size: 3 + variants: + - name: MII_GMII + description: GMII or MII + value: 0 + - name: RMII + description: RMII + value: 4 enum/ITCM_AXI_RAM_SIZE: bit_size: 2 variants: diff --git a/data/registers/syscfg_h7od.yaml b/data/registers/syscfg_h7od.yaml index 24f8b08..b90e2e1 100644 --- a/data/registers/syscfg_h7od.yaml +++ b/data/registers/syscfg_h7od.yaml @@ -138,7 +138,7 @@ fieldset/CCCSR: description: Code selection bit_offset: 1 bit_size: 1 - - name: READY + - name: RDY description: Compensation cell ready flag bit_offset: 8 bit_size: 1 @@ -217,10 +217,11 @@ fieldset/PMCR: description: Analog switch supply voltage selection bit_offset: 9 bit_size: 1 - - name: EPIS - description: Ethernet PHY Interface Selection + - name: ETH_SEL_PHY + description: Ethernet PHY interface selection. bit_offset: 21 bit_size: 3 + enum: ETH_SEL_PHY - name: PA0SO description: PA0 Switch Open bit_offset: 24 @@ -407,3 +408,12 @@ fieldset/UR9: description: Protected area start address for bank 2 bit_offset: 16 bit_size: 12 +enum/ETH_SEL_PHY: + bit_size: 3 + variants: + - name: MII_GMII + description: GMII or MII + value: 0 + - name: RMII + description: RMII + value: 4 diff --git a/data/registers/syscfg_h7rs.yaml b/data/registers/syscfg_h7rs.yaml new file mode 100644 index 0000000..6642ab2 --- /dev/null +++ b/data/registers/syscfg_h7rs.yaml @@ -0,0 +1,364 @@ +block/SYSCFG: + description: System configuration, boot and security. + items: + - name: BOOTSR + description: SBS boot status register. + byte_offset: 0 + fieldset: BOOTSR + - name: HDPLCR + description: SBS hide protection control register. + byte_offset: 16 + fieldset: HDPLCR + - name: HDPLSR + description: SBS hide protection status register. + byte_offset: 20 + fieldset: HDPLSR + - name: DBGCR + description: SBS debug control register. + byte_offset: 32 + fieldset: DBGCR + - name: DBGLOCKR + description: SBS debug lock register. + byte_offset: 36 + fieldset: DBGLOCKR + - name: RSSCMDR + description: SBS RSS command register. + byte_offset: 52 + fieldset: RSSCMDR + - name: PMCR + description: SBS product mode and configuration register. + byte_offset: 256 + fieldset: PMCR + - name: FPUIMR + description: SBS FPU interrupt mask register. + byte_offset: 260 + fieldset: FPUIMR + - name: MESR + description: SBS memory erase status register. + byte_offset: 264 + fieldset: MESR + - name: CCCSR + description: SBS I/O compensation cell control and status register. + byte_offset: 272 + fieldset: CCCSR + - name: CCVALR + description: SBS compensation cell for I/Os value register. + byte_offset: 276 + fieldset: CCVALR + - name: CCSWVALR + description: SBS compensation cell for I/Os software value register. + byte_offset: 280 + fieldset: CCSWVALR + - name: BKLOCKR + description: SBS break lockup register. + byte_offset: 288 + fieldset: BKLOCKR + - name: EXTICR + description: external interrupt configuration register + array: + len: 4 + stride: 4 + byte_offset: 304 + fieldset: EXTICR +fieldset/BKLOCKR: + description: SBS break lockup register. + fields: + - name: PVD_BL + description: PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset. + bit_offset: 2 + bit_size: 1 + - name: FLASHECC_BL + description: Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + bit_offset: 3 + bit_size: 1 + - name: CM7LCKUP_BL + description: Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + bit_offset: 6 + bit_size: 1 + - name: BKRAMECC_BL + description: Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + bit_offset: 7 + bit_size: 1 + - name: DTCMECC_BL + description: 'DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC.' + bit_offset: 13 + bit_size: 1 + - name: ITCMECC_BL + description: ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + bit_offset: 14 + bit_size: 1 + - name: ARAM3ECC_BL + description: AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset. + bit_offset: 21 + bit_size: 1 + - name: ARAM1ECC_BL + description: AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. + bit_offset: 23 + bit_size: 1 +fieldset/BOOTSR: + description: SBS boot status register. + fields: + - name: INITVTOR + description: initial vector for Cortex-M7 This register includes the physical boot address used by the Cortex-M7 after reset. + bit_offset: 0 + bit_size: 32 +fieldset/CCCSR: + description: SBS I/O compensation cell control and status register. + fields: + - name: COMP_EN + description: Compensation cell enable Set this bit to enable the compensation cell. + bit_offset: 0 + bit_size: 1 + - name: COMP_CODESEL + description: Compensation cell code selection This bit selects the code to be applied for the I/O compensation cell. + bit_offset: 1 + bit_size: 1 + - name: OCTO1_COMP_EN + description: XSPIM_P1 compensation cell enable Set this bit to enable the XSPIM_P1 compensation cell. + bit_offset: 2 + bit_size: 1 + - name: OCTO1_COMP_CODESEL + description: XSPIM_P1 compensation cell code selection This bit selects the code to be applied for the XSPIM_P1 I/O compensation cell. + bit_offset: 3 + bit_size: 1 + - name: OCTO2_COMP_EN + description: XSPIM_P2 compensation cell enable Set this bit to enable the XSPIM_P2 compensation cell. + bit_offset: 4 + bit_size: 1 + - name: OCTO2_COMP_CODESEL + description: XSPIM_P2 compensation cell code selection This bit selects the code to be applied for the XSPIM_P2 I/O compensation cell. + bit_offset: 5 + bit_size: 1 + - name: COMP_RDY + description: Compensation cell ready This bit provides the status of the compensation cell. + bit_offset: 8 + bit_size: 1 + - name: OCTO1_COMP_RDY + description: XSPIM_P1 compensation cell ready This bit provides the status of the XSPIM_P1 compensation cell. + bit_offset: 9 + bit_size: 1 + - name: OCTO2_COMP_RDY + description: XSPIM_P2 compensation cell ready This bit provides the status of the XSPIM_P2 compensation cell. + bit_offset: 10 + bit_size: 1 + - name: IOHSLV + description: I/O high speed at low voltage When this bit is set, the speed of the I/Os is optimized when the device voltage is low. This bit is active only if VDDIO_HSLV user option bit is set in FLASH. It must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. + bit_offset: 16 + bit_size: 1 + - name: OCTO1_IOHSLV + description: XSPIM_P1 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P1 I/Os is optimized when the device voltage is low. This bit is active only if OCTO1_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. + bit_offset: 17 + bit_size: 1 + - name: OCTO2_IOHSLV + description: XSPIM_P2 I/O high speed at low voltage When this bit is set, the speed of the XSPIM_P2 I/Os is optimized when the device voltage is low. This bit is active only if OCTO2_HSLV user option bit is set in FLASH. This bit must be used only if the device supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V may be destructive. + bit_offset: 18 + bit_size: 1 +fieldset/CCSWVALR: + description: SBS compensation cell for I/Os software value register. + fields: + - name: SW_NSRC + description: Software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register. + bit_offset: 0 + bit_size: 4 + - name: SW_PSRC + description: Software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 1 in SBS_CCCSR register. + bit_offset: 4 + bit_size: 4 + - name: OCTO1_SW_NSRC + description: XSPIM_P1 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew -ate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register. + bit_offset: 8 + bit_size: 4 + - name: OCTO1_SW_PSRC + description: XSPIM_P1 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 1 in SBS_CCCSR register. + bit_offset: 12 + bit_size: 4 + - name: OCTO2_SW_NSRC + description: XSPIM_P2 software NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register. + bit_offset: 16 + bit_size: 4 + - name: OCTO2_SW_PSRC + description: XSPIM_P2 software PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 1 in SBS_CCCSR register. + bit_offset: 20 + bit_size: 4 +fieldset/CCVALR: + description: SBS compensation cell for I/Os value register. + fields: + - name: NSRC + description: NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the NMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register. + bit_offset: 0 + bit_size: 4 + - name: PSRC + description: PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted to compensate the PMOS transistors slew rate in the functional range if COMP_CODESEL = 0 in SBS_CCCSR register. + bit_offset: 4 + bit_size: 4 + - name: OCTO1_NSRC + description: XSPIM_P1 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the NMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register. + bit_offset: 8 + bit_size: 4 + - name: OCTO1_PSRC + description: XSPIM_P1 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P1 to compensate the PMOS transistors slew rate in the functional range if OCTO1_COMP_CODESEL = 0 in SBS_CCCSR register. + bit_offset: 12 + bit_size: 4 + - name: OCTO2_NSRC + description: XSPIM_P2 NMOS transistors slew-rate compensation This bitfield returns the NMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the NMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register. + bit_offset: 16 + bit_size: 4 + - name: OCTO2_PSRC + description: XSPIM_P2 PMOS transistors slew-rate compensation This bitfield returns the PMOS transistors slew-rate compensation value computed by the cell. It is interpreted by XSPIM_P2 to compensate the PMOS transistors slew rate in the functional range if OCTO2_COMP_CODESEL = 0 in SBS_CCCSR register. + bit_offset: 20 + bit_size: 4 +fieldset/DBGCR: + description: SBS debug control register. + fields: + - name: AP_UNLOCK + description: access port unlock Write 0xB4 to this bitfield to open the device access port. + bit_offset: 0 + bit_size: 8 + - name: DBG_UNLOCK + description: debug unlock Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register. + bit_offset: 8 + bit_size: 8 + - name: DBG_AUTH_HDPL + description: 'authenticated debug hide protection level Writing to this bitfield defines at which HDPL the authenticated debug opens. Note: Writing any other values is ignored. Reading any other value means the authenticated debug always fails.' + bit_offset: 16 + bit_size: 8 + enum: DBG_AUTH_HDPL +fieldset/DBGLOCKR: + description: SBS debug lock register. + fields: + - name: DBGCFG_LOCK + description: 'debug configuration lock Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4. Other: Writes to SBS_DBGCR ignored Note: 0xC3 is the recommended value to lock the debug configuration using this bitfield.' + bit_offset: 0 + bit_size: 8 + enum: DBGCFG_LOCK +fieldset/EXTICR: + description: external interrupt configuration register 2 + fields: + - name: EXTI + description: EXTI x configuration (x = 4 to 7) + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 +fieldset/FPUIMR: + description: SBS FPU interrupt mask register. + fields: + - name: FPU_IE + description: 'FPU interrupt enable Set and cleared by software to enable the Cortex-M7 FPU interrupts xxxxx1: Invalid operation interrupt enabled (xxxxx0 to disable) xxxx1x: Divide-by-zero interrupt enabled (xxxx0x to disable) xxx1xx: Underflow interrupt enabled (xxx0xx to disable) xx1xxx: Overflow interrupt enabled (xx0xxx to disable) x1xxxx: Input denormal interrupt enabled (x0xxxx to disable) 1xxxxx: Inexact interrupt enabled (0xxxxx to disable), disabled by default.' + bit_offset: 0 + bit_size: 6 +fieldset/HDPLCR: + description: SBS hide protection control register. + fields: + - name: INCR_HDPL + description: increment HDPL Write 0x6A to increment device HDPL by one. After a write, the register value reverts to its default value (0xB4). + bit_offset: 0 + bit_size: 8 +fieldset/HDPLSR: + description: SBS hide protection status register. + fields: + - name: HDPL + description: 'hide protection level This bitfield returns the current HDPL of the device. 0x6F and other codes: HDPL3, corresponding to non-boot application. Note: The device state (open/close) is defined in FLASH_NVSTATER register of the embedded Flash memory.' + bit_offset: 0 + bit_size: 8 + enum: HDPL +fieldset/MESR: + description: SBS memory erase status register. + fields: + - name: MEF + description: 'memory erase flag This bit is set by hardware when BKPRAM and PKA SRAM erase is ongoing after a POWER ON reset or one tamper event (see Section 50: Tamper and backup registers (TAMP) for details). This bit is cleared when the erase is done.' + bit_offset: 0 + bit_size: 1 +fieldset/PMCR: + description: SBS product mode and configuration register. + fields: + - name: FMPLUS_PB6 + description: Fast-mode Plus on PB(6). + bit_offset: 4 + bit_size: 1 + - name: FMPLUS_PB7 + description: Fast-mode Plus on PB(7). + bit_offset: 5 + bit_size: 1 + - name: FMPLUS_PB8 + description: Fast-mode Plus on PB(8). + bit_offset: 6 + bit_size: 1 + - name: FMPLUS_PB9 + description: Fast-mode Plus on PB(9). + bit_offset: 7 + bit_size: 1 + - name: BOOSTEN + description: booster enable Set this bit to reduce the THD of the analog switches when the supply voltage is below 2.7 V. guaranteeing the same performance as with the full voltage range. To avoid current consumption due to booster activation when VDDA < 2.7 V and VDD > 2.7 V, VDD can be selected as supply voltage for analog switches by setting BOOSTVDDSEL bit in SBS_PMCR. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. + bit_offset: 8 + bit_size: 1 + - name: BOOSTVDDSEL + description: booster VDD selection This bit selects the analog switch supply voltage, between VDD, VDDA and booster. To avoid current consumption due to booster activation when VDDA < 2.7 V and VDD > 2.7 V, VDD can be selected as supply voltage for analog switches. In this case, the BOOSTEN bit must be cleared to avoid unwanted power consumption. When both VDD and VDDA are below 2.7 V, the booster is still needed to obtain full AC performances from the I/O analog switches. + bit_offset: 9 + bit_size: 1 + - name: ETH_SEL_PHY + description: Ethernet PHY interface selection. + bit_offset: 21 + bit_size: 3 + enum: ETH_SEL_PHY + - name: AXIRAM_WS + description: AXIRAM wait state Set this bit to add one wait state to all AXIRAMs when ECC = 0. When ECC = 1 there is one wait state by default. + bit_offset: 28 + bit_size: 1 + enum: AXIRAM_WS +fieldset/RSSCMDR: + description: SBS RSS command register. + fields: + - name: RSSCMD + description: RSS command The application can use this bitfield to pass on a command to the RSS, executed at the next reset. + bit_offset: 0 + bit_size: 16 +enum/AXIRAM_WS: + bit_size: 1 + variants: + - name: Ws0 + description: No wait state added when accessing any AXIRAM with ECC = 0. + value: 0 + - name: Ws1 + description: One wait state added when accessing any AXIRAM with ECC = 0. In this case, Fmax = 500 MHz is not guaranteed. (TBC). + value: 1 +enum/DBGCFG_LOCK: + bit_size: 8 + variants: + - name: Unlock + description: Writes to SBS_DBGCR allowed (default). + value: 180 +enum/DBG_AUTH_HDPL: + bit_size: 8 + variants: + - name: HDPL1 + description: HDPL1. + value: 81 + - name: HDPL3 + description: HDPL3. + value: 111 + - name: HDPL2 + description: HDPL2. + value: 138 +enum/ETH_SEL_PHY: + bit_size: 3 + variants: + - name: MII_GMII + description: GMII or MII + value: 0 + - name: RMII + description: RMII + value: 4 +enum/HDPL: + bit_size: 8 + variants: + - name: HDPL1 + description: HDPL1. + value: 81 + - name: HDPL2 + description: HDPL2. + value: 138 + - name: HDPL0 + description: HDPL0, corresponding to ST-RSS (default when device is close). + value: 180 diff --git a/data/registers/usbram_32_1024.yaml b/data/registers/usbram_32_1024.yaml new file mode 100644 index 0000000..4cb4416 --- /dev/null +++ b/data/registers/usbram_32_1024.yaml @@ -0,0 +1,9 @@ +block/USBRAM: + description: USB Endpoint memory + items: + - name: MEM + description: USB Endpoint memory + array: + len: 256 + stride: 4 + byte_offset: 0 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index fa6c5d0..9a86448 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -4,6 +4,8 @@ use std::collections::{HashMap, HashSet}; use stm32_data_serde::chip::core::peripheral::Pin; use super::*; +use crate::gpio_af::parse_signal_name; +use crate::normalize_peris::normalize_peri_name; mod xml { use serde::Deserialize; @@ -86,7 +88,7 @@ fn chip_name_from_package_name(x: &str) -> String { (regex!("^(STM32G0....).xN$"), "$1"), (regex!("^(STM32L5....).x[PQ]$"), "$1"), (regex!("^(STM32L0....).xS$"), "$1"), - (regex!("^(STM32H7....).xQ$"), "$1"), + (regex!("^(STM32H7....).x[QH]$"), "$1"), (regex!("^(STM32U5....).xQ$"), "$1"), (regex!("^(STM32H5....).xQ$"), "$1"), (regex!("^(STM32WBA....).x$"), "$1"), @@ -134,6 +136,7 @@ impl PeriMatcher { (".*:LPUART:sci3_v1_3", ("usart", "v4", "LPUART")), (".*:LPUART:sci3_v1_4", ("usart", "v4", "LPUART")), ("STM32[HU]5.*:RNG:.*", ("rng", "v3", "RNG")), + ("STM32U0.*:RNG:.*", ("rng", "v3", "RNG")), ("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")), ("STM32L4[PQ]5.*:RNG:.*", ("rng", "v2", "RNG")), ("STM32WL.*:RNG:.*", ("rng", "v2", "RNG")), @@ -149,6 +152,7 @@ impl PeriMatcher { ("STM32F7.*:AES:.*", ("aes", "f7", "AES")), ("STM32F4.*:AES:.*", ("aes", "v1", "AES")), ("STM32G0.*:AES:.*", ("aes", "v2", "AES")), + ("STM32U0.*:AES:.*", ("aes", "v2", "AES")), ("STM32G4.*:AES:.*", ("aes", "v2", "AES")), ("STM32L0.*:AES:.*", ("aes", "v1", "AES")), ("STM32L1.*:AES:.*", ("aes", "v1", "AES")), @@ -182,6 +186,7 @@ impl PeriMatcher { (".*:I2C:F0-i2c2_v1_1", ("i2c", "v2", "I2C")), (".*:I2C:i2c2_v1_1F7", ("i2c", "v2", "I2C")), (".*:I2C:i2c2_v1_1U5", ("i2c", "v2", "I2C")), + (".*:I2C:i2c1_v1_0H7RS", ("i2c", "v3", "I2C")), ("STM32F10[1357].*:DAC:dacif_v1_1F1", ("dac", "v1", "DAC")), // Original F1 are v1 (".*:DAC:dacif_v1_1F1", ("dac", "v2", "DAC")), (".*:DAC:F0dacif_v1_1", ("dac", "v2", "DAC")), @@ -191,6 +196,7 @@ impl PeriMatcher { ("STM32L4[1-9A].*:DAC:dacif_v2_0", ("dac", "v3", "DAC")), // L4 non-plus are v3 (".*:DAC:dacif_v2_0", ("dac", "v5", "DAC")), (".*:DAC:dacif_v2_0_U5", ("dac", "v6", "DAC")), + (".*:DAC:dacif_v2_0_U0", ("dac", "v4", "DAC")), (".*:DAC:dacif_v3_0", ("dac", "v4", "DAC")), (".*:DAC:WL_dacif_v3_0", ("dac", "v4", "DAC")), (".*:DAC:G4_dacif_v4_0", ("dac", "v7", "DAC")), @@ -211,26 +217,25 @@ impl PeriMatcher { ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")), - ("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")), + ("STM32U0.*:ADC:.*", ("adc", "u0", "ADC")), ("STM32G4.*:ADC:.*", ("adc", "g4", "ADC")), - ("STM32G4.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), - (".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")), - (".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")), - (".*:ADC_COMMON:aditf5_v2_2", ("adccommon", "v3", "ADC_COMMON")), - (".*:ADC_COMMON:aditf4_v3_0_WL", ("adccommon", "v3", "ADC_COMMON")), - (".*:ADC_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), - (".*:ADC3_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), + ("STM32G0.*:ADC\\d*_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")), + ("STM32U0.*:ADC\\d*_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")), + ("STM32G4.*:ADC\\d*_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), ( - "STM32H50.*:ADC_COMMON:aditf5_v3_0_H5", - ("adccommon", "h50", "ADC_COMMON"), + "STM32(L[45]|W[BL]).*:ADC\\d*_COMMON:.*", + ("adccommon", "v3", "ADC_COMMON"), ), - ("STM32H5.*:ADC_COMMON:aditf5_v3_0_H5", ("adccommon", "h5", "ADC_COMMON")), - ("STM32H7.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), - ("STM32H7.*:ADC3_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), + ("STM32F3.*:ADC\\d*_COMMON:.*", ("adccommon", "f3", "ADC_COMMON")), + ("STM32F[247].*:ADC\\d*_COMMON:.*", ("adccommon", "v2", "ADC_COMMON")), + ("STM32H50.*:ADC\\d*_COMMON:.*", ("adccommon", "h50", "ADC_COMMON")), + ("STM32H5.*:ADC\\d*_COMMON:.*", ("adccommon", "h5", "ADC_COMMON")), + ("STM32H7.*:ADC\\d*_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), ("STM32G4.*:OPAMP:G4_tsmc90_fastOpamp", ("opamp", "g4", "OPAMP")), ("STM32F3.*:OPAMP:tsmc018_ull_opamp_v1_0", ("opamp", "f3", "OPAMP")), ("STM32H7.*:OPAMP:.*", ("opamp", "h_v1", "OPAMP")), ("STM32H5.*:OPAMP:.*", ("opamp", "h_v2", "OPAMP")), + ("STM32U0.*:OPAMP:.*", ("opamp", "u0", "OPAMP")), (".*:DCMI:.*", ("dcmi", "v1", "DCMI")), ("STM32C0.*:SYSCFG:.*", ("syscfg", "c0", "SYSCFG")), ("STM32F0.*:SYSCFG:.*", ("syscfg", "f0", "SYSCFG")), @@ -244,6 +249,7 @@ impl PeriMatcher { ("STM32L5.*:SYSCFG:.*", ("syscfg", "l5", "SYSCFG")), ("STM32G0.*:SYSCFG:.*", ("syscfg", "g0", "SYSCFG")), ("STM32G4.*:SYSCFG:.*", ("syscfg", "g4", "SYSCFG")), + ("STM32H7[RS].*:SYSCFG:.*", ("syscfg", "h7rs", "SYSCFG")), ( "STM32H7(45|47|55|57|42|43|53|50).*:SYSCFG:.*", ("syscfg", "h7od", "SYSCFG"), @@ -255,8 +261,8 @@ impl PeriMatcher { ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")), ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")), ("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")), - ("STM32H50.*:SBS:.*", ("syscfg", "h50", "SYSCFG")), - ("STM32H5.*:SBS:.*", ("syscfg", "h5", "SYSCFG")), + ("STM32H50.*:SYSCFG:.*", ("syscfg", "h50", "SYSCFG")), + ("STM32H5.*:SYSCFG:.*", ("syscfg", "h5", "SYSCFG")), (".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")), (".*:IWDG:iwdg1_v2_0", ("iwdg", "v2", "IWDG")), (".*:IWDG:iwdg1_v3_0", ("iwdg", "v3", "IWDG")), @@ -264,6 +270,10 @@ impl PeriMatcher { (".*:WWDG:wwdg1_v2_0", ("wwdg", "v2", "WWDG")), (".*:JPEG:jpeg1_v1_0", ("jpeg", "v1", "JPEG")), (".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")), + (".*:DSIHOST:dsihost1_v1_0", ("dsihost", "v1", "DSIHOST")), + (".*:DSIHOST:dsihost1_v1_0_SHARK", ("dsihost", "v1", "DSIHOST")), + (".*:DSIHOST:dsihost1_v2_0", ("dsihost", "v2", "DSIHOST")), + (".*:DSIHOST:dsihost_U5", ("dsihost", "u5", "DSIHOST")), (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")), (".*:QUADSPI:.*", ("quadspi", "v1", "QUADSPI")), ("STM32F1.*:BKP.*", ("bkp", "v1", "BKP")), @@ -286,6 +296,7 @@ impl PeriMatcher { (".*:RTC:rtc3_v1_1", ("rtc", "v3", "RTC")), (".*:RTC:rtc3_v2_0", ("rtc", "v3", "RTC")), (".*:RTC:rtc3_v3_0", ("rtc", "v3", "RTC")), + (".*:RTC:rtc3_v3_5", ("rtc", "v3", "RTC")), (".*:SAI:sai1_v1_0", ("sai", "v1", "SAI")), (".*:SAI:sai1_v1_1", ("sai", "v2", "SAI")), (".*:SAI:sai1_v1_2", ("sai", "v2", "SAI")), @@ -308,8 +319,9 @@ impl PeriMatcher { ("STM32F373.*:USBRAM:.*", ("usbram", "16x2_512", "USBRAM")), ("STM32(F0|L[045]|G4|WB).*:USB:.*", ("usb", "v3", "USB")), ("STM32(F0|L[045]|G4|WB).*:USBRAM:.*", ("usbram", "16x2_1024", "USBRAM")), - ("STM32(G0|H5|U5).*:USB:.*", ("usb", "v4", "USB")), + ("STM32(G0|H5|U5|U0).*:USB:.*", ("usb", "v4", "USB")), ("STM32(G0|H5|U5).*:USBRAM:.*", ("usbram", "32_2048", "USBRAM")), + ("STM32U0.*:USBRAM:.*", ("usbram", "32_1024", "USBRAM")), // # USB OTG (".*:USB_OTG_FS:otgfs1_.*", ("otg", "v1", "OTG")), ("STM32U5A.*:USB_OTG_HS:otghs1_.*", ("otg", "v2", "OTG")), @@ -336,6 +348,7 @@ impl PeriMatcher { ("STM32F7.*:RCC:.*", ("rcc", "f7", "RCC")), ("STM32G0.*:RCC:.*", ("rcc", "g0", "RCC")), ("STM32G4.*:RCC:.*", ("rcc", "g4", "RCC")), + ("STM32H7[RS].*:RCC:.*", ("rcc", "h7rs", "RCC")), ("STM32H7[AB].*:RCC:.*", ("rcc", "h7ab", "RCC")), ("STM32H7(42|43|53|50).*:RCC:.*", ("rcc", "h7rm0433", "RCC")), ("STM32H7.*:RCC:.*", ("rcc", "h7", "RCC")), @@ -376,6 +389,7 @@ impl PeriMatcher { ("STM32G0.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32G4.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32U5.*:CRS:.*", ("crs", "v1", "CRS")), + ("STM32U0.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32H5.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32H7.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32WB.*:CRS:.*", ("crs", "v1", "CRS")), @@ -384,6 +398,7 @@ impl PeriMatcher { ("STM32C0.*:PWR:.*", ("pwr", "c0", "PWR")), ("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")), ("STM32G4.*:PWR:.*", ("pwr", "g4", "PWR")), + ("STM32H7[RS].*:PWR:.*", ("pwr", "h7rs", "PWR")), ("STM32H7(45|47|55|57).*:PWR:.*", ("pwr", "h7rm0399", "PWR")), ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7rm0433", "PWR")), ("STM32H7(23|25|33|35|30).*:PWR:.*", ("pwr", "h7rm0468", "PWR")), @@ -407,6 +422,7 @@ impl PeriMatcher { ("STM32WB.*:PWR:.*", ("pwr", "wb", "PWR")), ("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")), ("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")), + ("STM32H7[RS].*:FLASH:.*", ("flash", "h7rs", "FLASH")), ("STM32H7(A3|B3|B0).*:FLASH:.*", ("flash", "h7ab", "FLASH")), ("STM32H7.*:FLASH:.*", ("flash", "h7", "FLASH")), ("STM32F0.*:FLASH:.*", ("flash", "f0", "FLASH")), @@ -473,8 +489,9 @@ impl PeriMatcher { ("STM32F.*:TIM(9|12):.*", ("timer", "v1", "TIM_2CH")), ("STM32F.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32F.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), - ("STM32F.*:LPTIM1:.*", ("lptim", "v1", "LPTIM")), ("STM32F.*:HRTIM:.*", ("hrtim", "v1", "HRTIM")), + // LPTIM for STM32Fx serials + ("STM32(F4|F7).*:LPTIM.*:.*", ("lptim", "v1a", "LPTIM")), // AN4013 Table 3: STM32Lx serials // Override for STM32L0 serial ("STM32L0.*:TIM(2|3):.*", ("timer", "l0", "TIM_GP16")), @@ -491,8 +508,11 @@ impl PeriMatcher { ("STM32L.*:TIM(9|21|22):.*", ("timer", "v1", "TIM_2CH")), ("STM32L.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32L.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), - ("STM32L5.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")), - ("STM32L.*:LPTIM(1|2|3):.*", ("lptim", "v1", "LPTIM")), + // LPTIM for STM32Lx + ("STM32L5.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), + ("STM32L4[PQRS].*:LPTIM.*:.*", ("lptim", "v1b", "LPTIM")), + ("STM32L4[^PQRS].*:LPTIM.*:.*", ("lptim", "v1a", "LPTIM")), + ("STM32L0.*:LPTIM.*:.*", ("lptim", "v1", "LPTIM")), // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), @@ -507,9 +527,6 @@ impl PeriMatcher { ("STM32(G4|H5|U0|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")), ("STM32(G4|H5|U0|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")), ("STM32(G4|H5|U0|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")), - ("STM32WL.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")), - ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2b", "LPTIM_ADV")), - ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2b", "LPTIM_BASIC")), ("STM32G4.*:HRTIM1:.*", ("hrtim", "v2", "HRTIM")), // timer_v1 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32(C|G0|H7|WB|WL).*:TIM(1|8|20):.*", ("timer", "v1", "TIM_ADV")), @@ -520,8 +537,15 @@ impl PeriMatcher { ("STM32(C|G0|H7|WB|WL).*:TIM12:.*", ("timer", "v1", "TIM_2CH")), ("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), - ("STM32(C|G|H7|U|W).*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")), ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")), + // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials + ("STM32U0.*:LPTIM.*:.*", ("lptim", "v2b", "LPTIM")), + ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2a", "LPTIM_ADV")), + ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2a", "LPTIM_BASIC")), + ("STM32WL.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), + ("STM32H7.*:LPTIM.*:.*", ("lptim", "v1b_h7", "LPTIM")), + ("STM32G4.*:LPTIM.*:.*", ("lptim", "v1b_g4", "LPTIM")), + ("STM32(G0|WB).*:LPTIM.*:.*", ("lptim", "v1b", "LPTIM")), // //// TIM mapping ends here //// ("STM32F0.*:DBGMCU:.*", ("dbgmcu", "f0", "DBGMCU")), @@ -555,7 +579,9 @@ impl PeriMatcher { ("STM32WL5.*:HSEM:.*", ("hsem", "v3", "HSEM")), ("STM32WLE.*:HSEM:.*", ("hsem", "v4", "HSEM")), (".*:DMAMUX.*", ("dmamux", "v1", "DMAMUX")), - (r".*:GPDMA\d?:.*", ("gpdma", "v1", "GPDMA")), + (r".*:GPDMA\d?:.*", ("gpdma", "v1", "GPDMA")), // TODO there's multiple versions for with+without trustzone. + (r".*:HPDMA\d?:.*", ("gpdma", "v1", "GPDMA")), // TODO it has a few more bits like DWX + (r".*:LPDMA\d?:.*", ("lpdma", "v1", "LPDMA")), (r".*:BDMA\d?:.*", ("bdma", "v1", "DMA")), ("STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0", ("dma2d", "v2", "DMA2D")), (".*:DMA2D:dma2d1_v1_0", ("dma2d", "v1", "DMA2D")), @@ -580,6 +606,7 @@ impl PeriMatcher { ("STM32L[045].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32W[BL].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32C[0].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32U[0].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32U[5].*:CRC:.*", ("crc", "v3", "CRC")), (".*:LCD:lcdc1_v1.0.*", ("lcd", "v1", "LCD")), (".*:LCD:lcdc1_v1.2.*", ("lcd", "v2", "LCD")), @@ -630,6 +657,7 @@ impl PeriMatcher { ("STM32WBA.*:TSC:.*", ("tsc", "v1", "TSC")), ("STM32L[045].*:TSC:.*", ("tsc", "v3", "TSC")), ("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")), + ("STM32U0.*:TSC:.*", ("tsc", "v2", "TSC")), ("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")), ("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")), (".*:HASH:hash1_v1_0", ("hash", "v1", "HASH")), @@ -640,11 +668,13 @@ impl PeriMatcher { (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")), (".*:CRYP:cryp1_v1_0.*", ("cryp", "v1", "CRYP")), (".*:CRYP:cryp1_v2_0_H7.*", ("cryp", "v3", "CRYP")), + (".*:CRYP:cryp1-v2_5", ("cryp", "v4", "CRYP")), (".*:CRYP:cryp1_v2_0.*", ("cryp", "v2", "CRYP")), ("STM32F41.*:CRYP:cryp1_v2_2.*", ("cryp", "v1", "CRYP")), (".*:CRYP:cryp1_v2_2.*", ("cryp", "v2", "CRYP")), ("STM32G0.1.*:.*:COMP:.*", ("comp", "v1", "COMP")), ("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")), + ("STM32U0.*:.*:COMP:.*", ("comp", "u0", "COMP")), ("STM32WL.*:.*:COMP:.*", ("comp", "v3", "COMP")), ("STM32H7[45].*:COMP:.*", ("comp", "h7_b", "COMP")), ("STM32H7[AB].*:COMP:.*", ("comp", "h7_a", "COMP")), @@ -785,16 +815,6 @@ pub fn parse_groups() -> Result<(HashMap, Vec), anyhow: static NOPELIST: &[&str] = &[ // Not supported, not planned unless someone wants to do it. "STM32MP", - // not supported yet, planned. Pull requests welcome! - "STM32H52", - "STM32H53", - "STM32H7R", - "STM32H7S", - "STM32U5F", - "STM32U5G", - "STM32WBA50", - "STM32WBA54", - "STM32WBA55", // Does not exist in ST website. No datasheet, no RM. "STM32GBK", "STM32L485", @@ -984,7 +1004,7 @@ fn process_core( let mut peri_kinds = HashMap::new(); for ip in group.ips.values() { - let pname = ip.instance_name.clone(); + let pname = normalize_peri_name(&ip.instance_name); let pkind = format!("{}:{}", ip.name, ip.version); let pkind = pkind.strip_suffix("_Cube").unwrap_or(&pkind); @@ -997,6 +1017,14 @@ fn process_core( "IRTIM", // We add this as ghost peri "SYS", + "ADC_COMMON", + "ADC1_COMMON", + "ADC12_COMMON", + "ADC123_COMMON", + "ADC3_COMMON", + "ADC4_COMMON", + "ADC34_COMMON", + "ADC345_COMMON", // These are software libraries "FREERTOS", "PDM2PCM", @@ -1011,29 +1039,11 @@ fn process_core( "TOUCHSENSING", ]; - if FAKE_PERIPHERALS.contains(&pname.as_str()) { + if FAKE_PERIPHERALS.contains(&pname) { continue; } - let pname = match pname.as_str() { - "HDMI_CEC" => "CEC".to_string(), - "SUBGHZ" => "SUBGHZSPI".to_string(), - // remove when https://github.com/stm32-rs/stm32-rs/pull/789 merges - "USB_DRD_FS" => "USB".to_string(), - _ => pname, - }; - - if pname.starts_with("ADC") { - if let Entry::Vacant(entry) = peri_kinds.entry("ADC_COMMON".to_string()) { - entry.insert(format!("ADC_COMMON:{}", ip.version.strip_suffix("_Cube").unwrap())); - } - } - if pname.starts_with("ADC3") && (chip_name.starts_with("STM32H7") || chip_name.starts_with("STM32F3")) { - if let Entry::Vacant(entry) = peri_kinds.entry("ADC3_COMMON".to_string()) { - entry.insert(format!("ADC3_COMMON:{}", ip.version.strip_suffix("_Cube").unwrap())); - } - } - peri_kinds.insert(pname, pkind.to_string()); + peri_kinds.insert(pname.to_string(), pkind.to_string()); } const GHOST_PERIS: &[&str] = &[ "GPIOA", @@ -1075,9 +1085,17 @@ fn process_core( "VREFINTCAL", "UID", "HSEM", + "ADC1_COMMON", + "ADC12_COMMON", + "ADC123_COMMON", + "ADC3_COMMON", + "ADC4_COMMON", + "ADC34_COMMON", + "ADC345_COMMON", ]; for pname in GHOST_PERIS { - if let Entry::Vacant(entry) = peri_kinds.entry(pname.to_string()) { + let normalized_pname = normalize_peri_name(pname); + if let Entry::Vacant(entry) = peri_kinds.entry(normalized_pname.to_string()) { if defines.get_peri_addr(pname).is_some() { entry.insert("unknown".to_string()); } @@ -1117,27 +1135,21 @@ fn process_core( let mut periph_pins = HashMap::<_, Vec<_>>::new(); for (pin_name, pin) in &group.pins { for signal in &pin.signals { - let mut signal = signal.name.clone(); - if signal.starts_with("DEBUG_SUBGHZSPI-") { - signal = format!("SUBGHZSPI_{}", &signal[16..(signal.len() - 3)]); - } + let signal = &signal.name; // TODO: What are those signals (well, GPIO is clear) Which peripheral do they belong to? - if !["GPIO", "CEC", "AUDIOCLK", "VDDTCXO"].contains(&signal.as_str()) && !signal.contains("EXTI") { - // both peripherals and signals can have underscores in their names so there is no easy way to split - // check if signal name starts with one of the peripheral names - for periph in peri_kinds.keys() { - if let Some(signal) = signal.strip_prefix(&format!("{periph}_")) { - periph_pins.entry(periph.to_string()).or_default().push( - stm32_data_serde::chip::core::peripheral::Pin { - pin: pin_name.clone(), - signal: signal.to_string(), - af: None, - }, - ); - break; - } - } + if ["GPIO", "CEC", "AUDIOCLK", "VDDTCXO"].contains(&signal.as_str()) || signal.contains("EXTI") { + continue; } + let Some((signal_peri, signal_name)) = parse_signal_name(signal) else { + continue; + }; + periph_pins.entry(signal_peri.to_string()).or_default().push( + stm32_data_serde::chip::core::peripheral::Pin { + pin: pin_name.clone(), + signal: signal_name.to_string(), + af: None, + }, + ); } } for pins in periph_pins.values_mut() { @@ -1151,15 +1163,7 @@ fn process_core( continue; } - let addr = if (chip_name.starts_with("STM32F0") - || chip_name.starts_with("STM32L1") - || chip_name.starts_with("STM32L0")) - && pname == "ADC" - { - defines.get_peri_addr("ADC1") - } else if chip_name.starts_with("STM32H7") && pname == "HRTIM" { - defines.get_peri_addr("HRTIM1") - } else if let Some(cap) = regex!(r"^FDCANRAM(?P[0-9]+)$").captures(&pname) { + let addr = if let Some(cap) = regex!(r"^FDCANRAM(?P[0-9]+)$").captures(&pname) { defines.get_peri_addr("FDCANRAM").map(|addr| { if chip_name.starts_with("STM32H7") { addr @@ -1174,17 +1178,10 @@ fn process_core( defines.get_peri_addr(&pname) }; - let addr = match addr { - Some(addr) => addr, - None => continue, - }; + let Some(addr) = addr else { continue }; let mut p = stm32_data_serde::chip::core::Peripheral { - name: if pname == "SBS" { - "SYSCFG".to_string() - } else { - pname.clone() - }, + name: pname.clone(), address: addr, registers: None, rcc: None, @@ -1276,68 +1273,65 @@ fn process_core( let mut peripherals: Vec<_> = peripherals.into_values().collect(); peripherals.sort_by_key(|x| x.name.clone()); // Collect DMA versions in the chip - let mut chip_dmas: Vec<_> = group + let mut dmas: Vec<_> = group .ips .values() .filter_map(|ip| { let version = &ip.version; - let sort = match ip.name.as_str() { - "DMA" => 1, - "BDMA" => 2, - "BDMA1" => 3, - "BDMA2" => 4, - "GPDMA" => 5, - _ => 0, - }; - if sort > 0 && dma_channels.0.contains_key(version) { - Some((sort, version.clone())) + let instance = &ip.instance_name; + if let Some(dma) = dma_channels + .0 + .get(version) + .or_else(|| dma_channels.0.get(&format!("{version}:{instance}"))) + { + Some((ip.name.clone(), instance.clone(), dma)) } else { None } }) .collect(); - chip_dmas.sort(); - chip_dmas.dedup(); - let chip_dmas: Vec<_> = chip_dmas.into_iter().map(|(_sort, version)| version).collect(); - // Process DMA channels - let chs = chip_dmas - .iter() - .flat_map(|dma| dma_channels.0.get(dma).unwrap().channels.clone()); + dmas.sort_by_key(|(name, instance, _)| { + ( + match name.as_str() { + "DMA" => 1, + "BDMA" => 2, + "BDMA1" => 3, + "BDMA2" => 4, + "GPDMA" => 5, + "HPDMA" => 6, + _ => 0, + }, + instance.clone(), + ) + }); + // The dma_channels[xx] is generic for multiple chips. The current chip may have less DMAs, // so we have to filter it. - let chs: Vec<_> = chs.filter(|ch| have_peris.contains(&ch.dma)).collect(); - let core_dma_channels = chs.clone(); - let have_chs: HashSet<_> = chs.into_iter().collect(); + let dma_channels = dmas + .iter() + .flat_map(|(_, _, dma)| dma.channels.clone()) + .filter(|ch| have_peris.contains(&ch.dma)) + .collect::>(); + let have_chs: HashSet<_> = dma_channels.iter().map(|ch| ch.name.clone()).collect(); + // Process peripheral - DMA channel associations for p in &mut peripherals { let mut chs = Vec::new(); - for dma in &chip_dmas { - let mut peri_chs = dma_channels.0.get(dma).unwrap().peripherals.get(&p.name); - - // DAC1 is sometimes interchanged with DAC - if peri_chs.is_none() && p.name == "DAC1" { - peri_chs = dma_channels.0.get(dma).unwrap().peripherals.get("DAC"); - } - - if let Some(peri_chs) = peri_chs { + for (_, _, dma) in &dmas { + if let Some(peri_chs) = dma.peripherals.get(&p.name) { chs.extend( peri_chs .iter() - .filter(|ch| { - if let Some(ch_channel) = &ch.channel { - have_chs.iter().any(|x| &x.name == ch_channel) - } else { - true - } + .filter(|ch| match &ch.channel { + None => true, + Some(channel) => have_chs.contains(channel), }) .cloned(), ); } } - if !chs.is_empty() { - chs.sort_by_key(|ch| (ch.channel.clone(), ch.dmamux.clone(), ch.request)); - p.dma_channels = chs; - } + chs.sort_by_key(|ch| (ch.channel.clone(), ch.dmamux.clone(), ch.request)); + p.dma_channels = chs; } let mut core = stm32_data_serde::chip::Core { @@ -1345,7 +1339,7 @@ fn process_core( peripherals, nvic_priority_bits: None, interrupts: vec![], - dma_channels: core_dma_channels, + dma_channels, }; chip_interrupts.process(&mut core, chip_name, h, group); diff --git a/stm32-data-gen/src/dma.rs b/stm32-data-gen/src/dma.rs index 116edc7..2758ede 100644 --- a/stm32-data-gen/src/dma.rs +++ b/stm32-data-gen/src/dma.rs @@ -2,6 +2,8 @@ use std::collections::HashMap; use anyhow::Context; +use crate::normalize_peris::normalize_peri_name; + mod xml { use serde::Deserialize; @@ -150,7 +152,7 @@ impl DmaChannels { }; chip_dma .peripherals - .entry(target_peri_name.to_string()) + .entry(normalize_peri_name(target_peri_name).to_string()) .or_default() .push(stm32_data_serde::chip::core::peripheral::DmaChannel { signal: request.to_string(), @@ -270,7 +272,7 @@ impl DmaChannels { }; chip_dma .peripherals - .entry(target_peri_name.to_string()) + .entry(normalize_peri_name(target_peri_name).to_string()) .or_default() .push(entry); } @@ -294,11 +296,14 @@ impl DmaChannels { // GPDMA - for (file, gpdmax, instance, count, count_2d) in [ + for (file, instance, version, count, count_2d) in [ ("H5_GPDMA.yaml", "GPDMA1", "STM32H5_dma3_Cube", 8, 2), ("H5_GPDMA.yaml", "GPDMA2", "Instance2_STM32H5_dma3_Cube", 8, 2), ("U5_GPDMA1.yaml", "GPDMA1", "STM32U5_dma3_Cube", 16, 4), + ("U5_LPDMA.yaml", "LPDMA1", "STM32U5_dma3_Cube", 4, 0), ("WBA_GPDMA1.yaml", "GPDMA1", "STM32WBA_dma3_Cube", 8, 0), + ("H7RS_GPDMA.yaml", "GPDMA1", "STM32H7RS_dma3_Cube", 16, 4), + ("H7RS_HPDMA.yaml", "HPDMA1", "STM32H7RS_dma3_Cube", 16, 4), ] { let mut chip_dma = ChipDma { peripherals: HashMap::new(), @@ -320,11 +325,11 @@ impl DmaChannels { }; chip_dma .peripherals - .entry(target_peri_name.to_string()) + .entry(normalize_peri_name(target_peri_name).to_string()) .or_default() .push(stm32_data_serde::chip::core::peripheral::DmaChannel { signal: request.to_string(), - dma: Some(gpdmax.to_string()), + dma: Some(instance.to_string()), channel: None, dmamux: None, request: Some(request_num), @@ -333,8 +338,8 @@ impl DmaChannels { for i in 0..count { chip_dma.channels.push(stm32_data_serde::chip::core::DmaChannels { - name: format!("{gpdmax}_CH{i}"), - dma: gpdmax.to_string(), + name: format!("{instance}_CH{i}"), + dma: instance.to_string(), channel: i, dmamux: None, dmamux_channel: None, @@ -342,7 +347,7 @@ impl DmaChannels { }); } - dma_channels.insert(instance.to_string(), chip_dma); + dma_channels.insert(format!("{version}:{instance}"), chip_dma); } Ok(Self(dma_channels)) diff --git a/stm32-data-gen/src/gpio_af.rs b/stm32-data-gen/src/gpio_af.rs index baf6bae..4bfc176 100644 --- a/stm32-data-gen/src/gpio_af.rs +++ b/stm32-data-gen/src/gpio_af.rs @@ -1,5 +1,6 @@ use std::collections::HashMap; +use crate::normalize_peris::normalize_peri_name; use crate::regex; mod xml { @@ -102,7 +103,7 @@ impl Af { } } -fn parse_signal_name(signal_name: &str) -> Option<(&str, &str)> { +pub fn parse_signal_name(signal_name: &str) -> Option<(&str, &str)> { let (peri_name, signal_name) = { if let Some(signal_name) = signal_name.strip_prefix("USB_OTG_FS_") { ("USB_OTG_FS", signal_name) @@ -121,6 +122,6 @@ fn parse_signal_name(signal_name: &str) -> Option<(&str, &str)> { Some((peri_name, signal_name.strip_suffix("OUT").unwrap_or(signal_name))) } else { - Some((peri_name, signal_name)) + Some((normalize_peri_name(peri_name), signal_name)) } } diff --git a/stm32-data-gen/src/header.rs b/stm32-data-gen/src/header.rs index b6dfb44..5bddcb2 100644 --- a/stm32-data-gen/src/header.rs +++ b/stm32-data-gen/src/header.rs @@ -175,11 +175,14 @@ impl Defines { &["OCTOSPI2_R_BASE", "OCTOSPI2_R_BASE_NS", "OCTOSPI2_REG_BASE"], ), ("FLASH", &["FLASH_R_BASE", "FLASH_REG_BASE"]), + ("DAC", &["DAC1_BASE", "DAC_BASE"]), + ("DAC1", &["DAC1_BASE", "DAC_BASE"]), + ("ADC", &["ADC1_BASE", "ADC_BASE"]), + ("ADC1", &["ADC1_BASE", "ADC_BASE"]), ( - "ADC_COMMON", - &["ADC_COMMON", "ADC1_COMMON", "ADC12_COMMON", "ADC123_COMMON"], + "ADC1_COMMON", + &["ADC1_COMMON_BASE", "ADC_COMMON_BASE", "ADC1_COMMON", "ADC_COMMON"], ), - ("ADC3_COMMON", &["ADC3_COMMON", "ADC4_COMMON", "ADC34_COMMON"]), ("CAN", &["CAN_BASE", "CAN1_BASE"]), ("FMC", &["FMC_BASE", "FMC_R_BASE"]), ("FSMC", &["FSMC_R_BASE"]), @@ -190,6 +193,8 @@ impl Defines { ), ("FDCANRAM", &["SRAMCAN_BASE", "SRAMCAN_BASE_NS"]), ("VREFINTCAL", &["VREFINT_CAL_ADDR_CMSIS"]), + ("DSIHOST", &["DSI_BASE"]), + ("SYSCFG", &["SYSCFG_BASE", "SBS_BASE"]), ]; let alt_peri_defines: HashMap<_, _> = ALT_PERI_DEFINES.iter().copied().collect(); diff --git a/stm32-data-gen/src/interrupts.rs b/stm32-data-gen/src/interrupts.rs index cdbcd28..909c7a2 100644 --- a/stm32-data-gen/src/interrupts.rs +++ b/stm32-data-gen/src/interrupts.rs @@ -3,7 +3,9 @@ use std::collections::{HashMap, HashSet}; use log::*; use crate::chips::ChipGroup; +use crate::normalize_peris::normalize_peri_name; use crate::regex; +use crate::util::RegexMap; mod xml { use serde::Deserialize; @@ -103,12 +105,17 @@ impl ChipInterrupts { core.interrupts.sort_unstable_by_key(|x| x.number); // =================== Populate peripheral interrupts - let want_nvic_name = pick_nvic(chip_name, &core.name); + let core_name = &core.name; + let want_nvic_name = pick_nvic(chip_name, core_name); let chip_nvic = group .ips .values() .find(|x| x.name == want_nvic_name) - .ok_or_else(|| format!("couldn't find nvic. chip_name={chip_name} want_nvic_name={want_nvic_name}")) + .ok_or_else(|| { + format!( + "couldn't find nvic. chip_name={chip_name} core_name={core_name} want_nvic_name={want_nvic_name}" + ) + }) .unwrap(); let nvic_strings = self .irqs @@ -262,6 +269,8 @@ impl ChipInterrupts { let peri_names: Vec<_> = parts[2] .split(',') .map(|x| if x == "USB_DRD_FS" { "USB" } else { x }) + .map(|x| if x == "XPI1" { "XSPI1" } else { x }) + .map(|x| if x == "XPI2" { "XSPI2" } else { x }) .map(ToString::to_string) .collect(); @@ -342,6 +351,7 @@ impl ChipInterrupts { } for (p, s) in interrupt_signals { + let p = normalize_peri_name(&p).to_string(); let signals = chip_signals.entry(p).or_default(); let irqs = signals.entry(s).or_default(); irqs.insert(header_name.clone()); @@ -463,7 +473,7 @@ fn valid_signals(peri: &str) -> Vec { ("CAN", &["TX", "RX0", "RX1", "SCE"]), ("FDCAN", &["IT0", "IT1", "CAL"]), ("I2C", &["ER", "EV"]), - ("I3C", &["ER", "EV"]), + ("I3C", &["ER", "EV", "WKUP"]), ("FMPI2C", &["ER", "EV"]), ("TIM", &["BRK", "UP", "TRG", "COM", "CC"]), // ("HRTIM", &["Master", "TIMA", "TIMB", "TIMC", "TIMD", "TIME", "TIMF"]), @@ -491,6 +501,8 @@ fn valid_signals(peri: &str) -> Vec { ("USB_OTG_HS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]), ("USB", &["LP", "HP", "WKUP"]), ("GPU2D", &["ER"]), + ("SAI", &["A", "B"]), + ("ADF", &["FLT0"]), ]; for (prefix, signals) in IRQ_SIGNALS_MAP { @@ -501,33 +513,20 @@ fn valid_signals(peri: &str) -> Vec { vec!["GLOBAL".to_string()] } -fn pick_nvic(chip_name: &str, core_name: &str) -> String { - // Most chips have a single NVIC, named "NVIC" - let mut res = "NVIC"; - +static PICK_NVIC: RegexMap<&str> = RegexMap::new(&[ // Exception 1: Multicore: NVIC1 is the first core, NVIC2 is the second. We have to pick the right one. - if ["H745", "H747", "H755", "H757", "WL54", "WL55"].contains(&&chip_name[5..9]) { - if core_name == "cm7" { - res = "NVIC1"; - } else { - res = "NVIC2" - } - } - if &chip_name[5..8] == "WL5" { - if core_name == "cm4" { - res = "NVIC1"; - } else { - res = "NVIC2" - } - } - + ("STM32H7(45|47|55|57).*:cm7", "NVIC1"), + ("STM32H7(45|47|55|57).*:cm4", "NVIC2"), + ("STM32WL5.*:cm4", "NVIC1"), + ("STM32WL5.*:cm0p", "NVIC2"), // Exception 2: TrustZone: NVIC1 is Secure mode, NVIC2 is NonSecure mode. For now, we pick the NonSecure one. - if ["L5", "U5"].contains(&&chip_name[5..7]) { - res = "NVIC2" - } - if ["H56", "H57", "WBA"].contains(&&chip_name[5..8]) { - res = "NVIC2" - } + ("STM32(L5|U5|H5[2367]|WBA5[245]).*", "NVIC2"), + // Exception 3: NVICs are split for "bootloader" and "application", not sure what that means? + ("STM32H7[RS].*", "NVIC2"), + // catch-all: Most chips have a single NVIC, named "NVIC" + (".*", "NVIC"), +]); - res.to_string() +fn pick_nvic(chip_name: &str, core_name: &str) -> String { + PICK_NVIC.must_get(&format!("{chip_name}:{core_name}")).to_string() } diff --git a/stm32-data-gen/src/main.rs b/stm32-data-gen/src/main.rs index c687f42..74dc6aa 100644 --- a/stm32-data-gen/src/main.rs +++ b/stm32-data-gen/src/main.rs @@ -5,8 +5,10 @@ mod gpio_af; mod header; mod interrupts; mod memory; +mod normalize_peris; mod rcc; mod registers; +mod util; #[macro_export] macro_rules! regex { diff --git a/stm32-data-gen/src/memory.rs b/stm32-data-gen/src/memory.rs index e92fb15..ad7c627 100644 --- a/stm32-data-gen/src/memory.rs +++ b/stm32-data-gen/src/memory.rs @@ -1,7 +1,8 @@ -use regex::Regex; use stm32_data_serde::chip::memory::{self, Settings}; use stm32_data_serde::chip::Memory; +use crate::util::RegexMap; + struct Mem { name: &'static str, address: u32, @@ -121,7 +122,9 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[ ("STM32G0...4", mem!(BANK_1 0x08000000 16, SRAM 0x20000000 8)), ("STM32G0...C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 128)), ("STM32G0...E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM 0x20000000 128)), - ("STM32G0[34]..[68]", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)), + ("STM32G0[34]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)), + ("STM32G0(3..6|4.J6)", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 8)), + ("STM32G04..6", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 8)), ("STM32G0[56]..6", mem!(BANK_1 0x08000000 32, SRAM 0x20000000 16)), ("STM32G0[56]..8", mem!(BANK_1 0x08000000 64, SRAM 0x20000000 16)), ("STM32G0[78]..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 32)), @@ -137,10 +140,14 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[ ("STM32G47..B", mem!(BANK_1 0x08000000 128, SRAM 0x20000000 96, SRAM2 0x20014000 0)), ("STM32G47..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 96, SRAM2 0x20014000 0)), ("STM32G49..C", mem!(BANK_1 0x08000000 256, SRAM 0x20000000 32, SRAM2 0x20014000 0)), - // H5. TODO: check - ("STM32H5...B", mem!(BANK_1 0x08000000 64, BANK_2 0x08010000 64, SRAM 0x20000000 32, SRAM2 0x20004000 0)), - ("STM32H5...G", mem!(BANK_1 0x08000000 1024, SRAM 0x20000000 256, SRAM2 0x20040000 0)), - ("STM32H5...I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 256, SRAM2 0x20040000 0)), + // H5. + ("STM32H5...B", mem!(BANK_1 0x08000000 64, BANK_2 0x08010000 64, SRAM1 0x20000000 16, SRAM2 0x20004000 16)), + ("STM32H5...C", mem!(BANK_1 0x08000000 128, BANK_2 0x08020000 128, SRAM1 0x20000000 128, SRAM2 0x20020000 80, SRAM3 0x20034000 64)), + ("STM32H5...E", mem!(BANK_1 0x08000000 256, BANK_2 0x08040000 256, SRAM1 0x20000000 128, SRAM2 0x20020000 80, SRAM3 0x20034000 64)), + ("STM32H5...G", mem!(BANK_1 0x08000000 512, BANK_2 0x08080000 512, SRAM1 0x20000000 256, SRAM2 0x20040000 64, SRAM3 0x20050000 320)), + ("STM32H5...I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM1 0x20000000 256, SRAM2 0x20040000 64, SRAM3 0x20050000 320)), + // H7RS + ("STM32H7[RS].*", mem!(BANK_1 0x08000000 64, ITCM 0x00000000 192, DTCM 0x20000000 192, SRAM1 0x24000000 128, SRAM2 0x24020000 128, SRAM3 0x24040000 128, SRAM4 0x24060000 72, AHB_SRAM1 0x30000000 16, AHB_SRAM2 0x30004000 16)), // H7. TODO: check ("STM32H7...E", mem!(BANK_1 0x08000000 512, SRAM 0x24000000 128)), ("STM32H7[23]..G", mem!(BANK_1 0x08000000 1024, SRAM 0x24000000 128)), @@ -213,6 +220,7 @@ static MEMS: RegexMap<&[Mem]> = RegexMap::new(&[ ("STM32U5[78]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 192, SRAM2 0x20030000 64, SRAM3 0x20040000 512)), ("STM32U5[9A]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08100000 1024, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832)), ("STM32U5[9A]..J", mem!(BANK_1 0x08000000 2048, BANK_2 0x08200000 2048, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832)), + ("STM32U5[FG]..I", mem!(BANK_1 0x08000000 1024, BANK_2 0x08200000 1024, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832, SRAM6 0x20270000 512)), ("STM32U5[FG]..J", mem!(BANK_1 0x08000000 2048, BANK_2 0x08200000 2048, SRAM 0x20000000 768, SRAM2 0x200c0000 64, SRAM3 0x200d0000 832, SRAM5 0x201a0000 832, SRAM6 0x20270000 512)), // WB. TODO: check ("STM32WB...Y", mem!(BANK_1 0x08000000 640, SRAM 0x20000000 192)), @@ -240,6 +248,7 @@ struct FlashInfo { } #[rustfmt::skip] +#[allow(clippy::identity_op)] static FLASH_INFO: RegexMap = RegexMap::new(&[ ("STM32C0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }), ("STM32F030.C", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 2*1024, 0)] }), @@ -257,6 +266,7 @@ static FLASH_INFO: RegexMap = RegexMap::new(&[ ("STM32G4[78].*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 4*1024, 0)] }), ("STM32G4.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }), ("STM32H5.*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }), + ("STM32H7[RS].*", FlashInfo{ erase_value: 0xFF, write_size: 16, erase_size: &[( 8*1024, 0)] }), ("STM32H7[AB].*", FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[( 8*1024, 0)] }), ("STM32H7.*", FlashInfo{ erase_value: 0xFF, write_size: 32, erase_size: &[(128*1024, 0)] }), ("STM32L4[PQRS].*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 8*1024, 0)] }), @@ -274,28 +284,9 @@ static FLASH_INFO: RegexMap = RegexMap::new(&[ ("STM32.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }), ]); -struct RegexMap { - map: &'static [(&'static str, T)], -} - -impl RegexMap { - const fn new(map: &'static [(&'static str, T)]) -> Self { - Self { map } - } - - fn get(&self, key: &str) -> Option<&T> { - for (k, v) in self.map { - if Regex::new(&format!("^{k}$")).unwrap().is_match(key) { - return Some(v); - } - } - None - } -} - pub fn get(chip: &str) -> Vec { - let mems = *MEMS.get(chip).unwrap(); - let flash = FLASH_INFO.get(chip).unwrap(); + let mems = *MEMS.must_get(chip); + let flash = FLASH_INFO.must_get(chip); let mut res = Vec::new(); @@ -324,6 +315,7 @@ pub fn get(chip: &str) -> Vec { if i != flash.erase_size.len() - 1 { size = size.min(erase_size * count); } + #[allow(clippy::redundant_field_names)] res.push(Memory { name: format!("{}_REGION_{}", mem.name, i + 1), address: mem.address + offs, diff --git a/stm32-data-gen/src/normalize_peris.rs b/stm32-data-gen/src/normalize_peris.rs new file mode 100644 index 0000000..a11ba05 --- /dev/null +++ b/stm32-data-gen/src/normalize_peris.rs @@ -0,0 +1,17 @@ +#[rustfmt::skip] +static NORMALIZE: &[(&str, &str)] = &[ + ("ADC", "ADC1"), + ("DAC", "DAC1"), + ("HRTIM", "HRTIM1"), + ("HDMI_CEC", "CEC"), + ("SUBGHZ", "SUBGHZSPI"), + ("USB_DRD_FS", "USB"), + ("SBS", "SYSCFG"), +]; + +pub fn normalize_peri_name(name: &str) -> &str { + if let Some((_, res)) = NORMALIZE.iter().find(|(n, _)| *n == name) { + return res; + } + return name; +} diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index b5846ac..e0c4ebf 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -85,13 +85,19 @@ impl ParsedRccs { "PLL1_P_MUL_2", "PLL1_Q", "PLL1_R", + "PLL1_S", + "PLL1_T", "PLL1_VCO", // used for L0 USB "PLL2_P", "PLL2_Q", "PLL2_R", + "PLL2_S", + "PLL2_T", "PLL3_P", "PLL3_Q", "PLL3_R", + "PLL3_S", + "PLL3_T", "HSI", "SHSI", "HSI48", @@ -106,10 +112,10 @@ impl ParsedRccs { "AUDIOCLK", "PER", "CLK48", + "DSI_PHY", // TODO: variants to cleanup "AFIF", "HSI_HSE", - "DSI_PHY", "HSI_Div488", "SAI1_EXTCLK", "SAI2_EXTCLK", @@ -120,7 +126,6 @@ impl ParsedRccs { "DAC_HOLD_2", "RTCCLK", "RTC_WKUP", - "DSIPHY", "ICLK", "DCLK", "I2S1", @@ -131,6 +136,10 @@ impl ParsedRccs { "HSI256_MSIS1024_MSIK4", "HSI256_MSIK1024_MSIS4", "HSI256_MSIK1024_MSIK4", + "SPDIFRX_SYMB", + "ETH_RMII_REF", + "ETH", + "CLK48MOHCI", ]); let mux_regexes = &[ @@ -138,13 +147,19 @@ impl ParsedRccs { regex!(r"^CCIPR\d?/(.+)SEL$"), regex!(r"^D\dCCIP\d?R/(.+)SEL$"), regex!(r"^CFGR\d/(.+)SW$"), + regex!(r"^.+PERCKSELR/(.+)SEL$"), ]; + let mux_nopelist = &[regex!(r"^.+PERCKSELR/USBREFCKSEL$")]; let mut mux = HashMap::new(); for (reg, body) in &ir.fieldsets { for field in &body.fields { let key = format!("{}/{}", reg, field.name); if let Some(capture) = mux_regexes.iter().find_map(|r| r.captures(&key)) { + if mux_nopelist.iter().any(|r| r.is_match(&key)) { + continue; + } + let peri = capture.get(1).unwrap().as_str(); // TODO: these bits are duplicated on F4, we need to split the F4 RCCs more. @@ -264,6 +279,7 @@ impl ParsedRccs { ("DAC", &["DAC1", "ADCDAC"]), ("DAC1", &["DAC12", "ADCDAC"]), ("DAC2", &["DAC12", "ADCDAC"]), + ("DSIHOST", &["DSI"]), ("ETH", &["ETHMAC", "ETH1MAC"]), ("SPI1", &["SPI12", "SPI123"]), ("SPI2", &["SPI12", "SPI123"]), @@ -283,7 +299,7 @@ impl ParsedRccs { ("USART6", &["USART16910"]), ("USART10", &["USART16910"]), ("UART9", &["USART16910"]), - ("I2C1", &["I2C1235"]), + ("I2C1", &["I2C1235", "I2C1_I3C1"]), ("I2C2", &["I2C1235"]), ("I2C3", &["I2C1235"]), ("I2C5", &["I2C1235"]), @@ -331,6 +347,8 @@ impl ParsedRccs { maybe_kernel_clock = "PLL1_Q".to_string(); } else if rcc_version.starts_with("l1") { maybe_kernel_clock = "PLL1_VCO_DIV_2".to_string(); + } else if rcc_version.starts_with("h7rs") { + maybe_kernel_clock = "USB".to_string(); } else { panic!("rcc_{}: peripheral {} missing mux", rcc_version, peri_name) } diff --git a/stm32-data-gen/src/util.rs b/stm32-data-gen/src/util.rs new file mode 100644 index 0000000..37eefb8 --- /dev/null +++ b/stm32-data-gen/src/util.rs @@ -0,0 +1,28 @@ +use regex::Regex; + +pub struct RegexMap { + map: &'static [(&'static str, T)], +} + +impl RegexMap { + pub const fn new(map: &'static [(&'static str, T)]) -> Self { + Self { map } + } + + pub fn get(&self, key: &str) -> Option<&T> { + for (k, v) in self.map { + if Regex::new(&format!("^{k}$")).unwrap().is_match(key) { + return Some(v); + } + } + None + } + + #[track_caller] + pub fn must_get(&self, key: &str) -> &T { + let Some(res) = self.get(key) else { + panic!("no regexmap for key '{key}'") + }; + res + } +} diff --git a/stm32-metapac-gen/src/lib.rs b/stm32-metapac-gen/src/lib.rs index 3e2ea6f..cc1feed 100644 --- a/stm32-metapac-gen/src/lib.rs +++ b/stm32-metapac-gen/src/lib.rs @@ -415,48 +415,55 @@ fn gen_opts() -> generate::Options { fn gen_memory_x(out_dir: &Path, chip: &Chip) { let mut memory_x = String::new(); - let flash = chip - .memory - .iter() - .filter(|r| r.kind == MemoryRegionKind::Flash && r.name.starts_with("BANK_")); - let (flash_address, flash_size) = flash - .clone() - .map(|r| (r.address, r.size)) - .reduce(|acc, el| (u32::min(acc.0, el.0), acc.1 + el.1)) - .unwrap(); - let ram = chip.memory.iter().find(|r| r.kind == MemoryRegionKind::Ram).unwrap(); - let otp = chip - .memory - .iter() - .find(|r| r.kind == MemoryRegionKind::Flash && r.name == "OTP"); + let flash = get_memory_range(chip, MemoryRegionKind::Flash); + let ram = get_memory_range(chip, MemoryRegionKind::Ram); write!(memory_x, "MEMORY\n{{\n").unwrap(); writeln!( memory_x, " FLASH : ORIGIN = 0x{:08x}, LENGTH = {:>4}K /* {} */", - flash_address, - flash_size / 1024, - flash.map(|x| x.name.as_ref()).collect::>().join(" + ") + flash.0, + flash.1 / 1024, + flash.2 ) .unwrap(); writeln!( memory_x, - " RAM : ORIGIN = 0x{:08x}, LENGTH = {:>4}K", - ram.address, - ram.size / 1024, + " RAM : ORIGIN = 0x{:08x}, LENGTH = {:>4}K /* {} */", + ram.0, + ram.1 / 1024, + ram.2 ) .unwrap(); - if let Some(otp) = otp { - writeln!( - memory_x, - " OTP : ORIGIN = 0x{:08x}, LENGTH = {:>4}", - otp.address, otp.size, - ) - .unwrap(); - } write!(memory_x, "}}").unwrap(); fs::create_dir_all(out_dir.join("memory_x")).unwrap(); let mut file = File::create(out_dir.join("memory_x").join("memory.x")).unwrap(); file.write_all(memory_x.as_bytes()).unwrap(); } + +fn get_memory_range(chip: &Chip, kind: MemoryRegionKind) -> (u32, u32, String) { + let mut mems: Vec<_> = chip.memory.iter().filter(|m| m.kind == kind && m.size != 0).collect(); + mems.sort_by_key(|m| m.address); + + let mut start = u32::MAX; + let mut end = u32::MAX; + let mut names = Vec::new(); + let mut best: Option<(u32, u32, String)> = None; + for m in mems { + if m.address != end { + names = Vec::new(); + start = m.address; + end = m.address; + } + + end += m.size; + names.push(m.name.to_string()); + + if best.is_none() || end - start > best.as_ref().unwrap().1 { + best = Some((start, end - start, names.join(" + "))); + } + } + + best.unwrap() +} diff --git a/transforms/LPTIM_v2b.yaml b/transforms/LPTIM_v2.yaml similarity index 100% rename from transforms/LPTIM_v2b.yaml rename to transforms/LPTIM_v2.yaml diff --git a/transforms/LPTIM_v2a.yaml b/transforms/LPTIM_v2a.yaml deleted file mode 100644 index 7a53546..0000000 --- a/transforms/LPTIM_v2a.yaml +++ /dev/null @@ -1,8 +0,0 @@ -transforms: - - - !Rename - from: ^LPTIM1$ - to: LPTIM - - - !DeleteFieldsets - from: OR