rcc: more mux and enum cleanup

data/registers/rcc_c0.yaml

@@ -685,7 +685,7 @@ fieldset/ICSCR:
 enum/ADCSEL:
   bit_size: 2
   variants:
-  - name: SYSCLK
+  - name: SYS
     description: System clock
     value: 0
   - name: HSIKER
@@ -778,10 +778,10 @@ enum/HSIKERDIV:
 enum/I2C1SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK
     value: 1
   - name: HSIKER
@@ -790,7 +790,7 @@ enum/I2C1SEL:
 enum/I2S1SEL:
   bit_size: 2
   variants:
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK
     value: 0
   - name: HSIKER
@@ -853,10 +853,10 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock, MCO output disabled
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK selected as MCO source
     value: 1
   - name: HSI48
@@ -892,7 +892,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock used as RTC clock
     value: 0
   - name: LSE
@@ -949,10 +949,10 @@ enum/SYSDIV:
 enum/USART1SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK
     value: 1
   - name: HSIKER

data/registers/rcc_f0.yaml

@@ -799,7 +799,7 @@ enum/ICSW:
   - name: HSI
     description: HSI clock selected as I2C clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK clock selected as I2C clock source
     value: 1
 enum/LSEDRV:
@@ -859,7 +859,7 @@ enum/MCOSEL:
   - name: LSE
     description: External low speed (LSE) oscillator clock selected
     value: 3
-  - name: SYSCLK
+  - name: SYS
     description: System clock selected
     value: 4
   - name: HSI
@@ -1027,7 +1027,7 @@ enum/PREDIV:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE
@@ -1057,10 +1057,10 @@ enum/SW:
 enum/USARTSW:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK selected as USART clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK selected as USART clock source
     value: 1
   - name: LSE

data/registers/rcc_f1.yaml

@@ -801,7 +801,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_f100.yaml

@@ -823,7 +823,7 @@ enum/PREDIV1:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_f1cl.yaml

@@ -913,7 +913,7 @@ enum/PREDIV1SRC:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_f2.yaml

@@ -1950,7 +1950,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_f3.yaml

@@ -938,13 +938,13 @@ enum/ICSW:
   - name: HSI
     description: HSI clock selected as I2C clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK clock selected as I2C clock source
     value: 1
 enum/ISSRC:
   bit_size: 1
   variants:
-  - name: SYSCLK
+  - name: SYS
     description: System clock used as I2S clock source
     value: 0
   - name: CKIN
@@ -1004,7 +1004,7 @@ enum/MCOSEL:
   - name: LSE
     description: External low speed (LSE) oscillator clock selected
     value: 3
-  - name: SYSCLK
+  - name: SYS
     description: System clock selected
     value: 4
   - name: HSI
@@ -1166,7 +1166,7 @@ enum/PREDIV:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE
@@ -1244,7 +1244,7 @@ enum/SW:
 enum/TIMSW:
   bit_size: 1
   variants:
-  - name: PCLK2
+  - name: APB2
     description: PCLK2 clock (doubled frequency when prescaled)
     value: 0
   - name: PLL
@@ -1253,10 +1253,10 @@ enum/TIMSW:
 enum/USARTSW:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK selected as USART clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK selected as USART clock source
     value: 1
   - name: LSE

data/registers/rcc_f3_v2.yaml

@@ -914,13 +914,13 @@ enum/ICSW:
   - name: HSI
     description: HSI clock selected as I2C clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK clock selected as I2C clock source
     value: 1
 enum/ISSRC:
   bit_size: 1
   variants:
-  - name: SYSCLK
+  - name: SYS
     description: System clock used as I2S clock source
     value: 0
   - name: CKIN
@@ -971,7 +971,7 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 3
   variants:
-  - name: NoMCO
+  - name: DISABLE
     description: MCO output disabled, no clock on MCO
     value: 0
   - name: LSI
@@ -980,7 +980,7 @@ enum/MCOSEL:
   - name: LSE
     description: External low speed (LSE) oscillator clock selected
     value: 3
-  - name: SYSCLK
+  - name: SYS
     description: System clock selected
     value: 4
   - name: HSI
@@ -1142,7 +1142,7 @@ enum/PREDIV:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE
@@ -1220,7 +1220,7 @@ enum/SW:
 enum/TIMSW:
   bit_size: 1
   variants:
-  - name: PCLK2
+  - name: APB2
     description: PCLK2 clock (doubled frequency when prescaled)
     value: 0
   - name: PLL
@@ -1229,10 +1229,10 @@ enum/TIMSW:
 enum/USARTSW:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK selected as USART clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK selected as USART clock source
     value: 1
   - name: LSE

data/registers/rcc_f4.yaml

@@ -3365,7 +3365,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_f410.yaml

@@ -1896,7 +1896,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_f7.yaml

@@ -3090,7 +3090,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_g0.yaml

@@ -1179,13 +1179,13 @@ fieldset/PLLCFGR:
 enum/ADCSEL:
   bit_size: 2
   variants:
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as ADC clock source
     value: 0
   - name: PLLPCLK
     description: PLLPCLK used as ADC clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as ADC clock source
     value: 2
 enum/CECSEL:
@@ -1200,7 +1200,7 @@ enum/CECSEL:
 enum/FDCANSEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as FDCAN clock source
     value: 0
   - name: PLLQCLK
@@ -1269,25 +1269,25 @@ enum/HSIDIV:
 enum/I2C1SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as I2C1 clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as I2C1 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as I2C1 clock source
     value: 2
 enum/I2C2I2S1SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as I2C2/I2S2 clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as I2C2/I2S2 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as I2C2/I2S2 clock source
     value: 2
   - name: I2S_CKIN
@@ -1296,13 +1296,13 @@ enum/I2C2I2S1SEL:
 enum/I2S1SEL:
   bit_size: 2
   variants:
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as I2S1 clock source
     value: 0
   - name: PLLPCLK
     description: PLLPCLK used as I2S1 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI used as I2S1 clock source
     value: 2
   - name: I2S_CKIN
@@ -1311,13 +1311,13 @@ enum/I2S1SEL:
 enum/I2S2SEL:
   bit_size: 2
   variants:
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as I2S2 clock source
     value: 0
   - name: PLLPCLK
     description: PLLPCLK used as I2S2 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI used as I2S2 clock source
     value: 2
   - name: I2S_CKIN
@@ -1326,13 +1326,13 @@ enum/I2S2SEL:
 enum/LPTIM1SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as LPTIM1 clock source
     value: 0
   - name: LSI
     description: LSI used as LPTIM1 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as LPTIM1 clock source
     value: 2
   - name: LSE
@@ -1341,13 +1341,13 @@ enum/LPTIM1SEL:
 enum/LPTIM2SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as LPTIM2 clock source
     value: 0
   - name: LSI
     description: LSI used as LPTIM2 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as LPTIM2 clock source
     value: 2
   - name: LSE
@@ -1356,13 +1356,13 @@ enum/LPTIM2SEL:
 enum/LPUART1SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as LPUART1 clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as LPUART1 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as LPUART1 clock source
     value: 2
   - name: LSE
@@ -1371,13 +1371,13 @@ enum/LPUART1SEL:
 enum/LPUART2SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as LPUART2 clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as LPUART2 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as LPUART2 clock source
     value: 2
   - name: LSE
@@ -1437,16 +1437,16 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock, MCO output disabled
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK selected as MCO source
     value: 1
   - name: HSI48
     description: HSI48 selected as MCO source
     value: 2
-  - name: HSI16
+  - name: HSI
     description: HSI16 selected as MCO source
     value: 3
   - name: HSE
@@ -1755,10 +1755,10 @@ enum/PLLR:
 enum/PLLSRC:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected as PLL entry clock source
     value: 0
-  - name: HSI16
+  - name: HSI
     description: HSI16 selected as PLL entry clock source
     value: 2
   - name: HSE
@@ -1800,13 +1800,13 @@ enum/RNGDIV:
 enum/RNGSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock used as RNG clock source
     value: 0
   - name: HSI16_Div8
     description: HSI divided by 8 used as RNG clock source
     value: 1
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as RNG clock source
     value: 2
   - name: PLLQCLK
@@ -1815,7 +1815,7 @@ enum/RNGSEL:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock used as RTC clock
     value: 0
   - name: LSE
@@ -1866,13 +1866,13 @@ enum/TIM1SEL:
 enum/USART1SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as USART1 clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as USART1 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as USART1 clock source
     value: 2
   - name: LSE
@@ -1881,13 +1881,13 @@ enum/USART1SEL:
 enum/USART2SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as USART2 clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as USART2 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as USART2 clock source
     value: 2
   - name: LSE
@@ -1896,13 +1896,13 @@ enum/USART2SEL:
 enum/USART3SEL:
   bit_size: 2
   variants:
-  - name: PCLK
+  - name: APB1
     description: PCLK used as USART3 clock source
     value: 0
-  - name: SYSCLK
+  - name: SYS
     description: SYSCLK used as USART3 clock source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 used as USART3 clock source
     value: 2
   - name: LSE

data/registers/rcc_g4.yaml

@@ -1427,13 +1427,13 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock, MCO output disabled
     value: 0
   - name: SYS
     description: SYSCLK selected as MCO source
     value: 1
-  - name: HSI16
+  - name: HSI
     description: HSI16 selected as MCO source
     value: 3
   - name: HSE
@@ -1824,10 +1824,10 @@ enum/PLLR:
 enum/PLLSRC:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected as PLL entry clock source
     value: 0
-  - name: HSI16
+  - name: HSI
     description: HSI16 selected as PLL entry clock source
     value: 2
   - name: HSE
@@ -1854,7 +1854,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock used as RTC clock
     value: 0
   - name: LSE
@@ -1869,7 +1869,7 @@ enum/RTCSEL:
 enum/SW:
   bit_size: 2
   variants:
-  - name: HSI16
+  - name: HSI
     description: HSI16 selected as system clock
     value: 1
   - name: HSE

data/registers/rcc_h5.yaml

@@ -2125,7 +2125,7 @@ fieldset/SECCFGR:
 enum/ADCDACSEL:
   bit_size: 3
   variants:
-  - name: HCLK
+  - name: AHB1
     description: rcc_hclk selected as kernel clock (default after reset)
     value: 0
   - name: SYS
@@ -3925,7 +3925,7 @@ enum/RNGSEL:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: no clock (default after Backup domain reset)
     value: 0
   - name: LSE
@@ -4132,7 +4132,7 @@ enum/SW:
 enum/SYSTICKSEL:
   bit_size: 2
   variants:
-  - name: HCLK_DIV_8
+  - name: AHB1_DIV_8
     description: rcc_hclk/8 selected as clock source (default after reset)
     value: 0
   - name: LSI

data/registers/rcc_h50.yaml

@@ -1335,7 +1335,7 @@ fieldset/RSR:
 enum/ADCDACSEL:
   bit_size: 3
   variants:
-  - name: HCLK
+  - name: AHB1
     description: rcc_hclk selected as kernel clock (default after reset)
     value: 0
   - name: SYS
@@ -3093,7 +3093,7 @@ enum/RNGSEL:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: no clock (default after Backup domain reset)
     value: 0
   - name: LSE

data/registers/rcc_h7.yaml

@@ -5299,7 +5299,7 @@ enum/RNGSEL:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_h7ab.yaml

@@ -4234,7 +4234,7 @@ enum/RNGSEL:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_h7rm0433.yaml

@@ -5299,7 +5299,7 @@ enum/RNGSEL:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_l0.yaml

@@ -1030,7 +1030,7 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: SYSCLK
@@ -1168,7 +1168,7 @@ enum/RTCPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_l0_v2.yaml

@@ -1069,7 +1069,7 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: SYSCLK
@@ -1207,7 +1207,7 @@ enum/RTCPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_l1.yaml

@@ -883,7 +883,7 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: SYSCLK
@@ -1021,7 +1021,7 @@ enum/RTCPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_l4.yaml

@@ -1742,7 +1742,7 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: SYSCLK
@@ -2214,7 +2214,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_l5.yaml

@@ -2514,7 +2514,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: LSE

data/registers/rcc_u5.yaml

@@ -4290,7 +4290,7 @@ enum/RNGSEL:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected
     value: 0
   - name: LSE

data/registers/rcc_wb.yaml

@@ -1745,7 +1745,7 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: SYSCLK
@@ -2140,7 +2140,7 @@ enum/PLLR:
 enum/PLLSRC:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected as PLL entry clock source
     value: 0
   - name: MSI
@@ -2173,7 +2173,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected
     value: 0
   - name: LSE

data/registers/rcc_wba.yaml

@@ -1498,7 +1498,7 @@ enum/RNGSEL:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: no clock selected, RTC and TAMP kernel clock disabled
     value: 0
   - name: LSE

data/registers/rcc_wl5.yaml

@@ -1533,7 +1533,7 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: SYSCLK
@@ -1964,7 +1964,7 @@ enum/PLLR:
 enum/PLLSRC:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected as PLL entry clock source
     value: 0
   - name: MSI
@@ -1997,7 +1997,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected
     value: 0
   - name: LSE

data/registers/rcc_wle.yaml

@@ -1154,7 +1154,7 @@ enum/MCOPRE:
 enum/MCOSEL:
   bit_size: 4
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock
     value: 0
   - name: SYSCLK
@@ -1585,7 +1585,7 @@ enum/PLLR:
 enum/PLLSRC:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected as PLL entry clock source
     value: 0
   - name: MSI
@@ -1618,7 +1618,7 @@ enum/PPRE:
 enum/RTCSEL:
   bit_size: 2
   variants:
-  - name: NoClock
+  - name: DISABLE
     description: No clock selected
     value: 0
   - name: LSE

stm32-data-gen/src/rcc.rs

@@ -18,8 +18,17 @@ impl PeripheralToClock {
 
         for (rcc_name, ir) in &registers.registers {
             if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") {
-                let checked_rccs = HashSet::from(["h5", "h50", "h7", "h7ab", "h7rm0433", "g4"]);
+                let checked_rccs = HashSet::from([
+                    "c0", "f0", "f1", "f100", "f1c1", "f3", "f3_v2", "f4", "f410", "f7", "g0", "g4", "h5", "h50", "h7",
+                    "h7ab", "h7rm0433",
+                ]);
                 let prohibited_variants = HashSet::from([
+                    "APB",
+                    "AHB",
+                    "PCLK",
+                    "PCLK2",
+                    "PCLK3",
+                    "PCLK4",
                     "RCC_PCLK1",
                     "RCC_PCLK2",
                     "RCC_PCLK3",
@@ -29,16 +38,23 @@ impl PeripheralToClock {
                     "CSI_KER",
                     "LSI_KER",
                     "PER_CLK",
+                    "HCLK",
+                    "HCLK2",
+                    "HCLK3",
+                    "HCLK4",
                     "RCC_HCLK1",
                     "RCC_HCLK2",
                     "RCC_HCLK3",
                     "RCC_HCLK4",
                     "PLL3_1",
                     "NOCLK",
+                    "NoMCO",
+                    "NoClock",
                     "PLLP",
                     "PLLQ",
                     "PLLR",
                     "SYSCLK",
+                    "HSI16",
                 ]);
 
                 let rcc_enum_map: HashMap<&String, HashMap<&String, &Enum>> = {