diff --git a/data/registers/adc_f3_v1_1.yaml b/data/registers/adc_f3_v1_1.yaml index 9f373e6..d961aed 100644 --- a/data/registers/adc_f3_v1_1.yaml +++ b/data/registers/adc_f3_v1_1.yaml @@ -1,685 +1,685 @@ block/ADC: description: Analog-to-digital converter items: - - name: SR - description: status register - byte_offset: 0 - fieldset: SR - - name: CR1 - description: control register 1 - byte_offset: 4 - fieldset: CR1 - - name: CR2 - description: control register 2 - byte_offset: 8 - fieldset: CR2 - - name: SMPR1 - description: sample time register 1 - byte_offset: 12 - fieldset: SMPR1 - - name: SMPR2 - description: sample time register 2 - byte_offset: 16 - fieldset: SMPR2 - - name: SMPR3 - description: sample time register 3 - byte_offset: 20 - fieldset: SMPR3 - - name: JOFR1 - description: injected channel data offset register 1 - byte_offset: 24 - fieldset: JOFR1 - - name: JOFR2 - description: injected channel data offset register 2 - byte_offset: 28 - fieldset: JOFR2 - - name: JOFR3 - description: injected channel data offset register 3 - byte_offset: 32 - fieldset: JOFR3 - - name: JOFR4 - description: injected channel data offset register 4 - byte_offset: 36 - fieldset: JOFR4 - - name: HTR - description: watchdog higher threshold register - byte_offset: 40 - fieldset: HTR - - name: LTR - description: watchdog lower threshold register - byte_offset: 44 - fieldset: LTR - - name: SQR1 - description: regular sequence register 1 - byte_offset: 48 - fieldset: SQR1 - - name: SQR2 - description: regular sequence register 2 - byte_offset: 52 - fieldset: SQR2 - - name: SQR3 - description: regular sequence register 3 - byte_offset: 56 - fieldset: SQR3 - - name: SQR4 - description: regular sequence register 4 - byte_offset: 60 - fieldset: SQR4 - - name: SQR5 - description: regular sequence register 5 - byte_offset: 64 - fieldset: SQR5 - - name: JSQR - description: injected sequence register - byte_offset: 68 - fieldset: JSQR - - name: JDR1 - description: injected data register x1 - byte_offset: 72 - access: Read - fieldset: JDR1 - - name: JDR2 - description: injected data register 2 - byte_offset: 76 - access: Read - fieldset: JDR2 - - name: JDR3 - description: injected data register 3 - byte_offset: 80 - access: Read - fieldset: JDR3 - - name: JDR4 - description: injected data register 4 - byte_offset: 84 - access: Read - fieldset: JDR4 - - name: DR - description: regular data register - byte_offset: 88 - access: Read - fieldset: DR - - name: SMPR0 - description: sample time register 0 - byte_offset: 92 - fieldset: SMPR0 - - name: CSR - description: ADC common status register - byte_offset: 768 - access: Read - fieldset: CSR - - name: CCR - description: ADC common control register - byte_offset: 772 - fieldset: CCR + - name: SR + description: status register + byte_offset: 0 + fieldset: SR + - name: CR1 + description: control register 1 + byte_offset: 4 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 8 + fieldset: CR2 + - name: SMPR1 + description: sample time register 1 + byte_offset: 12 + fieldset: SMPR1 + - name: SMPR2 + description: sample time register 2 + byte_offset: 16 + fieldset: SMPR2 + - name: SMPR3 + description: sample time register 3 + byte_offset: 20 + fieldset: SMPR3 + - name: JOFR1 + description: injected channel data offset register 1 + byte_offset: 24 + fieldset: JOFR1 + - name: JOFR2 + description: injected channel data offset register 2 + byte_offset: 28 + fieldset: JOFR2 + - name: JOFR3 + description: injected channel data offset register 3 + byte_offset: 32 + fieldset: JOFR3 + - name: JOFR4 + description: injected channel data offset register 4 + byte_offset: 36 + fieldset: JOFR4 + - name: HTR + description: watchdog higher threshold register + byte_offset: 40 + fieldset: HTR + - name: LTR + description: watchdog lower threshold register + byte_offset: 44 + fieldset: LTR + - name: SQR1 + description: regular sequence register 1 + byte_offset: 48 + fieldset: SQR1 + - name: SQR2 + description: regular sequence register 2 + byte_offset: 52 + fieldset: SQR2 + - name: SQR3 + description: regular sequence register 3 + byte_offset: 56 + fieldset: SQR3 + - name: SQR4 + description: regular sequence register 4 + byte_offset: 60 + fieldset: SQR4 + - name: SQR5 + description: regular sequence register 5 + byte_offset: 64 + fieldset: SQR5 + - name: JSQR + description: injected sequence register + byte_offset: 68 + fieldset: JSQR + - name: JDR1 + description: injected data register x1 + byte_offset: 72 + access: Read + fieldset: JDR1 + - name: JDR2 + description: injected data register 2 + byte_offset: 76 + access: Read + fieldset: JDR2 + - name: JDR3 + description: injected data register 3 + byte_offset: 80 + access: Read + fieldset: JDR3 + - name: JDR4 + description: injected data register 4 + byte_offset: 84 + access: Read + fieldset: JDR4 + - name: DR + description: regular data register + byte_offset: 88 + access: Read + fieldset: DR + - name: SMPR0 + description: sample time register 0 + byte_offset: 92 + fieldset: SMPR0 + - name: CSR + description: ADC common status register + byte_offset: 768 + access: Read + fieldset: CSR + - name: CCR + description: ADC common control register + byte_offset: 772 + fieldset: CCR fieldset/CCR: description: ADC common control register fields: - - name: ADCPRE - description: ADC prescaler - bit_offset: 16 - bit_size: 2 - - name: TSVREFE - description: Temperature sensor and VREFINT enable - bit_offset: 23 - bit_size: 1 + - name: ADCPRE + description: ADC prescaler + bit_offset: 16 + bit_size: 2 + - name: TSVREFE + description: Temperature sensor and VREFINT enable + bit_offset: 23 + bit_size: 1 fieldset/CR1: description: control register 1 fields: - - name: AWDCH - description: Analog watchdog channel select bits - bit_offset: 0 - bit_size: 5 - - name: EOCIE - description: Interrupt enable for EOC - bit_offset: 5 - bit_size: 1 - - name: AWDIE - description: Analog watchdog interrupt enable - bit_offset: 6 - bit_size: 1 - - name: JEOCIE - description: Interrupt enable for injected channels - bit_offset: 7 - bit_size: 1 - - name: SCAN - description: Scan mode - bit_offset: 8 - bit_size: 1 - - name: AWDSGL - description: Enable the watchdog on a single channel in scan mode - bit_offset: 9 - bit_size: 1 - - name: JAUTO - description: Automatic injected group conversion - bit_offset: 10 - bit_size: 1 - - name: DISCEN - description: Discontinuous mode on regular channels - bit_offset: 11 - bit_size: 1 - - name: JDISCEN - description: Discontinuous mode on injected channels - bit_offset: 12 - bit_size: 1 - - name: DISCNUM - description: Discontinuous mode channel count - bit_offset: 13 - bit_size: 3 - enum: DISCNUM - - name: PDD - description: Power down during the delay phase - bit_offset: 16 - bit_size: 1 - - name: PDI - description: Power down during the idle phase - bit_offset: 17 - bit_size: 1 - - name: JAWDEN - description: Analog watchdog enable on injected channels - bit_offset: 22 - bit_size: 1 - - name: AWDEN - description: Analog watchdog enable on regular channels - bit_offset: 23 - bit_size: 1 - - name: RES - description: Resolution - bit_offset: 24 - bit_size: 2 - enum: RES - - name: OVRIE - description: Overrun interrupt enable - bit_offset: 26 - bit_size: 1 + - name: AWDCH + description: Analog watchdog channel select bits + bit_offset: 0 + bit_size: 5 + - name: EOCIE + description: Interrupt enable for EOC + bit_offset: 5 + bit_size: 1 + - name: AWDIE + description: Analog watchdog interrupt enable + bit_offset: 6 + bit_size: 1 + - name: JEOCIE + description: Interrupt enable for injected channels + bit_offset: 7 + bit_size: 1 + - name: SCAN + description: Scan mode + bit_offset: 8 + bit_size: 1 + - name: AWDSGL + description: Enable the watchdog on a single channel in scan mode + bit_offset: 9 + bit_size: 1 + - name: JAUTO + description: Automatic injected group conversion + bit_offset: 10 + bit_size: 1 + - name: DISCEN + description: Discontinuous mode on regular channels + bit_offset: 11 + bit_size: 1 + - name: JDISCEN + description: Discontinuous mode on injected channels + bit_offset: 12 + bit_size: 1 + - name: DISCNUM + description: Discontinuous mode channel count + bit_offset: 13 + bit_size: 3 + enum: DISCNUM + - name: PDD + description: Power down during the delay phase + bit_offset: 16 + bit_size: 1 + - name: PDI + description: Power down during the idle phase + bit_offset: 17 + bit_size: 1 + - name: JAWDEN + description: Analog watchdog enable on injected channels + bit_offset: 22 + bit_size: 1 + - name: AWDEN + description: Analog watchdog enable on regular channels + bit_offset: 23 + bit_size: 1 + - name: RES + description: Resolution + bit_offset: 24 + bit_size: 2 + enum: RES + - name: OVRIE + description: Overrun interrupt enable + bit_offset: 26 + bit_size: 1 fieldset/CR2: description: control register 2 fields: - - name: ADON - description: A/D Converter ON / OFF - bit_offset: 0 - bit_size: 1 - - name: CONT - description: Continuous conversion - bit_offset: 1 - bit_size: 1 - - name: ADC_CFG - description: ADC configuration - bit_offset: 2 - bit_size: 1 - enum: ADC_CFG - - name: DELS - description: Delay selection - bit_offset: 4 - bit_size: 3 - enum: DELS - - name: DMA - description: Direct memory access mode - bit_offset: 8 - bit_size: 1 - - name: DDS - description: DMA disable selection - bit_offset: 9 - bit_size: 1 - - name: EOCS - description: End of conversion selection - bit_offset: 10 - bit_size: 1 - - name: ALIGN - description: Data alignment - bit_offset: 11 - bit_size: 1 - - name: JEXTSEL - description: External event select for injected group - bit_offset: 16 - bit_size: 4 - enum: JEXTSEL - - name: JEXTEN - description: External trigger enable for injected channels - bit_offset: 20 - bit_size: 2 - enum: EXTEN - - name: JSWSTART - description: Start conversion of injected channels - bit_offset: 22 - bit_size: 1 - - name: EXTSEL - description: External event select for regular group - bit_offset: 24 - bit_size: 4 - enum: EXTSEL - - name: EXTEN - description: External trigger enable for regular channels - bit_offset: 28 - bit_size: 2 - enum: EXTEN - - name: SWSTART - description: Start conversion of regular channels - bit_offset: 30 - bit_size: 1 + - name: ADON + description: A/D Converter ON / OFF + bit_offset: 0 + bit_size: 1 + - name: CONT + description: Continuous conversion + bit_offset: 1 + bit_size: 1 + - name: ADC_CFG + description: ADC configuration + bit_offset: 2 + bit_size: 1 + enum: ADC_CFG + - name: DELS + description: Delay selection + bit_offset: 4 + bit_size: 3 + enum: DELS + - name: DMA + description: Direct memory access mode + bit_offset: 8 + bit_size: 1 + - name: DDS + description: DMA disable selection + bit_offset: 9 + bit_size: 1 + - name: EOCS + description: End of conversion selection + bit_offset: 10 + bit_size: 1 + - name: ALIGN + description: Data alignment + bit_offset: 11 + bit_size: 1 + - name: JEXTSEL + description: External event select for injected group + bit_offset: 16 + bit_size: 4 + enum: JEXTSEL + - name: JEXTEN + description: External trigger enable for injected channels + bit_offset: 20 + bit_size: 2 + enum: EXTEN + - name: JSWSTART + description: Start conversion of injected channels + bit_offset: 22 + bit_size: 1 + - name: EXTSEL + description: External event select for regular group + bit_offset: 24 + bit_size: 4 + enum: EXTSEL + - name: EXTEN + description: External trigger enable for regular channels + bit_offset: 28 + bit_size: 2 + enum: EXTEN + - name: SWSTART + description: Start conversion of regular channels + bit_offset: 30 + bit_size: 1 fieldset/CSR: description: ADC common status register fields: - - name: AWD1 - description: Analog watchdog flag of the ADC - bit_offset: 0 - bit_size: 1 - - name: EOC1 - description: End of conversion of the ADC - bit_offset: 1 - bit_size: 1 - - name: JEOC1 - description: Injected channel end of conversion of the ADC - bit_offset: 2 - bit_size: 1 - - name: JSTRT1 - description: Injected channel Start flag of the ADC - bit_offset: 3 - bit_size: 1 - - name: STRT1 - description: Regular channel Start flag of the ADC - bit_offset: 4 - bit_size: 1 - - name: OVR1 - description: Overrun flag of the ADC - bit_offset: 5 - bit_size: 1 - - name: ADONS1 - description: ADON Status of ADC1 - bit_offset: 6 - bit_size: 1 + - name: AWD1 + description: Analog watchdog flag of the ADC + bit_offset: 0 + bit_size: 1 + - name: EOC1 + description: End of conversion of the ADC + bit_offset: 1 + bit_size: 1 + - name: JEOC1 + description: Injected channel end of conversion of the ADC + bit_offset: 2 + bit_size: 1 + - name: JSTRT1 + description: Injected channel Start flag of the ADC + bit_offset: 3 + bit_size: 1 + - name: STRT1 + description: Regular channel Start flag of the ADC + bit_offset: 4 + bit_size: 1 + - name: OVR1 + description: Overrun flag of the ADC + bit_offset: 5 + bit_size: 1 + - name: ADONS1 + description: ADON Status of ADC1 + bit_offset: 6 + bit_size: 1 fieldset/DR: description: regular data register fields: - - name: rdata - description: Regular data - bit_offset: 0 - bit_size: 16 + - name: rdata + description: Regular data + bit_offset: 0 + bit_size: 16 fieldset/HTR: description: watchdog higher threshold register fields: - - name: HT - description: Analog watchdog higher threshold - bit_offset: 0 - bit_size: 12 + - name: HT + description: Analog watchdog higher threshold + bit_offset: 0 + bit_size: 12 fieldset/JDR1: description: injected data register x fields: - - name: JDATA - description: Injected data - bit_offset: 0 - bit_size: 16 + - name: JDATA + description: Injected data + bit_offset: 0 + bit_size: 16 fieldset/JDR2: description: injected data register x fields: - - name: JDATA - description: Injected data - bit_offset: 0 - bit_size: 16 + - name: JDATA + description: Injected data + bit_offset: 0 + bit_size: 16 fieldset/JDR3: description: injected data register x fields: - - name: JDATA - description: Injected data - bit_offset: 0 - bit_size: 16 + - name: JDATA + description: Injected data + bit_offset: 0 + bit_size: 16 fieldset/JDR4: description: injected data register x fields: - - name: JDATA - description: Injected data - bit_offset: 0 - bit_size: 16 + - name: JDATA + description: Injected data + bit_offset: 0 + bit_size: 16 fieldset/JOFR1: description: injected channel data offset register x fields: - - name: JOFFSET1 - description: Data offset for injected channel x - bit_offset: 0 - bit_size: 12 + - name: JOFFSET1 + description: Data offset for injected channel x + bit_offset: 0 + bit_size: 12 fieldset/JOFR2: description: injected channel data offset register x fields: - - name: JOFFSET2 - description: Data offset for injected channel x - bit_offset: 0 - bit_size: 12 + - name: JOFFSET2 + description: Data offset for injected channel x + bit_offset: 0 + bit_size: 12 fieldset/JOFR3: description: injected channel data offset register x fields: - - name: JOFFSET3 - description: Data offset for injected channel x - bit_offset: 0 - bit_size: 12 + - name: JOFFSET3 + description: Data offset for injected channel x + bit_offset: 0 + bit_size: 12 fieldset/JOFR4: description: injected channel data offset register x fields: - - name: JOFFSET4 - description: Data offset for injected channel x - bit_offset: 0 - bit_size: 12 + - name: JOFFSET4 + description: Data offset for injected channel x + bit_offset: 0 + bit_size: 12 fieldset/JSQR: description: injected sequence register fields: - - name: JSQ1 - description: 1st conversion in injected sequence - bit_offset: 0 - bit_size: 5 - - name: JSQ2 - description: 2nd conversion in injected sequence - bit_offset: 5 - bit_size: 5 - - name: JSQ3 - description: 3rd conversion in injected sequence - bit_offset: 10 - bit_size: 5 - - name: JSQ4 - description: 4th conversion in injected sequence - bit_offset: 15 - bit_size: 5 - - name: JL - description: Injected sequence length - bit_offset: 20 - bit_size: 2 + - name: JSQ1 + description: 1st conversion in injected sequence + bit_offset: 0 + bit_size: 5 + - name: JSQ2 + description: 2nd conversion in injected sequence + bit_offset: 5 + bit_size: 5 + - name: JSQ3 + description: 3rd conversion in injected sequence + bit_offset: 10 + bit_size: 5 + - name: JSQ4 + description: 4th conversion in injected sequence + bit_offset: 15 + bit_size: 5 + - name: JL + description: Injected sequence length + bit_offset: 20 + bit_size: 2 fieldset/LTR: description: watchdog lower threshold register fields: - - name: LT - description: Analog watchdog lower threshold - bit_offset: 0 - bit_size: 12 + - name: LT + description: Analog watchdog lower threshold + bit_offset: 0 + bit_size: 12 fieldset/SMPR0: description: sample time register 0 fields: - - name: SMP - description: channel 30-31 sampling time selection - bit_offset: 0 - bit_size: 3 - enum: SAMPLE_TIME - array: - len: 2 - stride: 3 + - name: SMP + description: channel 30-31 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 2 + stride: 3 + enum: SAMPLE_TIME fieldset/SMPR1: description: sample time register 1 fields: - - name: SMP - description: channel 20-29 sampling time selection - bit_offset: 0 - bit_size: 3 - enum: SAMPLE_TIME - array: - len: 10 - stride: 3 + - name: SMP + description: channel 20-29 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 + enum: SAMPLE_TIME fieldset/SMPR2: description: sample time register 2 fields: - - name: SMP - description: channel 10-19 sampling time selection - bit_offset: 0 - bit_size: 3 - enum: SAMPLE_TIME - array: - len: 10 - stride: 3 + - name: SMP + description: channel 10-19 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 + enum: SAMPLE_TIME fieldset/SMPR3: description: sample time register 3 fields: - - name: SMP - description: channel 0-9 sampling time selection - bit_offset: 0 - bit_size: 3 - enum: SAMPLE_TIME - array: - len: 10 - stride: 3 + - name: SMP + description: channel 0-9 sampling time selection + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 + enum: SAMPLE_TIME fieldset/SQR1: description: regular sequence register 1 fields: - - name: SQ - description: 25th-29th conversion in regular sequence - bit_offset: 0 - bit_size: 5 - array: - len: 4 - stride: 5 - - name: L - description: Regular channel sequence length - bit_offset: 20 - bit_size: 4 + - name: SQ + description: 25th-29th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 4 + stride: 5 + - name: L + description: Regular channel sequence length + bit_offset: 20 + bit_size: 4 fieldset/SQR2: description: regular sequence register 2 fields: - - name: SQ - description: 19th-24th conversion in regular sequence - bit_offset: 0 - bit_size: 5 - array: - len: 6 - stride: 5 + - name: SQ + description: 19th-24th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 fieldset/SQR3: description: regular sequence register 3 fields: - - name: SQ - description: 13th-18th conversion in regular sequence - bit_offset: 0 - bit_size: 5 - array: - len: 6 - stride: 5 + - name: SQ + description: 13th-18th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 fieldset/SQR4: description: regular sequence register 4 fields: - - name: SQ - description: 7th-12th conversion in regular sequence - bit_offset: 0 - bit_size: 5 - array: - len: 6 - stride: 5 + - name: SQ + description: 7th-12th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 fieldset/SQR5: description: regular sequence register 5 fields: - - name: SQ - description: 1st-6th conversion in regular sequence - bit_offset: 0 - bit_size: 5 - array: - len: 6 - stride: 5 + - name: SQ + description: 1st-6th conversion in regular sequence + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 fieldset/SR: description: status register fields: - - name: AWD - description: Analog watchdog flag - bit_offset: 0 - bit_size: 1 - - name: EOC - description: Regular channel end of conversion - bit_offset: 1 - bit_size: 1 - - name: JEOC - description: Injected channel end of conversion - bit_offset: 2 - bit_size: 1 - - name: JSTRT - description: Injected channel start flag - bit_offset: 3 - bit_size: 1 - - name: STRT - description: Regular channel start flag - bit_offset: 4 - bit_size: 1 - - name: OVR - description: Overrun - bit_offset: 5 - bit_size: 1 - - name: ADONS - description: ADC ON status - bit_offset: 6 - bit_size: 1 - - name: RCNR - description: Regular channel not ready - bit_offset: 8 - bit_size: 1 - - name: JCNR - description: Injected channel not ready - bit_offset: 9 - bit_size: 1 + - name: AWD + description: Analog watchdog flag + bit_offset: 0 + bit_size: 1 + - name: EOC + description: Regular channel end of conversion + bit_offset: 1 + bit_size: 1 + - name: JEOC + description: Injected channel end of conversion + bit_offset: 2 + bit_size: 1 + - name: JSTRT + description: Injected channel start flag + bit_offset: 3 + bit_size: 1 + - name: STRT + description: Regular channel start flag + bit_offset: 4 + bit_size: 1 + - name: OVR + description: Overrun + bit_offset: 5 + bit_size: 1 + - name: ADONS + description: ADC ON status + bit_offset: 6 + bit_size: 1 + - name: RCNR + description: Regular channel not ready + bit_offset: 8 + bit_size: 1 + - name: JCNR + description: Injected channel not ready + bit_offset: 9 + bit_size: 1 enum/ADC_CFG: bit_size: 1 variants: - - name: BANK_A - description: Bank A selected for channels ADC_IN0..31 - value: 0 - - name: BANK_B - description: Bank B selected for channels ADC_IN0..31b - value: 1 -enum/DISCNUM: - bit_size: 3 - variants: - - name: DISCNUM_1 - description: 1 conversions are discontinued and the conversion is carried out on one channel - value: 0 - - name: DISCNUM_2 - description: 2 conversion is discontinued and the conversions are carried out on 2 channels - value: 1 - - name: DISCNUM_3 - description: 3 conversions are discontinued and the conversions are carried out on 3 channels - value: 2 - - name: DISCNUM_4 - description: 4 conversions are discontinued and the conversions are carried out on 4 channels - value: 3 - - name: DISCNUM_5 - description: 5 conversions are discontinued and the conversions are carried out on 5 channels - value: 4 - - name: DISCNUM_6 - description: 6 conversions are discontinued and the conversions are carried out on 6 channels - value: 5 - - name: DISCNUM_7 - description: 7 conversions are discontinued and the conversions are carried out on 7 channels - value: 6 - - name: DISCNUM_8 - description: 8 conversions are discontinued and the conversions are carried out on 8 channels - value: 7 + - name: BANK_A + description: Bank A selected for channels ADC_IN0..31 + value: 0 + - name: BANK_B + description: Bank B selected for channels ADC_IN0..31b + value: 1 enum/DELS: bit_size: 3 variants: - - name: NO_DELAY - description: No Delay - value: 0 - - name: AFTER_READ - description: Until the converted data have been read - value: 1 - - name: DELAY_7_CLK - description: Delay 7 APB clock cycles after the conversion - value: 2 - - name: DELAY_15_CLK - description: Delay 16 APB clock cycles after the conversion - value: 3 - - name: DELAY_31_CLK - description: Delay 31 APB clock cycles after the conversion - value: 4 - - name: DELAY_63_CLK - description: Delay 63 APB clock cycles after the conversion - value: 5 - - name: DELAY_127_CLK - description: Delay 127 APB clock cycles after the conversion - value: 6 - - name: DELAY_255_CLK - description: Delay 255 APB clock cycles after the conversion - value: 7 + - name: NO_DELAY + description: No Delay + value: 0 + - name: AFTER_READ + description: Until the converted data have been read + value: 1 + - name: DELAY_7_CLK + description: Delay 7 APB clock cycles after the conversion + value: 2 + - name: DELAY_15_CLK + description: Delay 16 APB clock cycles after the conversion + value: 3 + - name: DELAY_31_CLK + description: Delay 31 APB clock cycles after the conversion + value: 4 + - name: DELAY_63_CLK + description: Delay 63 APB clock cycles after the conversion + value: 5 + - name: DELAY_127_CLK + description: Delay 127 APB clock cycles after the conversion + value: 6 + - name: DELAY_255_CLK + description: Delay 255 APB clock cycles after the conversion + value: 7 +enum/DISCNUM: + bit_size: 3 + variants: + - name: DISCNUM_1 + description: 1 conversions are discontinued and the conversion is carried out on one channel + value: 0 + - name: DISCNUM_2 + description: 2 conversion is discontinued and the conversions are carried out on 2 channels + value: 1 + - name: DISCNUM_3 + description: 3 conversions are discontinued and the conversions are carried out on 3 channels + value: 2 + - name: DISCNUM_4 + description: 4 conversions are discontinued and the conversions are carried out on 4 channels + value: 3 + - name: DISCNUM_5 + description: 5 conversions are discontinued and the conversions are carried out on 5 channels + value: 4 + - name: DISCNUM_6 + description: 6 conversions are discontinued and the conversions are carried out on 6 channels + value: 5 + - name: DISCNUM_7 + description: 7 conversions are discontinued and the conversions are carried out on 7 channels + value: 6 + - name: DISCNUM_8 + description: 8 conversions are discontinued and the conversions are carried out on 8 channels + value: 7 enum/EXTEN: bit_size: 2 variants: - - name: DISABLED - description: Trigger detection disabled - value: 0 - - name: RISING - description: Trigger detection on the rising edge - value: 1 - - name: FALLING - description: Trigger detection on the falling edge - value: 2 - - name: BOTH - description: Trigger detection on both edges - value: 3 + - name: DISABLED + description: Trigger detection disabled + value: 0 + - name: RISING + description: Trigger detection on the rising edge + value: 1 + - name: FALLING + description: Trigger detection on the falling edge + value: 2 + - name: BOTH + description: Trigger detection on both edges + value: 3 enum/EXTSEL: bit_size: 4 variants: - - name: TIM9_CC2 - description: Timer 9 CC2 event - value: 0 - - name: TIM9_TRGO - description: Timer 9 TRGO event - value: 1 - - name: TIM2_CC3 - description: Timer 2 CC3 event - value: 2 - - name: TIM2_CC2 - description: Timer 2 CC2 event - value: 3 - - name: TIM3_TRGO - description: Timer 3 TRGO event - value: 4 - - name: TIM4_CC4 - description: Timer 4 CC4 event - value: 5 - - name: TIM2_TRGO - description: Timer 2 TRGO event - value: 6 - - name: TIM3_CC1 - description: Timer 3 CC1 event - value: 7 - - name: TIM3_CC3 - description: Timer 3 CC3 event - value: 8 - - name: TIM4_TRGO - description: Timer 4 TRGO event - value: 9 - - name: TIM6_TRGO - description: Timer 6 TRGO event - value: 10 - - name: EXTI_LINE11 - description: External interrupt line 11 - value: 15 + - name: TIM9_CC2 + description: Timer 9 CC2 event + value: 0 + - name: TIM9_TRGO + description: Timer 9 TRGO event + value: 1 + - name: TIM2_CC3 + description: Timer 2 CC3 event + value: 2 + - name: TIM2_CC2 + description: Timer 2 CC2 event + value: 3 + - name: TIM3_TRGO + description: Timer 3 TRGO event + value: 4 + - name: TIM4_CC4 + description: Timer 4 CC4 event + value: 5 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 6 + - name: TIM3_CC1 + description: Timer 3 CC1 event + value: 7 + - name: TIM3_CC3 + description: Timer 3 CC3 event + value: 8 + - name: TIM4_TRGO + description: Timer 4 TRGO event + value: 9 + - name: TIM6_TRGO + description: Timer 6 TRGO event + value: 10 + - name: EXTI_LINE11 + description: External interrupt line 11 + value: 15 enum/JEXTSEL: bit_size: 4 variants: - - name: TIM9_CC1 - description: Timer 9 CC1 event - value: 0 - - name: TIM9_TRGO - description: Timer 9 TRGO event - value: 1 - - name: TIM2_TRGO - description: Timer 2 TRGO event - value: 2 - - name: TIM2_CC1 - description: Timer 2 CC1 event - value: 3 - - name: TIM3_CC4 - description: Timer 3 CC4 event - value: 4 - - name: TIM4_TRGO - description: Timer 4 TRGO event - value: 5 - - name: TIM4_CC1 - description: Timer 4 CC1 event - value: 6 - - name: TIM4_CC2 - description: Timer 4 CC2 event - value: 7 - - name: TIM4_CC3 - description: Timer 4 CC3 event - value: 8 - - name: TIM10_CC1 - description: Timer 4 CC3 event - value: 9 - - name: TIM7_TRGO - description: Timer 7 TRGO event - value: 10 - - name: EXTI_LINE15 - description: External interrupt line 15 - value: 15 + - name: TIM9_CC1 + description: Timer 9 CC1 event + value: 0 + - name: TIM9_TRGO + description: Timer 9 TRGO event + value: 1 + - name: TIM2_TRGO + description: Timer 2 TRGO event + value: 2 + - name: TIM2_CC1 + description: Timer 2 CC1 event + value: 3 + - name: TIM3_CC4 + description: Timer 3 CC4 event + value: 4 + - name: TIM4_TRGO + description: Timer 4 TRGO event + value: 5 + - name: TIM4_CC1 + description: Timer 4 CC1 event + value: 6 + - name: TIM4_CC2 + description: Timer 4 CC2 event + value: 7 + - name: TIM4_CC3 + description: Timer 4 CC3 event + value: 8 + - name: TIM10_CC1 + description: Timer 4 CC3 event + value: 9 + - name: TIM7_TRGO + description: Timer 7 TRGO event + value: 10 + - name: EXTI_LINE15 + description: External interrupt line 15 + value: 15 enum/RES: bit_size: 2 variants: @@ -698,27 +698,27 @@ enum/RES: enum/SAMPLE_TIME: bit_size: 3 variants: - - name: Cycles4 - description: 4 ADC clock cycles - value: 0 - - name: Cycles9 - description: 9 ADC clock cycles - value: 1 - - name: Cycles16 - description: 16 ADC clock cycles - value: 2 - - name: Cycles24 - description: 24 ADC clock cycles - value: 3 - - name: Cycles48 - description: 48 ADC clock cycles - value: 4 - - name: Cycles96 - description: 96 ADC clock cycles - value: 5 - - name: Cycles192 - description: 192 ADC clock cycles - value: 6 - - name: Cycles384 - description: 384 ADC clock cycles - value: 7 + - name: Cycles4 + description: 4 ADC clock cycles + value: 0 + - name: Cycles9 + description: 9 ADC clock cycles + value: 1 + - name: Cycles16 + description: 16 ADC clock cycles + value: 2 + - name: Cycles24 + description: 24 ADC clock cycles + value: 3 + - name: Cycles48 + description: 48 ADC clock cycles + value: 4 + - name: Cycles96 + description: 96 ADC clock cycles + value: 5 + - name: Cycles192 + description: 192 ADC clock cycles + value: 6 + - name: Cycles384 + description: 384 ADC clock cycles + value: 7 diff --git a/data/registers/adc_l0.yaml b/data/registers/adc_l0.yaml index f5f2cf7..f5b8de7 100644 --- a/data/registers/adc_l0.yaml +++ b/data/registers/adc_l0.yaml @@ -358,6 +358,45 @@ enum/OVRMOD: - name: Overwritten description: ADC_DR register is overwritten with the last conversion result when an overrun is detected value: 1 +enum/PRESC: + bit_size: 4 + variants: + - name: Div1 + description: Input ADC clock not divided. + value: 0 + - name: Div2 + description: Input ADC clock divided by 2. + value: 1 + - name: Div4 + description: Input ADC clock divided by 4. + value: 2 + - name: Div6 + description: Input ADC clock divided by 6. + value: 3 + - name: Div8 + description: Input ADC clock divided by 8. + value: 4 + - name: Div10 + description: Input ADC clock divided by 10. + value: 5 + - name: Div12 + description: Input ADC clock divided by 12. + value: 6 + - name: Div16 + description: Input ADC clock divided by 16. + value: 7 + - name: Div32 + description: Input ADC clock divided by 32. + value: 8 + - name: Div64 + description: Input ADC clock divided by 64. + value: 9 + - name: Div128 + description: Input ADC clock divided by 128. + value: 10 + - name: Div256 + description: Input ADC clock divided by 256. + value: 11 enum/RES: bit_size: 2 variants: @@ -400,45 +439,6 @@ enum/SAMPLE_TIME: - name: Cycles160_5 description: 160.5 cycles value: 7 -enum/PRESC: - bit_size: 4 - variants: - - name: Div1 - description: Input ADC clock not divided. - value: 0 - - name: Div2 - description: Input ADC clock divided by 2. - value: 1 - - name: Div4 - description: Input ADC clock divided by 4. - value: 2 - - name: Div6 - description: Input ADC clock divided by 6. - value: 3 - - name: Div8 - description: Input ADC clock divided by 8. - value: 4 - - name: Div10 - description: Input ADC clock divided by 10. - value: 5 - - name: Div12 - description: Input ADC clock divided by 12. - value: 6 - - name: Div16 - description: Input ADC clock divided by 16. - value: 7 - - name: Div32 - description: Input ADC clock divided by 32. - value: 8 - - name: Div64 - description: Input ADC clock divided by 64. - value: 9 - - name: Div128 - description: Input ADC clock divided by 128. - value: 10 - - name: Div256 - description: Input ADC clock divided by 256. - value: 11 enum/SCANDIR: bit_size: 1 variants: diff --git a/data/registers/adccommon_f3.yaml b/data/registers/adccommon_f3.yaml index cf37f6c..4e2441b 100644 --- a/data/registers/adccommon_f3.yaml +++ b/data/registers/adccommon_f3.yaml @@ -95,6 +95,13 @@ fieldset/CSR: description: End of injected sequence flag of the master ADC bit_offset: 6 bit_size: 1 + - name: AWD_MST + description: Analog watchdog flag of the master ADC + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 - name: JQOVF_MST description: Injected context queue overflow flag of the master ADC bit_offset: 10 @@ -127,17 +134,6 @@ fieldset/CSR: description: End of injected sequence flag of the slave ADC bit_offset: 22 bit_size: 1 - - name: JQOVF_SLV - description: Injected context queue overflow flag of the slave ADC - bit_offset: 26 - bit_size: 1 - - name: AWD_MST - description: Analog watchdog flag of the master ADC - bit_offset: 7 - bit_size: 1 - array: - len: 3 - stride: 1 - name: AWD_SLV description: Analog watchdog flag of the slave ADC bit_offset: 23 @@ -145,6 +141,10 @@ fieldset/CSR: array: len: 3 stride: 1 + - name: JQOVF_SLV + description: Injected context queue overflow flag of the slave ADC + bit_offset: 26 + bit_size: 1 enum/CKMODE: description: ADC clock mode bit_size: 2 diff --git a/data/registers/adccommon_v3.yaml b/data/registers/adccommon_v3.yaml index 3acd38f..9f6d45e 100644 --- a/data/registers/adccommon_v3.yaml +++ b/data/registers/adccommon_v3.yaml @@ -92,6 +92,13 @@ fieldset/CSR: description: JEOS_MST bit_offset: 6 bit_size: 1 + - name: AWD_MST + description: Analog watchdog flag of the master ADC + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 - name: JQOVF_MST description: JQOVF_MST bit_offset: 10 @@ -124,17 +131,6 @@ fieldset/CSR: description: End of injected sequence flag of the slave ADC bit_offset: 22 bit_size: 1 - - name: JQOVF_SLV - description: Injected Context Queue Overflow flag of the slave ADC - bit_offset: 26 - bit_size: 1 - - name: AWD_MST - description: Analog watchdog flag of the master ADC - bit_offset: 7 - bit_size: 1 - array: - len: 3 - stride: 1 - name: AWD_SLV description: Analog watchdog 1 flag of the slave ADC bit_offset: 23 @@ -142,3 +138,7 @@ fieldset/CSR: array: len: 3 stride: 1 + - name: JQOVF_SLV + description: Injected Context Queue Overflow flag of the slave ADC + bit_offset: 26 + bit_size: 1 diff --git a/data/registers/adccommon_v4.yaml b/data/registers/adccommon_v4.yaml index 68b0f3d..447d901 100644 --- a/data/registers/adccommon_v4.yaml +++ b/data/registers/adccommon_v4.yaml @@ -108,6 +108,13 @@ fieldset/CSR: description: End of injected sequence flag of the master ADC bit_offset: 6 bit_size: 1 + - name: AWD_MST + description: Analog watchdog flag of the master ADC + bit_offset: 7 + bit_size: 1 + array: + len: 3 + stride: 1 - name: JQOVF_MST description: Injected Context Queue Overflow flag of the master ADC bit_offset: 10 @@ -140,17 +147,6 @@ fieldset/CSR: description: End of injected sequence flag of the slave ADC bit_offset: 22 bit_size: 1 - - name: JQOVF_SLV - description: Injected Context Queue Overflow flag of the slave ADC - bit_offset: 26 - bit_size: 1 - - name: AWD_MST - description: Analog watchdog flag of the master ADC - bit_offset: 7 - bit_size: 1 - array: - len: 3 - stride: 1 - name: AWD_SLV description: Analog watchdog flag of the slave ADC bit_offset: 23 @@ -158,6 +154,10 @@ fieldset/CSR: array: len: 3 stride: 1 + - name: JQOVF_SLV + description: Injected Context Queue Overflow flag of the slave ADC + bit_offset: 26 + bit_size: 1 enum/CKMODE: bit_size: 2 variants: diff --git a/data/registers/adf_v1.yaml b/data/registers/adf_v1.yaml index 65206c0..8e3d8d3 100644 --- a/data/registers/adf_v1.yaml +++ b/data/registers/adf_v1.yaml @@ -403,214 +403,25 @@ fieldset/SITFCR: description: SITFACTIVE. bit_offset: 31 bit_size: 1 -enum/TRGSRC: - description: Digital filter trigger signal selection. - bit_size: 4 - variants: - - name: TRGO - description: TRGO Selected. - value: 0 - - name: TRG1 - description: adf_trg1 selected. - value: 2 -enum/TRGSENS: - description: CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0. - bit_size: 1 - variants: - - name: RisingEdge - description: A rising edge event triggers the activation of CKGEN dividers. - value: 0 - - name: FallingEdge - description: A falling edge even triggers the activation of CKGEN dividers. - value: 1 -enum/CCKDIR: - description: CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin. - bit_size: 1 - variants: - - name: Input - description: CCK is an input. - value: 0 - - name: Output - description: CCK is an output. - value: 1 -enum/CKGMOD: - description: Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1). - bit_size: 1 - variants: - - name: Immediate - description: The kernel clock is provided to the dividers as soon as CKGDEN is set to 1. - value: 0 - - name: Trigger - description: The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met. - value: 1 -enum/CCKEN: - description: CCK clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin. - bit_size: 1 - variants: - - name: NotGenerated - description: Bitstream clock not generated. - value: 0 - - name: Generated - description: Bitstream clock generated on the CCK pin. - value: 1 -enum/CCKDIV: - description: Divider to control the CCK clock. This bit is set and reset by software. It is used to control the frequency of the bitstream clock on the CCK pin. - bit_size: 4 - variants: - - name: DIV1 - description: The ADF_CCK clock is adf_proc_ck. - value: 0 - - name: DIV2 - description: The ADF_CCK clock is adf_proc_ck divided by 2. - value: 1 - - name: DIV3 - description: The ADF_CCK clock is adf_proc_ck divided by 3. - value: 2 - - name: DIV4 - description: The ADF_CCK clock is adf_proc_ck divided by 4. - value: 3 - - name: DIV5 - description: The ADF_CCK clock is adf_proc_ck divided by 5. - value: 4 - - name: DIV6 - description: The ADF_CCK clock is adf_proc_ck divided by 6. - value: 5 - - name: DIV7 - description: The ADF_CCK clock is adf_proc_ck divided by 7. - value: 6 - - name: DIV8 - description: The ADF_CCK clock is adf_proc_ck divided by 8. - value: 7 - - name: DIV9 - description: The ADF_CCK clock is adf_proc_ck divided by 9. - value: 8 - - name: DIV10 - description: The ADF_CCK clock is adf_proc_ck divided by 10. - value: 9 - - name: DIV11 - description: The ADF_CCK clock is adf_proc_ck divided by 11. - value: 10 - - name: DIV12 - description: The ADF_CCK clock is adf_proc_ck divided by 12. - value: 11 - - name: DIV13 - description: The ADF_CCK clock is adf_proc_ck divided by 13. - value: 12 - - name: DIV14 - description: The ADF_CCK clock is adf_proc_ck divided by 14. - value: 13 - - name: DIV15 - description: The ADF_CCK clock is adf_proc_ck divided by 15. - value: 14 - - name: DIV16 - description: The ADF_CCK clock is adf_proc_ck divided by 16. - value: 15 -enum/SADMOD: - description: SAD working mode. This bitfield is set and cleared by software. It is used to define the way the SAD works - bit_size: 2 - variants: - - name: ThresholdEstimatedAmbientNoise - description: Threshold value computed according to the estimated ambient noise. The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a voice activity detector. - value: 0 - - name: ThresholdMinimumNoiselevel - description: Threshold value equal to ANMIN[12:0], multiplied by the gain selected by SNTHR[3:0] The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a sound detector. - value: 1 - - name: ThresholdMinimumNoiselevelx4 - description: Threshold value given by 4 x ANMIN[12:0]. The SAD triggers when the estimated ambient noise (ANLVL), multiplied by the gain selected by SNTHR[3:0] is bigger than the defined threshold. In this mode, the SAD is working like an ambient noise estimator. Hysteresis function cannot be used in this mode. - value: 2 -enum/FRSIZE: - description: Frame size. This bitfield is set and cleared by software. it is used to define the size of one frame and also to define how many samples are taken into account to compute the short-term signal level. +enum/ACQMOD: + description: DFLT trigger mode. This bitfield is set and cleared by software. It is used to select the trigger mode of the DFLT0. bit_size: 3 variants: - - name: Samples8 - description: 8 sample. + - name: AsynchronousContinuous + description: Asynchronous continuous acquisition mode. value: 0 - - name: Samples16 - description: 16 samples. + - name: AsynchronousSingleShot + description: Asynchronous single-shot acquisition mode value: 1 - - name: Samples32 - description: 32 samples. + - name: SyncronousContinuous + description: Synchronous continuous acquisition mode. value: 2 - - name: Samples64 - description: 64 samples. + - name: SyncronousSingleShot + description: Synchronous single-shot acquisition mode. value: 3 - - name: Samples128 - description: 128 samples. + - name: WindowContinuous + description: Window continuous acquisition mode. value: 4 - - name: Samples256 - description: 256 samples. - value: 5 - - name: Samples512 - description: 512 samples. - value: 6 -enum/DATCAP: - description: Data capture mode. This bitfield is set and cleared by software. It is used to define in which conditions, the samples provided by DLFT0 are stored into the memory. - bit_size: 2 - variants: - - name: Disabled - description: Samples from DFLT0 not transfered into the memory. - value: 0 - - name: OnDetected - description: Samples from DFLT0 transfered into the memory when SAD is in DETECT state. - value: 1 - - name: Enabled - description: Samples from DFLT0 transfered into memory when SAD and DFLT0 are enabled. - value: 2 -enum/DETCFG: - description: Sound trigger event configuration. This bit is set and cleared by software. It is used to define if the sddet_evt event is generated only when the SAD enters to MONITOR state or when the SAD enters or exits the DETECT state. - bit_size: 1 - variants: - - name: Monitor - description: sddet_evt generated when SAD enters the MONITOR state. - value: 0 - - name: Detect - description: sddet_evt generated when SAD enters or exits the DETECT state. - value: 1 -enum/SADST: - description: SAD state. This bitfield is set and cleared by hardware. It indicates the SAD state and is meaningful only when SADEN = 1. - bit_size: 2 - variants: - - name: Learn - description: SAD in LEARN state. - value: 0 - - name: Monitor - description: SAD in MONITOR state. - value: 1 - - name: Detect - description: SAD in DETECT state. - value: 2 -enum/SCKSRC: - description: Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface. - bit_size: 2 - variants: - - name: CCK0 - description: Serial clock source is CCK0. - value: 0 - - name: CCK1 - description: Serial clock source is CCK1. - value: 1 - - name: CKI0 - description: Serial clock source is CCI0. - value: 2 - - name: CKI1 - description: Serial clock source is CCI1. - value: 3 -enum/SITFMOD: - description: Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode. - bit_size: 2 - variants: - - name: MasterSPI - description: LF_MASTER SPI mode. - value: 0 - - name: NormalSPI - description: Normal SPI mode. - value: 1 - - name: ManchesterFalling - description: Manchester mode rising edge = logic 0, falling edge = logic 1. - value: 2 - - name: ManchesterRising - description: Manchester mode rising edge = logic 1, falling edge = logic 0. - value: 3 enum/BSSEL: description: Bitstream selection. This bitfield is set and cleared by software. It is used to select the bitstream to be used by the DFLT0. bit_size: 5 @@ -711,6 +522,111 @@ enum/BSSEL: - name: BS15_F description: bsx_f provided to DFLTy (and SCDy). value: 31 +enum/CCKDIR: + description: CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin. + bit_size: 1 + variants: + - name: Input + description: CCK is an input. + value: 0 + - name: Output + description: CCK is an output. + value: 1 +enum/CCKDIV: + description: Divider to control the CCK clock. This bit is set and reset by software. It is used to control the frequency of the bitstream clock on the CCK pin. + bit_size: 4 + variants: + - name: DIV1 + description: The ADF_CCK clock is adf_proc_ck. + value: 0 + - name: DIV2 + description: The ADF_CCK clock is adf_proc_ck divided by 2. + value: 1 + - name: DIV3 + description: The ADF_CCK clock is adf_proc_ck divided by 3. + value: 2 + - name: DIV4 + description: The ADF_CCK clock is adf_proc_ck divided by 4. + value: 3 + - name: DIV5 + description: The ADF_CCK clock is adf_proc_ck divided by 5. + value: 4 + - name: DIV6 + description: The ADF_CCK clock is adf_proc_ck divided by 6. + value: 5 + - name: DIV7 + description: The ADF_CCK clock is adf_proc_ck divided by 7. + value: 6 + - name: DIV8 + description: The ADF_CCK clock is adf_proc_ck divided by 8. + value: 7 + - name: DIV9 + description: The ADF_CCK clock is adf_proc_ck divided by 9. + value: 8 + - name: DIV10 + description: The ADF_CCK clock is adf_proc_ck divided by 10. + value: 9 + - name: DIV11 + description: The ADF_CCK clock is adf_proc_ck divided by 11. + value: 10 + - name: DIV12 + description: The ADF_CCK clock is adf_proc_ck divided by 12. + value: 11 + - name: DIV13 + description: The ADF_CCK clock is adf_proc_ck divided by 13. + value: 12 + - name: DIV14 + description: The ADF_CCK clock is adf_proc_ck divided by 14. + value: 13 + - name: DIV15 + description: The ADF_CCK clock is adf_proc_ck divided by 15. + value: 14 + - name: DIV16 + description: The ADF_CCK clock is adf_proc_ck divided by 16. + value: 15 +enum/CCKEN: + description: CCK clock enable. This bit is set and reset by software. It is used to control the generation of the bitstream clock on the CCK pin. + bit_size: 1 + variants: + - name: NotGenerated + description: Bitstream clock not generated. + value: 0 + - name: Generated + description: Bitstream clock generated on the CCK pin. + value: 1 +enum/CICMOD: + description: Select the CIC order. This bitfield is set and cleared by software. It is used to select the MCIC order. + bit_size: 3 + variants: + - name: SINC4 + description: MCIC configured in single Sinc4 filter. + value: 4 + - name: SINC5 + description: MCIC configured in single Sinc5 filter. + value: 5 +enum/CKGMOD: + description: Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1). + bit_size: 1 + variants: + - name: Immediate + description: The kernel clock is provided to the dividers as soon as CKGDEN is set to 1. + value: 0 + - name: Trigger + description: The kernel clock is provided to the dividers when CKGDEN is set to 1 and the trigger condition met. + value: 1 +enum/DATCAP: + description: Data capture mode. This bitfield is set and cleared by software. It is used to define in which conditions, the samples provided by DLFT0 are stored into the memory. + bit_size: 2 + variants: + - name: Disabled + description: Samples from DFLT0 not transfered into the memory. + value: 0 + - name: OnDetected + description: Samples from DFLT0 transfered into the memory when SAD is in DETECT state. + value: 1 + - name: Enabled + description: Samples from DFLT0 transfered into memory when SAD and DFLT0 are enabled. + value: 2 enum/DATSRC: description: Source data for the digital filter. bit_size: 2 @@ -724,71 +640,41 @@ enum/DATSRC: - name: ADCITF2 description: Stream coming from the ADCITF2 selected value: 3 -enum/CICMOD: - description: Select the CIC order. This bitfield is set and cleared by software. It is used to select the MCIC order. +enum/DETCFG: + description: Sound trigger event configuration. This bit is set and cleared by software. It is used to define if the sddet_evt event is generated only when the SAD enters to MONITOR state or when the SAD enters or exits the DETECT state. + bit_size: 1 + variants: + - name: Monitor + description: sddet_evt generated when SAD enters the MONITOR state. + value: 0 + - name: Detect + description: sddet_evt generated when SAD enters or exits the DETECT state. + value: 1 +enum/FRSIZE: + description: Frame size. This bitfield is set and cleared by software. it is used to define the size of one frame and also to define how many samples are taken into account to compute the short-term signal level. bit_size: 3 variants: - - name: SINC4 - description: MCIC configured in single Sinc4 filter. + - name: Samples8 + description: 8 sample. + value: 0 + - name: Samples16 + description: 16 samples. + value: 1 + - name: Samples32 + description: 32 samples. + value: 2 + - name: Samples64 + description: 64 samples. + value: 3 + - name: Samples128 + description: 128 samples. value: 4 - - name: SINC5 - description: MCIC configured in single Sinc5 filter. + - name: Samples256 + description: 256 samples. value: 5 -enum/RSFLTD: - description: Reshaper filter decimation ratio. This bitfield is set and cleared by software. It is used to select the decimation ratio of the reshaper filter. - bit_size: 1 - variants: - - name: Decimation4 - description: Decimation ratio is 4 (default value). - value: 0 - - name: Decimation1 - description: Decimation ratio is 1. - value: 1 -enum/HPFC: - description: High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input. - bit_size: 2 - variants: - - name: Low - description: Cut-off frequency = 0.000625 x FPCM. - value: 0 - - name: Medium - description: Cut-off frequency = 0.00125 x FPCM. - value: 1 - - name: High - description: Cut-off frequency = 0.00250 x FPCM - value: 2 - - name: Maximum - description: Cut-off frequency = 0.00950 x FPCM - value: 3 -enum/ACQMOD: - description: DFLT trigger mode. This bitfield is set and cleared by software. It is used to select the trigger mode of the DFLT0. - bit_size: 3 - variants: - - name: AsynchronousContinuous - description: Asynchronous continuous acquisition mode. - value: 0 - - name: AsynchronousSingleShot - description: Asynchronous single-shot acquisition mode - value: 1 - - name: SyncronousContinuous - description: Synchronous continuous acquisition mode. - value: 2 - - name: SyncronousSingleShot - description: Synchronous single-shot acquisition mode. - value: 3 - - name: WindowContinuous - description: Window continuous acquisition mode. - value: 4 -enum/RXFIFO: - description: RXFIFO threshold selection. This bitfield is set and cleared by software. It is used to select the RXFIFO threshold. - bit_size: 1 - variants: - - name: NotEmpty - description: RXFIFO threshold event generated when the RXFIFO is not empty - value: 0 - - name: HalfFull - description: RXFIFO threshold event generated when the RXFIFO is half-full - value: 1 + - name: Samples512 + description: 512 samples. + value: 6 enum/HGOVR: description: Hangover time window. This bitfield is set and cleared by software. It is used to select the hangover time window. bit_size: 3 @@ -817,6 +703,22 @@ enum/HGOVR: - name: Frames 512 description: SAD back to MONITOR state if sound is below threshold for 4 frames. value: 7 +enum/HPFC: + description: High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input. + bit_size: 2 + variants: + - name: Low + description: Cut-off frequency = 0.000625 x FPCM. + value: 0 + - name: Medium + description: Cut-off frequency = 0.00125 x FPCM. + value: 1 + - name: High + description: Cut-off frequency = 0.00250 x FPCM + value: 2 + - name: Maximum + description: Cut-off frequency = 0.00950 x FPCM + value: 3 enum/LFRNB: description: LFRNB. This bitfield is set and cleared by software. It is used to define the number of learning frames to perform the first estimate of the noise level. bit_size: 3 @@ -836,6 +738,84 @@ enum/LFRNB: - name: Frames 32 description: 32 samples. value: 4 +enum/RSFLTD: + description: Reshaper filter decimation ratio. This bitfield is set and cleared by software. It is used to select the decimation ratio of the reshaper filter. + bit_size: 1 + variants: + - name: Decimation4 + description: Decimation ratio is 4 (default value). + value: 0 + - name: Decimation1 + description: Decimation ratio is 1. + value: 1 +enum/RXFIFO: + description: RXFIFO threshold selection. This bitfield is set and cleared by software. It is used to select the RXFIFO threshold. + bit_size: 1 + variants: + - name: NotEmpty + description: RXFIFO threshold event generated when the RXFIFO is not empty + value: 0 + - name: HalfFull + description: RXFIFO threshold event generated when the RXFIFO is half-full + value: 1 +enum/SADMOD: + description: SAD working mode. This bitfield is set and cleared by software. It is used to define the way the SAD works + bit_size: 2 + variants: + - name: ThresholdEstimatedAmbientNoise + description: Threshold value computed according to the estimated ambient noise. The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a voice activity detector. + value: 0 + - name: ThresholdMinimumNoiselevel + description: Threshold value equal to ANMIN[12:0], multiplied by the gain selected by SNTHR[3:0] The SAD triggers when the sound level (SDLVL) is bigger than the defined threshold. In this mode, the SAD works like a sound detector. + value: 1 + - name: ThresholdMinimumNoiselevelx4 + description: Threshold value given by 4 x ANMIN[12:0]. The SAD triggers when the estimated ambient noise (ANLVL), multiplied by the gain selected by SNTHR[3:0] is bigger than the defined threshold. In this mode, the SAD is working like an ambient noise estimator. Hysteresis function cannot be used in this mode. + value: 2 +enum/SADST: + description: SAD state. This bitfield is set and cleared by hardware. It indicates the SAD state and is meaningful only when SADEN = 1. + bit_size: 2 + variants: + - name: Learn + description: SAD in LEARN state. + value: 0 + - name: Monitor + description: SAD in MONITOR state. + value: 1 + - name: Detect + description: SAD in DETECT state. + value: 2 +enum/SCKSRC: + description: Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface. + bit_size: 2 + variants: + - name: CCK0 + description: Serial clock source is CCK0. + value: 0 + - name: CCK1 + description: Serial clock source is CCK1. + value: 1 + - name: CKI0 + description: Serial clock source is CCI0. + value: 2 + - name: CKI1 + description: Serial clock source is CCI1. + value: 3 +enum/SITFMOD: + description: Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode. + bit_size: 2 + variants: + - name: MasterSPI + description: LF_MASTER SPI mode. + value: 0 + - name: NormalSPI + description: Normal SPI mode. + value: 1 + - name: ManchesterFalling + description: Manchester mode rising edge = logic 0, falling edge = logic 1. + value: 2 + - name: ManchesterRising + description: Manchester mode rising edge = logic 1, falling edge = logic 0. + value: 3 enum/SNTHR: description: SNTHR. This bitfield is set and cleared by software. It is used to select the gain to be applied at CIC output. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back this bitfield informs the application on the current gain value. bit_size: 4 @@ -870,3 +850,23 @@ enum/SNTHR: - name: NOISE PLUS 30_1 description: Threshold is 30.1 dB higher than ANLVL value: 9 +enum/TRGSENS: + description: CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0. + bit_size: 1 + variants: + - name: RisingEdge + description: A rising edge event triggers the activation of CKGEN dividers. + value: 0 + - name: FallingEdge + description: A falling edge even triggers the activation of CKGEN dividers. + value: 1 +enum/TRGSRC: + description: Digital filter trigger signal selection. + bit_size: 4 + variants: + - name: TRGO + description: TRGO Selected. + value: 0 + - name: TRG1 + description: adf_trg1 selected. + value: 2 diff --git a/data/registers/can_bxcan.yaml b/data/registers/can_bxcan.yaml index 34c639e..3788850 100644 --- a/data/registers/can_bxcan.yaml +++ b/data/registers/can_bxcan.yaml @@ -581,6 +581,15 @@ fieldset/TSR: array: len: 3 stride: 1 +enum/IDE: + bit_size: 1 + variants: + - name: Standard + description: Standard identifier + value: 0 + - name: Extended + description: Extended identifier + value: 1 enum/LEC: bit_size: 3 variants: @@ -608,15 +617,6 @@ enum/LEC: - name: Custom description: Set by software value: 7 -enum/IDE: - bit_size: 1 - variants: - - name: Standard - description: Standard identifier - value: 0 - - name: Extended - description: Extended identifier - value: 1 enum/RTR: bit_size: 1 variants: diff --git a/data/registers/can_fdcan_h7.yaml b/data/registers/can_fdcan_h7.yaml index a1095be..1080567 100644 --- a/data/registers/can_fdcan_h7.yaml +++ b/data/registers/can_fdcan_h7.yaml @@ -944,9 +944,6 @@ fieldset/RXFC: fieldset/RXFS: description: FDCAN Rx FIFO X Status Register fields: - # FIXME: RX FIFO 1 Status Register contains a DMS (debug message status) field - # (bits 31:30); how do we accommodate this? do we have to do away with the - # array def for these regs? - name: FFL description: Rx FIFO X Fill Level bit_offset: 0 diff --git a/data/registers/comp_v1.yaml b/data/registers/comp_v1.yaml index c3e29d9..0836e39 100644 --- a/data/registers/comp_v1.yaml +++ b/data/registers/comp_v1.yaml @@ -1,103 +1,103 @@ block/COMP: description: Comparator v1. (RM0444 18) items: - - name: CSR - description: Comparator control and status register. - byte_offset: 0 - fieldset: CSR + - name: CSR + description: Comparator control and status register. + byte_offset: 0 + fieldset: CSR fieldset/CSR: description: Comparator control and status register. fields: - - name: EN - description: COMP enable bit. - bit_offset: 0 - bit_size: 1 - - name: INMSEL - description: Comparator signal selector for inverting input INM. - bit_offset: 4 - bit_size: 4 - - name: INPSEL - description: Comparator signal selector for non-inverting input INP. - bit_offset: 8 - bit_size: 2 - - name: WINMODE - description: Comparator non-inverting input selector for window mode. - bit_offset: 11 - bit_size: 1 - - name: WINOUT - description: Comparator output selector. - bit_offset: 14 - bit_size: 1 - - name: POLARITY - description: Comparator polarity selector. - bit_offset: 15 - bit_size: 1 - enum: POLARITY - - name: HYST - description: Comparator hysteresis selector. - bit_offset: 16 - bit_size: 2 - enum: HYST - - name: PWRMODE - description: Comparator power mode selector. - bit_offset: 18 - bit_size: 2 - enum: PWRMODE - - name: BLANKSEL - description: Comparator blanking source selector. - bit_offset: 20 - bit_size: 5 - enum: BLANKSEL - - name: VALUE_DO_NOT_SET - description: Comparator output status. (READ ONLY) - bit_offset: 30 - bit_size: 1 - - name: LOCK - description: CSR register lock. - bit_offset: 31 - bit_size: 1 -enum/POLARITY: - bit_size: 1 - variants: - - name: NonInverted - value: 0 - - name: Inverted - value: 1 -enum/HYST: - bit_size: 2 - variants: - - name: None - value: 0 - - name: Low - value: 1 - - name: Medium - value: 2 - - name: High - value: 3 -enum/PWRMODE: - bit_size: 2 - variants: - - name: HighSpeed - value: 0 - - name: MediumSpeed - value: 1 + - name: EN + description: COMP enable bit. + bit_offset: 0 + bit_size: 1 + - name: INMSEL + description: Comparator signal selector for inverting input INM. + bit_offset: 4 + bit_size: 4 + - name: INPSEL + description: Comparator signal selector for non-inverting input INP. + bit_offset: 8 + bit_size: 2 + - name: WINMODE + description: Comparator non-inverting input selector for window mode. + bit_offset: 11 + bit_size: 1 + - name: WINOUT + description: Comparator output selector. + bit_offset: 14 + bit_size: 1 + - name: POLARITY + description: Comparator polarity selector. + bit_offset: 15 + bit_size: 1 + enum: POLARITY + - name: HYST + description: Comparator hysteresis selector. + bit_offset: 16 + bit_size: 2 + enum: HYST + - name: PWRMODE + description: Comparator power mode selector. + bit_offset: 18 + bit_size: 2 + enum: PWRMODE + - name: BLANKSEL + description: Comparator blanking source selector. + bit_offset: 20 + bit_size: 5 + enum: BLANKSEL + - name: VALUE_DO_NOT_SET + description: Comparator output status. (READ ONLY) + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: CSR register lock. + bit_offset: 31 + bit_size: 1 enum/BLANKSEL: bit_size: 5 variants: - - name: None - value: 0 - - name: Tim1Oc4 - description: TIM1 OC4 - value: 1 - - name: Tim1Oc5 - description: TIM1 OC5 - value: 2 - - name: Tim2Oc3 - description: TIM2 OC3 - value: 4 - - name: Tim3Oc3 - description: TIM3 OC3 - value: 8 - - name: Tim15Oc2 - description: TIM15 OC2 - value: 16 + - name: None + value: 0 + - name: Tim1Oc4 + description: TIM1 OC4 + value: 1 + - name: Tim1Oc5 + description: TIM1 OC5 + value: 2 + - name: Tim2Oc3 + description: TIM2 OC3 + value: 4 + - name: Tim3Oc3 + description: TIM3 OC3 + value: 8 + - name: Tim15Oc2 + description: TIM15 OC2 + value: 16 +enum/HYST: + bit_size: 2 + variants: + - name: None + value: 0 + - name: Low + value: 1 + - name: Medium + value: 2 + - name: High + value: 3 +enum/POLARITY: + bit_size: 1 + variants: + - name: NonInverted + value: 0 + - name: Inverted + value: 1 +enum/PWRMODE: + bit_size: 2 + variants: + - name: HighSpeed + value: 0 + - name: MediumSpeed + value: 1 diff --git a/data/registers/comp_v2.yaml b/data/registers/comp_v2.yaml index 0bef876..c7c2a61 100644 --- a/data/registers/comp_v2.yaml +++ b/data/registers/comp_v2.yaml @@ -50,38 +50,38 @@ fieldset/CSR: description: CSR register lock. bit_offset: 31 bit_size: 1 -enum/POLARITY: - bit_size: 1 - variants: - - name: NonInverted - description: Non-inverted polarity - value: 0 - - name: Inverted - description: Inverted polarity - value: 1 enum/HYST: bit_size: 3 variants: - - name: None - value: 0 - - name: Hyst10m - description: 10mV hysteresis - value: 1 - - name: Hyst20m - description: 20mV hysteresis - value: 2 - - name: Hyst30m - description: 30mV hysteresis - value: 3 - - name: Hyst40m - description: 40mV hysteresis - value: 4 - - name: Hyst50m - description: 50mV hysteresis - value: 5 - - name: Hyst60m - description: 60mV hysteresis - value: 6 - - name: Hyst70m - description: 70mV hysteresis - value: 7 \ No newline at end of file + - name: None + value: 0 + - name: Hyst10m + description: 10mV hysteresis + value: 1 + - name: Hyst20m + description: 20mV hysteresis + value: 2 + - name: Hyst30m + description: 30mV hysteresis + value: 3 + - name: Hyst40m + description: 40mV hysteresis + value: 4 + - name: Hyst50m + description: 50mV hysteresis + value: 5 + - name: Hyst60m + description: 60mV hysteresis + value: 6 + - name: Hyst70m + description: 70mV hysteresis + value: 7 +enum/POLARITY: + bit_size: 1 + variants: + - name: NonInverted + description: Non-inverted polarity + value: 0 + - name: Inverted + description: Inverted polarity + value: 1 diff --git a/data/registers/comp_v3.yaml b/data/registers/comp_v3.yaml index b0436bf..e129852 100644 --- a/data/registers/comp_v3.yaml +++ b/data/registers/comp_v3.yaml @@ -1,109 +1,109 @@ block/COMP: description: Comparator. items: - - name: CSR - description: Comparator control and status register. - byte_offset: 0 - fieldset: CSR + - name: CSR + description: Comparator control and status register. + byte_offset: 0 + fieldset: CSR fieldset/CSR: description: control and status register. fields: - - name: EN - description: Enable - bit_offset: 0 - bit_size: 1 - - name: PWRMODE - description: Power Mode. - bit_offset: 2 - bit_size: 2 - enum: PWRMODE - - name: INMSEL - description: Input minus selection bits. - bit_offset: 4 - bit_size: 3 - - name: INPSEL - description: Input plus selection bit. - bit_offset: 7 - bit_size: 2 - - name: POLARITY - description: Polarity selection bit. - bit_offset: 15 - bit_size: 1 - enum: POLARITY - - name: HYST - description: Hysteresis selection bits. - bit_offset: 16 - bit_size: 2 - enum: HYST - - name: BLANKING - description: Blanking source selection bits. - bit_offset: 18 - bit_size: 3 - enum: BLANKING - - name: BRGEN - description: Scaler bridge enable. - bit_offset: 22 - bit_size: 1 - - name: SCALEN - description: Voltage scaler enable bit. - bit_offset: 23 - bit_size: 1 - - name: INMESEL - description: Input minus extended selection bits. - bit_offset: 25 - bit_size: 2 - - name: VALUE - description: Output status bit. - bit_offset: 30 - bit_size: 1 - - name: LOCK - description: Register lock bit. - bit_offset: 31 - bit_size: 1 + - name: EN + description: Enable + bit_offset: 0 + bit_size: 1 + - name: PWRMODE + description: Power Mode. + bit_offset: 2 + bit_size: 2 + enum: PWRMODE + - name: INMSEL + description: Input minus selection bits. + bit_offset: 4 + bit_size: 3 + - name: INPSEL + description: Input plus selection bit. + bit_offset: 7 + bit_size: 2 + - name: POLARITY + description: Polarity selection bit. + bit_offset: 15 + bit_size: 1 + enum: POLARITY + - name: HYST + description: Hysteresis selection bits. + bit_offset: 16 + bit_size: 2 + enum: HYST + - name: BLANKING + description: Blanking source selection bits. + bit_offset: 18 + bit_size: 3 + enum: BLANKING + - name: BRGEN + description: Scaler bridge enable. + bit_offset: 22 + bit_size: 1 + - name: SCALEN + description: Voltage scaler enable bit. + bit_offset: 23 + bit_size: 1 + - name: INMESEL + description: Input minus extended selection bits. + bit_offset: 25 + bit_size: 2 + - name: VALUE + description: Output status bit. + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: Register lock bit. + bit_offset: 31 + bit_size: 1 enum/BLANKING: bit_size: 3 variants: - - name: NoBlanking - description: No blanking. - value: 0 - - name: TIM1OC5 - description: TIM1 OC5 selected as blanking source. - value: 1 - - name: TIM2OC3 - description: TIM2 OC3 selected as blanking source. - value: 2 + - name: NoBlanking + description: No blanking. + value: 0 + - name: TIM1OC5 + description: TIM1 OC5 selected as blanking source. + value: 1 + - name: TIM2OC3 + description: TIM2 OC3 selected as blanking source. + value: 2 enum/HYST: bit_size: 2 variants: - - name: None - value: 0 - - name: Low - value: 1 - - name: Medium - value: 2 - - name: High - value: 3 + - name: None + value: 0 + - name: Low + value: 1 + - name: Medium + value: 2 + - name: High + value: 3 enum/POLARITY: bit_size: 1 variants: - - name: NotInverted - description: Output is not inverted. - value: 0 - - name: Inverted - description: Output is inverted. - value: 1 + - name: NotInverted + description: Output is not inverted. + value: 0 + - name: Inverted + description: Output is inverted. + value: 1 enum/PWRMODE: bit_size: 2 variants: - - name: HighSpeed - description: High speed / full power. - value: 0 - - name: MediumSpeed - description: Medium speed / medium power. - value: 1 - - name: LowSpeed - description: Low speed / low power. - value: 2 - - name: VeryLowSpeed - description: Very-low speed / ultra-low power. - value: 3 + - name: HighSpeed + description: High speed / full power. + value: 0 + - name: MediumSpeed + description: Medium speed / medium power. + value: 1 + - name: LowSpeed + description: Low speed / low power. + value: 2 + - name: VeryLowSpeed + description: Very-low speed / ultra-low power. + value: 3 diff --git a/data/registers/cordic_v1.yaml b/data/registers/cordic_v1.yaml index 8887d72..7c65d5c 100644 --- a/data/registers/cordic_v1.yaml +++ b/data/registers/cordic_v1.yaml @@ -8,13 +8,9 @@ block/CORDIC: - name: WDATA description: Argument register. byte_offset: 4 - bit_offset: 0 - bit_size: 32 - name: RDATA description: Result register. byte_offset: 8 - bit_offset: 0 - bit_size: 32 fieldset/CSR: description: Control and status register. fields: @@ -184,4 +180,4 @@ enum/RESSIZE: value: 0 - name: Bits16 description: Use 16 bit output values. - value: 1 \ No newline at end of file + value: 1 diff --git a/data/registers/cryp_v1.yaml b/data/registers/cryp_v1.yaml index 2832b52..bad6bb6 100644 --- a/data/registers/cryp_v1.yaml +++ b/data/registers/cryp_v1.yaml @@ -1,165 +1,165 @@ block/CRYP: description: Cryptographic processor. items: - - name: CR - description: control register. - byte_offset: 0 - fieldset: CR - - name: SR - description: status register. - byte_offset: 4 - access: Read - fieldset: SR - - name: DIN - description: data input register. - byte_offset: 8 - - name: DOUT - description: data output register. - byte_offset: 12 - access: Read - - name: DMACR - description: DMA control register. - byte_offset: 16 - fieldset: DMACR - - name: IMSCR - description: interrupt mask set/clear register. - byte_offset: 20 - fieldset: IMSCR - - name: RISR - description: raw interrupt status register. - byte_offset: 24 - access: Read - fieldset: RISR - - name: MISR - description: masked interrupt status register. - byte_offset: 28 - access: Read - fieldset: MISR - - name: KEY - description: Cluster KEY%s, containing K?LR, K?RR. - array: - len: 4 - stride: 8 - byte_offset: 32 - block: KEY - - name: INIT - description: Cluster INIT%s, containing IV?LR, IV?RR. - array: - len: 2 - stride: 8 - byte_offset: 64 - block: INIT + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: DIN + description: data input register. + byte_offset: 8 + - name: DOUT + description: data output register. + byte_offset: 12 + access: Read + - name: DMACR + description: DMA control register. + byte_offset: 16 + fieldset: DMACR + - name: IMSCR + description: interrupt mask set/clear register. + byte_offset: 20 + fieldset: IMSCR + - name: RISR + description: raw interrupt status register. + byte_offset: 24 + access: Read + fieldset: RISR + - name: MISR + description: masked interrupt status register. + byte_offset: 28 + access: Read + fieldset: MISR + - name: KEY + description: Cluster KEY%s, containing K?LR, K?RR. + array: + len: 4 + stride: 8 + byte_offset: 32 + block: KEY + - name: INIT + description: Cluster INIT%s, containing IV?LR, IV?RR. + array: + len: 2 + stride: 8 + byte_offset: 64 + block: INIT block/INIT: description: Cluster INIT%s, containing IV?LR, IV?RR. items: - - name: IVLR - description: initialization vector registers. - byte_offset: 0 - - name: IVRR - description: initialization vector registers. - byte_offset: 4 + - name: IVLR + description: initialization vector registers. + byte_offset: 0 + - name: IVRR + description: initialization vector registers. + byte_offset: 4 block/KEY: description: Cluster KEY%s, containing K?LR, K?RR. items: - - name: KLR - description: key registers. - byte_offset: 0 - access: Write - - name: KRR - description: key registers. - byte_offset: 4 - access: Write + - name: KLR + description: key registers. + byte_offset: 0 + access: Write + - name: KRR + description: key registers. + byte_offset: 4 + access: Write fieldset/CR: description: control register. fields: - - name: ALGODIR - description: Algorithm direction. - bit_offset: 2 - bit_size: 1 - - name: ALGOMODE - description: Algorithm mode. - bit_offset: 3 - bit_size: 3 - - name: DATATYPE - description: Data type selection. - bit_offset: 6 - bit_size: 2 - - name: KEYSIZE - description: Key size selection (AES mode only). - bit_offset: 8 - bit_size: 2 - - name: FFLUSH - description: FIFO flush. - bit_offset: 14 - bit_size: 1 - - name: CRYPEN - description: Cryptographic processor enable. - bit_offset: 15 - bit_size: 1 + - name: ALGODIR + description: Algorithm direction. + bit_offset: 2 + bit_size: 1 + - name: ALGOMODE + description: Algorithm mode. + bit_offset: 3 + bit_size: 3 + - name: DATATYPE + description: Data type selection. + bit_offset: 6 + bit_size: 2 + - name: KEYSIZE + description: Key size selection (AES mode only). + bit_offset: 8 + bit_size: 2 + - name: FFLUSH + description: FIFO flush. + bit_offset: 14 + bit_size: 1 + - name: CRYPEN + description: Cryptographic processor enable. + bit_offset: 15 + bit_size: 1 fieldset/DMACR: description: DMA control register. fields: - - name: DIEN - description: DMA input enable. - bit_offset: 0 - bit_size: 1 - - name: DOEN - description: DMA output enable. - bit_offset: 1 - bit_size: 1 + - name: DIEN + description: DMA input enable. + bit_offset: 0 + bit_size: 1 + - name: DOEN + description: DMA output enable. + bit_offset: 1 + bit_size: 1 fieldset/IMSCR: description: interrupt mask set/clear register. fields: - - name: INIM - description: Input FIFO service interrupt mask. - bit_offset: 0 - bit_size: 1 - - name: OUTIM - description: Output FIFO service interrupt mask. - bit_offset: 1 - bit_size: 1 + - name: INIM + description: Input FIFO service interrupt mask. + bit_offset: 0 + bit_size: 1 + - name: OUTIM + description: Output FIFO service interrupt mask. + bit_offset: 1 + bit_size: 1 fieldset/MISR: description: masked interrupt status register. fields: - - name: INMIS - description: Input FIFO service masked interrupt status. - bit_offset: 0 - bit_size: 1 - - name: OUTMIS - description: Output FIFO service masked interrupt status. - bit_offset: 1 - bit_size: 1 + - name: INMIS + description: Input FIFO service masked interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTMIS + description: Output FIFO service masked interrupt status. + bit_offset: 1 + bit_size: 1 fieldset/RISR: description: raw interrupt status register. fields: - - name: INRIS - description: Input FIFO service raw interrupt status. - bit_offset: 0 - bit_size: 1 - - name: OUTRIS - description: Output FIFO service raw interrupt status. - bit_offset: 1 - bit_size: 1 + - name: INRIS + description: Input FIFO service raw interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTRIS + description: Output FIFO service raw interrupt status. + bit_offset: 1 + bit_size: 1 fieldset/SR: description: status register. fields: - - name: IFEM - description: Input FIFO empty. - bit_offset: 0 - bit_size: 1 - - name: IFNF - description: Input FIFO not full. - bit_offset: 1 - bit_size: 1 - - name: OFNE - description: Output FIFO not empty. - bit_offset: 2 - bit_size: 1 - - name: OFFU - description: Output FIFO full. - bit_offset: 3 - bit_size: 1 - - name: BUSY - description: Busy bit. - bit_offset: 4 - bit_size: 1 + - name: IFEM + description: Input FIFO empty. + bit_offset: 0 + bit_size: 1 + - name: IFNF + description: Input FIFO not full. + bit_offset: 1 + bit_size: 1 + - name: OFNE + description: Output FIFO not empty. + bit_offset: 2 + bit_size: 1 + - name: OFFU + description: Output FIFO full. + bit_offset: 3 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 4 + bit_size: 1 diff --git a/data/registers/cryp_v2.yaml b/data/registers/cryp_v2.yaml index 04df876..1694f97 100644 --- a/data/registers/cryp_v2.yaml +++ b/data/registers/cryp_v2.yaml @@ -1,185 +1,185 @@ block/CRYP: description: Cryptographic processor. items: - - name: CR - description: control register. - byte_offset: 0 - fieldset: CR - - name: SR - description: status register. - byte_offset: 4 - access: Read - fieldset: SR - - name: DIN - description: data input register. - byte_offset: 8 - - name: DOUT - description: data output register. - byte_offset: 12 - access: Read - - name: DMACR - description: DMA control register. - byte_offset: 16 - fieldset: DMACR - - name: IMSCR - description: interrupt mask set/clear register. - byte_offset: 20 - fieldset: IMSCR - - name: RISR - description: raw interrupt status register. - byte_offset: 24 - access: Read - fieldset: RISR - - name: MISR - description: masked interrupt status register. - byte_offset: 28 - access: Read - fieldset: MISR - - name: KEY - description: Cluster KEY%s, containing K?LR, K?RR. - array: - len: 4 - stride: 8 - byte_offset: 32 - block: KEY - - name: INIT - description: Cluster INIT%s, containing IV?LR, IV?RR. - array: - len: 2 - stride: 8 - byte_offset: 64 - block: INIT - - name: CSGCMCCMR - description: context swap register. - array: - len: 8 - stride: 4 - byte_offset: 80 - - name: CSGCMR - description: context swap register. - array: - len: 8 - stride: 4 - byte_offset: 112 + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: DIN + description: data input register. + byte_offset: 8 + - name: DOUT + description: data output register. + byte_offset: 12 + access: Read + - name: DMACR + description: DMA control register. + byte_offset: 16 + fieldset: DMACR + - name: IMSCR + description: interrupt mask set/clear register. + byte_offset: 20 + fieldset: IMSCR + - name: RISR + description: raw interrupt status register. + byte_offset: 24 + access: Read + fieldset: RISR + - name: MISR + description: masked interrupt status register. + byte_offset: 28 + access: Read + fieldset: MISR + - name: KEY + description: Cluster KEY%s, containing K?LR, K?RR. + array: + len: 4 + stride: 8 + byte_offset: 32 + block: KEY + - name: INIT + description: Cluster INIT%s, containing IV?LR, IV?RR. + array: + len: 2 + stride: 8 + byte_offset: 64 + block: INIT + - name: CSGCMCCMR + description: context swap register. + array: + len: 8 + stride: 4 + byte_offset: 80 + - name: CSGCMR + description: context swap register. + array: + len: 8 + stride: 4 + byte_offset: 112 block/INIT: description: Cluster INIT%s, containing IV?LR, IV?RR. items: - - name: IVLR - description: initialization vector registers. - byte_offset: 0 - - name: IVRR - description: initialization vector registers. - byte_offset: 4 + - name: IVLR + description: initialization vector registers. + byte_offset: 0 + - name: IVRR + description: initialization vector registers. + byte_offset: 4 block/KEY: description: Cluster KEY%s, containing K?LR, K?RR. items: - - name: KLR - description: key registers. - byte_offset: 0 - access: Write - - name: KRR - description: key registers. - byte_offset: 4 - access: Write + - name: KLR + description: key registers. + byte_offset: 0 + access: Write + - name: KRR + description: key registers. + byte_offset: 4 + access: Write fieldset/CR: description: control register. fields: - - name: ALGODIR - description: Algorithm direction. - bit_offset: 2 - bit_size: 1 - - name: ALGOMODE0 - description: Algorithm mode. - bit_offset: 3 - bit_size: 3 - - name: DATATYPE - description: Data type selection. - bit_offset: 6 - bit_size: 2 - - name: KEYSIZE - description: Key size selection (AES mode only). - bit_offset: 8 - bit_size: 2 - - name: FFLUSH - description: FIFO flush. - bit_offset: 14 - bit_size: 1 - - name: CRYPEN - description: Cryptographic processor enable. - bit_offset: 15 - bit_size: 1 - - name: GCM_CCMPH - description: GCM_CCMPH. - bit_offset: 16 - bit_size: 2 - - name: ALGOMODE3 - description: ALGOMODE. - bit_offset: 19 - bit_size: 1 + - name: ALGODIR + description: Algorithm direction. + bit_offset: 2 + bit_size: 1 + - name: ALGOMODE0 + description: Algorithm mode. + bit_offset: 3 + bit_size: 3 + - name: DATATYPE + description: Data type selection. + bit_offset: 6 + bit_size: 2 + - name: KEYSIZE + description: Key size selection (AES mode only). + bit_offset: 8 + bit_size: 2 + - name: FFLUSH + description: FIFO flush. + bit_offset: 14 + bit_size: 1 + - name: CRYPEN + description: Cryptographic processor enable. + bit_offset: 15 + bit_size: 1 + - name: GCM_CCMPH + description: GCM_CCMPH. + bit_offset: 16 + bit_size: 2 + - name: ALGOMODE3 + description: ALGOMODE. + bit_offset: 19 + bit_size: 1 fieldset/DMACR: description: DMA control register. fields: - - name: DIEN - description: DMA input enable. - bit_offset: 0 - bit_size: 1 - - name: DOEN - description: DMA output enable. - bit_offset: 1 - bit_size: 1 + - name: DIEN + description: DMA input enable. + bit_offset: 0 + bit_size: 1 + - name: DOEN + description: DMA output enable. + bit_offset: 1 + bit_size: 1 fieldset/IMSCR: description: interrupt mask set/clear register. fields: - - name: INIM - description: Input FIFO service interrupt mask. - bit_offset: 0 - bit_size: 1 - - name: OUTIM - description: Output FIFO service interrupt mask. - bit_offset: 1 - bit_size: 1 + - name: INIM + description: Input FIFO service interrupt mask. + bit_offset: 0 + bit_size: 1 + - name: OUTIM + description: Output FIFO service interrupt mask. + bit_offset: 1 + bit_size: 1 fieldset/MISR: description: masked interrupt status register. fields: - - name: INMIS - description: Input FIFO service masked interrupt status. - bit_offset: 0 - bit_size: 1 - - name: OUTMIS - description: Output FIFO service masked interrupt status. - bit_offset: 1 - bit_size: 1 + - name: INMIS + description: Input FIFO service masked interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTMIS + description: Output FIFO service masked interrupt status. + bit_offset: 1 + bit_size: 1 fieldset/RISR: description: raw interrupt status register. fields: - - name: INRIS - description: Input FIFO service raw interrupt status. - bit_offset: 0 - bit_size: 1 - - name: OUTRIS - description: Output FIFO service raw interrupt status. - bit_offset: 1 - bit_size: 1 + - name: INRIS + description: Input FIFO service raw interrupt status. + bit_offset: 0 + bit_size: 1 + - name: OUTRIS + description: Output FIFO service raw interrupt status. + bit_offset: 1 + bit_size: 1 fieldset/SR: description: status register. fields: - - name: IFEM - description: Input FIFO empty. - bit_offset: 0 - bit_size: 1 - - name: IFNF - description: Input FIFO not full. - bit_offset: 1 - bit_size: 1 - - name: OFNE - description: Output FIFO not empty. - bit_offset: 2 - bit_size: 1 - - name: OFFU - description: Output FIFO full. - bit_offset: 3 - bit_size: 1 - - name: BUSY - description: Busy bit. - bit_offset: 4 - bit_size: 1 + - name: IFEM + description: Input FIFO empty. + bit_offset: 0 + bit_size: 1 + - name: IFNF + description: Input FIFO not full. + bit_offset: 1 + bit_size: 1 + - name: OFNE + description: Output FIFO not empty. + bit_offset: 2 + bit_size: 1 + - name: OFFU + description: Output FIFO full. + bit_offset: 3 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 4 + bit_size: 1 diff --git a/data/registers/dac_v1.yaml b/data/registers/dac_v1.yaml index 517625f..c06e7ff 100644 --- a/data/registers/dac_v1.yaml +++ b/data/registers/dac_v1.yaml @@ -1,5 +1,3 @@ -# DAC v1, only used in RM0008 STM32F101/102/103/105/107. - block/DAC: description: Digital-to-analog converter items: diff --git a/data/registers/dac_v2.yaml b/data/registers/dac_v2.yaml index 94c369b..2d5ee17 100644 --- a/data/registers/dac_v2.yaml +++ b/data/registers/dac_v2.yaml @@ -1,6 +1,3 @@ -# DAC v2, used in F100, F0, F2, F4, F7, L0, L1. -# Adds SR with DMAUDR1/2 fields, and adds DMAUDRIE1/2 fields to CR. - block/DAC: description: Digital-to-analog converter items: diff --git a/data/registers/dac_v3.yaml b/data/registers/dac_v3.yaml index 3f30955..e01f4d9 100644 --- a/data/registers/dac_v3.yaml +++ b/data/registers/dac_v3.yaml @@ -1,8 +1,3 @@ -# DAC v3, only used in L4. -# Adds CCR, MCR, SHSR, SHHR, SHRR registers. -# Adds CEN fields to CR and BWST and CAL_FLAG fields to SR. -# Deletes BOFF fields from CR. - block/DAC: description: Digital-to-analog converter items: @@ -218,10 +213,10 @@ fieldset/MCR: description: DAC channel mode bit_offset: 0 bit_size: 3 - enum: MODE array: len: 2 stride: 16 + enum: MODE fieldset/SHHR: description: sample and hold hold time register fields: @@ -286,30 +281,30 @@ fieldset/SWTRIGR: enum/MODE: bit_size: 3 variants: - - name: NORMAL_EXT_BUFEN - description: Normal mode, external pin only, buffer enabled - value: 0 - - name: NORMAL_EXT_INT_BUFEN - description: Normal mode, external pin and internal peripherals, buffer enabled - value: 1 - - name: NORMAL_EXT_BUFDIS - description: Normal mode, external pin only, buffer disabled - value: 2 - - name: NORMAL_INT_BUFDIS - description: Normal mode, internal peripherals only, buffer disabled - value: 3 - - name: SAMPHOLD_EXT_BUFEN - description: Sample and hold mode, external pin only, buffer enabled - value: 4 - - name: SAMPHOLD_EXT_INT_BUFEN - description: Sample and hold mode, external pin and internal peripherals, buffer enabled - value: 5 - - name: SAMPHOLD_EXT_INT_BUFDIS - description: Sample and hold mode, external pin and internal peripherals, buffer disabled - value: 6 - - name: SAMPHOLD_INT_BUFDIS - description: Sample and hold mode, internal peripherals only, buffer disabled - value: 7 + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/dac_v4.yaml b/data/registers/dac_v4.yaml index 9a42d0c..07277bb 100644 --- a/data/registers/dac_v4.yaml +++ b/data/registers/dac_v4.yaml @@ -1,6 +1,3 @@ -# DAC v4, used in G0, H7, WL. -# Moves CR.TEN to bit 1, extends CR.TSEL to be 4 bits (2 to 5). - block/DAC: description: Digital-to-analog converter items: @@ -216,10 +213,10 @@ fieldset/MCR: description: DAC channel mode bit_offset: 0 bit_size: 3 - enum: MODE array: len: 2 stride: 16 + enum: MODE fieldset/SHHR: description: sample and hold hold time register fields: @@ -284,30 +281,30 @@ fieldset/SWTRIGR: enum/MODE: bit_size: 3 variants: - - name: NORMAL_EXT_BUFEN - description: Normal mode, external pin only, buffer enabled - value: 0 - - name: NORMAL_EXT_INT_BUFEN - description: Normal mode, external pin and internal peripherals, buffer enabled - value: 1 - - name: NORMAL_EXT_BUFDIS - description: Normal mode, external pin only, buffer disabled - value: 2 - - name: NORMAL_INT_BUFDIS - description: Normal mode, internal peripherals only, buffer disabled - value: 3 - - name: SAMPHOLD_EXT_BUFEN - description: Sample and hold mode, external pin only, buffer enabled - value: 4 - - name: SAMPHOLD_EXT_INT_BUFEN - description: Sample and hold mode, external pin and internal peripherals, buffer enabled - value: 5 - - name: SAMPHOLD_EXT_INT_BUFDIS - description: Sample and hold mode, external pin and internal peripherals, buffer disabled - value: 6 - - name: SAMPHOLD_INT_BUFDIS - description: Sample and hold mode, internal peripherals only, buffer disabled - value: 7 + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/dac_v5.yaml b/data/registers/dac_v5.yaml index 1a74a29..6999af6 100644 --- a/data/registers/dac_v5.yaml +++ b/data/registers/dac_v5.yaml @@ -1,6 +1,3 @@ -# DAC v5, used in L4+ and L5. -# Adds HFSEL field to CR. - block/DAC: description: Digital-to-analog converter items: @@ -220,10 +217,10 @@ fieldset/MCR: description: DAC channel mode bit_offset: 0 bit_size: 3 - enum: MODE array: len: 2 stride: 16 + enum: MODE fieldset/SHHR: description: sample and hold hold time register fields: @@ -288,30 +285,30 @@ fieldset/SWTRIGR: enum/MODE: bit_size: 3 variants: - - name: NORMAL_EXT_BUFEN - description: Normal mode, external pin only, buffer enabled - value: 0 - - name: NORMAL_EXT_INT_BUFEN - description: Normal mode, external pin and internal peripherals, buffer enabled - value: 1 - - name: NORMAL_EXT_BUFDIS - description: Normal mode, external pin only, buffer disabled - value: 2 - - name: NORMAL_INT_BUFDIS - description: Normal mode, internal peripherals only, buffer disabled - value: 3 - - name: SAMPHOLD_EXT_BUFEN - description: Sample and hold mode, external pin only, buffer enabled - value: 4 - - name: SAMPHOLD_EXT_INT_BUFEN - description: Sample and hold mode, external pin and internal peripherals, buffer enabled - value: 5 - - name: SAMPHOLD_EXT_INT_BUFDIS - description: Sample and hold mode, external pin and internal peripherals, buffer disabled - value: 6 - - name: SAMPHOLD_INT_BUFDIS - description: Sample and hold mode, internal peripherals only, buffer disabled - value: 7 + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/dac_v6.yaml b/data/registers/dac_v6.yaml index a4c748f..cb750fc 100644 --- a/data/registers/dac_v6.yaml +++ b/data/registers/dac_v6.yaml @@ -1,8 +1,3 @@ -# DAC v6, used in H5 and U5. -# Adds DMADOUBLE and SINFORMAT fields to MCR, DACRDY and DORSTAT fields to SR -# Adds B data fields to data holding registers -# Moves HFSEL from CR to MCR and makes it 2 bits. - block/DAC: description: Digital-to-analog converter items: @@ -234,10 +229,10 @@ fieldset/MCR: description: DAC channel mode bit_offset: 0 bit_size: 3 - enum: MODE array: len: 2 stride: 16 + enum: MODE - name: DMADOUBLE description: channel DMA double data mode. bit_offset: 8 @@ -341,30 +336,30 @@ fieldset/SWTRIGR: enum/MODE: bit_size: 3 variants: - - name: NORMAL_EXT_BUFEN - description: Normal mode, external pin only, buffer enabled - value: 0 - - name: NORMAL_EXT_INT_BUFEN - description: Normal mode, external pin and internal peripherals, buffer enabled - value: 1 - - name: NORMAL_EXT_BUFDIS - description: Normal mode, external pin only, buffer disabled - value: 2 - - name: NORMAL_INT_BUFDIS - description: Normal mode, internal peripherals only, buffer disabled - value: 3 - - name: SAMPHOLD_EXT_BUFEN - description: Sample and hold mode, external pin only, buffer enabled - value: 4 - - name: SAMPHOLD_EXT_INT_BUFEN - description: Sample and hold mode, external pin and internal peripherals, buffer enabled - value: 5 - - name: SAMPHOLD_EXT_INT_BUFDIS - description: Sample and hold mode, external pin and internal peripherals, buffer disabled - value: 6 - - name: SAMPHOLD_INT_BUFDIS - description: Sample and hold mode, internal peripherals only, buffer disabled - value: 7 + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/dac_v7.yaml b/data/registers/dac_v7.yaml index 4733672..941d21a 100644 --- a/data/registers/dac_v7.yaml +++ b/data/registers/dac_v7.yaml @@ -1,6 +1,3 @@ -# DAC v7, used in G4. -# Adds STR, STMODR for sawtooth control. - block/DAC: description: Digital-to-analog converter items: @@ -83,11 +80,11 @@ block/DAC: fieldset: SHRR - name: STR description: Sawtooth register - byte_offset: 88 - fieldset: STR array: len: 2 stride: 4 + byte_offset: 88 + fieldset: STR - name: STMODR description: Sawtooth Mode register byte_offset: 96 @@ -243,10 +240,10 @@ fieldset/MCR: description: DAC channel mode bit_offset: 0 bit_size: 3 - enum: MODE array: len: 2 stride: 16 + enum: MODE - name: DMADOUBLE description: channel DMA double data mode. bit_offset: 8 @@ -382,30 +379,30 @@ fieldset/SWTRIGR: enum/MODE: bit_size: 3 variants: - - name: NORMAL_EXT_BUFEN - description: Normal mode, external pin only, buffer enabled - value: 0 - - name: NORMAL_EXT_INT_BUFEN - description: Normal mode, external pin and internal peripherals, buffer enabled - value: 1 - - name: NORMAL_EXT_BUFDIS - description: Normal mode, external pin only, buffer disabled - value: 2 - - name: NORMAL_INT_BUFDIS - description: Normal mode, internal peripherals only, buffer disabled - value: 3 - - name: SAMPHOLD_EXT_BUFEN - description: Sample and hold mode, external pin only, buffer enabled - value: 4 - - name: SAMPHOLD_EXT_INT_BUFEN - description: Sample and hold mode, external pin and internal peripherals, buffer enabled - value: 5 - - name: SAMPHOLD_EXT_INT_BUFDIS - description: Sample and hold mode, external pin and internal peripherals, buffer disabled - value: 6 - - name: SAMPHOLD_INT_BUFDIS - description: Sample and hold mode, internal peripherals only, buffer disabled - value: 7 + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/eth_v1a.yaml b/data/registers/eth_v1a.yaml index 490d8ef..b2c8976 100644 --- a/data/registers/eth_v1a.yaml +++ b/data/registers/eth_v1a.yaml @@ -135,6 +135,20 @@ block/ETHERNET_MAC: description: Ethernet MAC address 0 low register byte_offset: 68 fieldset: MACA0LR + - name: MACAHR + description: Ethernet MAC address 1/2/3 high register + array: + len: 3 + stride: 8 + byte_offset: 72 + fieldset: MACAHR + - name: MACALR + description: Ethernet MAC address 1/2/3 low register + array: + len: 3 + stride: 8 + byte_offset: 76 + fieldset: MACALR - name: MMCCR description: Ethernet MMC control register byte_offset: 256 @@ -186,20 +200,6 @@ block/ETHERNET_MAC: byte_offset: 452 access: Read fieldset: MMCRGUFCR - - name: MACAHR - description: Ethernet MAC address 1/2/3 high register - array: - len: 3 - stride: 8 - byte_offset: 72 - fieldset: MACAHR - - name: MACALR - description: Ethernet MAC address 1/2/3 low register - array: - len: 3 - stride: 8 - byte_offset: 76 - fieldset: MACALR block/ETHERNET_PTP: description: 'Ethernet: Precision time protocol' items: diff --git a/data/registers/eth_v1b.yaml b/data/registers/eth_v1b.yaml index fa1e7d2..b303b9d 100644 --- a/data/registers/eth_v1b.yaml +++ b/data/registers/eth_v1b.yaml @@ -139,6 +139,20 @@ block/ETHERNET_MAC: description: Ethernet MAC address 0 low register byte_offset: 68 fieldset: MACA0LR + - name: MACAHR + description: Ethernet MAC address 1/2/3 high register + array: + len: 3 + stride: 8 + byte_offset: 72 + fieldset: MACAHR + - name: MACALR + description: Ethernet MAC address 1/2/3 low register + array: + len: 3 + stride: 8 + byte_offset: 76 + fieldset: MACALR - name: MMCCR description: Ethernet MMC control register byte_offset: 256 @@ -190,20 +204,6 @@ block/ETHERNET_MAC: byte_offset: 452 access: Read fieldset: MMCRGUFCR - - name: MACAHR - description: Ethernet MAC address 1/2/3 high register - array: - len: 3 - stride: 8 - byte_offset: 72 - fieldset: MACAHR - - name: MACALR - description: Ethernet MAC address 1/2/3 low register - array: - len: 3 - stride: 8 - byte_offset: 76 - fieldset: MACALR block/ETHERNET_PTP: description: 'Ethernet: Precision time protocol' items: diff --git a/data/registers/eth_v1c.yaml b/data/registers/eth_v1c.yaml index 63c2f4c..2109851 100644 --- a/data/registers/eth_v1c.yaml +++ b/data/registers/eth_v1c.yaml @@ -139,6 +139,20 @@ block/ETHERNET_MAC: description: Ethernet MAC address 0 low register byte_offset: 68 fieldset: MACA0LR + - name: MACAHR + description: Ethernet MAC address 1/2/3 high register + array: + len: 3 + stride: 8 + byte_offset: 72 + fieldset: MACAHR + - name: MACALR + description: Ethernet MAC address 1/2/3 low register + array: + len: 3 + stride: 8 + byte_offset: 76 + fieldset: MACALR - name: MMCCR description: Ethernet MMC control register byte_offset: 256 @@ -190,20 +204,6 @@ block/ETHERNET_MAC: byte_offset: 452 access: Read fieldset: MMCRGUFCR - - name: MACAHR - description: Ethernet MAC address 1/2/3 high register - array: - len: 3 - stride: 8 - byte_offset: 72 - fieldset: MACAHR - - name: MACALR - description: Ethernet MAC address 1/2/3 low register - array: - len: 3 - stride: 8 - byte_offset: 76 - fieldset: MACALR block/ETHERNET_PTP: description: 'Ethernet: Precision time protocol' items: diff --git a/data/registers/eth_v2.yaml b/data/registers/eth_v2.yaml index f0b98f7..4e17a0b 100644 --- a/data/registers/eth_v2.yaml +++ b/data/registers/eth_v2.yaml @@ -126,6 +126,13 @@ block/ETHERNET_MAC: description: Watchdog timeout register byte_offset: 12 fieldset: MACWTR + - name: MACHTR + description: Hash Table 0/1 register + array: + len: 2 + stride: 4 + byte_offset: 16 + fieldset: MACHTR - name: MACVTR description: VLAN tag register byte_offset: 80 @@ -224,6 +231,20 @@ block/ETHERNET_MAC: description: Address 0 low register byte_offset: 772 fieldset: MACA0LR + - name: MACAHR + description: Address 1/2/3 high register + array: + len: 3 + stride: 8 + byte_offset: 776 + fieldset: MACAHR + - name: MACALR + description: Address 1/2/3 low register + array: + len: 3 + stride: 8 + byte_offset: 780 + fieldset: MACALR - name: MMC_CONTROL description: MMC control register byte_offset: 1792 @@ -463,27 +484,6 @@ block/ETHERNET_MAC: description: Log message interval register byte_offset: 3024 fieldset: MACLMIR - - name: MACAHR - description: Address 1/2/3 high register - array: - len: 3 - stride: 8 - byte_offset: 776 - fieldset: MACAHR - - name: MACALR - description: Address 1/2/3 low register - array: - len: 3 - stride: 8 - byte_offset: 780 - fieldset: MACALR - - name: MACHTR - description: Hash Table 0/1 register - array: - len: 2 - stride: 4 - byte_offset: 16 - fieldset: MACHTR block/ETHERNET_MTL: description: 'Ethernet: MTL mode register (MTL)' items: diff --git a/data/registers/fdcanram_h7.yaml b/data/registers/fdcanram_h7.yaml index 3ea15da..6274e9e 100644 --- a/data/registers/fdcanram_h7.yaml +++ b/data/registers/fdcanram_h7.yaml @@ -7,4 +7,3 @@ block/FDCANRAM: len: 2560 stride: 4 byte_offset: 0 - bit_size: 32 diff --git a/data/registers/fdcanram_v1.yaml b/data/registers/fdcanram_v1.yaml index 73c2ee1..cc1aa69 100644 --- a/data/registers/fdcanram_v1.yaml +++ b/data/registers/fdcanram_v1.yaml @@ -7,39 +7,33 @@ block/FDCANRAM: len: 28 stride: 4 byte_offset: 0 - bit_size: 32 - name: FLESA description: 29-bit filter array: len: 16 stride: 4 byte_offset: 112 - bit_size: 32 - name: RXFIFO0 description: Rx FIFO 0 array: len: 54 stride: 4 byte_offset: 176 - bit_size: 32 - name: RXFIFO1 description: Rx FIFO 1 array: len: 54 stride: 4 byte_offset: 392 - bit_size: 32 - name: TXEFIFO description: Tx event FIFO array: len: 6 stride: 4 byte_offset: 608 - bit_size: 32 - name: TXBUF description: Tx buffer array: len: 54 stride: 4 byte_offset: 632 - bit_size: 32 diff --git a/data/registers/icache_v1.yaml b/data/registers/icache_v1.yaml index 72180ad..c0e4972 100644 --- a/data/registers/icache_v1.yaml +++ b/data/registers/icache_v1.yaml @@ -5,36 +5,6 @@ block/CRR: description: ICACHE control register. byte_offset: 0 fieldset: CRRX -fieldset/CRRX: - description: ICACHE region configuration register. - fields: - - name: BASEADDR - description: base address for region. - bit_offset: 0 - bit_size: 8 - - name: RSIZE - description: size for region. - bit_offset: 9 - bit_size: 3 - enum: RSIZE - - name: REN - description: enable for region. - bit_offset: 15 - bit_size: 1 - - name: REMAPADDR - description: remapped address for region. - bit_offset: 16 - bit_size: 11 - - name: MSTSEL - description: AHB cache master selection for region. - bit_offset: 28 - bit_size: 1 - enum: MSTSEL - - name: HBURST - description: output burst type for region. - bit_offset: 31 - bit_size: 1 - enum: HBURST block/ICACHE: description: Instruction Cache Control Registers. items: @@ -108,6 +78,36 @@ fieldset/CR: bit_offset: 19 bit_size: 1 enum: MISSMRST +fieldset/CRRX: + description: ICACHE region configuration register. + fields: + - name: BASEADDR + description: base address for region. + bit_offset: 0 + bit_size: 8 + - name: RSIZE + description: size for region. + bit_offset: 9 + bit_size: 3 + enum: RSIZE + - name: REN + description: enable for region. + bit_offset: 15 + bit_size: 1 + - name: REMAPADDR + description: remapped address for region. + bit_offset: 16 + bit_size: 11 + - name: MSTSEL + description: AHB cache master selection for region. + bit_offset: 28 + bit_size: 1 + enum: MSTSEL + - name: HBURST + description: output burst type for region. + bit_offset: 31 + bit_size: 1 + enum: HBURST fieldset/FCR: description: ICACHE flag clear register. fields: @@ -165,6 +165,32 @@ enum/CACHEINV: - name: Invalidate description: Invalidate entire cache value: 1 +enum/HBURST: + bit_size: 1 + variants: + - name: Wrap + value: 0 + - name: Increment + value: 1 +enum/HITMRST: + bit_size: 1 + variants: + - name: Reset + description: Reset cache hit monitor + value: 1 +enum/MISSMRST: + bit_size: 1 + variants: + - name: Reset + description: Reset cache miss monitor + value: 1 +enum/MSTSEL: + bit_size: 1 + variants: + - name: Master1Selected + value: 0 + - name: Master2Selected + value: 1 enum/RSIZE: bit_size: 3 variants: @@ -182,32 +208,6 @@ enum/RSIZE: value: 6 - name: OneTwentyEightMegabytes value: 7 -enum/HBURST: - bit_size: 1 - variants: - - name: Wrap - value: 0 - - name: Increment - value: 1 -enum/MSTSEL: - bit_size: 1 - variants: - - name: Master1Selected - value: 0 - - name: Master2Selected - value: 1 -enum/MISSMRST: - bit_size: 1 - variants: - - name: Reset - description: Reset cache miss monitor - value: 1 -enum/HITMRST: - bit_size: 1 - variants: - - name: Reset - description: Reset cache hit monitor - value: 1 enum/WAYSEL: bit_size: 1 variants: diff --git a/data/registers/opamp_g4.yaml b/data/registers/opamp_g4.yaml index 5b27243..a52b291 100644 --- a/data/registers/opamp_g4.yaml +++ b/data/registers/opamp_g4.yaml @@ -129,15 +129,6 @@ enum/FORCE_VP: - name: Calibration description: Calibration mode. Non-inverting input connected to calibration reference value: 1 -enum/OUTCAL: - bit_size: 1 - variants: - - name: Low - description: Non-inverting < inverting - value: 0 - - name: High - description: Non-inverting > inverting - value: 1 enum/OPAHSM: bit_size: 1 variants: @@ -156,6 +147,15 @@ enum/OPAINTOEN: - name: ADCChannel description: Output is connected internally to ADC channel value: 1 +enum/OUTCAL: + bit_size: 1 + variants: + - name: Low + description: Non-inverting < inverting + value: 0 + - name: High + description: Non-inverting > inverting + value: 1 enum/PGA_GAIN: bit_size: 5 variants: diff --git a/data/registers/rcc_f37.yaml b/data/registers/rcc_f37.yaml index dc8b054..befe368 100644 --- a/data/registers/rcc_f37.yaml +++ b/data/registers/rcc_f37.yaml @@ -499,7 +499,7 @@ fieldset/CFGR: bit_size: 1 enum: PLLSRC - name: PLLXTPRE - description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products." + description: 'HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products.' bit_offset: 17 bit_size: 1 enum: PLLXTPRE diff --git a/data/registers/rcc_f3v1.yaml b/data/registers/rcc_f3v1.yaml index 32a8076..52ab833 100644 --- a/data/registers/rcc_f3v1.yaml +++ b/data/registers/rcc_f3v1.yaml @@ -523,7 +523,7 @@ fieldset/CFGR: bit_size: 1 enum: PLLSRC - name: PLLXTPRE - description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products." + description: 'HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products.' bit_offset: 17 bit_size: 1 enum: PLLXTPRE diff --git a/data/registers/rcc_f3v2.yaml b/data/registers/rcc_f3v2.yaml index 68aecd4..8ba03bf 100644 --- a/data/registers/rcc_f3v2.yaml +++ b/data/registers/rcc_f3v2.yaml @@ -523,7 +523,7 @@ fieldset/CFGR: bit_size: 1 enum: PLLSRC - name: PLLXTPRE - description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products." + description: 'HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products.' bit_offset: 17 bit_size: 1 enum: PLLXTPRE diff --git a/data/registers/rcc_f3v3.yaml b/data/registers/rcc_f3v3.yaml index 211cd00..6ae1958 100644 --- a/data/registers/rcc_f3v3.yaml +++ b/data/registers/rcc_f3v3.yaml @@ -523,7 +523,7 @@ fieldset/CFGR: bit_size: 2 enum: PLLSRC - name: PLLXTPRE - description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products." + description: 'HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products.' bit_offset: 17 bit_size: 1 enum: PLLXTPRE diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml index 969ee68..47ca6c4 100644 --- a/data/registers/rcc_g4.yaml +++ b/data/registers/rcc_g4.yaml @@ -1353,6 +1353,15 @@ enum/ADCSEL: - name: SYS description: System clock selected as ADC clock value: 2 +enum/CLK48SEL: + bit_size: 2 + variants: + - name: HSI48 + description: HSI48 oscillator clock selected as 48 MHz clock + value: 0 + - name: PLL1_Q + description: PLLQCLK selected as 48 MHz clock + value: 2 enum/FDCANSEL: bit_size: 2 variants: @@ -1365,15 +1374,6 @@ enum/FDCANSEL: - name: PCLK1 description: PCLK used as FDCAN clock source value: 2 -enum/CLK48SEL: - bit_size: 2 - variants: - - name: HSI48 - description: HSI48 oscillator clock selected as 48 MHz clock - value: 0 - - name: PLL1_Q - description: PLLQCLK selected as 48 MHz clock - value: 2 enum/HPRE: bit_size: 4 variants: diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index e98446c..a29e2a5 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -5,14 +5,14 @@ block/RCC: description: clock control register byte_offset: 0 fieldset: CR - - name: ICSCR - description: RCC Internal Clock Source Calibration Register - byte_offset: 4 - fieldset: ICSCR - name: HSICFGR description: RCC HSI configuration register byte_offset: 4 fieldset: HSICFGR + - name: ICSCR + description: RCC Internal Clock Source Calibration Register + byte_offset: 4 + fieldset: ICSCR - name: CRRCR description: RCC Clock Recovery RC Register byte_offset: 8 @@ -554,14 +554,14 @@ fieldset/AHB3ENR: description: FMC Peripheral Clocks Enable bit_offset: 12 bit_size: 1 - - name: QUADSPIEN - description: QUADSPI and QUADSPI Delay Clock Enable - bit_offset: 14 - bit_size: 1 - name: OCTOSPI1EN description: OCTOSPI2 and OCTOSPI2 delay block enable bit_offset: 14 bit_size: 1 + - name: QUADSPIEN + description: QUADSPI and QUADSPI Delay Clock Enable + bit_offset: 14 + bit_size: 1 - name: SDMMC1EN description: SDMMC1 and SDMMC1 Delay Clock Enable bit_offset: 16 @@ -621,14 +621,14 @@ fieldset/AHB3LPENR: description: FMC Peripheral Clocks Enable During CSleep Mode bit_offset: 12 bit_size: 1 - - name: QUADSPILPEN - description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode - bit_offset: 14 - bit_size: 1 - name: OCTOSPI1LPEN description: OCTOSPI1 and OCTOSPI1 delay block enable during CSleep Mode bit_offset: 14 bit_size: 1 + - name: QUADSPILPEN + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 - name: SDMMC1LPEN description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode bit_offset: 16 @@ -684,14 +684,14 @@ fieldset/AHB3RSTR: description: FMC block reset bit_offset: 12 bit_size: 1 - - name: QUADSPIRST - description: QUADSPI and QUADSPI delay block reset - bit_offset: 14 - bit_size: 1 - name: OCTOSPI1RST description: OCTOSPI1 and OCTOSPI1 delay block reset bit_offset: 14 bit_size: 1 + - name: QUADSPIRST + description: QUADSPI and QUADSPI delay block reset + bit_offset: 14 + bit_size: 1 - name: SDMMC1RST description: SDMMC1 and SDMMC1 delay block reset bit_offset: 16 @@ -3062,13 +3062,13 @@ fieldset/D1CCIPR: bit_offset: 0 bit_size: 2 enum: FMCSEL - - name: QUADSPISEL - description: QUADSPI kernel clock source selection + - name: OCTOSPISEL + description: OCTOSPI kernel clock source selection bit_offset: 4 bit_size: 2 enum: FMCSEL - - name: OCTOSPISEL - description: OCTOSPI kernel clock source selection + - name: QUADSPISEL + description: QUADSPI kernel clock source selection bit_offset: 4 bit_size: 2 enum: FMCSEL diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index 12ee476..79fe6b4 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -5,14 +5,14 @@ block/RCC: description: clock control register byte_offset: 0 fieldset: CR - - name: ICSCR - description: RCC Internal Clock Source Calibration Register - byte_offset: 4 - fieldset: ICSCR - name: HSICFGR description: RCC HSI configuration register byte_offset: 4 fieldset: HSICFGR + - name: ICSCR + description: RCC Internal Clock Source Calibration Register + byte_offset: 4 + fieldset: ICSCR - name: CRRCR description: RCC Clock Recovery RC Register byte_offset: 8 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 904cf86..947f3c3 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1938,18 +1938,6 @@ enum/ADCSEL: - name: SYS description: SYSCLK clock selected value: 3 -enum/FDCANSEL: - bit_size: 2 - variants: - - name: HSE - description: HSE clock selected - value: 0 - - name: PLL1_Q - description: PLL "Q" clock selected - value: 1 - - name: PLLSAI1_P - description: PLLSAI "P" clock selected - value: 2 enum/CLK48SEL: bit_size: 2 variants: @@ -1965,6 +1953,18 @@ enum/CLK48SEL: - name: MSI description: MSI clock selected value: 3 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: HSE + description: HSE clock selected + value: 0 + - name: PLL1_Q + description: PLL "Q" clock selected + value: 1 + - name: PLLSAI1_P + description: PLLSAI "P" clock selected + value: 2 enum/HPRE: bit_size: 4 variants: diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml index 71382a0..a1b98ad 100644 --- a/data/registers/rcc_u5.yaml +++ b/data/registers/rcc_u5.yaml @@ -2568,21 +2568,6 @@ enum/HSPISEL: - name: PLL3_R description: PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz value: 3 -enum/ICLKSEL: - bit_size: 2 - variants: - - name: HSI48 - description: HSI48 clock selected - value: 0 - - name: PLL2_Q - description: PLL2 Q (pll2_q_ck) selected - value: 1 - - name: PLL1_Q - description: PLL1 Q (pll1_q_ck) selected - value: 2 - - name: MSIK - description: MSIK clock selected - value: 3 enum/I2CSEL: bit_size: 2 variants: @@ -2598,6 +2583,21 @@ enum/I2CSEL: - name: MSIK description: MSIK selected value: 3 +enum/ICLKSEL: + bit_size: 2 + variants: + - name: HSI48 + description: HSI48 clock selected + value: 0 + - name: PLL2_Q + description: PLL2 Q (pll2_q_ck) selected + value: 1 + - name: PLL1_Q + description: PLL1 Q (pll1_q_ck) selected + value: 2 + - name: MSIK + description: MSIK clock selected + value: 3 enum/LPTIMSEL: bit_size: 2 variants: diff --git a/data/registers/sdmmc_v1.yaml b/data/registers/sdmmc_v1.yaml index cb9263a..0494800 100644 --- a/data/registers/sdmmc_v1.yaml +++ b/data/registers/sdmmc_v1.yaml @@ -361,13 +361,6 @@ fieldset/POWER: description: PWRCTRL bit_offset: 0 bit_size: 2 -fieldset/RESPxR: - description: response 1..4 register - fields: - - name: CARDSTATUS - description: see Table 132 - bit_offset: 0 - bit_size: 32 fieldset/RESPCMDR: description: command response register fields: @@ -375,6 +368,13 @@ fieldset/RESPCMDR: description: Response command index bit_offset: 0 bit_size: 6 +fieldset/RESPxR: + description: response 1..4 register + fields: + - name: CARDSTATUS + description: see Table 132 + bit_offset: 0 + bit_size: 32 fieldset/STAR: description: status register fields: diff --git a/data/registers/sdmmc_v2.yaml b/data/registers/sdmmc_v2.yaml index a8710cc..c119115 100644 --- a/data/registers/sdmmc_v2.yaml +++ b/data/registers/sdmmc_v2.yaml @@ -501,13 +501,6 @@ fieldset/POWER: description: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00). bit_offset: 4 bit_size: 1 -fieldset/RESPxR: - description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. - fields: - - name: CARDSTATUS - description: see Table 432 - bit_offset: 0 - bit_size: 32 fieldset/RESPCMDR: description: SDMMC command response register fields: @@ -515,6 +508,13 @@ fieldset/RESPCMDR: description: Response command index bit_offset: 0 bit_size: 6 +fieldset/RESPxR: + description: The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response. + fields: + - name: CARDSTATUS + description: see Table 432 + bit_offset: 0 + bit_size: 32 fieldset/STAR: description: 'The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)' fields: diff --git a/data/registers/syscfg_f0.yaml b/data/registers/syscfg_f0.yaml index 9619f74..ded981b 100644 --- a/data/registers/syscfg_f0.yaml +++ b/data/registers/syscfg_f0.yaml @@ -25,7 +25,7 @@ fieldset/CFGR1: bit_size: 2 enum: MEM_MODE - name: PA11_PA12_RMP - description: | + description: |- PA11 and PA12 remapping bit for small packages (28 and 20 pins) 0: Pin pair PA9/PA10 mapped on the pins 1: Pin pair PA11/PA12 mapped instead of PA9/PA10 @@ -37,56 +37,56 @@ fieldset/CFGR1: bit_size: 2 enum: IR_MOD - name: ADC_DMA_RMP - description: | + description: |- ADC DMA remapping bit 0: ADC DMA request mapped on DMA channel 1 1: ADC DMA request mapped on DMA channel 2 bit_offset: 8 bit_size: 1 - name: USART1_TX_DMA_RMP - description: | + description: |- USART1_TX DMA remapping bit 0: USART1_TX DMA request mapped on DMA channel 2 1: USART1_TX DMA request mapped on DMA channel 4 bit_offset: 9 bit_size: 1 - name: USART1_RX_DMA_RMP - description: | + description: |- USART1_RX DMA request remapping bit 0: USART1_RX DMA request mapped on DMA channel 3 1: USART1_RX DMA request mapped on DMA channel 5 bit_offset: 10 bit_size: 1 - name: TIM16_DMA_RMP - description: | + description: |- TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 bit_offset: 11 bit_size: 1 - name: TIM17_DMA_RMP - description: | + description: |- TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 bit_offset: 12 bit_size: 1 - name: TIM16_DMA_RMP2 - description: | + description: |- TIM16 alternate DMA request remapping bit 0: TIM16 DMA request mapped according to TIM16_DMA_RMP bit 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 bit_offset: 13 bit_size: 1 - name: TIM17_DMA_RMP2 - description: | + description: |- TIM17 alternate DMA request remapping bit 0: TIM17 DMA request mapped according to TIM16_DMA_RMP bit 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 bit_offset: 14 bit_size: 1 - name: I2C_PB6_FMP - description: | + description: |- Fast Mode Plus (FM plus) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed @@ -94,7 +94,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C_PB7_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed @@ -102,7 +102,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C_PB8_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed @@ -110,7 +110,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C_PB9_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed @@ -118,7 +118,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C1_FMP - description: | + description: |- FM+ driving capability activation for I2C1 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers @@ -126,7 +126,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C2_FMP - description: | + description: |- FM+ driving capability activation for I2C2 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers @@ -134,7 +134,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C_PA9_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits 0: PA9 pin operate in standard mode 1: I2C FM+ mode enabled on PA9 and the Speed control is bypassed @@ -142,7 +142,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C_PA10_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits 0: PA10 pin operate in standard mode 1: I2C FM+ mode enabled on PA10 and the Speed control is bypassed @@ -150,49 +150,49 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: SPI2_DMA_RMP - description: | + description: |- SPI2 DMA request remapping bit 0: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively 1: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively bit_offset: 24 bit_size: 1 - name: USART2_DMA_RMP - description: | + description: |- USART2 DMA request remapping bit 0: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively 1: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively bit_offset: 25 bit_size: 1 - name: USART3_DMA_RMP - description: | + description: |- USART3 DMA request remapping bit 0: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) 1: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively bit_offset: 26 bit_size: 1 - name: I2C1_DMA_RMP - description: | + description: |- I2C1 DMA request remapping bit 0: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively 1: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively bit_offset: 27 bit_size: 1 - name: TIM1_DMA_RMP - description: | + description: |- TIM1 DMA request remapping bit 0: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively 1: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 bit_offset: 28 bit_size: 1 - name: TIM2_DMA_RMP - description: | + description: |- TIM2 DMA request remapping bit 0: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively 1: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 bit_offset: 29 bit_size: 1 - name: TIM3_DMA_RMP - description: | + description: |- TIM3 DMA request remapping bit 0: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 1: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 diff --git a/data/registers/syscfg_f3.yaml b/data/registers/syscfg_f3.yaml index 0fb3c1e..01b3bbc 100644 --- a/data/registers/syscfg_f3.yaml +++ b/data/registers/syscfg_f3.yaml @@ -37,105 +37,105 @@ fieldset/CFGR1: bit_size: 2 enum: MEM_MODE - name: USB_IT_RMP - description: | + description: |- USB interrupt remap 0: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively 1: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively bit_offset: 5 bit_size: 1 - name: TIM1_ITR3_RMP - description: | + description: |- Timer 1 ITR3 selection 0: Not remapped 1: TIM1_ITR3 = TIM17_OC bit_offset: 6 bit_size: 1 - name: DAC1_TRIG_RMP - description: | + description: |- DAC trigger remap (when TSEL = 001) 0: DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices 1: DAC trigger is TIM3_TRGO bit_offset: 7 bit_size: 1 - name: DAC_TRIG_RMP - description: | + description: |- DAC trigger remap (when TSEL = 001) 0: Not remapped 1: DAC trigger is TIM3_TRGO bit_offset: 7 bit_size: 1 - name: ADC2_DMA_RMP - description: | + description: |- ADC24 DMA remapping bit 0: ADC24 DMA requests mapped on DMA2 channels 1 and 2 1: ADC24 DMA requests mapped on DMA2 channels 3 and 4 bit_offset: 8 bit_size: 1 - name: TIM16_DMA_RMP - description: | + description: |- TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 bit_offset: 11 bit_size: 1 - name: TIM17_DMA_RMP - description: | + description: |- TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 bit_offset: 12 bit_size: 1 - name: TIM6_DAC1_CH1_DMA_RMP - description: | + description: |- TIM6 and DAC1 DMA request remapping bit 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - name: TIM6_DAC1_DMA_RMP - description: | + description: |- TIM6 and DAC1 DMA request remapping bit 0: TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 1: TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - name: TIM6_DAC1_OUT1_DMA_RMP - description: | + description: |- TIM6 and DAC1 DMA request remapping bit 0: TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3 1: TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3 bit_offset: 13 bit_size: 1 - name: TIM7_DAC1_CH2_DMA_RMP - description: | + description: |- TIM7 and DAC2 DMA request remapping bit 0: Not remapped 1: TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4 bit_offset: 14 bit_size: 1 - name: TIM7_DAC1_OUT2_DMA_RMP - description: | + description: |- TIM7 and DAC2 DMA request remapping bit 0: TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4 1: TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4 bit_offset: 14 bit_size: 1 - name: DAC2_CH1_DMA_RMP - description: | + description: |- DAC2 channel1 DMA remap 0: Not remapped 1: DAC2_CH1 DMA requests mapped on DMA1 channel 5 bit_offset: 15 bit_size: 1 - name: TIM18_DAC2_OUT1_DMA_RMP - description: | + description: |- TIM18 and DAC2_OUT1 DMA request remapping bit 0: TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5 1: TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5 bit_offset: 15 bit_size: 1 - name: I2C_PB6_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed @@ -143,7 +143,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C_PB7_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed @@ -151,7 +151,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C_PB8_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed @@ -159,7 +159,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C_PB9_FMP - description: | + description: |- Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed @@ -167,7 +167,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C1_FMP - description: | + description: |- I2C1 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits @@ -175,7 +175,7 @@ fieldset/CFGR1: bit_size: 1 enum: FMP - name: I2C2_FMP - description: | + description: |- I2C2 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits @@ -188,7 +188,7 @@ fieldset/CFGR1: bit_size: 2 enum: ENCODER_MODE - name: I2C3_FMP - description: | + description: |- I2C3 Fast Mode Plus 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits @@ -269,7 +269,7 @@ fieldset/CFGR3: bit_size: 1 enum: DAC1_TRIG3_RMP - name: DAC1_TRIG5_RMP - description: | + description: |- DAC1_CH1 / DAC1_CH2 Trigger remap 0: Not remapped 1: DAC trigger is HRTIM1_DAC1_TRIG2