diff --git a/data/registers/dbgmcu_h7.yaml b/data/registers/dbgmcu_h7.yaml new file mode 100644 index 0000000..9a826af --- /dev/null +++ b/data/registers/dbgmcu_h7.yaml @@ -0,0 +1,191 @@ +--- +block/DBGMCU: + description: Debug support + items: + - name: IDC + description: Identity code + byte_offset: 0 + access: Read + fieldset: IDC + - name: CR + description: Configuration register + byte_offset: 4 + fieldset: CR + - name: APB3FZ1 + description: APB3 peripheral freeze register + byte_offset: 52 + fieldset: APB3FZ1 + - name: APB1LFZ1 + description: APB1L peripheral freeze register + byte_offset: 60 + fieldset: APB1LFZ1 + - name: APB2FZ1 + description: APB2 peripheral freeze register + byte_offset: 76 + fieldset: APB2FZ1 + - name: APB4FZ1 + description: APB4 peripheral freeze register + byte_offset: 84 + fieldset: APB4FZ1 +fieldset/APB1LFZ1: + description: APB1L peripheral freeze register + fields: + - name: TIM2 + description: TIM2 stop in debug mode + bit_offset: 0 + bit_size: 1 + - name: TIM3 + description: TIM3 stop in debug mode + bit_offset: 1 + bit_size: 1 + - name: TIM4 + description: TIM4 stop in debug mode + bit_offset: 2 + bit_size: 1 + - name: TIM5 + description: TIM5 stop in debug mode + bit_offset: 3 + bit_size: 1 + - name: TIM6 + description: TIM6 stop in debug mode + bit_offset: 4 + bit_size: 1 + - name: TIM7 + description: TIM7 stop in debug mode + bit_offset: 5 + bit_size: 1 + - name: TIM12 + description: TIM12 stop in debug mode + bit_offset: 6 + bit_size: 1 + - name: TIM13 + description: TIM13 stop in debug mode + bit_offset: 7 + bit_size: 1 + - name: TIM14 + description: TIM14 stop in debug mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1 + description: LPTIM1 stop in debug mode + bit_offset: 9 + bit_size: 1 + - name: I2C1 + description: I2C1 SMBUS timeout stop in debug mode + bit_offset: 21 + bit_size: 1 + - name: I2C2 + description: I2C2 SMBUS timeout stop in debug mode + bit_offset: 22 + bit_size: 1 + - name: I2C3 + description: I2C3 SMBUS timeout stop in debug mode + bit_offset: 23 + bit_size: 1 +fieldset/APB2FZ1: + description: APB2 peripheral freeze register + fields: + - name: TIM1 + description: TIM1 stop in debug mode + bit_offset: 0 + bit_size: 1 + - name: TIM8 + description: TIM8 stop in debug mode + bit_offset: 1 + bit_size: 1 + - name: TIM15 + description: TIM15 stop in debug mode + bit_offset: 16 + bit_size: 1 + - name: TIM16 + description: TIM16 stop in debug mode + bit_offset: 17 + bit_size: 1 + - name: TIM17 + description: TIM17 stop in debug mode + bit_offset: 18 + bit_size: 1 + - name: HRTIM + description: HRTIM stop in debug mode + bit_offset: 29 + bit_size: 1 +fieldset/APB3FZ1: + description: APB3 peripheral freeze register + fields: + - name: WWDG1 + description: WWDG1 stop in debug mode + bit_offset: 6 + bit_size: 1 +fieldset/APB4FZ1: + description: APB4 peripheral freeze register + fields: + - name: I2C4 + description: I2C4 SMBUS timeout stop in debug mode + bit_offset: 7 + bit_size: 1 + - name: LPTIM2 + description: LPTIM2 stop in debug mode + bit_offset: 9 + bit_size: 1 + - name: LPTIM3 + description: LPTIM3 stop in debug mode + bit_offset: 10 + bit_size: 1 + - name: LPTIM4 + description: LPTIM4 stop in debug mode + bit_offset: 11 + bit_size: 1 + - name: LPTIM5 + description: LPTIM5 stop in debug mode + bit_offset: 12 + bit_size: 1 + - name: RTC + description: RTC stop in debug mode + bit_offset: 16 + bit_size: 1 + - name: IWDG1 + description: Independent watchdog for D1 stop in debug mode + bit_offset: 18 + bit_size: 1 +fieldset/CR: + description: Configuration register + fields: + - name: DBGSLEEP_D1 + description: Allow debug in D1 Sleep mode + bit_offset: 0 + bit_size: 1 + - name: DBGSTOP_D1 + description: Allow debug in D1 Stop mode + bit_offset: 1 + bit_size: 1 + - name: DBGSTBY_D1 + description: Allow debug in D1 Standby mode + bit_offset: 2 + bit_size: 1 + - name: TRACECLKEN + description: Trace clock enable enable + bit_offset: 20 + bit_size: 1 + - name: D1DBGCKEN + description: D1 debug clock enable enable + bit_offset: 21 + bit_size: 1 + - name: D3DBGCKEN + description: D3 debug clock enable enable + bit_offset: 22 + bit_size: 1 + - name: TRGOEN + description: External trigger output enable + bit_offset: 28 + bit_size: 1 +fieldset/IDC: + description: Identity code + fields: + - name: DEV_ID + description: Device ID + bit_offset: 0 + bit_size: 12 + - name: REV_ID + description: Revision ID + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/flash_h7.yaml b/data/registers/flash_h7.yaml new file mode 100644 index 0000000..28363b1 --- /dev/null +++ b/data/registers/flash_h7.yaml @@ -0,0 +1,637 @@ +--- +block/BANK: + description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R" + items: + - name: KEYR + description: FLASH key register for bank 1 + byte_offset: 0 + access: Write + fieldset: KEYR + - name: CR + description: FLASH control register for bank 1 + byte_offset: 8 + fieldset: CR + - name: SR + description: FLASH status register for bank 1 + byte_offset: 12 + fieldset: SR + - name: CCR + description: FLASH clear control register for bank 1 + byte_offset: 16 + fieldset: CCR + - name: PRAR_CUR + description: FLASH protection address for bank 1 + byte_offset: 36 + access: Read + fieldset: PRAR_CUR + - name: PRAR_PRG + description: FLASH protection address for bank 1 + byte_offset: 40 + fieldset: PRAR_PRG + - name: SCAR_CUR + description: FLASH secure address for bank 1 + byte_offset: 44 + fieldset: SCAR_CUR + - name: SCAR_PRG + description: FLASH secure address for bank 1 + byte_offset: 48 + fieldset: SCAR_PRG + - name: WPSN_CURR + description: FLASH write sector protection for bank 1 + byte_offset: 52 + access: Read + fieldset: WPSN_CURR + - name: WPSN_PRGR + description: FLASH write sector protection for bank 1 + byte_offset: 56 + fieldset: WPSN_PRGR + - name: CRCCR + description: FLASH CRC control register for bank 1 + byte_offset: 76 + fieldset: CRCCR + - name: CRCSADDR + description: FLASH CRC start address register for bank 1 + byte_offset: 80 + fieldset: CRCSADDR + - name: CRCEADDR + description: FLASH CRC end address register for bank 1 + byte_offset: 84 + fieldset: CRCEADDR + - name: FAR + description: FLASH ECC fail address for bank 1 + byte_offset: 92 + access: Read + fieldset: FAR +block/FLASH: + description: Flash + items: + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: BANK + description: "Cluster BANK%s, containing KEYR?, CR?, SR?, CCR?, PRAR_CUR?, PRAR_PRG?, SCAR_CUR?, SCAR_PRG?, WPSN_CUR?R, WPSN_PRG?R, CRCCR?, CRCSADD?R, CRCEADD?R, ECC_FA?R" + array: + len: 2 + stride: 256 + byte_offset: 4 + block: BANK + - name: OPTKEYR + description: FLASH option key register + byte_offset: 8 + fieldset: OPTKEYR + - name: OPTCR + description: FLASH option control register + byte_offset: 24 + fieldset: OPTCR + - name: OPTSR_CUR + description: FLASH option status register + byte_offset: 28 + fieldset: OPTSR_CUR + - name: OPTSR_PRG + description: FLASH option status register + byte_offset: 32 + fieldset: OPTSR_PRG + - name: OPTCCR + description: FLASH option clear control register + byte_offset: 36 + access: Write + fieldset: OPTCCR + - name: BOOT_CURR + description: FLASH register with boot address + byte_offset: 64 + access: Read + fieldset: BOOT_CURR + - name: BOOT_PRGR + description: FLASH register with boot address + byte_offset: 68 + fieldset: BOOT_PRGR + - name: CRCDATAR + description: FLASH CRC data register + byte_offset: 92 + fieldset: CRCDATAR +fieldset/ACR: + description: Access control register + fields: + - name: LATENCY + description: Read latency + bit_offset: 0 + bit_size: 3 + - name: WRHIGHFREQ + description: Flash signal delay + bit_offset: 4 + bit_size: 2 +fieldset/BOOT_CURR: + description: FLASH register with boot address + fields: + - name: BOOT_ADD0 + description: Boot address 0 + bit_offset: 0 + bit_size: 16 + - name: BOOT_ADD1 + description: Boot address 1 + bit_offset: 16 + bit_size: 16 +fieldset/BOOT_PRGR: + description: FLASH register with boot address + fields: + - name: BOOT_ADD0 + description: Boot address 0 + bit_offset: 0 + bit_size: 16 + - name: BOOT_ADD1 + description: Boot address 1 + bit_offset: 16 + bit_size: 16 +fieldset/CCR: + description: FLASH clear control register for bank 1 + fields: + - name: CLR_EOP + description: Bank 1 EOP1 flag clear bit + bit_offset: 16 + bit_size: 1 + - name: CLR_WRPERR + description: Bank 1 WRPERR1 flag clear bit + bit_offset: 17 + bit_size: 1 + - name: CLR_PGSERR + description: Bank 1 PGSERR1 flag clear bi + bit_offset: 18 + bit_size: 1 + - name: CLR_STRBERR + description: Bank 1 STRBERR1 flag clear bit + bit_offset: 19 + bit_size: 1 + - name: CLR_INCERR + description: Bank 1 INCERR1 flag clear bit + bit_offset: 21 + bit_size: 1 + - name: CLR_OPERR + description: Bank 1 OPERR1 flag clear bit + bit_offset: 22 + bit_size: 1 + - name: CLR_RDPERR + description: Bank 1 RDPERR1 flag clear bit + bit_offset: 23 + bit_size: 1 + - name: CLR_RDSERR + description: Bank 1 RDSERR1 flag clear bit + bit_offset: 24 + bit_size: 1 + - name: CLR_SNECCERR + description: Bank 1 SNECCERR1 flag clear bit + bit_offset: 25 + bit_size: 1 + - name: CLR_DBECCERR + description: Bank 1 DBECCERR1 flag clear bit + bit_offset: 26 + bit_size: 1 + - name: CLR_CRCEND + description: Bank 1 CRCEND1 flag clear bit + bit_offset: 27 + bit_size: 1 +fieldset/CR: + description: FLASH control register for bank 1 + fields: + - name: LOCK + description: Bank 1 configuration lock bit + bit_offset: 0 + bit_size: 1 + - name: PG + description: Bank 1 program enable bit + bit_offset: 1 + bit_size: 1 + - name: SER + description: Bank 1 sector erase request + bit_offset: 2 + bit_size: 1 + - name: BER + description: Bank 1 erase request + bit_offset: 3 + bit_size: 1 + - name: PSIZE + description: Bank 1 program size + bit_offset: 4 + bit_size: 2 + - name: FW + description: Bank 1 write forcing control bit + bit_offset: 6 + bit_size: 1 + - name: START + description: Bank 1 bank or sector erase start control bit + bit_offset: 7 + bit_size: 1 + - name: SNB + description: Bank 1 sector erase selection number + bit_offset: 8 + bit_size: 3 + - name: CRC_EN + description: Bank 1 CRC control bit + bit_offset: 15 + bit_size: 1 + - name: EOPIE + description: Bank 1 end-of-program interrupt control bit + bit_offset: 16 + bit_size: 1 + - name: WRPERRIE + description: Bank 1 write protection error interrupt enable bit + bit_offset: 17 + bit_size: 1 + - name: PGSERRIE + description: Bank 1 programming sequence error interrupt enable bit + bit_offset: 18 + bit_size: 1 + - name: STRBERRIE + description: Bank 1 strobe error interrupt enable bit + bit_offset: 19 + bit_size: 1 + - name: INCERRIE + description: Bank 1 inconsistency error interrupt enable bit + bit_offset: 21 + bit_size: 1 + - name: OPERRIE + description: Bank 1 write/erase error interrupt enable bit + bit_offset: 22 + bit_size: 1 + - name: RDPERRIE + description: Bank 1 read protection error interrupt enable bit + bit_offset: 23 + bit_size: 1 + - name: RDSERRIE + description: Bank 1 secure error interrupt enable bit + bit_offset: 24 + bit_size: 1 + - name: SNECCERRIE + description: Bank 1 ECC single correction error interrupt enable bit + bit_offset: 25 + bit_size: 1 + - name: DBECCERRIE + description: Bank 1 ECC double detection error interrupt enable bit + bit_offset: 26 + bit_size: 1 + - name: CRCENDIE + description: Bank 1 end of CRC calculation interrupt enable bit + bit_offset: 27 + bit_size: 1 +fieldset/CRCCR: + description: FLASH CRC control register for bank 1 + fields: + - name: CRC_SECT + description: Bank 1 CRC sector number + bit_offset: 0 + bit_size: 3 + - name: ALL_BANK + description: Bank 1 CRC select bit + bit_offset: 7 + bit_size: 1 + - name: CRC_BY_SECT + description: Bank 1 CRC sector mode select bit + bit_offset: 8 + bit_size: 1 + - name: ADD_SECT + description: Bank 1 CRC sector select bit + bit_offset: 9 + bit_size: 1 + - name: CLEAN_SECT + description: Bank 1 CRC sector list clear bit + bit_offset: 10 + bit_size: 1 + - name: START_CRC + description: Bank 1 CRC start bit + bit_offset: 16 + bit_size: 1 + - name: CLEAN_CRC + description: Bank 1 CRC clear bit + bit_offset: 17 + bit_size: 1 + - name: CRC_BURST + description: Bank 1 CRC burst size + bit_offset: 20 + bit_size: 2 +fieldset/CRCDATAR: + description: FLASH CRC data register + fields: + - name: CRC_DATA + description: CRC result + bit_offset: 0 + bit_size: 32 +fieldset/CRCEADDR: + description: FLASH CRC end address register for bank 1 + fields: + - name: CRC_END_ADDR + description: CRC end address on bank 1 + bit_offset: 0 + bit_size: 32 +fieldset/CRCSADDR: + description: FLASH CRC start address register for bank 1 + fields: + - name: CRC_START_ADDR + description: CRC start address on bank 1 + bit_offset: 0 + bit_size: 32 +fieldset/FAR: + description: FLASH ECC fail address for bank 1 + fields: + - name: FAIL_ECC_ADDR + description: Bank 1 ECC error address + bit_offset: 0 + bit_size: 15 +fieldset/KEYR: + description: FLASH key register for bank 1 + fields: + - name: KEYR + description: Bank 1 access configuration unlock key + bit_offset: 0 + bit_size: 32 +fieldset/OPTCCR: + description: FLASH option clear control register + fields: + - name: CLR_OPTCHANGEERR + description: OPTCHANGEERR reset bit + bit_offset: 30 + bit_size: 1 +fieldset/OPTCR: + description: FLASH option control register + fields: + - name: OPTLOCK + description: FLASH_OPTCR lock option configuration bit + bit_offset: 0 + bit_size: 1 + - name: OPTSTART + description: Option byte start change option configuration bit + bit_offset: 1 + bit_size: 1 + - name: MER + description: Flash mass erase enable bit + bit_offset: 4 + bit_size: 1 + - name: OPTCHANGEERRIE + description: Option byte change error interrupt enable bit + bit_offset: 30 + bit_size: 1 + - name: SWAP_BANK + description: Bank swapping configuration bit + bit_offset: 31 + bit_size: 1 +fieldset/OPTKEYR: + description: FLASH option key register + fields: + - name: OPTKEYR + description: Unlock key option bytes + bit_offset: 0 + bit_size: 32 +fieldset/OPTSR_CUR: + description: FLASH option status register + fields: + - name: OPT_BUSY + description: Option byte change ongoing flag + bit_offset: 0 + bit_size: 1 + - name: BOR_LEV + description: Brownout level option status bit + bit_offset: 2 + bit_size: 2 + - name: IWDG1_HW + description: IWDG1 control option status bit + bit_offset: 4 + bit_size: 1 + - name: nRST_STOP_D1 + description: D1 DStop entry reset option status bit + bit_offset: 6 + bit_size: 1 + - name: nRST_STBY_D1 + description: D1 DStandby entry reset option status bit + bit_offset: 7 + bit_size: 1 + - name: RDP + description: Readout protection level option status byte + bit_offset: 8 + bit_size: 8 + - name: FZ_IWDG_STOP + description: IWDG Stop mode freeze option status bit + bit_offset: 17 + bit_size: 1 + - name: FZ_IWDG_SDBY + description: IWDG Standby mode freeze option status bit + bit_offset: 18 + bit_size: 1 + - name: ST_RAM_SIZE + description: DTCM RAM size option status + bit_offset: 19 + bit_size: 2 + - name: SECURITY + description: Security enable option status bit + bit_offset: 21 + bit_size: 1 + - name: RSS1 + description: User option bit 1 + bit_offset: 26 + bit_size: 1 + - name: PERSO_OK + description: Device personalization status bit + bit_offset: 28 + bit_size: 1 + - name: IO_HSLV + description: I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V) + bit_offset: 29 + bit_size: 1 + - name: OPTCHANGEERR + description: Option byte change error flag + bit_offset: 30 + bit_size: 1 + - name: SWAP_BANK_OPT + description: Bank swapping option status bit + bit_offset: 31 + bit_size: 1 +fieldset/OPTSR_PRG: + description: FLASH option status register + fields: + - name: BOR_LEV + description: BOR reset level option configuration bits + bit_offset: 2 + bit_size: 2 + - name: IWDG1_HW + description: IWDG1 option configuration bit + bit_offset: 4 + bit_size: 1 + - name: nRST_STOP_D1 + description: Option byte erase after D1 DStop option configuration bit + bit_offset: 6 + bit_size: 1 + - name: nRST_STBY_D1 + description: Option byte erase after D1 DStandby option configuration bit + bit_offset: 7 + bit_size: 1 + - name: RDP + description: Readout protection level option configuration byte + bit_offset: 8 + bit_size: 8 + - name: FZ_IWDG_STOP + description: IWDG Stop mode freeze option configuration bit + bit_offset: 17 + bit_size: 1 + - name: FZ_IWDG_SDBY + description: IWDG Standby mode freeze option configuration bit + bit_offset: 18 + bit_size: 1 + - name: ST_RAM_SIZE + description: DTCM size select option configuration bits + bit_offset: 19 + bit_size: 2 + - name: SECURITY + description: Security option configuration bit + bit_offset: 21 + bit_size: 1 + - name: RSS1 + description: User option configuration bit 1 + bit_offset: 26 + bit_size: 1 + - name: RSS2 + description: User option configuration bit 2 + bit_offset: 27 + bit_size: 1 + - name: IO_HSLV + description: I/O high-speed at low-voltage (PRODUCT_BELOW_25V) + bit_offset: 29 + bit_size: 1 + - name: SWAP_BANK_OPT + description: Bank swapping option configuration bit + bit_offset: 31 + bit_size: 1 +fieldset/PRAR_CUR: + description: FLASH protection address for bank 1 + fields: + - name: PROT_AREA_START + description: Bank 1 lowest PCROP protected address + bit_offset: 0 + bit_size: 12 + - name: PROT_AREA_END + description: Bank 1 highest PCROP protected address + bit_offset: 16 + bit_size: 12 + - name: DMEP + description: Bank 1 PCROP protected erase enable option status bit + bit_offset: 31 + bit_size: 1 +fieldset/PRAR_PRG: + description: FLASH protection address for bank 1 + fields: + - name: PROT_AREA_START + description: Bank 1 lowest PCROP protected address configuration + bit_offset: 0 + bit_size: 12 + - name: PROT_AREA_END + description: Bank 1 highest PCROP protected address configuration + bit_offset: 16 + bit_size: 12 + - name: DMEP + description: Bank 1 PCROP protected erase enable option configuration bit + bit_offset: 31 + bit_size: 1 +fieldset/SCAR_CUR: + description: FLASH secure address for bank 1 + fields: + - name: SEC_AREA_START + description: Bank 1 lowest secure protected address + bit_offset: 0 + bit_size: 12 + - name: SEC_AREA_END + description: Bank 1 highest secure protected address + bit_offset: 16 + bit_size: 12 + - name: DMES + description: Bank 1 secure protected erase enable option status bit + bit_offset: 31 + bit_size: 1 +fieldset/SCAR_PRG: + description: FLASH secure address for bank 1 + fields: + - name: SEC_AREA_START + description: Bank 1 lowest secure protected address configuration + bit_offset: 0 + bit_size: 12 + - name: SEC_AREA_END + description: Bank 1 highest secure protected address configuration + bit_offset: 16 + bit_size: 12 + - name: DMES + description: Bank 1 secure protected erase enable option configuration bit + bit_offset: 31 + bit_size: 1 +fieldset/SR: + description: FLASH status register for bank 1 + fields: + - name: BSY + description: Bank 1 ongoing program flag + bit_offset: 0 + bit_size: 1 + - name: WBNE + description: Bank 1 write buffer not empty flag + bit_offset: 1 + bit_size: 1 + - name: QW + description: Bank 1 wait queue flag + bit_offset: 2 + bit_size: 1 + - name: CRC_BUSY + description: Bank 1 CRC busy flag + bit_offset: 3 + bit_size: 1 + - name: EOP + description: Bank 1 end-of-program flag + bit_offset: 16 + bit_size: 1 + - name: WRPERR + description: Bank 1 write protection error flag + bit_offset: 17 + bit_size: 1 + - name: PGSERR + description: Bank 1 programming sequence error flag + bit_offset: 18 + bit_size: 1 + - name: STRBERR + description: Bank 1 strobe error flag + bit_offset: 19 + bit_size: 1 + - name: INCERR + description: Bank 1 inconsistency error flag + bit_offset: 21 + bit_size: 1 + - name: OPERR + description: Bank 1 write/erase error flag + bit_offset: 22 + bit_size: 1 + - name: RDPERR + description: Bank 1 read protection error flag + bit_offset: 23 + bit_size: 1 + - name: RDSERR + description: Bank 1 secure error flag + bit_offset: 24 + bit_size: 1 + - name: SNECCERR1 + description: Bank 1 single correction error flag + bit_offset: 25 + bit_size: 1 + - name: DBECCERR + description: Bank 1 ECC double detection error flag + bit_offset: 26 + bit_size: 1 + - name: CRCEND + description: Bank 1 CRC-complete flag + bit_offset: 27 + bit_size: 1 +fieldset/WPSN_CURR: + description: FLASH write sector protection for bank 1 + fields: + - name: WRPSn + description: Bank 1 sector write protection option status byte + bit_offset: 0 + bit_size: 8 +fieldset/WPSN_PRGR: + description: FLASH write sector protection for bank 1 + fields: + - name: WRPSn + description: Bank 1 sector write protection configuration byte + bit_offset: 0 + bit_size: 8 diff --git a/data/registers/pwr_h7.yaml b/data/registers/pwr_h7.yaml new file mode 100644 index 0000000..9649635 --- /dev/null +++ b/data/registers/pwr_h7.yaml @@ -0,0 +1,252 @@ +--- +block/PWR: + description: PWR + items: + - name: CR1 + description: PWR control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CSR1 + description: PWR control status register 1 + byte_offset: 4 + access: Read + fieldset: CSR1 + - name: CR2 + description: "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection." + byte_offset: 8 + fieldset: CR2 + - name: CR3 + description: "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value." + byte_offset: 12 + fieldset: CR3 + - name: CPUCR + description: This register allows controlling CPU1 power. + byte_offset: 16 + fieldset: CPUCR + - name: D3CR + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + byte_offset: 24 + fieldset: D3CR + - name: WKUPCR + description: "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)." + byte_offset: 32 + fieldset: WKUPCR + - name: WKUPFR + description: "reset only by system reset, not reset by wakeup from Standby mode" + byte_offset: 36 + fieldset: WKUPFR + - name: WKUPEPR + description: "Reset only by system reset, not reset by wakeup from Standby mode" + byte_offset: 40 + fieldset: WKUPEPR +fieldset/CPUCR: + description: This register allows controlling CPU1 power. + fields: + - name: PDDS_D1 + description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain. + bit_offset: 0 + bit_size: 1 + - name: PDDS_D2 + description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain. + bit_offset: 1 + bit_size: 1 + - name: PDDS_D3 + description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain. + bit_offset: 2 + bit_size: 1 + - name: STOPF + description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit. + bit_offset: 5 + bit_size: 1 + - name: SBF + description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit + bit_offset: 6 + bit_size: 1 + - name: SBF_D1 + description: "D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode." + bit_offset: 7 + bit_size: 1 + - name: SBF_D2 + description: "D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode." + bit_offset: 8 + bit_size: 1 + - name: CSSF + description: "Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware." + bit_offset: 9 + bit_size: 1 + - name: RUN_D3 + description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes + bit_offset: 11 + bit_size: 1 +fieldset/CR1: + description: PWR control register 1 + fields: + - name: LPDS + description: "Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit)" + bit_offset: 0 + bit_size: 1 + - name: PVDE + description: Programmable voltage detector enable + bit_offset: 4 + bit_size: 1 + - name: PLS + description: "Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details." + bit_offset: 5 + bit_size: 3 + - name: DBP + description: "Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers." + bit_offset: 8 + bit_size: 1 + - name: FLPS + description: "Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode." + bit_offset: 9 + bit_size: 1 + - name: SVOS + description: "System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." + bit_offset: 14 + bit_size: 2 + - name: AVDEN + description: Peripheral voltage monitor on VDDA enable + bit_offset: 16 + bit_size: 1 + - name: ALS + description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD. + bit_offset: 17 + bit_size: 2 +fieldset/CR2: + description: "This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection." + fields: + - name: BREN + description: "Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes." + bit_offset: 0 + bit_size: 1 + - name: MONEN + description: "VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled." + bit_offset: 4 + bit_size: 1 + - name: BRRDY + description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready. + bit_offset: 16 + bit_size: 1 + - name: VBATL + description: VBAT level monitoring versus low threshold + bit_offset: 20 + bit_size: 1 + - name: VBATH + description: VBAT level monitoring versus high threshold + bit_offset: 21 + bit_size: 1 + - name: TEMPL + description: Temperature level monitoring versus low threshold + bit_offset: 22 + bit_size: 1 + - name: TEMPH + description: Temperature level monitoring versus high threshold + bit_offset: 23 + bit_size: 1 +fieldset/CR3: + description: "Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value." + fields: + - name: BYPASS + description: Power management unit bypass + bit_offset: 0 + bit_size: 1 + - name: LDOEN + description: Low drop-out regulator enable + bit_offset: 1 + bit_size: 1 + - name: SCUEN + description: SD converter Enable + bit_offset: 2 + bit_size: 1 + - name: VBE + description: VBAT charging enable + bit_offset: 8 + bit_size: 1 + - name: VBRS + description: VBAT charging resistor selection + bit_offset: 9 + bit_size: 1 + - name: USB33DEN + description: VDD33USB voltage level detector enable. + bit_offset: 24 + bit_size: 1 + - name: USBREGEN + description: USB regulator enable. + bit_offset: 25 + bit_size: 1 + - name: USB33RDY + description: USB supply ready. + bit_offset: 26 + bit_size: 1 +fieldset/CSR1: + description: PWR control status register 1 + fields: + - name: PVDO + description: "Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." + bit_offset: 4 + bit_size: 1 + - name: ACTVOSRDY + description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: ACTVOS + description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU. + bit_offset: 14 + bit_size: 2 + - name: AVDO + description: "Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set." + bit_offset: 16 + bit_size: 1 +fieldset/D3CR: + description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software + fields: + - name: VOSRDY + description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3). + bit_offset: 13 + bit_size: 1 + - name: VOS + description: "Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling." + bit_offset: 14 + bit_size: 2 +fieldset/WKUPCR: + description: "reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)." + fields: + - name: WKUPC + description: Clear Wakeup pin flag for WKUP. These bits are always read as 0. + bit_offset: 0 + bit_size: 6 +fieldset/WKUPEPR: + description: "Reset only by system reset, not reset by wakeup from Standby mode" + fields: + - name: WKUPEN + description: "Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPP + description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin. + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 1 + - name: WKUPPUPD + description: Wakeup pin pull configuration + bit_offset: 16 + bit_size: 2 + array: + len: 6 + stride: 2 +fieldset/WKUPFR: + description: "reset only by system reset, not reset by wakeup from Standby mode" + fields: + - name: WKUPF + description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR). + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 1 diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml new file mode 100644 index 0000000..34749b4 --- /dev/null +++ b/data/registers/rcc_h7.yaml @@ -0,0 +1,5232 @@ +--- +block/RCC: + description: Reset and clock control + items: + - name: CR + description: clock control register + byte_offset: 0 + fieldset: CR + - name: HSICFGR + description: RCC HSI configuration register + byte_offset: 4 + fieldset: HSICFGR + - name: ICSCR + description: RCC Internal Clock Source Calibration Register + byte_offset: 4 + fieldset: ICSCR + - name: CRRCR + description: RCC Clock Recovery RC Register + byte_offset: 8 + access: Read + fieldset: CRRCR + - name: CSICFGR + description: RCC CSI configuration register + byte_offset: 12 + fieldset: CSICFGR + - name: CFGR + description: RCC Clock Configuration Register + byte_offset: 16 + fieldset: CFGR + - name: D1CFGR + description: RCC Domain 1 Clock Configuration Register + byte_offset: 24 + fieldset: D1CFGR + - name: D2CFGR + description: RCC Domain 2 Clock Configuration Register + byte_offset: 28 + fieldset: D2CFGR + - name: D3CFGR + description: RCC Domain 3 Clock Configuration Register + byte_offset: 32 + fieldset: D3CFGR + - name: PLLCKSELR + description: RCC PLLs Clock Source Selection Register + byte_offset: 40 + fieldset: PLLCKSELR + - name: PLLCFGR + description: RCC PLLs Configuration Register + byte_offset: 44 + fieldset: PLLCFGR + - name: PLLDIVR + description: RCC PLL1 Dividers Configuration Register + array: + len: 3 + stride: 8 + byte_offset: 48 + fieldset: PLL1DIVR + - name: PLLFRACR + description: RCC PLL1 Fractional Divider Register + array: + len: 3 + stride: 8 + byte_offset: 52 + fieldset: PLL1FRACR + - name: D1CCIPR + description: RCC Domain 1 Kernel Clock Configuration Register + byte_offset: 76 + fieldset: D1CCIPR + - name: D2CCIP1R + description: RCC Domain 2 Kernel Clock Configuration Register + byte_offset: 80 + fieldset: D2CCIP1R + - name: D2CCIP2R + description: RCC Domain 2 Kernel Clock Configuration Register + byte_offset: 84 + fieldset: D2CCIP2R + - name: D3CCIPR + description: RCC Domain 3 Kernel Clock Configuration Register + byte_offset: 88 + fieldset: D3CCIPR + - name: CIER + description: RCC Clock Source Interrupt Enable Register + byte_offset: 96 + fieldset: CIER + - name: CIFR + description: RCC Clock Source Interrupt Flag Register + byte_offset: 100 + access: Read + fieldset: CIFR + - name: CICR + description: RCC Clock Source Interrupt Clear Register + byte_offset: 104 + fieldset: CICR + - name: BDCR + description: RCC Backup Domain Control Register + byte_offset: 112 + fieldset: BDCR + - name: CSR + description: RCC Clock Control and Status Register + byte_offset: 116 + fieldset: CSR + - name: AHB3RSTR + description: RCC AHB3 Reset Register + byte_offset: 124 + fieldset: AHB3RSTR + - name: AHB1RSTR + description: RCC AHB1 Peripheral Reset Register + byte_offset: 128 + fieldset: AHB1RSTR + - name: AHB2RSTR + description: RCC AHB2 Peripheral Reset Register + byte_offset: 132 + fieldset: AHB2RSTR + - name: AHB4RSTR + description: RCC AHB4 Peripheral Reset Register + byte_offset: 136 + fieldset: AHB4RSTR + - name: APB3RSTR + description: RCC APB3 Peripheral Reset Register + byte_offset: 140 + fieldset: APB3RSTR + - name: APB1LRSTR + description: RCC APB1 Peripheral Reset Register + byte_offset: 144 + fieldset: APB1LRSTR + - name: APB1HRSTR + description: RCC APB1 Peripheral Reset Register + byte_offset: 148 + fieldset: APB1HRSTR + - name: APB2RSTR + description: RCC APB2 Peripheral Reset Register + byte_offset: 152 + fieldset: APB2RSTR + - name: APB4RSTR + description: RCC APB4 Peripheral Reset Register + byte_offset: 156 + fieldset: APB4RSTR + - name: GCR + description: RCC Global Control Register + byte_offset: 160 + fieldset: GCR + - name: D3AMR + description: RCC D3 Autonomous mode Register + byte_offset: 168 + fieldset: D3AMR + - name: RSR + description: RCC Reset Status Register + byte_offset: 208 + fieldset: RSR + - name: AHB3ENR + description: RCC AHB3 Clock Register + byte_offset: 212 + fieldset: AHB3ENR + - name: AHB1ENR + description: RCC AHB1 Clock Register + byte_offset: 216 + fieldset: AHB1ENR + - name: AHB2ENR + description: RCC AHB2 Clock Register + byte_offset: 220 + fieldset: AHB2ENR + - name: AHB4ENR + description: RCC AHB4 Clock Register + byte_offset: 224 + fieldset: AHB4ENR + - name: APB3ENR + description: RCC APB3 Clock Register + byte_offset: 228 + fieldset: APB3ENR + - name: APB1LENR + description: RCC APB1 Clock Register + byte_offset: 232 + fieldset: APB1LENR + - name: APB1HENR + description: RCC APB1 Clock Register + byte_offset: 236 + fieldset: APB1HENR + - name: APB2ENR + description: RCC APB2 Clock Register + byte_offset: 240 + fieldset: APB2ENR + - name: APB4ENR + description: RCC APB4 Clock Register + byte_offset: 244 + fieldset: APB4ENR + - name: AHB3LPENR + description: RCC AHB3 Sleep Clock Register + byte_offset: 252 + fieldset: AHB3LPENR + - name: AHB1LPENR + description: RCC AHB1 Sleep Clock Register + byte_offset: 256 + fieldset: AHB1LPENR + - name: AHB2LPENR + description: RCC AHB2 Sleep Clock Register + byte_offset: 260 + fieldset: AHB2LPENR + - name: AHB4LPENR + description: RCC AHB4 Sleep Clock Register + byte_offset: 264 + fieldset: AHB4LPENR + - name: APB3LPENR + description: RCC APB3 Sleep Clock Register + byte_offset: 268 + fieldset: APB3LPENR + - name: APB1LLPENR + description: RCC APB1 Low Sleep Clock Register + byte_offset: 272 + fieldset: APB1LLPENR + - name: APB1HLPENR + description: RCC APB1 High Sleep Clock Register + byte_offset: 276 + fieldset: APB1HLPENR + - name: APB2LPENR + description: RCC APB2 Sleep Clock Register + byte_offset: 280 + fieldset: APB2LPENR + - name: APB4LPENR + description: RCC APB4 Sleep Clock Register + byte_offset: 284 + fieldset: APB4LPENR + - name: C1_RSR + description: RCC Reset Status Register + byte_offset: 304 + fieldset: C1_RSR + - name: C1_AHB3ENR + description: RCC AHB3 Clock Register + byte_offset: 308 + fieldset: C1_AHB3ENR + - name: C1_AHB1ENR + description: RCC AHB1 Clock Register + byte_offset: 312 + fieldset: C1_AHB1ENR + - name: C1_AHB2ENR + description: RCC AHB2 Clock Register + byte_offset: 316 + fieldset: C1_AHB2ENR + - name: C1_AHB4ENR + description: RCC AHB4 Clock Register + byte_offset: 320 + fieldset: C1_AHB4ENR + - name: C1_APB3ENR + description: RCC APB3 Clock Register + byte_offset: 324 + fieldset: C1_APB3ENR + - name: C1_APB1LENR + description: RCC APB1 Clock Register + byte_offset: 328 + fieldset: C1_APB1LENR + - name: C1_APB1HENR + description: RCC APB1 Clock Register + byte_offset: 332 + fieldset: C1_APB1HENR + - name: C1_APB2ENR + description: RCC APB2 Clock Register + byte_offset: 336 + fieldset: C1_APB2ENR + - name: C1_APB4ENR + description: RCC APB4 Clock Register + byte_offset: 340 + fieldset: C1_APB4ENR + - name: C1_AHB3LPENR + description: RCC AHB3 Sleep Clock Register + byte_offset: 348 + fieldset: C1_AHB3LPENR + - name: C1_AHB1LPENR + description: RCC AHB1 Sleep Clock Register + byte_offset: 352 + fieldset: C1_AHB1LPENR + - name: C1_AHB2LPENR + description: RCC AHB2 Sleep Clock Register + byte_offset: 356 + fieldset: C1_AHB2LPENR + - name: C1_AHB4LPENR + description: RCC AHB4 Sleep Clock Register + byte_offset: 360 + fieldset: C1_AHB4LPENR + - name: C1_APB3LPENR + description: RCC APB3 Sleep Clock Register + byte_offset: 364 + fieldset: C1_APB3LPENR + - name: C1_APB1LLPENR + description: RCC APB1 Low Sleep Clock Register + byte_offset: 368 + fieldset: C1_APB1LLPENR + - name: C1_APB1HLPENR + description: RCC APB1 High Sleep Clock Register + byte_offset: 372 + fieldset: C1_APB1HLPENR + - name: C1_APB2LPENR + description: RCC APB2 Sleep Clock Register + byte_offset: 376 + fieldset: C1_APB2LPENR + - name: C1_APB4LPENR + description: RCC APB4 Sleep Clock Register + byte_offset: 380 + fieldset: C1_APB4LPENR +fieldset/AHB1ENR: + description: RCC AHB1 Clock Register + fields: + - name: DMA1EN + description: DMA1 Clock Enable + bit_offset: 0 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: DMA2EN + description: DMA2 Clock Enable + bit_offset: 1 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: ADC12EN + description: ADC1/2 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: ETH1MACEN + description: Ethernet MAC bus interface Clock Enable + bit_offset: 15 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: ETH1TXEN + description: Ethernet Transmission Clock Enable + bit_offset: 16 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: ETH1RXEN + description: Ethernet Reception Clock Enable + bit_offset: 17 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: USB2OTGHSULPIEN + description: " Enable USB_PHY2 clocks " + bit_offset: 18 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: USB1OTGEN + description: USB1OTG Peripheral Clocks Enable + bit_offset: 25 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: USB1ULPIEN + description: USB_PHY1 Clocks Enable + bit_offset: 26 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: USB2OTGEN + description: USB2OTG Peripheral Clocks Enable + bit_offset: 27 + bit_size: 1 + enum: AHB1ENR_DMA1EN + - name: USB2ULPIEN + description: USB_PHY2 Clocks Enable + bit_offset: 28 + bit_size: 1 + enum: AHB1ENR_DMA1EN +fieldset/AHB1LPENR: + description: RCC AHB1 Sleep Clock Register + fields: + - name: DMA1LPEN + description: DMA1 Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: DMA2LPEN + description: DMA2 Clock Enable During CSleep Mode + bit_offset: 1 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: ADC12LPEN + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: ETH1MACLPEN + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: ETH1TXLPEN + description: Ethernet Transmission Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: ETH1RXLPEN + description: Ethernet Reception Clock Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: USB1OTGLPEN + description: USB1OTG peripheral clock enable during CSleep mode + bit_offset: 25 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: USB1OTGHSULPILPEN + description: USB_PHY1 clock enable during CSleep mode + bit_offset: 26 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: USB2OTGLPEN + description: USB2OTG peripheral clock enable during CSleep mode + bit_offset: 27 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN + - name: USB2OTGHSULPILPEN + description: USB_PHY2 clocks enable during CSleep mode + bit_offset: 28 + bit_size: 1 + enum: AHB1LPENR_DMA1LPEN +fieldset/AHB1RSTR: + description: RCC AHB1 Peripheral Reset Register + fields: + - name: DMA1RST + description: DMA1 block reset + bit_offset: 0 + bit_size: 1 + enum: DMA1RST + - name: DMA2RST + description: DMA2 block reset + bit_offset: 1 + bit_size: 1 + enum: DMA1RST + - name: ADC12RST + description: ADC1&2 block reset + bit_offset: 5 + bit_size: 1 + enum: DMA1RST + - name: ETH1MACRST + description: ETH1MAC block reset + bit_offset: 15 + bit_size: 1 + enum: DMA1RST + - name: USB1OTGRST + description: USB1OTG block reset + bit_offset: 25 + bit_size: 1 + enum: DMA1RST + - name: USB2OTGRST + description: USB2OTG block reset + bit_offset: 27 + bit_size: 1 + enum: DMA1RST +fieldset/AHB2ENR: + description: RCC AHB2 Clock Register + fields: + - name: DCMIEN + description: DCMI peripheral clock + bit_offset: 0 + bit_size: 1 + enum: AHB2ENR_DCMIEN + - name: CRYPTEN + description: CRYPT peripheral clock enable + bit_offset: 4 + bit_size: 1 + enum: AHB2ENR_DCMIEN + - name: HASHEN + description: HASH peripheral clock enable + bit_offset: 5 + bit_size: 1 + enum: AHB2ENR_DCMIEN + - name: RNGEN + description: RNG peripheral clocks enable + bit_offset: 6 + bit_size: 1 + enum: AHB2ENR_DCMIEN + - name: SDMMC2EN + description: SDMMC2 and SDMMC2 delay clock enable + bit_offset: 9 + bit_size: 1 + enum: AHB2ENR_DCMIEN + - name: SRAM1EN + description: SRAM1 block enable + bit_offset: 29 + bit_size: 1 + enum: AHB2ENR_DCMIEN + - name: SRAM2EN + description: SRAM2 block enable + bit_offset: 30 + bit_size: 1 + enum: AHB2ENR_DCMIEN + - name: SRAM3EN + description: SRAM3 block enable + bit_offset: 31 + bit_size: 1 + enum: AHB2ENR_DCMIEN +fieldset/AHB2LPENR: + description: RCC AHB2 Sleep Clock Register + fields: + - name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode + bit_offset: 0 + bit_size: 1 + enum: AHB2LPENR_DCMILPEN + - name: CRYPTLPEN + description: CRYPT peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + enum: AHB2LPENR_DCMILPEN + - name: HASHLPEN + description: HASH peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + enum: AHB2LPENR_DCMILPEN + - name: RNGLPEN + description: RNG peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + enum: AHB2LPENR_DCMILPEN + - name: SDMMC2LPEN + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + enum: AHB2LPENR_DCMILPEN + - name: SRAM1LPEN + description: SRAM1 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + enum: AHB2LPENR_DCMILPEN + - name: SRAM2LPEN + description: SRAM2 Clock Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + enum: AHB2LPENR_DCMILPEN + - name: SRAM3LPEN + description: SRAM3 Clock Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 + enum: AHB2LPENR_DCMILPEN +fieldset/AHB2RSTR: + description: RCC AHB2 Peripheral Reset Register + fields: + - name: CAMITFRST + description: CAMITF block reset + bit_offset: 0 + bit_size: 1 + enum: CAMITFRST + - name: CRYPTRST + description: Cryptography block reset + bit_offset: 4 + bit_size: 1 + enum: CAMITFRST + - name: HASHRST + description: Hash block reset + bit_offset: 5 + bit_size: 1 + enum: CAMITFRST + - name: RNGRST + description: Random Number Generator block reset + bit_offset: 6 + bit_size: 1 + enum: CAMITFRST + - name: SDMMC2RST + description: SDMMC2 and SDMMC2 Delay block reset + bit_offset: 9 + bit_size: 1 + enum: CAMITFRST +fieldset/AHB3ENR: + description: RCC AHB3 Clock Register + fields: + - name: MDMAEN + description: MDMA Peripheral Clock Enable + bit_offset: 0 + bit_size: 1 + enum: AHB3ENR_MDMAEN + - name: DMA2DEN + description: DMA2D Peripheral Clock Enable + bit_offset: 4 + bit_size: 1 + enum: AHB3ENR_MDMAEN + - name: JPGDECEN + description: JPGDEC Peripheral Clock Enable + bit_offset: 5 + bit_size: 1 + enum: AHB3ENR_MDMAEN + - name: FMCEN + description: FMC Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + enum: AHB3ENR_MDMAEN + - name: QSPIEN + description: QUADSPI and QUADSPI Delay Clock Enable + bit_offset: 14 + bit_size: 1 + enum: AHB3ENR_MDMAEN + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 Delay Clock Enable + bit_offset: 16 + bit_size: 1 + enum: AHB3ENR_MDMAEN +fieldset/AHB3LPENR: + description: RCC AHB3 Sleep Clock Register + fields: + - name: MDMALPEN + description: MDMA Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: DMA2DLPEN + description: DMA2D Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: JPGDECLPEN + description: JPGDEC Clock Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: FLASHLPEN + description: FLITF Clock Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: FMCLPEN + description: FMC Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: QSPILPEN + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: SDMMC1LPEN + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: D1DTCM1LPEN + description: D1DTCM1 Block Clock Enable During CSleep mode + bit_offset: 28 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: DTCM2LPEN + description: D1 DTCM2 Block Clock Enable During CSleep mode + bit_offset: 29 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: ITCMLPEN + description: D1ITCM Block Clock Enable During CSleep mode + bit_offset: 30 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN + - name: AXISRAMLPEN + description: AXISRAM Block Clock Enable During CSleep mode + bit_offset: 31 + bit_size: 1 + enum: AHB3LPENR_MDMALPEN +fieldset/AHB3RSTR: + description: RCC AHB3 Reset Register + fields: + - name: MDMARST + description: MDMA block reset + bit_offset: 0 + bit_size: 1 + enum: MDMARST + - name: DMA2DRST + description: DMA2D block reset + bit_offset: 4 + bit_size: 1 + enum: MDMARST + - name: JPGDECRST + description: JPGDEC block reset + bit_offset: 5 + bit_size: 1 + enum: MDMARST + - name: FMCRST + description: FMC block reset + bit_offset: 12 + bit_size: 1 + enum: MDMARST + - name: QSPIRST + description: QUADSPI and QUADSPI delay block reset + bit_offset: 14 + bit_size: 1 + enum: MDMARST + - name: SDMMC1RST + description: SDMMC1 and SDMMC1 delay block reset + bit_offset: 16 + bit_size: 1 + enum: MDMARST + - name: CPURST + description: CPU reset + bit_offset: 31 + bit_size: 1 + enum: MDMARST +fieldset/AHB4ENR: + description: RCC AHB4 Clock Register + fields: + - name: GPIOAEN + description: 0GPIO peripheral clock enable + bit_offset: 0 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOBEN + description: 0GPIO peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOCEN + description: 0GPIO peripheral clock enable + bit_offset: 2 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIODEN + description: 0GPIO peripheral clock enable + bit_offset: 3 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOEEN + description: 0GPIO peripheral clock enable + bit_offset: 4 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOFEN + description: 0GPIO peripheral clock enable + bit_offset: 5 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOGEN + description: 0GPIO peripheral clock enable + bit_offset: 6 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOHEN + description: 0GPIO peripheral clock enable + bit_offset: 7 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOIEN + description: 0GPIO peripheral clock enable + bit_offset: 8 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOJEN + description: 0GPIO peripheral clock enable + bit_offset: 9 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: GPIOKEN + description: 0GPIO peripheral clock enable + bit_offset: 10 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: CRCEN + description: CRC peripheral clock enable + bit_offset: 19 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: BDMAEN + description: BDMA and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: ADC3EN + description: ADC3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: HSEMEN + description: HSEM peripheral clock enable + bit_offset: 25 + bit_size: 1 + enum: AHB4ENR_GPIOAEN + - name: BKPRAMEN + description: Backup RAM Clock Enable + bit_offset: 28 + bit_size: 1 + enum: AHB4ENR_GPIOAEN +fieldset/AHB4LPENR: + description: RCC AHB4 Sleep Clock Register + fields: + - name: GPIOALPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOBLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOCLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIODLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOELPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOFLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOGLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOHLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOILPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOJLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 9 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: GPIOKLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 10 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: CRCLPEN + description: CRC peripheral clock enable during CSleep mode + bit_offset: 19 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: BDMALPEN + description: BDMA Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: ADC3LPEN + description: ADC3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: BKPRAMLPEN + description: Backup RAM Clock Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN + - name: SRAM4LPEN + description: SRAM4 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + enum: AHB4LPENR_GPIOALPEN +fieldset/AHB4RSTR: + description: RCC AHB4 Peripheral Reset Register + fields: + - name: GPIOARST + description: GPIO block reset + bit_offset: 0 + bit_size: 1 + enum: GPIOARST + - name: GPIOBRST + description: GPIO block reset + bit_offset: 1 + bit_size: 1 + enum: GPIOARST + - name: GPIOCRST + description: GPIO block reset + bit_offset: 2 + bit_size: 1 + enum: GPIOARST + - name: GPIODRST + description: GPIO block reset + bit_offset: 3 + bit_size: 1 + enum: GPIOARST + - name: GPIOERST + description: GPIO block reset + bit_offset: 4 + bit_size: 1 + enum: GPIOARST + - name: GPIOFRST + description: GPIO block reset + bit_offset: 5 + bit_size: 1 + enum: GPIOARST + - name: GPIOGRST + description: GPIO block reset + bit_offset: 6 + bit_size: 1 + enum: GPIOARST + - name: GPIOHRST + description: GPIO block reset + bit_offset: 7 + bit_size: 1 + enum: GPIOARST + - name: GPIOIRST + description: GPIO block reset + bit_offset: 8 + bit_size: 1 + enum: GPIOARST + - name: GPIOJRST + description: GPIO block reset + bit_offset: 9 + bit_size: 1 + enum: GPIOARST + - name: GPIOKRST + description: GPIO block reset + bit_offset: 10 + bit_size: 1 + enum: GPIOARST + - name: CRCRST + description: CRC block reset + bit_offset: 19 + bit_size: 1 + enum: GPIOARST + - name: BDMARST + description: BDMA block reset + bit_offset: 21 + bit_size: 1 + enum: GPIOARST + - name: ADC3RST + description: ADC3 block reset + bit_offset: 24 + bit_size: 1 + enum: GPIOARST + - name: HSEMRST + description: HSEM block reset + bit_offset: 25 + bit_size: 1 + enum: GPIOARST +fieldset/APB1HENR: + description: RCC APB1 Clock Register + fields: + - name: CRSEN + description: Clock Recovery System peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: APB1HENR_CRSEN + - name: SWPEN + description: SWPMI Peripheral Clocks Enable + bit_offset: 2 + bit_size: 1 + enum: APB1HENR_CRSEN + - name: OPAMPEN + description: OPAMP peripheral clock enable + bit_offset: 4 + bit_size: 1 + enum: APB1HENR_CRSEN + - name: MDIOSEN + description: MDIOS peripheral clock enable + bit_offset: 5 + bit_size: 1 + enum: APB1HENR_CRSEN + - name: FDCANEN + description: FDCAN Peripheral Clocks Enable + bit_offset: 8 + bit_size: 1 + enum: APB1HENR_CRSEN +fieldset/APB1HLPENR: + description: RCC APB1 High Sleep Clock Register + fields: + - name: CRSLPEN + description: Clock Recovery System peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: APB1HLPENR_CRSLPEN + - name: SWPLPEN + description: SWPMI Peripheral Clocks Enable During CSleep Mode + bit_offset: 2 + bit_size: 1 + enum: APB1HLPENR_CRSLPEN + - name: OPAMPLPEN + description: OPAMP peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + enum: APB1HLPENR_CRSLPEN + - name: MDIOSLPEN + description: MDIOS peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + enum: APB1HLPENR_CRSLPEN + - name: FDCANLPEN + description: FDCAN Peripheral Clocks Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + enum: APB1HLPENR_CRSLPEN +fieldset/APB1HRSTR: + description: RCC APB1 Peripheral Reset Register + fields: + - name: CRSRST + description: Clock Recovery System reset + bit_offset: 1 + bit_size: 1 + enum: CRSRST + - name: SWPRST + description: SWPMI block reset + bit_offset: 2 + bit_size: 1 + enum: CRSRST + - name: OPAMPRST + description: OPAMP block reset + bit_offset: 4 + bit_size: 1 + enum: CRSRST + - name: MDIOSRST + description: MDIOS block reset + bit_offset: 5 + bit_size: 1 + enum: CRSRST + - name: FDCANRST + description: FDCAN block reset + bit_offset: 8 + bit_size: 1 + enum: CRSRST +fieldset/APB1LENR: + description: RCC APB1 Clock Register + fields: + - name: TIM2EN + description: TIM peripheral clock enable + bit_offset: 0 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: TIM3EN + description: TIM peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: TIM4EN + description: TIM peripheral clock enable + bit_offset: 2 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: TIM5EN + description: TIM peripheral clock enable + bit_offset: 3 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: TIM6EN + description: TIM peripheral clock enable + bit_offset: 4 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: TIM7EN + description: TIM peripheral clock enable + bit_offset: 5 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: TIM12EN + description: TIM peripheral clock enable + bit_offset: 6 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: TIM13EN + description: TIM peripheral clock enable + bit_offset: 7 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: TIM14EN + description: TIM peripheral clock enable + bit_offset: 8 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: LPTIM1EN + description: LPTIM1 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: SPI2EN + description: SPI2 Peripheral Clocks Enable + bit_offset: 14 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: SPI3EN + description: SPI3 Peripheral Clocks Enable + bit_offset: 15 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: SPDIFRXEN + description: SPDIFRX Peripheral Clocks Enable + bit_offset: 16 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: USART2EN + description: USART2 Peripheral Clocks Enable + bit_offset: 17 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: USART3EN + description: USART3 Peripheral Clocks Enable + bit_offset: 18 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: UART4EN + description: UART4 Peripheral Clocks Enable + bit_offset: 19 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: UART5EN + description: UART5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: I2C1EN + description: I2C1 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: I2C2EN + description: I2C2 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: I2C3EN + description: I2C3 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: CECEN + description: HDMI-CEC peripheral clock enable + bit_offset: 27 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: DAC12EN + description: DAC1&2 peripheral clock enable + bit_offset: 29 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: UART7EN + description: UART7 Peripheral Clocks Enable + bit_offset: 30 + bit_size: 1 + enum: APB1LENR_TIM2EN + - name: UART8EN + description: UART8 Peripheral Clocks Enable + bit_offset: 31 + bit_size: 1 + enum: APB1LENR_TIM2EN +fieldset/APB1LLPENR: + description: RCC APB1 Low Sleep Clock Register + fields: + - name: TIM2LPEN + description: TIM2 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: TIM3LPEN + description: TIM3 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: TIM4LPEN + description: TIM4 peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: TIM5LPEN + description: TIM5 peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: TIM6LPEN + description: TIM6 peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: TIM7LPEN + description: TIM7 peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: TIM12LPEN + description: TIM12 peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: TIM13LPEN + description: TIM13 peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: TIM14LPEN + description: TIM14 peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: LPTIM1LPEN + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: SPI2LPEN + description: SPI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: SPI3LPEN + description: SPI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: SPDIFRXLPEN + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: USART2LPEN + description: USART2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: USART3LPEN + description: USART3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 18 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: UART4LPEN + description: UART4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 19 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: UART5LPEN + description: UART5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: I2C1LPEN + description: I2C1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: I2C2LPEN + description: I2C2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: I2C3LPEN + description: I2C3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: CECLPEN + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + bit_offset: 27 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: DAC12LPEN + description: DAC1/2 peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN + - name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 + enum: APB1LLPENR_TIM2LPEN +fieldset/APB1LRSTR: + description: RCC APB1 Peripheral Reset Register + fields: + - name: TIM2RST + description: TIM block reset + bit_offset: 0 + bit_size: 1 + enum: TIM2RST + - name: TIM3RST + description: TIM block reset + bit_offset: 1 + bit_size: 1 + enum: TIM2RST + - name: TIM4RST + description: TIM block reset + bit_offset: 2 + bit_size: 1 + enum: TIM2RST + - name: TIM5RST + description: TIM block reset + bit_offset: 3 + bit_size: 1 + enum: TIM2RST + - name: TIM6RST + description: TIM block reset + bit_offset: 4 + bit_size: 1 + enum: TIM2RST + - name: TIM7RST + description: TIM block reset + bit_offset: 5 + bit_size: 1 + enum: TIM2RST + - name: TIM12RST + description: TIM block reset + bit_offset: 6 + bit_size: 1 + enum: TIM2RST + - name: TIM13RST + description: TIM block reset + bit_offset: 7 + bit_size: 1 + enum: TIM2RST + - name: TIM14RST + description: TIM block reset + bit_offset: 8 + bit_size: 1 + enum: TIM2RST + - name: LPTIM1RST + description: TIM block reset + bit_offset: 9 + bit_size: 1 + enum: TIM2RST + - name: SPI2RST + description: SPI2 block reset + bit_offset: 14 + bit_size: 1 + enum: TIM2RST + - name: SPI3RST + description: SPI3 block reset + bit_offset: 15 + bit_size: 1 + enum: TIM2RST + - name: SPDIFRXRST + description: SPDIFRX block reset + bit_offset: 16 + bit_size: 1 + enum: TIM2RST + - name: USART2RST + description: USART2 block reset + bit_offset: 17 + bit_size: 1 + enum: TIM2RST + - name: USART3RST + description: USART3 block reset + bit_offset: 18 + bit_size: 1 + enum: TIM2RST + - name: UART4RST + description: UART4 block reset + bit_offset: 19 + bit_size: 1 + enum: TIM2RST + - name: UART5RST + description: UART5 block reset + bit_offset: 20 + bit_size: 1 + enum: TIM2RST + - name: I2C1RST + description: I2C1 block reset + bit_offset: 21 + bit_size: 1 + enum: TIM2RST + - name: I2C2RST + description: I2C2 block reset + bit_offset: 22 + bit_size: 1 + enum: TIM2RST + - name: I2C3RST + description: I2C3 block reset + bit_offset: 23 + bit_size: 1 + enum: TIM2RST + - name: CECRST + description: HDMI-CEC block reset + bit_offset: 27 + bit_size: 1 + enum: TIM2RST + - name: DAC12RST + description: DAC1 and 2 Blocks Reset + bit_offset: 29 + bit_size: 1 + enum: TIM2RST + - name: UART7RST + description: UART7 block reset + bit_offset: 30 + bit_size: 1 + enum: TIM2RST + - name: UART8RST + description: UART8 block reset + bit_offset: 31 + bit_size: 1 + enum: TIM2RST +fieldset/APB2ENR: + description: RCC APB2 Clock Register + fields: + - name: TIM1EN + description: TIM1 peripheral clock enable + bit_offset: 0 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: TIM8EN + description: TIM8 peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: USART1EN + description: USART1 Peripheral Clocks Enable + bit_offset: 4 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: USART6EN + description: USART6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: SPI1EN + description: SPI1 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: SPI4EN + description: SPI4 Peripheral Clocks Enable + bit_offset: 13 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: TIM15EN + description: TIM15 peripheral clock enable + bit_offset: 16 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: TIM16EN + description: TIM16 peripheral clock enable + bit_offset: 17 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: TIM17EN + description: TIM17 peripheral clock enable + bit_offset: 18 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: SPI5EN + description: SPI5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: SAI1EN + description: SAI1 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: SAI2EN + description: SAI2 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: SAI3EN + description: SAI3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: DFSDM1EN + description: DFSDM1 Peripheral Clocks Enable + bit_offset: 28 + bit_size: 1 + enum: APB2ENR_TIM1EN + - name: HRTIMEN + description: HRTIM peripheral clock enable + bit_offset: 29 + bit_size: 1 + enum: APB2ENR_TIM1EN +fieldset/APB2LPENR: + description: RCC APB2 Sleep Clock Register + fields: + - name: TIM1LPEN + description: TIM1 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: TIM8LPEN + description: TIM8 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: USART1LPEN + description: USART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: USART6LPEN + description: USART6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: SPI1LPEN + description: SPI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: SPI4LPEN + description: SPI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 13 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: TIM15LPEN + description: TIM15 peripheral clock enable during CSleep mode + bit_offset: 16 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: TIM16LPEN + description: TIM16 peripheral clock enable during CSleep mode + bit_offset: 17 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: TIM17LPEN + description: TIM17 peripheral clock enable during CSleep mode + bit_offset: 18 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: SPI5LPEN + description: SPI5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: SAI1LPEN + description: SAI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: SAI2LPEN + description: SAI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: SAI3LPEN + description: SAI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: DFSDM1LPEN + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN + - name: HRTIMLPEN + description: HRTIM peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + enum: APB2LPENR_TIM1LPEN +fieldset/APB2RSTR: + description: RCC APB2 Peripheral Reset Register + fields: + - name: TIM1RST + description: TIM1 block reset + bit_offset: 0 + bit_size: 1 + enum: TIM1RST + - name: TIM8RST + description: TIM8 block reset + bit_offset: 1 + bit_size: 1 + enum: TIM1RST + - name: USART1RST + description: USART1 block reset + bit_offset: 4 + bit_size: 1 + enum: TIM1RST + - name: USART6RST + description: USART6 block reset + bit_offset: 5 + bit_size: 1 + enum: TIM1RST + - name: SPI1RST + description: SPI1 block reset + bit_offset: 12 + bit_size: 1 + enum: TIM1RST + - name: SPI4RST + description: SPI4 block reset + bit_offset: 13 + bit_size: 1 + enum: TIM1RST + - name: TIM15RST + description: TIM15 block reset + bit_offset: 16 + bit_size: 1 + enum: TIM1RST + - name: TIM16RST + description: TIM16 block reset + bit_offset: 17 + bit_size: 1 + enum: TIM1RST + - name: TIM17RST + description: TIM17 block reset + bit_offset: 18 + bit_size: 1 + enum: TIM1RST + - name: SPI5RST + description: SPI5 block reset + bit_offset: 20 + bit_size: 1 + enum: TIM1RST + - name: SAI1RST + description: SAI1 block reset + bit_offset: 22 + bit_size: 1 + enum: TIM1RST + - name: SAI2RST + description: SAI2 block reset + bit_offset: 23 + bit_size: 1 + enum: TIM1RST + - name: SAI3RST + description: SAI3 block reset + bit_offset: 24 + bit_size: 1 + enum: TIM1RST + - name: DFSDM1RST + description: DFSDM1 block reset + bit_offset: 28 + bit_size: 1 + enum: TIM1RST + - name: HRTIMRST + description: HRTIM block reset + bit_offset: 29 + bit_size: 1 + enum: TIM1RST +fieldset/APB3ENR: + description: RCC APB3 Clock Register + fields: + - name: LTDCEN + description: LTDC peripheral clock enable + bit_offset: 3 + bit_size: 1 + enum: APB3ENR_LTDCEN + - name: WWDG1EN + description: WWDG1 Clock Enable + bit_offset: 6 + bit_size: 1 + enum: APB3ENR_LTDCEN +fieldset/APB3LPENR: + description: RCC APB3 Sleep Clock Register + fields: + - name: LTDCLPEN + description: LTDC peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + enum: APB3LPENR_LTDCLPEN + - name: WWDG1LPEN + description: WWDG1 Clock Enable During CSleep Mode + bit_offset: 6 + bit_size: 1 + enum: APB3LPENR_LTDCLPEN +fieldset/APB3RSTR: + description: RCC APB3 Peripheral Reset Register + fields: + - name: LTDCRST + description: LTDC block reset + bit_offset: 3 + bit_size: 1 + enum: LTDCRST +fieldset/APB4ENR: + description: RCC APB4 Clock Register + fields: + - name: SYSCFGEN + description: SYSCFG peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: LPUART1EN + description: LPUART1 Peripheral Clocks Enable + bit_offset: 3 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: SPI6EN + description: SPI6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: I2C4EN + description: I2C4 Peripheral Clocks Enable + bit_offset: 7 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: LPTIM2EN + description: LPTIM2 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: LPTIM3EN + description: LPTIM3 Peripheral Clocks Enable + bit_offset: 10 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: LPTIM4EN + description: LPTIM4 Peripheral Clocks Enable + bit_offset: 11 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: LPTIM5EN + description: LPTIM5 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: COMP12EN + description: COMP1/2 peripheral clock enable + bit_offset: 14 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: VREFEN + description: VREF peripheral clock enable + bit_offset: 15 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: RTCAPBEN + description: RTC APB Clock Enable + bit_offset: 16 + bit_size: 1 + enum: APB4ENR_SYSCFGEN + - name: SAI4EN + description: SAI4 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + enum: APB4ENR_SYSCFGEN +fieldset/APB4LPENR: + description: RCC APB4 Sleep Clock Register + fields: + - name: SYSCFGLPEN + description: SYSCFG peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: LPUART1LPEN + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 3 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: SPI6LPEN + description: SPI6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: I2C4LPEN + description: I2C4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 7 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: LPTIM2LPEN + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: LPTIM3LPEN + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 10 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: LPTIM4LPEN + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: LPTIM5LPEN + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: COMP12LPEN + description: COMP1/2 peripheral clock enable during CSleep mode + bit_offset: 14 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: VREFLPEN + description: VREF peripheral clock enable during CSleep mode + bit_offset: 15 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: RTCAPBLPEN + description: RTC APB Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN + - name: SAI4LPEN + description: SAI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + enum: APB4LPENR_SYSCFGLPEN +fieldset/APB4RSTR: + description: RCC APB4 Peripheral Reset Register + fields: + - name: SYSCFGRST + description: SYSCFG block reset + bit_offset: 1 + bit_size: 1 + enum: SYSCFGRST + - name: LPUART1RST + description: LPUART1 block reset + bit_offset: 3 + bit_size: 1 + enum: SYSCFGRST + - name: SPI6RST + description: SPI6 block reset + bit_offset: 5 + bit_size: 1 + enum: SYSCFGRST + - name: I2C4RST + description: I2C4 block reset + bit_offset: 7 + bit_size: 1 + enum: SYSCFGRST + - name: LPTIM2RST + description: LPTIM2 block reset + bit_offset: 9 + bit_size: 1 + enum: SYSCFGRST + - name: LPTIM3RST + description: LPTIM3 block reset + bit_offset: 10 + bit_size: 1 + enum: SYSCFGRST + - name: LPTIM4RST + description: LPTIM4 block reset + bit_offset: 11 + bit_size: 1 + enum: SYSCFGRST + - name: LPTIM5RST + description: LPTIM5 block reset + bit_offset: 12 + bit_size: 1 + enum: SYSCFGRST + - name: COMP12RST + description: COMP12 Blocks Reset + bit_offset: 14 + bit_size: 1 + enum: SYSCFGRST + - name: VREFRST + description: VREF block reset + bit_offset: 15 + bit_size: 1 + enum: SYSCFGRST + - name: SAI4RST + description: SAI4 block reset + bit_offset: 21 + bit_size: 1 + enum: SYSCFGRST +fieldset/BDCR: + description: RCC Backup Domain Control Register + fields: + - name: LSEON + description: LSE oscillator enabled + bit_offset: 0 + bit_size: 1 + enum: LSEON + - name: LSERDY + description: LSE oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSERDYR + - name: LSEBYP + description: LSE oscillator bypass + bit_offset: 2 + bit_size: 1 + enum: LSEBYP + - name: LSEDRV + description: LSE oscillator driving capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: LSECSSON + description: LSE clock security system enable + bit_offset: 5 + bit_size: 1 + enum: LSECSSON + - name: LSECSSD + description: LSE clock security system failure detection + bit_offset: 6 + bit_size: 1 + enum_read: LSECSSDR + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + enum: RTCEN + - name: BDRST + description: VSwitch domain software reset + bit_offset: 16 + bit_size: 1 + enum: BDRST +fieldset/C1_AHB1ENR: + description: RCC AHB1 Clock Register + fields: + - name: DMA1EN + description: DMA1 Clock Enable + bit_offset: 0 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: DMA2EN + description: DMA2 Clock Enable + bit_offset: 1 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: ADC12EN + description: ADC1/2 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: ETH1MACEN + description: Ethernet MAC bus interface Clock Enable + bit_offset: 15 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: ETH1TXEN + description: Ethernet Transmission Clock Enable + bit_offset: 16 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: ETH1RXEN + description: Ethernet Reception Clock Enable + bit_offset: 17 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: USB1OTGEN + description: USB1OTG Peripheral Clocks Enable + bit_offset: 25 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: USB1ULPIEN + description: USB_PHY1 Clocks Enable + bit_offset: 26 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: USB2OTGEN + description: USB2OTG Peripheral Clocks Enable + bit_offset: 27 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN + - name: USB2ULPIEN + description: USB_PHY2 Clocks Enable + bit_offset: 28 + bit_size: 1 + enum: C1_AHB1ENR_DMA1EN +fieldset/C1_AHB1LPENR: + description: RCC AHB1 Sleep Clock Register + fields: + - name: DMA1LPEN + description: DMA1 Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: DMA2LPEN + description: DMA2 Clock Enable During CSleep Mode + bit_offset: 1 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: ADC12LPEN + description: ADC1/2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: ETH1MACLPEN + description: Ethernet MAC bus interface Clock Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: ETH1TXLPEN + description: Ethernet Transmission Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: ETH1RXLPEN + description: Ethernet Reception Clock Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: USB1OTGLPEN + description: USB1OTG peripheral clock enable during CSleep mode + bit_offset: 25 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: USB1ULPILPEN + description: USB_PHY1 clock enable during CSleep mode + bit_offset: 26 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: USB2OTGLPEN + description: USB2OTG peripheral clock enable during CSleep mode + bit_offset: 27 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN + - name: USB2ULPILPEN + description: USB_PHY2 clocks enable during CSleep mode + bit_offset: 28 + bit_size: 1 + enum: C1_AHB1LPENR_DMA1LPEN +fieldset/C1_AHB2ENR: + description: RCC AHB2 Clock Register + fields: + - name: DCMIEN + description: DCMI peripheral clock + bit_offset: 0 + bit_size: 1 + enum: C1_AHB2ENR_DCMIEN + - name: CRYPTEN + description: CRYPT peripheral clock enable + bit_offset: 4 + bit_size: 1 + enum: C1_AHB2ENR_DCMIEN + - name: HASHEN + description: HASH peripheral clock enable + bit_offset: 5 + bit_size: 1 + enum: C1_AHB2ENR_DCMIEN + - name: RNGEN + description: RNG peripheral clocks enable + bit_offset: 6 + bit_size: 1 + enum: C1_AHB2ENR_DCMIEN + - name: SDMMC2EN + description: SDMMC2 and SDMMC2 delay clock enable + bit_offset: 9 + bit_size: 1 + enum: C1_AHB2ENR_DCMIEN + - name: SRAM1EN + description: SRAM1 block enable + bit_offset: 29 + bit_size: 1 + enum: C1_AHB2ENR_DCMIEN + - name: SRAM2EN + description: SRAM2 block enable + bit_offset: 30 + bit_size: 1 + enum: C1_AHB2ENR_DCMIEN + - name: SRAM3EN + description: SRAM3 block enable + bit_offset: 31 + bit_size: 1 + enum: C1_AHB2ENR_DCMIEN +fieldset/C1_AHB2LPENR: + description: RCC AHB2 Sleep Clock Register + fields: + - name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode + bit_offset: 0 + bit_size: 1 + enum: C1_AHB2LPENR_DCMILPEN + - name: CRYPTLPEN + description: CRYPT peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + enum: C1_AHB2LPENR_DCMILPEN + - name: HASHLPEN + description: HASH peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + enum: C1_AHB2LPENR_DCMILPEN + - name: RNGLPEN + description: RNG peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + enum: C1_AHB2LPENR_DCMILPEN + - name: SDMMC2LPEN + description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + enum: C1_AHB2LPENR_DCMILPEN + - name: SRAM1LPEN + description: SRAM1 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + enum: C1_AHB2LPENR_DCMILPEN + - name: SRAM2LPEN + description: SRAM2 Clock Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + enum: C1_AHB2LPENR_DCMILPEN + - name: SRAM3LPEN + description: SRAM3 Clock Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 + enum: C1_AHB2LPENR_DCMILPEN +fieldset/C1_AHB3ENR: + description: RCC AHB3 Clock Register + fields: + - name: MDMAEN + description: MDMA Peripheral Clock Enable + bit_offset: 0 + bit_size: 1 + enum: C1_AHB3ENR_MDMAEN + - name: DMA2DEN + description: DMA2D Peripheral Clock Enable + bit_offset: 4 + bit_size: 1 + enum: C1_AHB3ENR_MDMAEN + - name: JPGDECEN + description: JPGDEC Peripheral Clock Enable + bit_offset: 5 + bit_size: 1 + enum: C1_AHB3ENR_MDMAEN + - name: FMCEN + description: FMC Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + enum: C1_AHB3ENR_MDMAEN + - name: QSPIEN + description: QUADSPI and QUADSPI Delay Clock Enable + bit_offset: 14 + bit_size: 1 + enum: C1_AHB3ENR_MDMAEN + - name: SDMMC1EN + description: SDMMC1 and SDMMC1 Delay Clock Enable + bit_offset: 16 + bit_size: 1 + enum: C1_AHB3ENR_MDMAEN +fieldset/C1_AHB3LPENR: + description: RCC AHB3 Sleep Clock Register + fields: + - name: MDMALPEN + description: MDMA Clock Enable During CSleep Mode + bit_offset: 0 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: DMA2DLPEN + description: DMA2D Clock Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: JPGDECLPEN + description: JPGDEC Clock Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: FLASHPREN + description: Flash interface clock enable during csleep mode + bit_offset: 8 + bit_size: 1 + - name: FMCLPEN + description: FMC Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: QSPILPEN + description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: SDMMC1LPEN + description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: D1DTCM1LPEN + description: D1DTCM1 Block Clock Enable During CSleep mode + bit_offset: 28 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: DTCM2LPEN + description: D1 DTCM2 Block Clock Enable During CSleep mode + bit_offset: 29 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: ITCMLPEN + description: D1ITCM Block Clock Enable During CSleep mode + bit_offset: 30 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN + - name: AXISRAMLPEN + description: AXISRAM Block Clock Enable During CSleep mode + bit_offset: 31 + bit_size: 1 + enum: C1_AHB3LPENR_MDMALPEN +fieldset/C1_AHB4ENR: + description: RCC AHB4 Clock Register + fields: + - name: GPIOAEN + description: 0GPIO peripheral clock enable + bit_offset: 0 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOBEN + description: 0GPIO peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOCEN + description: 0GPIO peripheral clock enable + bit_offset: 2 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIODEN + description: 0GPIO peripheral clock enable + bit_offset: 3 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOEEN + description: 0GPIO peripheral clock enable + bit_offset: 4 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOFEN + description: 0GPIO peripheral clock enable + bit_offset: 5 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOGEN + description: 0GPIO peripheral clock enable + bit_offset: 6 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOHEN + description: 0GPIO peripheral clock enable + bit_offset: 7 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOIEN + description: 0GPIO peripheral clock enable + bit_offset: 8 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOJEN + description: 0GPIO peripheral clock enable + bit_offset: 9 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: GPIOKEN + description: 0GPIO peripheral clock enable + bit_offset: 10 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: CRCEN + description: CRC peripheral clock enable + bit_offset: 19 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: BDMAEN + description: BDMA and DMAMUX2 Clock Enable + bit_offset: 21 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: ADC3EN + description: ADC3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: HSEMEN + description: HSEM peripheral clock enable + bit_offset: 25 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN + - name: BKPRAMEN + description: Backup RAM Clock Enable + bit_offset: 28 + bit_size: 1 + enum: C1_AHB4ENR_GPIOAEN +fieldset/C1_AHB4LPENR: + description: RCC AHB4 Sleep Clock Register + fields: + - name: GPIOALPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOBLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOCLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIODLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOELPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOFLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOGLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOHLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOILPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOJLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 9 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: GPIOKLPEN + description: GPIO peripheral clock enable during CSleep mode + bit_offset: 10 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: CRCLPEN + description: CRC peripheral clock enable during CSleep mode + bit_offset: 19 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: BDMALPEN + description: BDMA Clock Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: ADC3LPEN + description: ADC3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: BKPRAMLPEN + description: Backup RAM Clock Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN + - name: SRAM4LPEN + description: SRAM4 Clock Enable During CSleep Mode + bit_offset: 29 + bit_size: 1 + enum: C1_AHB4LPENR_GPIOALPEN +fieldset/C1_APB1HENR: + description: RCC APB1 Clock Register + fields: + - name: CRSEN + description: Clock Recovery System peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: C1_APB1HENR_CRSEN + - name: SWPEN + description: SWPMI Peripheral Clocks Enable + bit_offset: 2 + bit_size: 1 + enum: C1_APB1HENR_CRSEN + - name: OPAMPEN + description: OPAMP peripheral clock enable + bit_offset: 4 + bit_size: 1 + enum: C1_APB1HENR_CRSEN + - name: MDIOSEN + description: MDIOS peripheral clock enable + bit_offset: 5 + bit_size: 1 + enum: C1_APB1HENR_CRSEN + - name: FDCANEN + description: FDCAN Peripheral Clocks Enable + bit_offset: 8 + bit_size: 1 + enum: C1_APB1HENR_CRSEN +fieldset/C1_APB1HLPENR: + description: RCC APB1 High Sleep Clock Register + fields: + - name: CRSLPEN + description: Clock Recovery System peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: C1_APB1HLPENR_CRSLPEN + - name: SWPLPEN + description: SWPMI Peripheral Clocks Enable During CSleep Mode + bit_offset: 2 + bit_size: 1 + enum: C1_APB1HLPENR_CRSLPEN + - name: OPAMPLPEN + description: OPAMP peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + enum: C1_APB1HLPENR_CRSLPEN + - name: MDIOSLPEN + description: MDIOS peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + enum: C1_APB1HLPENR_CRSLPEN + - name: FDCANLPEN + description: FDCAN Peripheral Clocks Enable During CSleep Mode + bit_offset: 8 + bit_size: 1 + enum: C1_APB1HLPENR_CRSLPEN +fieldset/C1_APB1LENR: + description: RCC APB1 Clock Register + fields: + - name: TIM2EN + description: TIM peripheral clock enable + bit_offset: 0 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: TIM3EN + description: TIM peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: TIM4EN + description: TIM peripheral clock enable + bit_offset: 2 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: TIM5EN + description: TIM peripheral clock enable + bit_offset: 3 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: TIM6EN + description: TIM peripheral clock enable + bit_offset: 4 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: TIM7EN + description: TIM peripheral clock enable + bit_offset: 5 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: TIM12EN + description: TIM peripheral clock enable + bit_offset: 6 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: TIM13EN + description: TIM peripheral clock enable + bit_offset: 7 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: TIM14EN + description: TIM peripheral clock enable + bit_offset: 8 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: LPTIM1EN + description: LPTIM1 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: SPI2EN + description: SPI2 Peripheral Clocks Enable + bit_offset: 14 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: SPI3EN + description: SPI3 Peripheral Clocks Enable + bit_offset: 15 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: SPDIFRXEN + description: SPDIFRX Peripheral Clocks Enable + bit_offset: 16 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: USART2EN + description: USART2 Peripheral Clocks Enable + bit_offset: 17 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: USART3EN + description: USART3 Peripheral Clocks Enable + bit_offset: 18 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: UART4EN + description: UART4 Peripheral Clocks Enable + bit_offset: 19 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: UART5EN + description: UART5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: I2C1EN + description: I2C1 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: I2C2EN + description: I2C2 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: I2C3EN + description: I2C3 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: CECEN + description: HDMI-CEC peripheral clock enable + bit_offset: 27 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: DAC12EN + description: DAC1&2 peripheral clock enable + bit_offset: 29 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: UART7EN + description: UART7 Peripheral Clocks Enable + bit_offset: 30 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN + - name: UART8EN + description: UART8 Peripheral Clocks Enable + bit_offset: 31 + bit_size: 1 + enum: C1_APB1LENR_TIM2EN +fieldset/C1_APB1LLPENR: + description: RCC APB1 Low Sleep Clock Register + fields: + - name: TIM2LPEN + description: TIM2 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM3LPEN + description: TIM3 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM4LPEN + description: TIM4 peripheral clock enable during CSleep mode + bit_offset: 2 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM5LPEN + description: TIM5 peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM6LPEN + description: TIM6 peripheral clock enable during CSleep mode + bit_offset: 4 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM7LPEN + description: TIM7 peripheral clock enable during CSleep mode + bit_offset: 5 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM12LPEN + description: TIM12 peripheral clock enable during CSleep mode + bit_offset: 6 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM13LPEN + description: TIM13 peripheral clock enable during CSleep mode + bit_offset: 7 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: TIM14LPEN + description: TIM14 peripheral clock enable during CSleep mode + bit_offset: 8 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: LPTIM1LPEN + description: LPTIM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: SPI2LPEN + description: SPI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 14 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: SPI3LPEN + description: SPI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 15 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: SPDIFRXLPEN + description: SPDIFRX Peripheral Clocks Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: USART2LPEN + description: USART2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 17 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: USART3LPEN + description: USART3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 18 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: UART4LPEN + description: UART4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 19 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: UART5LPEN + description: UART5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: I2C1LPEN + description: I2C1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: I2C2LPEN + description: I2C2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: I2C3LPEN + description: I2C3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: CECLPEN + description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode + bit_offset: 27 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: DAC12LPEN + description: DAC1/2 peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + bit_offset: 30 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN + - name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode + bit_offset: 31 + bit_size: 1 + enum: C1_APB1LLPENR_TIM2LPEN +fieldset/C1_APB2ENR: + description: RCC APB2 Clock Register + fields: + - name: TIM1EN + description: TIM1 peripheral clock enable + bit_offset: 0 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: TIM8EN + description: TIM8 peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: USART1EN + description: USART1 Peripheral Clocks Enable + bit_offset: 4 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: USART6EN + description: USART6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: SPI1EN + description: SPI1 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: SPI4EN + description: SPI4 Peripheral Clocks Enable + bit_offset: 13 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: TIM15EN + description: TIM15 peripheral clock enable + bit_offset: 16 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: TIM16EN + description: TIM16 peripheral clock enable + bit_offset: 17 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: TIM17EN + description: TIM17 peripheral clock enable + bit_offset: 18 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: SPI5EN + description: SPI5 Peripheral Clocks Enable + bit_offset: 20 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: SAI1EN + description: SAI1 Peripheral Clocks Enable + bit_offset: 22 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: SAI2EN + description: SAI2 Peripheral Clocks Enable + bit_offset: 23 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: SAI3EN + description: SAI3 Peripheral Clocks Enable + bit_offset: 24 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: DFSDM1EN + description: DFSDM1 Peripheral Clocks Enable + bit_offset: 28 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN + - name: HRTIMEN + description: HRTIM peripheral clock enable + bit_offset: 29 + bit_size: 1 + enum: C1_APB2ENR_TIM1EN +fieldset/C1_APB2LPENR: + description: RCC APB2 Sleep Clock Register + fields: + - name: TIM1LPEN + description: TIM1 peripheral clock enable during CSleep mode + bit_offset: 0 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: TIM8LPEN + description: TIM8 peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: USART1LPEN + description: USART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 4 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: USART6LPEN + description: USART6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: SPI1LPEN + description: SPI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: SPI4LPEN + description: SPI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 13 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: TIM15LPEN + description: TIM15 peripheral clock enable during CSleep mode + bit_offset: 16 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: TIM16LPEN + description: TIM16 peripheral clock enable during CSleep mode + bit_offset: 17 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: TIM17LPEN + description: TIM17 peripheral clock enable during CSleep mode + bit_offset: 18 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: SPI5LPEN + description: SPI5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 20 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: SAI1LPEN + description: SAI1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 22 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: SAI2LPEN + description: SAI2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 23 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: SAI3LPEN + description: SAI3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 24 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: DFSDM1LPEN + description: DFSDM1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 28 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN + - name: HRTIMLPEN + description: HRTIM peripheral clock enable during CSleep mode + bit_offset: 29 + bit_size: 1 + enum: C1_APB2LPENR_TIM1LPEN +fieldset/C1_APB3ENR: + description: RCC APB3 Clock Register + fields: + - name: LTDCEN + description: LTDC peripheral clock enable + bit_offset: 3 + bit_size: 1 + enum: C1_APB3ENR_LTDCEN + - name: WWDG1EN + description: WWDG1 Clock Enable + bit_offset: 6 + bit_size: 1 + enum: C1_APB3ENR_LTDCEN +fieldset/C1_APB3LPENR: + description: RCC APB3 Sleep Clock Register + fields: + - name: LTDCLPEN + description: LTDC peripheral clock enable during CSleep mode + bit_offset: 3 + bit_size: 1 + enum: C1_APB3LPENR_LTDCLPEN + - name: WWDG1LPEN + description: WWDG1 Clock Enable During CSleep Mode + bit_offset: 6 + bit_size: 1 + enum: C1_APB3LPENR_LTDCLPEN +fieldset/C1_APB4ENR: + description: RCC APB4 Clock Register + fields: + - name: SYSCFGEN + description: SYSCFG peripheral clock enable + bit_offset: 1 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: LPUART1EN + description: LPUART1 Peripheral Clocks Enable + bit_offset: 3 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: SPI6EN + description: SPI6 Peripheral Clocks Enable + bit_offset: 5 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: I2C4EN + description: I2C4 Peripheral Clocks Enable + bit_offset: 7 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: LPTIM2EN + description: LPTIM2 Peripheral Clocks Enable + bit_offset: 9 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: LPTIM3EN + description: LPTIM3 Peripheral Clocks Enable + bit_offset: 10 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: LPTIM4EN + description: LPTIM4 Peripheral Clocks Enable + bit_offset: 11 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: LPTIM5EN + description: LPTIM5 Peripheral Clocks Enable + bit_offset: 12 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: COMP12EN + description: COMP1/2 peripheral clock enable + bit_offset: 14 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: VREFEN + description: VREF peripheral clock enable + bit_offset: 15 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: RTCAPBEN + description: RTC APB Clock Enable + bit_offset: 16 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN + - name: SAI4EN + description: SAI4 Peripheral Clocks Enable + bit_offset: 21 + bit_size: 1 + enum: C1_APB4ENR_SYSCFGEN +fieldset/C1_APB4LPENR: + description: RCC APB4 Sleep Clock Register + fields: + - name: SYSCFGLPEN + description: SYSCFG peripheral clock enable during CSleep mode + bit_offset: 1 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPUART1LPEN + description: LPUART1 Peripheral Clocks Enable During CSleep Mode + bit_offset: 3 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: SPI6LPEN + description: SPI6 Peripheral Clocks Enable During CSleep Mode + bit_offset: 5 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: I2C4LPEN + description: I2C4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 7 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPTIM2LPEN + description: LPTIM2 Peripheral Clocks Enable During CSleep Mode + bit_offset: 9 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPTIM3LPEN + description: LPTIM3 Peripheral Clocks Enable During CSleep Mode + bit_offset: 10 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPTIM4LPEN + description: LPTIM4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 11 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: LPTIM5LPEN + description: LPTIM5 Peripheral Clocks Enable During CSleep Mode + bit_offset: 12 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: COMP12LPEN + description: COMP1/2 peripheral clock enable during CSleep mode + bit_offset: 14 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: VREFLPEN + description: VREF peripheral clock enable during CSleep mode + bit_offset: 15 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: RTCAPBLPEN + description: RTC APB Clock Enable During CSleep Mode + bit_offset: 16 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN + - name: SAI4LPEN + description: SAI4 Peripheral Clocks Enable During CSleep Mode + bit_offset: 21 + bit_size: 1 + enum: C1_APB4LPENR_SYSCFGLPEN +fieldset/C1_RSR: + description: RCC Reset Status Register + fields: + - name: RMVF + description: Remove reset flag + bit_offset: 16 + bit_size: 1 + enum: C1_RSR_RMVF + - name: CPURSTF + description: CPU reset flag + bit_offset: 17 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: D1RSTF + description: D1 domain power switch reset flag + bit_offset: 19 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: D2RSTF + description: D2 domain power switch reset flag + bit_offset: 20 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: BORRSTF + description: BOR reset flag + bit_offset: 21 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: PINRSTF + description: Pin reset flag (NRST) + bit_offset: 22 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 23 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: SFTRSTF + description: System reset from CPU reset flag + bit_offset: 24 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: IWDG1RSTF + description: Independent Watchdog reset flag + bit_offset: 26 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: WWDG1RSTF + description: Window Watchdog reset flag + bit_offset: 28 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR + - name: LPWRRSTF + description: Reset due to illegal D1 DStandby or CPU CStop flag + bit_offset: 30 + bit_size: 1 + enum_read: C1_RSR_CPURSTFR +fieldset/CFGR: + description: RCC Clock Configuration Register + fields: + - name: SW + description: System clock switch + bit_offset: 0 + bit_size: 3 + enum: SW + - name: SWS + description: System clock switch status + bit_offset: 3 + bit_size: 3 + enum_read: SWSR + - name: STOPWUCK + description: System clock selection after a wake up from system Stop + bit_offset: 6 + bit_size: 1 + enum: STOPWUCK + - name: STOPKERWUCK + description: Kernel clock selection after a wake up from system Stop + bit_offset: 7 + bit_size: 1 + enum: STOPWUCK + - name: RTCPRE + description: HSE division factor for RTC clock + bit_offset: 8 + bit_size: 6 + - name: HRTIMSEL + description: High Resolution Timer clock prescaler selection + bit_offset: 14 + bit_size: 1 + enum: HRTIMSEL + - name: TIMPRE + description: Timers clocks prescaler selection + bit_offset: 15 + bit_size: 1 + enum: TIMPRE + - name: MCO1PRE + description: MCO1 prescaler + bit_offset: 18 + bit_size: 4 + - name: MCO1 + description: Micro-controller clock output 1 + bit_offset: 22 + bit_size: 3 + enum: MCO1 + - name: MCO2PRE + description: MCO2 prescaler + bit_offset: 25 + bit_size: 4 + - name: MCO2 + description: Micro-controller clock output 2 + bit_offset: 29 + bit_size: 3 + enum: MCO2 +fieldset/CICR: + description: RCC Clock Source Interrupt Clear Register + fields: + - name: LSIRDYC + description: LSI ready Interrupt Clear + bit_offset: 0 + bit_size: 1 + enum: LSIRDYC + - name: LSERDYC + description: LSE ready Interrupt Clear + bit_offset: 1 + bit_size: 1 + enum: LSIRDYC + - name: HSIRDYC + description: HSI ready Interrupt Clear + bit_offset: 2 + bit_size: 1 + enum: LSIRDYC + - name: HSERDYC + description: HSE ready Interrupt Clear + bit_offset: 3 + bit_size: 1 + enum: LSIRDYC + - name: HSE_ready_Interrupt_Clear + description: CSI ready Interrupt Clear + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYC + description: RC48 ready Interrupt Clear + bit_offset: 5 + bit_size: 1 + enum: LSIRDYC + - name: PLLRDYC + description: PLL1 ready Interrupt Clear + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: LSIRDYC + - name: LSECSSC + description: LSE clock security system Interrupt Clear + bit_offset: 9 + bit_size: 1 + enum: LSIRDYC + - name: HSECSSC + description: HSE clock security system Interrupt Clear + bit_offset: 10 + bit_size: 1 + enum: LSIRDYC +fieldset/CIER: + description: RCC Clock Source Interrupt Enable Register + fields: + - name: LSIRDYIE + description: LSI ready Interrupt Enable + bit_offset: 0 + bit_size: 1 + enum: LSIRDYIE + - name: LSERDYIE + description: LSE ready Interrupt Enable + bit_offset: 1 + bit_size: 1 + enum: LSIRDYIE + - name: HSIRDYIE + description: HSI ready Interrupt Enable + bit_offset: 2 + bit_size: 1 + enum: LSIRDYIE + - name: HSERDYIE + description: HSE ready Interrupt Enable + bit_offset: 3 + bit_size: 1 + enum: LSIRDYIE + - name: CSIRDYIE + description: CSI ready Interrupt Enable + bit_offset: 4 + bit_size: 1 + enum: LSIRDYIE + - name: HSI48RDYIE + description: RC48 ready Interrupt Enable + bit_offset: 5 + bit_size: 1 + enum: LSIRDYIE + - name: PLLRDYIE + description: PLL1 ready Interrupt Enable + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: LSIRDYIE + - name: LSECSSIE + description: LSE clock security system Interrupt Enable + bit_offset: 9 + bit_size: 1 + enum: LSIRDYIE +fieldset/CIFR: + description: RCC Clock Source Interrupt Flag Register + fields: + - name: LSIRDYF + description: LSI ready Interrupt Flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE ready Interrupt Flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI ready Interrupt Flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE ready Interrupt Flag + bit_offset: 3 + bit_size: 1 + - name: CSIRDY + description: CSI ready Interrupt Flag + bit_offset: 4 + bit_size: 1 + - name: HSI48RDYF + description: RC48 ready Interrupt Flag + bit_offset: 5 + bit_size: 1 + - name: PLLRDYF + description: PLL1 ready Interrupt Flag + bit_offset: 6 + bit_size: 1 + array: + len: 3 + stride: 1 + - name: LSECSSF + description: LSE clock security system Interrupt Flag + bit_offset: 9 + bit_size: 1 + - name: HSECSSF + description: HSE clock security system Interrupt Flag + bit_offset: 10 + bit_size: 1 +fieldset/CR: + description: clock control register + fields: + - name: HSION + description: Internal high-speed clock enable + bit_offset: 0 + bit_size: 1 + enum: HSION + - name: HSIKERON + description: High Speed Internal clock enable in Stop mode + bit_offset: 1 + bit_size: 1 + enum: HSION + - name: HSIRDY + description: HSI clock ready flag + bit_offset: 2 + bit_size: 1 + enum_read: HSIRDYR + - name: HSIDIV + description: HSI clock divider + bit_offset: 3 + bit_size: 2 + enum: HSIDIV + - name: HSIDIVF + description: HSI divider flag + bit_offset: 5 + bit_size: 1 + enum_read: HSIDIVFR + - name: CSION + description: CSI clock enable + bit_offset: 7 + bit_size: 1 + enum: HSION + - name: CSIRDY + description: CSI clock ready flag + bit_offset: 8 + bit_size: 1 + enum_read: HSIRDYR + - name: CSIKERON + description: CSI clock enable in Stop mode + bit_offset: 9 + bit_size: 1 + enum: HSION + - name: HSI48ON + description: RC48 clock enable + bit_offset: 12 + bit_size: 1 + enum: HSION + - name: HSI48RDY + description: RC48 clock ready flag + bit_offset: 13 + bit_size: 1 + enum_read: HSIRDYR + - name: D1CKRDY + description: D1 domain clocks ready flag + bit_offset: 14 + bit_size: 1 + enum_read: HSIRDYR + - name: D2CKRDY + description: D2 domain clocks ready flag + bit_offset: 15 + bit_size: 1 + enum_read: HSIRDYR + - name: HSEON + description: HSE clock enable + bit_offset: 16 + bit_size: 1 + enum: HSION + - name: HSERDY + description: HSE clock ready flag + bit_offset: 17 + bit_size: 1 + enum_read: HSIRDYR + - name: HSEBYP + description: HSE clock bypass + bit_offset: 18 + bit_size: 1 + enum: HSEBYP + - name: HSECSSON + description: HSE Clock Security System enable + bit_offset: 19 + bit_size: 1 + enum: HSION + - name: PLL1ON + description: PLL1 enable + bit_offset: 24 + bit_size: 1 + enum: HSION + - name: PLL1RDY + description: PLL1 clock ready flag + bit_offset: 25 + bit_size: 1 + enum_read: HSIRDYR + - name: PLL2ON + description: PLL2 enable + bit_offset: 26 + bit_size: 1 + enum: HSION + - name: PLL2RDY + description: PLL2 clock ready flag + bit_offset: 27 + bit_size: 1 + enum_read: HSIRDYR + - name: PLL3ON + description: PLL3 enable + bit_offset: 28 + bit_size: 1 + enum: HSION + - name: PLL3RDY + description: PLL3 clock ready flag + bit_offset: 29 + bit_size: 1 + enum_read: HSIRDYR +fieldset/CRRCR: + description: RCC Clock Recovery RC Register + fields: + - name: HSI48CAL + description: Internal RC 48 MHz clock calibration + bit_offset: 0 + bit_size: 10 +fieldset/CSICFGR: + description: RCC CSI configuration register + fields: + - name: CSICAL + description: CSI clock calibration + bit_offset: 0 + bit_size: 9 + - name: CSITRIM + description: CSI clock trimming + bit_offset: 24 + bit_size: 6 +fieldset/CSR: + description: RCC Clock Control and Status Register + fields: + - name: LSION + description: LSI oscillator enable + bit_offset: 0 + bit_size: 1 + enum: LSION + - name: LSIRDY + description: LSI oscillator ready + bit_offset: 1 + bit_size: 1 + enum_read: LSIRDYR +fieldset/D1CCIPR: + description: RCC Domain 1 Kernel Clock Configuration Register + fields: + - name: FMCSEL + description: FMC kernel clock source selection + bit_offset: 0 + bit_size: 2 + enum: FMCSEL + - name: QSPISEL + description: QUADSPI kernel clock source selection + bit_offset: 4 + bit_size: 2 + enum: FMCSEL + - name: SDMMCSEL + description: SDMMC kernel clock source selection + bit_offset: 16 + bit_size: 1 + enum: SDMMCSEL + - name: CKPERSEL + description: per_ck clock source selection + bit_offset: 28 + bit_size: 2 + enum: CKPERSEL +fieldset/D1CFGR: + description: RCC Domain 1 Clock Configuration Register + fields: + - name: HPRE + description: D1 domain AHB prescaler + bit_offset: 0 + bit_size: 4 + enum: HPRE + - name: D1PPRE + description: D1 domain APB3 prescaler + bit_offset: 4 + bit_size: 3 + enum: D1PPRE + - name: D1CPRE + description: D1 domain Core prescaler + bit_offset: 8 + bit_size: 4 + enum: HPRE +fieldset/D2CCIP1R: + description: RCC Domain 2 Kernel Clock Configuration Register + fields: + - name: SAI1SEL + description: SAI1 and DFSDM1 kernel Aclk clock source selection + bit_offset: 0 + bit_size: 3 + enum: SAI1SEL + - name: SAI23SEL + description: SAI2 and SAI3 kernel clock source selection + bit_offset: 6 + bit_size: 3 + enum: SAI1SEL + - name: SPI123SEL + description: "SPI/I2S1,2 and 3 kernel clock source selection" + bit_offset: 12 + bit_size: 3 + enum: SAI1SEL + - name: SPI45SEL + description: SPI4 and 5 kernel clock source selection + bit_offset: 16 + bit_size: 3 + enum: SPI45SEL + - name: SPDIFSEL + description: SPDIFRX kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: SPDIFSEL + - name: DFSDM1SEL + description: DFSDM1 kernel Clk clock source selection + bit_offset: 24 + bit_size: 1 + enum: DFSDM1SEL + - name: FDCANSEL + description: FDCAN kernel clock source selection + bit_offset: 28 + bit_size: 2 + enum: FDCANSEL + - name: SWPSEL + description: SWPMI kernel clock source selection + bit_offset: 31 + bit_size: 1 + enum: SWPSEL +fieldset/D2CCIP2R: + description: RCC Domain 2 Kernel Clock Configuration Register + fields: + - name: USART234578SEL + description: "USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection" + bit_offset: 0 + bit_size: 3 + enum: USART234578SEL + - name: USART16SEL + description: USART1 and 6 kernel clock source selection + bit_offset: 3 + bit_size: 3 + enum: USART16SEL + - name: RNGSEL + description: RNG kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: RNGSEL + - name: I2C123SEL + description: "I2C1,2,3 kernel clock source selection" + bit_offset: 12 + bit_size: 2 + enum: I2C123SEL + - name: USBSEL + description: USBOTG 1 and 2 kernel clock source selection + bit_offset: 20 + bit_size: 2 + enum: USBSEL + - name: CECSEL + description: HDMI-CEC kernel clock source selection + bit_offset: 22 + bit_size: 2 + enum: CECSEL + - name: LPTIM1SEL + description: LPTIM1 kernel clock source selection + bit_offset: 28 + bit_size: 3 + enum: LPTIM1SEL +fieldset/D2CFGR: + description: RCC Domain 2 Clock Configuration Register + fields: + - name: D2PPRE1 + description: D2 domain APB1 prescaler + bit_offset: 4 + bit_size: 3 + enum: D2PPRE1 + - name: D2PPRE2 + description: D2 domain APB2 prescaler + bit_offset: 8 + bit_size: 3 + enum: D2PPRE1 +fieldset/D3AMR: + description: RCC D3 Autonomous mode Register + fields: + - name: BDMAAMEN + description: BDMA and DMAMUX Autonomous mode enable + bit_offset: 0 + bit_size: 1 + enum: BDMAAMEN + - name: LPUART1AMEN + description: LPUART1 Autonomous mode enable + bit_offset: 3 + bit_size: 1 + enum: BDMAAMEN + - name: SPI6AMEN + description: SPI6 Autonomous mode enable + bit_offset: 5 + bit_size: 1 + enum: BDMAAMEN + - name: I2C4AMEN + description: I2C4 Autonomous mode enable + bit_offset: 7 + bit_size: 1 + enum: BDMAAMEN + - name: LPTIM2AMEN + description: LPTIM2 Autonomous mode enable + bit_offset: 9 + bit_size: 1 + enum: BDMAAMEN + - name: LPTIM3AMEN + description: LPTIM3 Autonomous mode enable + bit_offset: 10 + bit_size: 1 + enum: BDMAAMEN + - name: LPTIM4AMEN + description: LPTIM4 Autonomous mode enable + bit_offset: 11 + bit_size: 1 + enum: BDMAAMEN + - name: LPTIM5AMEN + description: LPTIM5 Autonomous mode enable + bit_offset: 12 + bit_size: 1 + enum: BDMAAMEN + - name: COMP12AMEN + description: COMP12 Autonomous mode enable + bit_offset: 14 + bit_size: 1 + enum: BDMAAMEN + - name: VREFAMEN + description: VREF Autonomous mode enable + bit_offset: 15 + bit_size: 1 + enum: BDMAAMEN + - name: RTCAMEN + description: RTC Autonomous mode enable + bit_offset: 16 + bit_size: 1 + enum: BDMAAMEN + - name: CRCAMEN + description: CRC Autonomous mode enable + bit_offset: 19 + bit_size: 1 + enum: BDMAAMEN + - name: SAI4AMEN + description: SAI4 Autonomous mode enable + bit_offset: 21 + bit_size: 1 + enum: BDMAAMEN + - name: ADC3AMEN + description: ADC3 Autonomous mode enable + bit_offset: 24 + bit_size: 1 + enum: BDMAAMEN + - name: BKPRAMAMEN + description: Backup RAM Autonomous mode enable + bit_offset: 28 + bit_size: 1 + enum: BDMAAMEN + - name: SRAM4AMEN + description: SRAM4 Autonomous mode enable + bit_offset: 29 + bit_size: 1 + enum: BDMAAMEN +fieldset/D3CCIPR: + description: RCC Domain 3 Kernel Clock Configuration Register + fields: + - name: LPUART1SEL + description: LPUART1 kernel clock source selection + bit_offset: 0 + bit_size: 3 + enum: LPUART1SEL + - name: I2C4SEL + description: I2C4 kernel clock source selection + bit_offset: 8 + bit_size: 2 + enum: I2C4SEL + - name: LPTIM2SEL + description: LPTIM2 kernel clock source selection + bit_offset: 10 + bit_size: 3 + enum: LPTIM2SEL + - name: LPTIM345SEL + description: "LPTIM3,4,5 kernel clock source selection" + bit_offset: 13 + bit_size: 3 + enum: LPTIM2SEL + - name: ADCSEL + description: SAR ADC kernel clock source selection + bit_offset: 16 + bit_size: 2 + enum: ADCSEL + - name: SAI4ASEL + description: Sub-Block A of SAI4 kernel clock source selection + bit_offset: 21 + bit_size: 3 + enum: SAI4ASEL + - name: SAI4BSEL + description: Sub-Block B of SAI4 kernel clock source selection + bit_offset: 24 + bit_size: 3 + enum: SAI4ASEL + - name: SPI6SEL + description: SPI6 kernel clock source selection + bit_offset: 28 + bit_size: 3 + enum: SPI6SEL +fieldset/D3CFGR: + description: RCC Domain 3 Clock Configuration Register + fields: + - name: D3PPRE + description: D3 domain APB4 prescaler + bit_offset: 4 + bit_size: 3 + enum: D3PPRE +fieldset/GCR: + description: RCC Global Control Register + fields: + - name: WW1RSC + description: WWDG1 reset scope control + bit_offset: 0 + bit_size: 1 + enum: WW1RSC +fieldset/HSICFGR: + description: RCC HSI configuration register + fields: + - name: HSICAL + description: HSI clock calibration + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 24 + bit_size: 7 +fieldset/ICSCR: + description: RCC Internal Clock Source Calibration Register + fields: + - name: HSICAL + description: HSI clock calibration + bit_offset: 0 + bit_size: 12 + - name: HSITRIM + description: HSI clock trimming + bit_offset: 12 + bit_size: 6 + - name: CSICAL + description: CSI clock calibration + bit_offset: 18 + bit_size: 8 + - name: CSITRIM + description: CSI clock trimming + bit_offset: 26 + bit_size: 5 +fieldset/PLL1DIVR: + description: RCC PLL1 Dividers Configuration Register + fields: + - name: DIVN1 + description: Multiplication factor for PLL1 VCO + bit_offset: 0 + bit_size: 9 + - name: DIVP1 + description: PLL1 DIVP division factor + bit_offset: 9 + bit_size: 7 + enum: DIVP1 + - name: DIVQ1 + description: PLL1 DIVQ division factor + bit_offset: 16 + bit_size: 7 + - name: DIVR1 + description: PLL1 DIVR division factor + bit_offset: 24 + bit_size: 7 +fieldset/PLL1FRACR: + description: RCC PLL1 Fractional Divider Register + fields: + - name: FRACN1 + description: Fractional part of the multiplication factor for PLL1 VCO + bit_offset: 3 + bit_size: 13 +fieldset/PLL2DIVR: + description: RCC PLL2 Dividers Configuration Register + fields: + - name: DIVN2 + description: Multiplication factor for PLL1 VCO + bit_offset: 0 + bit_size: 9 + - name: DIVP2 + description: PLL1 DIVP division factor + bit_offset: 9 + bit_size: 7 + - name: DIVQ2 + description: PLL1 DIVQ division factor + bit_offset: 16 + bit_size: 7 + - name: DIVR2 + description: PLL1 DIVR division factor + bit_offset: 24 + bit_size: 7 +fieldset/PLL2FRACR: + description: RCC PLL2 Fractional Divider Register + fields: + - name: FRACN2 + description: Fractional part of the multiplication factor for PLL VCO + bit_offset: 3 + bit_size: 13 +fieldset/PLL3DIVR: + description: RCC PLL3 Dividers Configuration Register + fields: + - name: DIVN3 + description: Multiplication factor for PLL1 VCO + bit_offset: 0 + bit_size: 9 + - name: DIVP3 + description: PLL DIVP division factor + bit_offset: 9 + bit_size: 7 + - name: DIVQ3 + description: PLL DIVQ division factor + bit_offset: 16 + bit_size: 7 + - name: DIVR3 + description: PLL DIVR division factor + bit_offset: 24 + bit_size: 7 +fieldset/PLL3FRACR: + description: RCC PLL3 Fractional Divider Register + fields: + - name: FRACN3 + description: Fractional part of the multiplication factor for PLL3 VCO + bit_offset: 3 + bit_size: 13 +fieldset/PLLCFGR: + description: RCC PLLs Configuration Register + fields: + - name: PLLFRACEN + description: PLL1 fractional latch enable + bit_offset: 0 + bit_size: 1 + array: + len: 3 + stride: 4 + enum: PLL1FRACEN + - name: PLLVCOSEL + description: PLL1 VCO selection + bit_offset: 1 + bit_size: 1 + array: + len: 3 + stride: 4 + enum: PLL1VCOSEL + - name: PLLRGE + description: PLL1 input frequency range + bit_offset: 2 + bit_size: 2 + array: + len: 3 + stride: 4 + enum: PLL1RGE + - name: DIVPEN + description: PLL1 DIVP divider output enable + bit_offset: 16 + bit_size: 1 + array: + len: 3 + stride: 3 + enum: DIVP1EN + - name: DIVQEN + description: PLL1 DIVQ divider output enable + bit_offset: 17 + bit_size: 1 + array: + len: 3 + stride: 3 + enum: DIVP1EN + - name: DIVREN + description: PLL1 DIVR divider output enable + bit_offset: 18 + bit_size: 1 + array: + len: 3 + stride: 3 + enum: DIVP1EN +fieldset/PLLCKSELR: + description: RCC PLLs Clock Source Selection Register + fields: + - name: PLLSRC + description: DIVMx and PLLs clock source selection + bit_offset: 0 + bit_size: 2 + enum: PLLSRC + - name: DIVM + description: Prescaler for PLL1 + bit_offset: 4 + bit_size: 6 + array: + len: 3 + stride: 8 +fieldset/RSR: + description: RCC Reset Status Register + fields: + - name: RMVF + description: Remove reset flag + bit_offset: 16 + bit_size: 1 + enum: RSR_RMVF + - name: CPURSTF + description: CPU reset flag + bit_offset: 17 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: D1RSTF + description: D1 domain power switch reset flag + bit_offset: 19 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: D2RSTF + description: D2 domain power switch reset flag + bit_offset: 20 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: BORRSTF + description: BOR reset flag + bit_offset: 21 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: PINRSTF + description: Pin reset flag (NRST) + bit_offset: 22 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 23 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: SFTRSTF + description: System reset from CPU reset flag + bit_offset: 24 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: IWDG1RSTF + description: Independent Watchdog reset flag + bit_offset: 26 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: WWDG1RSTF + description: Window Watchdog reset flag + bit_offset: 28 + bit_size: 1 + enum_read: RSR_CPURSTFR + - name: LPWRRSTF + description: Reset due to illegal D1 DStandby or CPU CStop flag + bit_offset: 30 + bit_size: 1 + enum_read: RSR_CPURSTFR +enum/ADCSEL: + bit_size: 2 + variants: + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: PER + description: PER selected as peripheral clock + value: 2 +enum/AHB1ENR_DMA1EN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/AHB1LPENR_DMA1LPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/AHB2ENR_DCMIEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/AHB2LPENR_DCMILPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/AHB3ENR_MDMAEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/AHB3LPENR_MDMALPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/AHB4ENR_GPIOAEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/AHB4LPENR_GPIOALPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/APB1HENR_CRSEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/APB1HLPENR_CRSLPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/APB1LENR_TIM2EN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/APB1LLPENR_TIM2LPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/APB2ENR_TIM1EN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/APB2LPENR_TIM1LPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/APB3ENR_LTDCEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/APB3LPENR_LTDCLPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/APB4ENR_SYSCFGEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/APB4LPENR_SYSCFGLPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/BDMAAMEN: + bit_size: 1 + variants: + - name: Disabled + description: Clock disabled in autonomous mode + value: 0 + - name: Enabled + description: Clock enabled in autonomous mode + value: 1 +enum/BDRST: + bit_size: 1 + variants: + - name: Reset + description: Resets the entire VSW domain + value: 1 +enum/C1_AHB1ENR_DMA1EN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_AHB1LPENR_DMA1LPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_AHB2ENR_DCMIEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_AHB2LPENR_DCMILPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_AHB3ENR_MDMAEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_AHB3LPENR_MDMALPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_AHB4ENR_GPIOAEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_AHB4LPENR_GPIOALPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_APB1HENR_CRSEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_APB1HLPENR_CRSLPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_APB1LENR_TIM2EN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_APB1LLPENR_TIM2LPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_APB2ENR_TIM1EN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_APB2LPENR_TIM1LPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_APB3ENR_LTDCEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_APB3LPENR_LTDCLPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_APB4ENR_SYSCFGEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled + value: 0 + - name: Enabled + description: The selected clock is enabled + value: 1 +enum/C1_APB4LPENR_SYSCFGLPEN: + bit_size: 1 + variants: + - name: Disabled + description: The selected clock is disabled during csleep mode + value: 0 + - name: Enabled + description: The selected clock is enabled during csleep mode + value: 1 +enum/C1_RSR_CPURSTFR: + bit_size: 1 + variants: + - name: NoResetOccoured + description: No reset occoured for block + value: 0 + - name: ResetOccourred + description: Reset occoured for block + value: 1 +enum/C1_RSR_RMVF: + bit_size: 1 + variants: + - name: NotActive + description: Not clearing the the reset flags + value: 0 + - name: Clear + description: Clear the reset flags + value: 1 +enum/CAMITFRST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/CECSEL: + bit_size: 2 + variants: + - name: LSE + description: LSE selected as peripheral clock + value: 0 + - name: LSI + description: LSI selected as peripheral clock + value: 1 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 2 +enum/CKPERSEL: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as peripheral clock + value: 0 + - name: CSI + description: CSI selected as peripheral clock + value: 1 + - name: HSE + description: HSE selected as peripheral clock + value: 2 +enum/CRSRST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/D1PPRE: + bit_size: 3 + variants: + - name: Div1 + description: rcc_hclk not divided + value: 0 + - name: Div2 + description: rcc_hclk divided by 2 + value: 4 + - name: Div4 + description: rcc_hclk divided by 4 + value: 5 + - name: Div8 + description: rcc_hclk divided by 8 + value: 6 + - name: Div16 + description: rcc_hclk divided by 16 + value: 7 +enum/D2PPRE1: + bit_size: 3 + variants: + - name: Div1 + description: rcc_hclk not divided + value: 0 + - name: Div2 + description: rcc_hclk divided by 2 + value: 4 + - name: Div4 + description: rcc_hclk divided by 4 + value: 5 + - name: Div8 + description: rcc_hclk divided by 8 + value: 6 + - name: Div16 + description: rcc_hclk divided by 16 + value: 7 +enum/D3PPRE: + bit_size: 3 + variants: + - name: Div1 + description: rcc_hclk not divided + value: 0 + - name: Div2 + description: rcc_hclk divided by 2 + value: 4 + - name: Div4 + description: rcc_hclk divided by 4 + value: 5 + - name: Div8 + description: rcc_hclk divided by 8 + value: 6 + - name: Div16 + description: rcc_hclk divided by 16 + value: 7 +enum/DFSDM1SEL: + bit_size: 1 + variants: + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: SYS + description: System clock selected as peripheral clock + value: 1 +enum/DIVP1: + bit_size: 7 + variants: + - name: Div1 + description: pll_p_ck = vco_ck + value: 0 + - name: Div2 + description: pll_p_ck = vco_ck / 2 + value: 1 + - name: Div4 + description: pll_p_ck = vco_ck / 4 + value: 3 + - name: Div6 + description: pll_p_ck = vco_ck / 6 + value: 5 + - name: Div8 + description: pll_p_ck = vco_ck / 8 + value: 7 + - name: Div10 + description: pll_p_ck = vco_ck / 10 + value: 9 + - name: Div12 + description: pll_p_ck = vco_ck / 12 + value: 11 + - name: Div14 + description: pll_p_ck = vco_ck / 14 + value: 13 + - name: Div16 + description: pll_p_ck = vco_ck / 16 + value: 15 + - name: Div18 + description: pll_p_ck = vco_ck / 18 + value: 17 + - name: Div20 + description: pll_p_ck = vco_ck / 20 + value: 19 + - name: Div22 + description: pll_p_ck = vco_ck / 22 + value: 21 + - name: Div24 + description: pll_p_ck = vco_ck / 24 + value: 23 + - name: Div26 + description: pll_p_ck = vco_ck / 26 + value: 25 + - name: Div28 + description: pll_p_ck = vco_ck / 28 + value: 27 + - name: Div30 + description: pll_p_ck = vco_ck / 30 + value: 29 + - name: Div32 + description: pll_p_ck = vco_ck / 32 + value: 31 + - name: Div34 + description: pll_p_ck = vco_ck / 34 + value: 33 + - name: Div36 + description: pll_p_ck = vco_ck / 36 + value: 35 + - name: Div38 + description: pll_p_ck = vco_ck / 38 + value: 37 + - name: Div40 + description: pll_p_ck = vco_ck / 40 + value: 39 + - name: Div42 + description: pll_p_ck = vco_ck / 42 + value: 41 + - name: Div44 + description: pll_p_ck = vco_ck / 44 + value: 43 + - name: Div46 + description: pll_p_ck = vco_ck / 46 + value: 45 + - name: Div48 + description: pll_p_ck = vco_ck / 48 + value: 47 + - name: Div50 + description: pll_p_ck = vco_ck / 50 + value: 49 + - name: Div52 + description: pll_p_ck = vco_ck / 52 + value: 51 + - name: Div54 + description: pll_p_ck = vco_ck / 54 + value: 53 + - name: Div56 + description: pll_p_ck = vco_ck / 56 + value: 55 + - name: Div58 + description: pll_p_ck = vco_ck / 58 + value: 57 + - name: Div60 + description: pll_p_ck = vco_ck / 60 + value: 59 + - name: Div62 + description: pll_p_ck = vco_ck / 62 + value: 61 + - name: Div64 + description: pll_p_ck = vco_ck / 64 + value: 63 + - name: Div66 + description: pll_p_ck = vco_ck / 66 + value: 65 + - name: Div68 + description: pll_p_ck = vco_ck / 68 + value: 67 + - name: Div70 + description: pll_p_ck = vco_ck / 70 + value: 69 + - name: Div72 + description: pll_p_ck = vco_ck / 72 + value: 71 + - name: Div74 + description: pll_p_ck = vco_ck / 74 + value: 73 + - name: Div76 + description: pll_p_ck = vco_ck / 76 + value: 75 + - name: Div78 + description: pll_p_ck = vco_ck / 78 + value: 77 + - name: Div80 + description: pll_p_ck = vco_ck / 80 + value: 79 + - name: Div82 + description: pll_p_ck = vco_ck / 82 + value: 81 + - name: Div84 + description: pll_p_ck = vco_ck / 84 + value: 83 + - name: Div86 + description: pll_p_ck = vco_ck / 86 + value: 85 + - name: Div88 + description: pll_p_ck = vco_ck / 88 + value: 87 + - name: Div90 + description: pll_p_ck = vco_ck / 90 + value: 89 + - name: Div92 + description: pll_p_ck = vco_ck / 92 + value: 91 + - name: Div94 + description: pll_p_ck = vco_ck / 94 + value: 93 + - name: Div96 + description: pll_p_ck = vco_ck / 96 + value: 95 + - name: Div98 + description: pll_p_ck = vco_ck / 98 + value: 97 + - name: Div100 + description: pll_p_ck = vco_ck / 100 + value: 99 + - name: Div102 + description: pll_p_ck = vco_ck / 102 + value: 101 + - name: Div104 + description: pll_p_ck = vco_ck / 104 + value: 103 + - name: Div106 + description: pll_p_ck = vco_ck / 106 + value: 105 + - name: Div108 + description: pll_p_ck = vco_ck / 108 + value: 107 + - name: Div110 + description: pll_p_ck = vco_ck / 110 + value: 109 + - name: Div112 + description: pll_p_ck = vco_ck / 112 + value: 111 + - name: Div114 + description: pll_p_ck = vco_ck / 114 + value: 113 + - name: Div116 + description: pll_p_ck = vco_ck / 116 + value: 115 + - name: Div118 + description: pll_p_ck = vco_ck / 118 + value: 117 + - name: Div120 + description: pll_p_ck = vco_ck / 120 + value: 119 + - name: Div122 + description: pll_p_ck = vco_ck / 122 + value: 121 + - name: Div124 + description: pll_p_ck = vco_ck / 124 + value: 123 + - name: Div126 + description: pll_p_ck = vco_ck / 126 + value: 125 + - name: Div128 + description: pll_p_ck = vco_ck / 128 + value: 127 +enum/DIVP1EN: + bit_size: 1 + variants: + - name: Disabled + description: Clock ouput is disabled + value: 0 + - name: Enabled + description: Clock output is enabled + value: 1 +enum/DMA1RST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/FDCANSEL: + bit_size: 2 + variants: + - name: HSE + description: HSE selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 2 +enum/FMCSEL: + bit_size: 2 + variants: + - name: RCC_HCLK3 + description: rcc_hclk3 selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 2 + - name: PER + description: PER selected as peripheral clock + value: 3 +enum/GPIOARST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: sys_ck not divided + value: 0 + - name: Div2 + description: sys_ck divided by 2 + value: 8 + - name: Div4 + description: sys_ck divided by 4 + value: 9 + - name: Div8 + description: sys_ck divided by 8 + value: 10 + - name: Div16 + description: sys_ck divided by 16 + value: 11 + - name: Div64 + description: sys_ck divided by 64 + value: 12 + - name: Div128 + description: sys_ck divided by 128 + value: 13 + - name: Div256 + description: sys_ck divided by 256 + value: 14 + - name: Div512 + description: sys_ck divided by 512 + value: 15 +enum/HRTIMSEL: + bit_size: 1 + variants: + - name: TIMY_KER + description: The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck) + value: 0 + - name: C_CK + description: The HRTIM prescaler clock source is the CPU clock (c_ck) + value: 1 +enum/HSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: HSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: HSE crystal oscillator bypassed with external clock + value: 1 +enum/HSIDIV: + bit_size: 2 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 +enum/HSIDIVFR: + bit_size: 1 + variants: + - name: NotPropagated + description: New HSIDIV ratio has not yet propagated to hsi_ck + value: 0 + - name: Propagated + description: HSIDIV ratio has propagated to hsi_ck + value: 1 +enum/HSION: + bit_size: 1 + variants: + - name: "Off" + description: Clock Off + value: 0 + - name: "On" + description: Clock On + value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: Clock not ready + value: 0 + - name: Ready + description: Clock ready + value: 1 +enum/I2C123SEL: + bit_size: 2 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 +enum/I2C4SEL: + bit_size: 2 + variants: + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 1 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 2 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 3 +enum/LPTIM1SEL: + bit_size: 3 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 +enum/LPTIM2SEL: + bit_size: 3 + variants: + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: LSE + description: LSE selected as peripheral clock + value: 3 + - name: LSI + description: LSI selected as peripheral clock + value: 4 + - name: PER + description: PER selected as peripheral clock + value: 5 +enum/LPUART1SEL: + bit_size: 3 + variants: + - name: RCC_PCLK_D3 + description: rcc_pclk_d3 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/LSEBYP: + bit_size: 1 + variants: + - name: NotBypassed + description: LSE crystal oscillator not bypassed + value: 0 + - name: Bypassed + description: LSE crystal oscillator bypassed with external clock + value: 1 +enum/LSECSSDR: + bit_size: 1 + variants: + - name: NoFailure + description: No failure detected on 32 kHz oscillator + value: 0 + - name: Failure + description: Failure detected on 32 kHz oscillator + value: 1 +enum/LSECSSON: + bit_size: 1 + variants: + - name: SecurityOff + description: Clock security system on 32 kHz oscillator off + value: 0 + - name: SecurityOn + description: Clock security system on 32 kHz oscillator on + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Lowest + description: Lowest LSE oscillator driving capability + value: 0 + - name: MediumLow + description: Medium low LSE oscillator driving capability + value: 1 + - name: MediumHigh + description: Medium high LSE oscillator driving capability + value: 2 + - name: Highest + description: Highest LSE oscillator driving capability + value: 3 +enum/LSEON: + bit_size: 1 + variants: + - name: "Off" + description: LSE oscillator Off + value: 0 + - name: "On" + description: LSE oscillator On + value: 1 +enum/LSERDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSE oscillator not ready + value: 0 + - name: Ready + description: LSE oscillator ready + value: 1 +enum/LSION: + bit_size: 1 + variants: + - name: "Off" + description: LSI oscillator Off + value: 0 + - name: "On" + description: LSI oscillator On + value: 1 +enum/LSIRDYC: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag + value: 1 +enum/LSIRDYIE: + bit_size: 1 + variants: + - name: Disabled + description: Interrupt disabled + value: 0 + - name: Enabled + description: Interrupt enabled + value: 1 +enum/LSIRDYR: + bit_size: 1 + variants: + - name: NotReady + description: LSI oscillator not ready + value: 0 + - name: Ready + description: LSI oscillator ready + value: 1 +enum/LTDCRST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/MCO1: + bit_size: 3 + variants: + - name: HSI + description: HSI selected for micro-controller clock output + value: 0 + - name: LSE + description: LSE selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_Q + description: pll1_q selected for micro-controller clock output + value: 3 + - name: HSI48 + description: HSI48 selected for micro-controller clock output + value: 4 +enum/MCO2: + bit_size: 3 + variants: + - name: SYSCLK + description: System clock selected for micro-controller clock output + value: 0 + - name: PLL2_P + description: pll2_p selected for micro-controller clock output + value: 1 + - name: HSE + description: HSE selected for micro-controller clock output + value: 2 + - name: PLL1_P + description: pll1_p selected for micro-controller clock output + value: 3 + - name: CSI + description: CSI selected for micro-controller clock output + value: 4 + - name: LSI + description: LSI selected for micro-controller clock output + value: 5 +enum/MDMARST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/PLL1FRACEN: + bit_size: 1 + variants: + - name: Reset + description: Reset latch to tranfer FRACN to the Sigma-Delta modulator + value: 0 + - name: Set + description: Set latch to tranfer FRACN to the Sigma-Delta modulator + value: 1 +enum/PLL1RGE: + bit_size: 2 + variants: + - name: Range1 + description: Frequency is between 1 and 2 MHz + value: 0 + - name: Range2 + description: Frequency is between 2 and 4 MHz + value: 1 + - name: Range4 + description: Frequency is between 4 and 8 MHz + value: 2 + - name: Range8 + description: Frequency is between 8 and 16 MHz + value: 3 +enum/PLL1VCOSEL: + bit_size: 1 + variants: + - name: WideVCO + description: VCO frequency range 192 to 836 MHz + value: 0 + - name: MediumVCO + description: VCO frequency range 150 to 420 MHz + value: 1 +enum/PLLSRC: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as PLL clock + value: 0 + - name: CSI + description: CSI selected as PLL clock + value: 1 + - name: HSE + description: HSE selected as PLL clock + value: 2 + - name: None + description: No clock sent to DIVMx dividers and PLLs + value: 3 +enum/RNGSEL: + bit_size: 2 + variants: + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: LSE + description: LSE selected as peripheral clock + value: 2 + - name: LSI + description: LSI selected as peripheral clock + value: 3 +enum/RSR_CPURSTFR: + bit_size: 1 + variants: + - name: NoResetOccoured + description: No reset occoured for block + value: 0 + - name: ResetOccourred + description: Reset occoured for block + value: 1 +enum/RSR_RMVF: + bit_size: 1 + variants: + - name: NotActive + description: Not clearing the the reset flags + value: 0 + - name: Clear + description: Clear the reset flags + value: 1 +enum/RTCEN: + bit_size: 1 + variants: + - name: Disabled + description: RTC clock disabled + value: 0 + - name: Enabled + description: RTC clock enabled + value: 1 +enum/RTCSEL: + bit_size: 2 + variants: + - name: NoClock + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SAI1SEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: I2S_CKIN selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 +enum/SAI4ASEL: + bit_size: 3 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_P + description: pll2_p selected as peripheral clock + value: 1 + - name: PLL3_P + description: pll3_p selected as peripheral clock + value: 2 + - name: I2S_CKIN + description: i2s_ckin selected as peripheral clock + value: 3 + - name: PER + description: PER selected as peripheral clock + value: 4 +enum/SDMMCSEL: + bit_size: 1 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 +enum/SPDIFSEL: + bit_size: 2 + variants: + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 0 + - name: PLL2_R + description: pll2_r selected as peripheral clock + value: 1 + - name: PLL3_R + description: pll3_r selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 +enum/SPI45SEL: + bit_size: 3 + variants: + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/SPI6SEL: + bit_size: 3 + variants: + - name: RCC_PCLK4 + description: rcc_pclk4 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: HSE + description: HSE selected as peripheral clock + value: 5 +enum/STOPWUCK: + bit_size: 1 + variants: + - name: HSI + description: HSI selected as wake up clock from system Stop + value: 0 + - name: CSI + description: CSI selected as wake up clock from system Stop + value: 1 +enum/SW: + bit_size: 3 + variants: + - name: HSI + description: HSI selected as system clock + value: 0 + - name: CSI + description: CSI selected as system clock + value: 1 + - name: HSE + description: HSE selected as system clock + value: 2 + - name: PLL1 + description: PLL1 selected as system clock + value: 3 +enum/SWPSEL: + bit_size: 1 + variants: + - name: PCLK + description: pclk selected as peripheral clock + value: 0 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 1 +enum/SWSR: + bit_size: 3 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: CSI + description: CSI oscillator used as system clock + value: 1 + - name: HSE + description: HSE oscillator used as system clock + value: 2 + - name: PLL1 + description: PLL1 used as system clock + value: 3 +enum/SYSCFGRST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/TIM1RST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/TIM2RST: + bit_size: 1 + variants: + - name: Reset + description: Reset the selected module + value: 1 +enum/TIMPRE: + bit_size: 1 + variants: + - name: DefaultX2 + description: Timer kernel clock equal to 2x pclk by default + value: 0 + - name: DefaultX4 + description: Timer kernel clock equal to 4x pclk by default + value: 1 +enum/USART16SEL: + bit_size: 3 + variants: + - name: RCC_PCLK2 + description: rcc_pclk2 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USART234578SEL: + bit_size: 3 + variants: + - name: RCC_PCLK1 + description: rcc_pclk1 selected as peripheral clock + value: 0 + - name: PLL2_Q + description: pll2_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI_KER + description: hsi_ker selected as peripheral clock + value: 3 + - name: CSI_KER + description: csi_ker selected as peripheral clock + value: 4 + - name: LSE + description: LSE selected as peripheral clock + value: 5 +enum/USBSEL: + bit_size: 2 + variants: + - name: DISABLE + description: Disable the kernel clock + value: 0 + - name: PLL1_Q + description: pll1_q selected as peripheral clock + value: 1 + - name: PLL3_Q + description: pll3_q selected as peripheral clock + value: 2 + - name: HSI48 + description: HSI48 selected as peripheral clock + value: 3 +enum/WW1RSC: + bit_size: 1 + variants: + - name: Clear + description: Clear WWDG1 scope control + value: 0 + - name: Set + description: Set WWDG1 scope control + value: 1 diff --git a/parse.py b/parse.py index f260ad2..b2e3cc7 100644 --- a/parse.py +++ b/parse.py @@ -240,6 +240,10 @@ perimap = [ ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'), ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'), ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'), + ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'), + ('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'), + ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), + ('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'), ] @@ -330,7 +334,7 @@ def parse_chips(): 'flash': flash, 'ram': ram, 'gpio_af': gpio_af, - 'rcc': rcc, # temporarily stashing it here + 'rcc': rcc, # temporarily stashing it here 'packages': [], 'peripherals': {}, # 'peripherals': peris, @@ -379,7 +383,7 @@ def parse_chips(): if pname in clocks[rcc]: p['clock'] = clocks[rcc][pname] - #else: + # else: #print( f'peri {pname} -> no clock') if block := match_peri(chip_name+':'+pname+':'+pkind): @@ -420,6 +424,28 @@ def parse_chips(): 'block': 'exti_v1/EXTI', }) + # FLASH is not in the cubedb XMLs + if addr := h['defines'].get('FLASH_R_BASE'): + kind = 'FLASH:' + chip_name[:7] + '_flash_v1_0' + flash_peri = OrderedDict({ + 'address': addr, + 'kind': kind, + }) + if block := match_peri(kind): + flash_peri['block'] = block + peris['FLASH'] = flash_peri + + # DBGMCU is not in the cubedb XMLs + if addr := h['defines'].get('DBGMCU_BASE'): + kind = 'DBGMCU:' + chip_name[:7] + '_dbgmcu_v1_0' + dbg_peri = OrderedDict({ + 'address': addr, + 'kind': kind, + }) + if block := match_peri(kind): + dbg_peri['block'] = block + peris['DBGMCU'] = dbg_peri + chip['peripherals'] = peris with open('data/chips/'+chip_name+'.yaml', 'w') as f: @@ -468,8 +494,10 @@ def parse_gpio_af(): with open('data/gpio_af/'+ff+'.yaml', 'w') as f: f.write(yaml.dump(pins)) + clocks = {} + def parse_clocks(): for f in glob('sources/cubedb/mcu/IP/RCC-*rcc_v1_0_Modes.xml'): ff = removeprefix(f, 'sources/cubedb/mcu/IP/RCC-')