2ch_cmp, 2ch merged
This commit is contained in:
eZio Pan
parent
65a7e873c6
commit
864e7a7078
@ -1,572 +0,0 @@
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block/TIM_2CH:
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description: 2-channel timers
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items:
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- name: CR1
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description: control register 1
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byte_offset: 0
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fieldset: CR1_2CH
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- name: CR2
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description: control register 2
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byte_offset: 4
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fieldset: CR2_2CH
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- name: SMCR
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description: slave mode control register
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byte_offset: 8
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fieldset: SMCR_2CH
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- name: DIER
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description: DMA/Interrupt enable register
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byte_offset: 12
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fieldset: DIER_2CH
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- name: SR
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description: status register
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byte_offset: 16
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fieldset: SR_2CH
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- name: EGR
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description: event generation register
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byte_offset: 20
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access: Write
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fieldset: EGR_2CH
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- name: CCMR_Input
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description: capture/compare mode register 1 (input mode)
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array:
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len: 1
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Input_2CH
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- name: CCMR_Output
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description: capture/compare mode register 1 (output mode)
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array:
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len: 1
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Output_2CH
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- name: CCER
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description: capture/compare enable register
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byte_offset: 32
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fieldset: CCER_2CH
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- name: CNT
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description: counter
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byte_offset: 36
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fieldset: CNT_2CH
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- name: PSC
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description: prescaler
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byte_offset: 40
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fieldset: PSC_2CH
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- name: ARR
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description: auto-reload register (Dither mode disabled)
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byte_offset: 44
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fieldset: ARR_2CH
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- name: ARR_DITHER
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description: auto-reload register (Dither mode enabled)
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byte_offset: 44
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fieldset: ARR_DITHER_2CH
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- name: CCR
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description: capture/compare register x (x=1-2) (Dither mode disabled)
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array:
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len: 2
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stride: 4
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byte_offset: 52
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fieldset: CCR_2CH
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- name: CCR_DITHER
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description: capture/compare register x (x=1-2) (Dither mode enabled)
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array:
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len: 2
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_2CH
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- name: TISEL
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description: input selection register
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byte_offset: 92
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fieldset: TISEL_2CH
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fieldset/ARR_2CH:
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description: auto-reload register (Dither mode disabled)
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fields:
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- name: ARR
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description: Auto-reload value
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bit_offset: 0
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bit_size: 16
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fieldset/ARR_DITHER_2CH:
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description: auto-reload register (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: ARR
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description: Auto-reload value
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bit_offset: 4
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bit_size: 16
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fieldset/CCER_2CH:
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description: capture/compare enable register
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fields:
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- name: CCE
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description: Capture/Compare x (x=1-2) output enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 4
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- name: CCP
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description: Capture/Compare x (x=1-2) output Polarity
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 4
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- name: CCNP
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description: Capture/Compare x (x=1-2) output Polarity
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bit_offset: 3
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bit_size: 1
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array:
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len: 2
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stride: 4
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fieldset/CCMR_Input_2CH:
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description: capture/compare mode register x (x=1) (input mode)
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fields:
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- name: CCS
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description: Capture/Compare y selection
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bit_offset: 0
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bit_size: 2
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array:
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len: 2
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stride: 8
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enum: CCMR_Input_CCS
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- name: ICPSC
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description: Input capture y prescaler
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bit_offset: 2
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bit_size: 2
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array:
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len: 2
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stride: 8
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- name: ICF
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description: Input capture y filter
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bit_offset: 4
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bit_size: 4
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array:
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len: 2
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stride: 8
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enum: FilterValue
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fieldset/CCMR_Output_2CH:
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description: capture/compare mode register x (x=1) (output mode)
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fields:
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- name: CCS
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description: Capture/Compare y selection
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bit_offset: 0
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bit_size: 2
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array:
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len: 2
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stride: 8
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enum: CCMR_Output_CCS
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- name: OCFE
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description: Output compare y fast enable
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bit_offset: 2
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bit_size: 1
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array:
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len: 2
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stride: 8
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- name: OCPE
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description: Output compare y preload enable
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bit_offset: 3
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bit_size: 1
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array:
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len: 2
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stride: 8
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- name: OCM
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description: Output compare y mode
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bit_offset: 4
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bit_size: 3
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array:
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len: 2
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stride: 8
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enum: OCM
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fieldset/CCR_2CH:
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description: capture/compare register x (x=1,2) (Dither mode disabled)
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fields:
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- name: CCR
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description: capture/compare x (x=1,2) value
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bit_offset: 0
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bit_size: 16
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fieldset/CCR_DITHER_2CH:
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description: capture/compare register x (x=1,2) (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: CCR
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description: capture/compare x (x=1-2) value
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bit_offset: 4
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bit_size: 16
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fieldset/CNT_2CH:
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description: counter
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fields:
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- name: CNT
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description: counter value
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bit_offset: 0
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bit_size: 16
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- name: UIFCPY
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description: UIF copy
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bit_offset: 31
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bit_size: 1
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fieldset/CR1_2CH:
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description: control register 1
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fields:
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- name: CEN
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description: Counter enable
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bit_offset: 0
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bit_size: 1
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- name: UDIS
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description: Update disable
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bit_offset: 1
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bit_size: 1
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- name: URS
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description: Update request source
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bit_offset: 2
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bit_size: 1
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enum: URS
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- name: OPM
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description: One-pulse mode enbaled
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bit_offset: 3
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bit_size: 1
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- name: ARPE
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description: Auto-reload preload enable
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bit_offset: 7
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bit_size: 1
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- name: CKD
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description: Clock division
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bit_offset: 8
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bit_size: 2
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enum: CKD
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- name: UIFREMAP
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description: UIF status bit remapping enable
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bit_offset: 11
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bit_size: 1
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- name: DITHEN
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description: Dithering enable
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bit_offset: 12
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bit_size: 1
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fieldset/CR2_2CH:
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description: control register 2
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fields:
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- name: MMS
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description: Master mode selection
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bit_offset: 4
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bit_size: 3
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enum: MMS
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- name: TI1S
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description: TI1 selection
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bit_offset: 7
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bit_size: 1
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enum: TI1S
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fieldset/DIER_2CH:
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description: DMA/Interrupt enable register
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fields:
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- name: UIE
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description: Update interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: CCIE
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description: Capture/Compare x (x=1-2) interrupt enable
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: TIE
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description: Trigger interrupt enable
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bit_offset: 6
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bit_size: 1
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fieldset/EGR_2CH:
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description: event generation register
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fields:
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- name: UG
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description: Update generation
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bit_offset: 0
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bit_size: 1
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- name: CCG
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description: Capture/compare x (x=1-2) generation
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: TG
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description: Trigger generation
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bit_offset: 6
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bit_size: 1
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fieldset/PSC_2CH:
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description: prescaler
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fields:
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- name: PSC
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description: Prescaler value
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bit_offset: 0
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bit_size: 16
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fieldset/SMCR_2CH:
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description: slave mode control register
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fields:
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- name: SMS
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description: Slave mode selection
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bit_offset: 0
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bit_size: 3
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enum: SMS
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- name: TS
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description: Trigger selection
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bit_offset: 4
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bit_size: 3
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enum: TS
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- name: MSM
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description: Master/Slave mode
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bit_offset: 7
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bit_size: 1
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enum: MSM
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fieldset/SR_2CH:
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description: status register
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fields:
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- name: UIF
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description: Update interrupt flag
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bit_offset: 0
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bit_size: 1
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- name: CCIF
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description: Capture/compare x (x=1-2) interrupt flag
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: TIF
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description: Trigger interrupt flag
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bit_offset: 6
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bit_size: 1
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- name: CCOF
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description: Capture/Compare x (x=1-2) overcapture flag
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bit_offset: 9
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bit_size: 1
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array:
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len: 2
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stride: 1
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fieldset/TISEL_2CH:
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description: input selection register
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fields:
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- name: TISEL
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description: Selects TIM_TIx (x=1-2) input
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bit_offset: 0
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bit_size: 4
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array:
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len: 2
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stride: 8
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enum/CCMR_Input_CCS:
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bit_size: 2
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variants:
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- name: TI4
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description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx'
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value: 1
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- name: TI3
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description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)
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value: 2
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- name: TRC
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description: CCx channel is configured as input, ICx is mapped on TRC
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value: 3
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enum/CCMR_Output_CCS:
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bit_size: 2
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variants:
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- name: Output
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description: CCx channel is configured as output
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value: 0
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enum/CKD:
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bit_size: 2
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variants:
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- name: Div1
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description: t_DTS = t_CK_INT
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value: 0
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- name: Div2
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description: t_DTS = 2 × t_CK_INT
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value: 1
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- name: Div4
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description: t_DTS = 4 × t_CK_INT
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value: 2
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enum/FilterValue:
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bit_size: 4
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variants:
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- name: NoFilter
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description: No filter, sampling is done at fDTS
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value: 0
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- name: FCK_INT_N2
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description: fSAMPLING=fCK_INT, N=2
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value: 1
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- name: FCK_INT_N4
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description: fSAMPLING=fCK_INT, N=4
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value: 2
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- name: FCK_INT_N8
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description: fSAMPLING=fCK_INT, N=8
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value: 3
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- name: FDTS_Div2_N6
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description: fSAMPLING=fDTS/2, N=6
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value: 4
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- name: FDTS_Div2_N8
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description: fSAMPLING=fDTS/2, N=8
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value: 5
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- name: FDTS_Div4_N6
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description: fSAMPLING=fDTS/4, N=6
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value: 6
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- name: FDTS_Div4_N8
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description: fSAMPLING=fDTS/4, N=8
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value: 7
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- name: FDTS_Div8_N6
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description: fSAMPLING=fDTS/8, N=6
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value: 8
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- name: FDTS_Div8_N8
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description: fSAMPLING=fDTS/8, N=8
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value: 9
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- name: FDTS_Div16_N5
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description: fSAMPLING=fDTS/16, N=5
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value: 10
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- name: FDTS_Div16_N6
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description: fSAMPLING=fDTS/16, N=6
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value: 11
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||||||
- name: FDTS_Div16_N8
|
|
||||||
description: fSAMPLING=fDTS/16, N=8
|
|
||||||
value: 12
|
|
||||||
- name: FDTS_Div32_N5
|
|
||||||
description: fSAMPLING=fDTS/32, N=5
|
|
||||||
value: 13
|
|
||||||
- name: FDTS_Div32_N6
|
|
||||||
description: fSAMPLING=fDTS/32, N=6
|
|
||||||
value: 14
|
|
||||||
- name: FDTS_Div32_N8
|
|
||||||
description: fSAMPLING=fDTS/32, N=8
|
|
||||||
value: 15
|
|
||||||
enum/MMS:
|
|
||||||
bit_size: 3
|
|
||||||
variants:
|
|
||||||
- name: Reset
|
|
||||||
description: The UG bit from the TIMx_EGR register is used as trigger output
|
|
||||||
value: 0
|
|
||||||
- name: Enable
|
|
||||||
description: The counter enable signal, CNT_EN, is used as trigger output
|
|
||||||
value: 1
|
|
||||||
- name: Update
|
|
||||||
description: The update event is selected as trigger output
|
|
||||||
value: 2
|
|
||||||
- name: ComparePulse
|
|
||||||
description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
|
|
||||||
value: 3
|
|
||||||
- name: CompareOC1
|
|
||||||
description: OC1REF signal is used as trigger output
|
|
||||||
value: 4
|
|
||||||
- name: CompareOC2
|
|
||||||
description: OC2REF signal is used as trigger output
|
|
||||||
value: 5
|
|
||||||
- name: CompareOC3
|
|
||||||
description: OC3REF signal is used as trigger output
|
|
||||||
value: 6
|
|
||||||
- name: CompareOC4
|
|
||||||
description: OC4REF signal is used as trigger output
|
|
||||||
value: 7
|
|
||||||
enum/MSM:
|
|
||||||
bit_size: 1
|
|
||||||
variants:
|
|
||||||
- name: NoSync
|
|
||||||
description: No action
|
|
||||||
value: 0
|
|
||||||
- name: Sync
|
|
||||||
description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
|
|
||||||
value: 1
|
|
||||||
enum/OCM:
|
|
||||||
bit_size: 3
|
|
||||||
variants:
|
|
||||||
- name: Frozen
|
|
||||||
description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
|
|
||||||
value: 0
|
|
||||||
- name: ActiveOnMatch
|
|
||||||
description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
|
|
||||||
value: 1
|
|
||||||
- name: InactiveOnMatch
|
|
||||||
description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
|
|
||||||
value: 2
|
|
||||||
- name: Toggle
|
|
||||||
description: OCyREF toggles when TIMx_CNT=TIMx_CCRy
|
|
||||||
value: 3
|
|
||||||
- name: ForceInactive
|
|
||||||
description: OCyREF is forced low
|
|
||||||
value: 4
|
|
||||||
- name: ForceActive
|
|
||||||
description: OCyREF is forced high
|
|
||||||
value: 5
|
|
||||||
- name: PwmMode1
|
|
||||||
description: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
|
|
||||||
value: 6
|
|
||||||
- name: PwmMode2
|
|
||||||
description: Inversely to PwmMode1
|
|
||||||
value: 7
|
|
||||||
enum/SMS:
|
|
||||||
bit_size: 3
|
|
||||||
variants:
|
|
||||||
- name: Disabled
|
|
||||||
description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
|
|
||||||
value: 0
|
|
||||||
- name: Encoder_Mode_1
|
|
||||||
description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
|
|
||||||
value: 1
|
|
||||||
- name: Encoder_Mode_2
|
|
||||||
description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
|
|
||||||
value: 2
|
|
||||||
- name: Encoder_Mode_3
|
|
||||||
description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
|
|
||||||
value: 3
|
|
||||||
- name: Reset_Mode
|
|
||||||
description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
|
|
||||||
value: 4
|
|
||||||
- name: Gated_Mode
|
|
||||||
description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
|
|
||||||
value: 5
|
|
||||||
- name: Trigger_Mode
|
|
||||||
description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
|
|
||||||
value: 6
|
|
||||||
- name: Ext_Clock_Mode
|
|
||||||
description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
|
|
||||||
value: 7
|
|
||||||
enum/TI1S:
|
|
||||||
bit_size: 1
|
|
||||||
variants:
|
|
||||||
- name: Normal
|
|
||||||
description: The TIMx_CH1 pin is connected to TI1 input
|
|
||||||
value: 0
|
|
||||||
- name: XOR
|
|
||||||
description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
|
|
||||||
value: 1
|
|
||||||
enum/TS:
|
|
||||||
bit_size: 3
|
|
||||||
variants:
|
|
||||||
- name: ITR0
|
|
||||||
description: Internal Trigger 0 (ITR0)
|
|
||||||
value: 0
|
|
||||||
- name: ITR1
|
|
||||||
description: Internal Trigger 1 (ITR1)
|
|
||||||
value: 1
|
|
||||||
- name: ITR2
|
|
||||||
description: Internal Trigger 2 (ITR2)
|
|
||||||
value: 2
|
|
||||||
- name: ITR3
|
|
||||||
description: Internal Trigger 3 (ITR3)
|
|
||||||
value: 3
|
|
||||||
- name: TI1F_ED
|
|
||||||
description: TI1 Edge Detector (TI1F_ED)
|
|
||||||
value: 4
|
|
||||||
- name: TI1FP1
|
|
||||||
description: Filtered Timer Input 1 (TI1FP1)
|
|
||||||
value: 5
|
|
||||||
- name: TI2FP2
|
|
||||||
description: Filtered Timer Input 2 (TI2FP2)
|
|
||||||
value: 6
|
|
||||||
- name: ETRF
|
|
||||||
description: External Trigger input (ETRF)
|
|
||||||
value: 7
|
|
||||||
enum/URS:
|
|
||||||
bit_size: 1
|
|
||||||
variants:
|
|
||||||
- name: AnyEvent
|
|
||||||
description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
|
|
||||||
value: 0
|
|
||||||
- name: CounterOnly
|
|
||||||
description: Only counter overflow/underflow generates an update interrupt or DMA request
|
|
||||||
value: 1
|
|
||||||
@ -1,112 +1,145 @@
|
|||||||
block/TIM_2CH_CMP:
|
block/TIM_2CH:
|
||||||
description: 2-channel with one complementary output timers
|
description: 2-channel timers
|
||||||
items:
|
items:
|
||||||
- name: CR1
|
- name: CR1
|
||||||
description: control register 1
|
description: control register 1
|
||||||
byte_offset: 0
|
byte_offset: 0
|
||||||
fieldset: CR1_1CH_CMP
|
fieldset: CR1_2CH
|
||||||
- name: CR2
|
- name: CR2
|
||||||
description: control register 2
|
description: control register 2
|
||||||
byte_offset: 4
|
byte_offset: 4
|
||||||
fieldset: CR2_1CH_CMP
|
fieldset: CR2_2CH
|
||||||
- name: SMCR
|
- name: SMCR
|
||||||
description: slave mode control register
|
description: slave mode control register
|
||||||
byte_offset: 8
|
byte_offset: 8
|
||||||
fieldset: SMCR_1CH_CMP
|
fieldset: SMCR_2CH
|
||||||
- name: DIER
|
- name: DIER
|
||||||
description: DMA/Interrupt enable register
|
description: DMA/Interrupt enable register
|
||||||
byte_offset: 12
|
byte_offset: 12
|
||||||
fieldset: DIER_1CH_CMP
|
fieldset: DIER_2CH
|
||||||
- name: SR
|
- name: SR
|
||||||
description: status register
|
description: status register
|
||||||
byte_offset: 16
|
byte_offset: 16
|
||||||
fieldset: SR_1CH_CMP
|
fieldset: SR_2CH
|
||||||
- name: EGR
|
- name: EGR
|
||||||
description: event generation register
|
description: event generation register
|
||||||
byte_offset: 20
|
byte_offset: 20
|
||||||
access: Write
|
access: Write
|
||||||
fieldset: EGR_1CH_CMP
|
fieldset: EGR_2CH
|
||||||
- name: CCMR_Input
|
- name: CCMR_Input
|
||||||
description: capture/compare mode register 1 (input mode)
|
description: capture/compare mode register 1 (input mode)
|
||||||
array:
|
array:
|
||||||
len: 1
|
len: 1
|
||||||
stride: 4
|
stride: 4
|
||||||
byte_offset: 24
|
byte_offset: 24
|
||||||
fieldset: CCMR_Input_1CH_CMP
|
fieldset: CCMR_Input_2CH
|
||||||
- name: CCMR_Output
|
- name: CCMR_Output
|
||||||
description: capture/compare mode register 1 (output mode)
|
description: capture/compare mode register 1 (output mode)
|
||||||
array:
|
array:
|
||||||
len: 1
|
len: 1
|
||||||
stride: 4
|
stride: 4
|
||||||
byte_offset: 24
|
byte_offset: 24
|
||||||
fieldset: CCMR_Output_1CH_CMP
|
fieldset: CCMR_Output_2CH
|
||||||
- name: CCER
|
- name: CCER
|
||||||
description: capture/compare enable register
|
description: capture/compare enable register
|
||||||
byte_offset: 32
|
byte_offset: 32
|
||||||
fieldset: CCER_1CH_CMP
|
fieldset: CCER_2CH
|
||||||
- name: CNT
|
- name: CNT
|
||||||
description: counter
|
description: counter
|
||||||
byte_offset: 36
|
byte_offset: 36
|
||||||
fieldset: CNT_1CH_CMP
|
fieldset: CNT_2CH
|
||||||
- name: PSC
|
- name: PSC
|
||||||
description: prescaler
|
description: prescaler
|
||||||
byte_offset: 40
|
byte_offset: 40
|
||||||
fieldset: PSC_1CH_CMP
|
fieldset: PSC_2CH
|
||||||
- name: ARR
|
- name: ARR
|
||||||
description: auto-reload register (Dither mode disabled)
|
description: auto-reload register (Dither mode disabled)
|
||||||
byte_offset: 44
|
byte_offset: 44
|
||||||
fieldset: ARR_1CH_CMP
|
fieldset: ARR_2CH
|
||||||
- name: ARR_DITHER
|
- name: ARR_DITHER
|
||||||
description: auto-reload register (Dither mode enabled)
|
description: auto-reload register (Dither mode enabled)
|
||||||
byte_offset: 44
|
byte_offset: 44
|
||||||
fieldset: ARR_DITHER_1CH_CMP
|
fieldset: ARR_DITHER_2CH
|
||||||
- name: RCR
|
|
||||||
description: repetition counter register
|
|
||||||
byte_offset: 48
|
|
||||||
fieldset: RCR_1CH_CMP
|
|
||||||
- name: CCR
|
- name: CCR
|
||||||
description: capture/compare register x (x=1-2) (Dither mode disabled)
|
description: capture/compare register x (x=1-2) (Dither mode disabled)
|
||||||
array:
|
array:
|
||||||
len: 2
|
len: 2
|
||||||
stride: 4
|
stride: 4
|
||||||
byte_offset: 52
|
byte_offset: 52
|
||||||
fieldset: CCR_1CH_CMP
|
fieldset: CCR_2CH
|
||||||
- name: CCR_DITHER
|
- name: CCR_DITHER
|
||||||
description: capture/compare register x (x=1-2) (Dither mode enabled)
|
description: capture/compare register x (x=1-2) (Dither mode enabled)
|
||||||
array:
|
array:
|
||||||
len: 2
|
len: 2
|
||||||
stride: 4
|
stride: 4
|
||||||
byte_offset: 52
|
byte_offset: 52
|
||||||
fieldset: CCR_DITHER_1CH_CMP
|
fieldset: CCR_DITHER_2CH
|
||||||
- name: BDTR
|
|
||||||
description: break and dead-time register
|
|
||||||
byte_offset: 68
|
|
||||||
fieldset: BDTR_1CH_CMP
|
|
||||||
- name: DTR2
|
|
||||||
description: break and dead-time register
|
|
||||||
byte_offset: 84
|
|
||||||
fieldset: DTR2_1CH_CMP
|
|
||||||
- name: TISEL
|
- name: TISEL
|
||||||
description: input selection register
|
description: input selection register
|
||||||
byte_offset: 92
|
byte_offset: 92
|
||||||
fieldset: TISEL_1CH_CMP
|
fieldset: TISEL_2CH
|
||||||
|
block/TIM_2CH_CMP:
|
||||||
|
extends: TIM_2CH
|
||||||
|
description: 2-channel with one complementary output timers
|
||||||
|
items:
|
||||||
|
- name: CR2
|
||||||
|
description: control register 2
|
||||||
|
byte_offset: 4
|
||||||
|
fieldset: CR2_2CH_CMP
|
||||||
|
- name: SMCR
|
||||||
|
description: slave mode control register
|
||||||
|
byte_offset: 8
|
||||||
|
fieldset: SMCR_2CH_CMP
|
||||||
|
- name: DIER
|
||||||
|
description: DMA/Interrupt enable register
|
||||||
|
byte_offset: 12
|
||||||
|
fieldset: DIER_2CH_CMP
|
||||||
|
- name: SR
|
||||||
|
description: status register
|
||||||
|
byte_offset: 16
|
||||||
|
fieldset: SR_2CH_CMP
|
||||||
|
- name: EGR
|
||||||
|
description: event generation register
|
||||||
|
byte_offset: 20
|
||||||
|
access: Write
|
||||||
|
fieldset: EGR_2CH_CMP
|
||||||
|
- name: CCER
|
||||||
|
description: capture/compare enable register
|
||||||
|
byte_offset: 32
|
||||||
|
fieldset: CCER_2CH_CMP
|
||||||
|
- name: RCR
|
||||||
|
description: repetition counter register
|
||||||
|
byte_offset: 48
|
||||||
|
fieldset: RCR_2CH_CMP
|
||||||
|
- name: BDTR
|
||||||
|
description: break and dead-time register
|
||||||
|
byte_offset: 68
|
||||||
|
fieldset: BDTR_2CH_CMP
|
||||||
|
- name: DTR2
|
||||||
|
description: break and dead-time register
|
||||||
|
byte_offset: 84
|
||||||
|
fieldset: DTR2_2CH_CMP
|
||||||
|
- name: TISEL
|
||||||
|
description: input selection register
|
||||||
|
byte_offset: 92
|
||||||
|
fieldset: TISEL_2CH_CMP
|
||||||
- name: AF1
|
- name: AF1
|
||||||
description: alternate function register 1
|
description: alternate function register 1
|
||||||
byte_offset: 96
|
byte_offset: 96
|
||||||
fieldset: AF1_1CH_CMP
|
fieldset: AF1_2CH_CMP
|
||||||
- name: AF2
|
- name: AF2
|
||||||
description: alternate function register 2
|
description: alternate function register 2
|
||||||
byte_offset: 100
|
byte_offset: 100
|
||||||
fieldset: AF2_1CH_CMP
|
fieldset: AF2_2CH_CMP
|
||||||
- name: DCR
|
- name: DCR
|
||||||
description: DMA control register
|
description: DMA control register
|
||||||
byte_offset: 988
|
byte_offset: 988
|
||||||
fieldset: DCR_1CH_CMP
|
fieldset: DCR_2CH_CMP
|
||||||
- name: DMAR
|
- name: DMAR
|
||||||
description: DMA address for full transfer
|
description: DMA address for full transfer
|
||||||
byte_offset: 992
|
byte_offset: 992
|
||||||
fieldset: DMAR_1CH_CMP
|
fieldset: DMAR_2CH_CMP
|
||||||
fieldset/AF1_1CH_CMP:
|
fieldset/AF1_2CH_CMP:
|
||||||
description: alternate function register 1
|
description: alternate function register 1
|
||||||
fields:
|
fields:
|
||||||
- name: BKINE
|
- name: BKINE
|
||||||
@ -133,21 +166,21 @@ fieldset/AF1_1CH_CMP:
|
|||||||
len: 4
|
len: 4
|
||||||
stride: 1
|
stride: 1
|
||||||
enum: BKINP
|
enum: BKINP
|
||||||
fieldset/AF2_1CH_CMP:
|
fieldset/AF2_2CH_CMP:
|
||||||
description: alternate function register 2
|
description: alternate function register 2
|
||||||
fields:
|
fields:
|
||||||
- name: OCRSEL
|
- name: OCRSEL
|
||||||
description: ocref_clr source selection
|
description: ocref_clr source selection
|
||||||
bit_offset: 16
|
bit_offset: 16
|
||||||
bit_size: 3
|
bit_size: 3
|
||||||
fieldset/ARR_1CH_CMP:
|
fieldset/ARR_2CH:
|
||||||
description: auto-reload register (Dither mode disabled)
|
description: auto-reload register (Dither mode disabled)
|
||||||
fields:
|
fields:
|
||||||
- name: ARR
|
- name: ARR
|
||||||
description: Auto-reload value
|
description: Auto-reload value
|
||||||
bit_offset: 0
|
bit_offset: 0
|
||||||
bit_size: 16
|
bit_size: 16
|
||||||
fieldset/ARR_DITHER_1CH_CMP:
|
fieldset/ARR_DITHER_2CH:
|
||||||
description: auto-reload register (Dither mode enabled)
|
description: auto-reload register (Dither mode enabled)
|
||||||
fields:
|
fields:
|
||||||
- name: DITHER
|
- name: DITHER
|
||||||
@ -158,7 +191,7 @@ fieldset/ARR_DITHER_1CH_CMP:
|
|||||||
description: Auto-reload value
|
description: Auto-reload value
|
||||||
bit_offset: 4
|
bit_offset: 4
|
||||||
bit_size: 16
|
bit_size: 16
|
||||||
fieldset/BDTR_1CH_CMP:
|
fieldset/BDTR_2CH_CMP:
|
||||||
description: break and dead-time register
|
description: break and dead-time register
|
||||||
fields:
|
fields:
|
||||||
- name: DTG
|
- name: DTG
|
||||||
@ -227,7 +260,7 @@ fieldset/BDTR_1CH_CMP:
|
|||||||
len: 1
|
len: 1
|
||||||
stride: 1
|
stride: 1
|
||||||
enum: BKBID
|
enum: BKBID
|
||||||
fieldset/CCER_1CH_CMP:
|
fieldset/CCER_2CH:
|
||||||
description: capture/compare enable register
|
description: capture/compare enable register
|
||||||
fields:
|
fields:
|
||||||
- name: CCE
|
- name: CCE
|
||||||
@ -244,13 +277,6 @@ fieldset/CCER_1CH_CMP:
|
|||||||
array:
|
array:
|
||||||
len: 2
|
len: 2
|
||||||
stride: 4
|
stride: 4
|
||||||
- name: CCNE
|
|
||||||
description: Capture/Compare x (x=1) complementary output enable
|
|
||||||
bit_offset: 2
|
|
||||||
bit_size: 1
|
|
||||||
array:
|
|
||||||
len: 1
|
|
||||||
stride: 4
|
|
||||||
- name: CCNP
|
- name: CCNP
|
||||||
description: Capture/Compare x (x=1-2) output Polarity
|
description: Capture/Compare x (x=1-2) output Polarity
|
||||||
bit_offset: 3
|
bit_offset: 3
|
||||||
@ -258,7 +284,18 @@ fieldset/CCER_1CH_CMP:
|
|||||||
array:
|
array:
|
||||||
len: 2
|
len: 2
|
||||||
stride: 4
|
stride: 4
|
||||||
fieldset/CCMR_Input_1CH_CMP:
|
fieldset/CCER_2CH_CMP:
|
||||||
|
extends: CCER_2CH
|
||||||
|
description: capture/compare enable register
|
||||||
|
fields:
|
||||||
|
- name: CCNE
|
||||||
|
description: Capture/Compare x (x=1) complementary output enable
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 1
|
||||||
|
stride: 4
|
||||||
|
fieldset/CCMR_Input_2CH:
|
||||||
description: capture/compare mode register x (x=1) (input mode)
|
description: capture/compare mode register x (x=1) (input mode)
|
||||||
fields:
|
fields:
|
||||||
- name: CCS
|
- name: CCS
|
||||||
@ -284,7 +321,7 @@ fieldset/CCMR_Input_1CH_CMP:
|
|||||||
len: 2
|
len: 2
|
||||||
stride: 8
|
stride: 8
|
||||||
enum: FilterValue
|
enum: FilterValue
|
||||||
fieldset/CCMR_Output_1CH_CMP:
|
fieldset/CCMR_Output_2CH:
|
||||||
description: capture/compare mode register x (x=1) (output mode)
|
description: capture/compare mode register x (x=1) (output mode)
|
||||||
fields:
|
fields:
|
||||||
- name: CCS
|
- name: CCS
|
||||||
@ -317,21 +354,14 @@ fieldset/CCMR_Output_1CH_CMP:
|
|||||||
len: 2
|
len: 2
|
||||||
stride: 8
|
stride: 8
|
||||||
enum: OCM
|
enum: OCM
|
||||||
- name: OCCE
|
fieldset/CCR_2CH:
|
||||||
description: Output compare y clear enable
|
|
||||||
bit_offset: 7
|
|
||||||
bit_size: 1
|
|
||||||
array:
|
|
||||||
len: 2
|
|
||||||
stride: 8
|
|
||||||
fieldset/CCR_1CH_CMP:
|
|
||||||
description: capture/compare register x (x=1,2) (Dither mode disabled)
|
description: capture/compare register x (x=1,2) (Dither mode disabled)
|
||||||
fields:
|
fields:
|
||||||
- name: CCR
|
- name: CCR
|
||||||
description: capture/compare x (x=1,2) value
|
description: capture/compare x (x=1,2) value
|
||||||
bit_offset: 0
|
bit_offset: 0
|
||||||
bit_size: 16
|
bit_size: 16
|
||||||
fieldset/CCR_DITHER_1CH_CMP:
|
fieldset/CCR_DITHER_2CH:
|
||||||
description: capture/compare register x (x=1,2) (Dither mode enabled)
|
description: capture/compare register x (x=1,2) (Dither mode enabled)
|
||||||
fields:
|
fields:
|
||||||
- name: DITHER
|
- name: DITHER
|
||||||
@ -342,7 +372,7 @@ fieldset/CCR_DITHER_1CH_CMP:
|
|||||||
description: capture/compare x (x=1-2) value
|
description: capture/compare x (x=1-2) value
|
||||||
bit_offset: 4
|
bit_offset: 4
|
||||||
bit_size: 16
|
bit_size: 16
|
||||||
fieldset/CNT_1CH_CMP:
|
fieldset/CNT_2CH:
|
||||||
description: counter
|
description: counter
|
||||||
fields:
|
fields:
|
||||||
- name: CNT
|
- name: CNT
|
||||||
@ -353,7 +383,7 @@ fieldset/CNT_1CH_CMP:
|
|||||||
description: UIF copy
|
description: UIF copy
|
||||||
bit_offset: 31
|
bit_offset: 31
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
fieldset/CR1_1CH_CMP:
|
fieldset/CR1_2CH:
|
||||||
description: control register 1
|
description: control register 1
|
||||||
fields:
|
fields:
|
||||||
- name: CEN
|
- name: CEN
|
||||||
@ -390,7 +420,22 @@ fieldset/CR1_1CH_CMP:
|
|||||||
description: Dithering enable
|
description: Dithering enable
|
||||||
bit_offset: 12
|
bit_offset: 12
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
fieldset/CR2_1CH_CMP:
|
|
||||||
|
fieldset/CR2_2CH:
|
||||||
|
description: control register 2
|
||||||
|
fields:
|
||||||
|
- name: MMS
|
||||||
|
description: Master mode selection
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 3
|
||||||
|
enum: MMS
|
||||||
|
- name: TI1S
|
||||||
|
description: TI1 selection
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
enum: TI1S
|
||||||
|
fieldset/CR2_2CH_CMP:
|
||||||
|
extends: CR2_2CH
|
||||||
description: control register 2
|
description: control register 2
|
||||||
fields:
|
fields:
|
||||||
- name: CCPC
|
- name: CCPC
|
||||||
@ -406,16 +451,6 @@ fieldset/CR2_1CH_CMP:
|
|||||||
bit_offset: 3
|
bit_offset: 3
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
enum: CCDS
|
enum: CCDS
|
||||||
- name: MMS
|
|
||||||
description: Master mode selection
|
|
||||||
bit_offset: 4
|
|
||||||
bit_size: 3
|
|
||||||
enum: MMS
|
|
||||||
- name: TI1S
|
|
||||||
description: TI1 selection
|
|
||||||
bit_offset: 7
|
|
||||||
bit_size: 1
|
|
||||||
enum: TI1S
|
|
||||||
- name: OIS
|
- name: OIS
|
||||||
description: Output Idle state x (x=1,2)
|
description: Output Idle state x (x=1,2)
|
||||||
bit_offset: 8
|
bit_offset: 8
|
||||||
@ -430,7 +465,7 @@ fieldset/CR2_1CH_CMP:
|
|||||||
array:
|
array:
|
||||||
len: 1
|
len: 1
|
||||||
stride: 2
|
stride: 2
|
||||||
fieldset/DCR_1CH_CMP:
|
fieldset/DCR_2CH_CMP:
|
||||||
description: DMA control register
|
description: DMA control register
|
||||||
fields:
|
fields:
|
||||||
- name: DBA
|
- name: DBA
|
||||||
@ -446,7 +481,7 @@ fieldset/DCR_1CH_CMP:
|
|||||||
bit_offset: 16
|
bit_offset: 16
|
||||||
bit_size: 4
|
bit_size: 4
|
||||||
enum: DBSS
|
enum: DBSS
|
||||||
fieldset/DIER_1CH_CMP:
|
fieldset/DIER_2CH:
|
||||||
description: DMA/Interrupt enable register
|
description: DMA/Interrupt enable register
|
||||||
fields:
|
fields:
|
||||||
- name: UIE
|
- name: UIE
|
||||||
@ -460,14 +495,18 @@ fieldset/DIER_1CH_CMP:
|
|||||||
array:
|
array:
|
||||||
len: 2
|
len: 2
|
||||||
stride: 1
|
stride: 1
|
||||||
- name: COMIE
|
|
||||||
description: COM interrupt enable
|
|
||||||
bit_offset: 5
|
|
||||||
bit_size: 1
|
|
||||||
- name: TIE
|
- name: TIE
|
||||||
description: Trigger interrupt enable
|
description: Trigger interrupt enable
|
||||||
bit_offset: 6
|
bit_offset: 6
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
|
fieldset/DIER_2CH_CMP:
|
||||||
|
extends: DIER_2CH
|
||||||
|
description: DMA/Interrupt enable register
|
||||||
|
fields:
|
||||||
|
- name: COMIE
|
||||||
|
description: COM interrupt enable
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
- name: BIE
|
- name: BIE
|
||||||
description: Break interrupt enable
|
description: Break interrupt enable
|
||||||
bit_offset: 7
|
bit_offset: 7
|
||||||
@ -491,14 +530,14 @@ fieldset/DIER_1CH_CMP:
|
|||||||
description: Trigger DMA request enable
|
description: Trigger DMA request enable
|
||||||
bit_offset: 14
|
bit_offset: 14
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
fieldset/DMAR_1CH_CMP:
|
fieldset/DMAR_2CH_CMP:
|
||||||
description: DMA address for full transfer
|
description: DMA address for full transfer
|
||||||
fields:
|
fields:
|
||||||
- name: DMAB
|
- name: DMAB
|
||||||
description: DMA register for burst accesses
|
description: DMA register for burst accesses
|
||||||
bit_offset: 0
|
bit_offset: 0
|
||||||
bit_size: 32
|
bit_size: 32
|
||||||
fieldset/DTR2_1CH_CMP:
|
fieldset/DTR2_2CH_CMP:
|
||||||
description: deadtime register 2
|
description: deadtime register 2
|
||||||
fields:
|
fields:
|
||||||
- name: DTGF
|
- name: DTGF
|
||||||
@ -514,7 +553,7 @@ fieldset/DTR2_1CH_CMP:
|
|||||||
description: Deadtime preload enable
|
description: Deadtime preload enable
|
||||||
bit_offset: 17
|
bit_offset: 17
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
fieldset/EGR_1CH_CMP:
|
fieldset/EGR_2CH:
|
||||||
description: event generation register
|
description: event generation register
|
||||||
fields:
|
fields:
|
||||||
- name: UG
|
- name: UG
|
||||||
@ -528,14 +567,18 @@ fieldset/EGR_1CH_CMP:
|
|||||||
array:
|
array:
|
||||||
len: 2
|
len: 2
|
||||||
stride: 1
|
stride: 1
|
||||||
- name: COMG
|
|
||||||
description: Capture/Compare control update generation
|
|
||||||
bit_offset: 5
|
|
||||||
bit_size: 1
|
|
||||||
- name: TG
|
- name: TG
|
||||||
description: Trigger generation
|
description: Trigger generation
|
||||||
bit_offset: 6
|
bit_offset: 6
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
|
fieldset/EGR_2CH_CMP:
|
||||||
|
extends: EGR_2CH
|
||||||
|
description: event generation register
|
||||||
|
fields:
|
||||||
|
- name: COMG
|
||||||
|
description: Capture/Compare control update generation
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
- name: BG
|
- name: BG
|
||||||
description: Break x (x=1) generation
|
description: Break x (x=1) generation
|
||||||
bit_offset: 7
|
bit_offset: 7
|
||||||
@ -543,21 +586,21 @@ fieldset/EGR_1CH_CMP:
|
|||||||
array:
|
array:
|
||||||
len: 1
|
len: 1
|
||||||
stride: 1
|
stride: 1
|
||||||
fieldset/PSC_1CH_CMP:
|
fieldset/PSC_2CH:
|
||||||
description: prescaler
|
description: prescaler
|
||||||
fields:
|
fields:
|
||||||
- name: PSC
|
- name: PSC
|
||||||
description: Prescaler value
|
description: Prescaler value
|
||||||
bit_offset: 0
|
bit_offset: 0
|
||||||
bit_size: 16
|
bit_size: 16
|
||||||
fieldset/RCR_1CH_CMP:
|
fieldset/RCR_2CH_CMP:
|
||||||
description: repetition counter register
|
description: repetition counter register
|
||||||
fields:
|
fields:
|
||||||
- name: REP
|
- name: REP
|
||||||
description: Repetition counter value
|
description: Repetition counter value
|
||||||
bit_offset: 0
|
bit_offset: 0
|
||||||
bit_size: 8
|
bit_size: 8
|
||||||
fieldset/SMCR_1CH_CMP:
|
fieldset/SMCR_2CH:
|
||||||
description: slave mode control register
|
description: slave mode control register
|
||||||
fields:
|
fields:
|
||||||
- name: SMS
|
- name: SMS
|
||||||
@ -575,11 +618,15 @@ fieldset/SMCR_1CH_CMP:
|
|||||||
bit_offset: 7
|
bit_offset: 7
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
enum: MSM
|
enum: MSM
|
||||||
|
fieldset/SMCR_2CH_CMP:
|
||||||
|
extends: SMCR_2CH
|
||||||
|
description: slave mode control register
|
||||||
|
fields:
|
||||||
- name: SMSPE
|
- name: SMSPE
|
||||||
description: SMS preload enable
|
description: SMS preload enable
|
||||||
bit_offset: 24
|
bit_offset: 24
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
fieldset/SR_1CH_CMP:
|
fieldset/SR_2CH:
|
||||||
description: status register
|
description: status register
|
||||||
fields:
|
fields:
|
||||||
- name: UIF
|
- name: UIF
|
||||||
@ -593,14 +640,25 @@ fieldset/SR_1CH_CMP:
|
|||||||
array:
|
array:
|
||||||
len: 2
|
len: 2
|
||||||
stride: 1
|
stride: 1
|
||||||
- name: COMIF
|
|
||||||
description: COM interrupt flag
|
|
||||||
bit_offset: 5
|
|
||||||
bit_size: 1
|
|
||||||
- name: TIF
|
- name: TIF
|
||||||
description: Trigger interrupt flag
|
description: Trigger interrupt flag
|
||||||
bit_offset: 6
|
bit_offset: 6
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
|
- name: CCOF
|
||||||
|
description: Capture/Compare x (x=1-2) overcapture flag
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
fieldset/SR_2CH_CMP:
|
||||||
|
extends: SR_2CH
|
||||||
|
description: status register
|
||||||
|
fields:
|
||||||
|
- name: COMIF
|
||||||
|
description: COM interrupt flag
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
- name: BIF
|
- name: BIF
|
||||||
description: Break x (x=1) interrupt flag
|
description: Break x (x=1) interrupt flag
|
||||||
bit_offset: 7
|
bit_offset: 7
|
||||||
@ -608,14 +666,17 @@ fieldset/SR_1CH_CMP:
|
|||||||
array:
|
array:
|
||||||
len: 1
|
len: 1
|
||||||
stride: 1
|
stride: 1
|
||||||
- name: CCOF
|
fieldset/TISEL_2CH:
|
||||||
description: Capture/Compare x (x=1-2) overcapture flag
|
description: input selection register
|
||||||
bit_offset: 9
|
fields:
|
||||||
bit_size: 1
|
- name: TISEL
|
||||||
|
description: Selects TIM_TIx (x=1-2) input
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
array:
|
array:
|
||||||
len: 2
|
len: 2
|
||||||
stride: 1
|
stride: 8
|
||||||
fieldset/TISEL_1CH_CMP:
|
fieldset/TISEL_2CH_CMP:
|
||||||
description: input selection register
|
description: input selection register
|
||||||
fields:
|
fields:
|
||||||
- name: TISEL
|
- name: TISEL
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user