From 84b6d351dcb0a57c60d85e5c474a83fd0ea776ce Mon Sep 17 00:00:00 2001 From: Thales Fragoso Date: Thu, 20 May 2021 22:04:22 -0300 Subject: [PATCH] Add H7 DBGMCU --- data/registers/dbgmcu_h7.yaml | 191 ++++++++++++++++++++++++++++++++++ parse.py | 12 +++ 2 files changed, 203 insertions(+) create mode 100644 data/registers/dbgmcu_h7.yaml diff --git a/data/registers/dbgmcu_h7.yaml b/data/registers/dbgmcu_h7.yaml new file mode 100644 index 0000000..9a826af --- /dev/null +++ b/data/registers/dbgmcu_h7.yaml @@ -0,0 +1,191 @@ +--- +block/DBGMCU: + description: Debug support + items: + - name: IDC + description: Identity code + byte_offset: 0 + access: Read + fieldset: IDC + - name: CR + description: Configuration register + byte_offset: 4 + fieldset: CR + - name: APB3FZ1 + description: APB3 peripheral freeze register + byte_offset: 52 + fieldset: APB3FZ1 + - name: APB1LFZ1 + description: APB1L peripheral freeze register + byte_offset: 60 + fieldset: APB1LFZ1 + - name: APB2FZ1 + description: APB2 peripheral freeze register + byte_offset: 76 + fieldset: APB2FZ1 + - name: APB4FZ1 + description: APB4 peripheral freeze register + byte_offset: 84 + fieldset: APB4FZ1 +fieldset/APB1LFZ1: + description: APB1L peripheral freeze register + fields: + - name: TIM2 + description: TIM2 stop in debug mode + bit_offset: 0 + bit_size: 1 + - name: TIM3 + description: TIM3 stop in debug mode + bit_offset: 1 + bit_size: 1 + - name: TIM4 + description: TIM4 stop in debug mode + bit_offset: 2 + bit_size: 1 + - name: TIM5 + description: TIM5 stop in debug mode + bit_offset: 3 + bit_size: 1 + - name: TIM6 + description: TIM6 stop in debug mode + bit_offset: 4 + bit_size: 1 + - name: TIM7 + description: TIM7 stop in debug mode + bit_offset: 5 + bit_size: 1 + - name: TIM12 + description: TIM12 stop in debug mode + bit_offset: 6 + bit_size: 1 + - name: TIM13 + description: TIM13 stop in debug mode + bit_offset: 7 + bit_size: 1 + - name: TIM14 + description: TIM14 stop in debug mode + bit_offset: 8 + bit_size: 1 + - name: LPTIM1 + description: LPTIM1 stop in debug mode + bit_offset: 9 + bit_size: 1 + - name: I2C1 + description: I2C1 SMBUS timeout stop in debug mode + bit_offset: 21 + bit_size: 1 + - name: I2C2 + description: I2C2 SMBUS timeout stop in debug mode + bit_offset: 22 + bit_size: 1 + - name: I2C3 + description: I2C3 SMBUS timeout stop in debug mode + bit_offset: 23 + bit_size: 1 +fieldset/APB2FZ1: + description: APB2 peripheral freeze register + fields: + - name: TIM1 + description: TIM1 stop in debug mode + bit_offset: 0 + bit_size: 1 + - name: TIM8 + description: TIM8 stop in debug mode + bit_offset: 1 + bit_size: 1 + - name: TIM15 + description: TIM15 stop in debug mode + bit_offset: 16 + bit_size: 1 + - name: TIM16 + description: TIM16 stop in debug mode + bit_offset: 17 + bit_size: 1 + - name: TIM17 + description: TIM17 stop in debug mode + bit_offset: 18 + bit_size: 1 + - name: HRTIM + description: HRTIM stop in debug mode + bit_offset: 29 + bit_size: 1 +fieldset/APB3FZ1: + description: APB3 peripheral freeze register + fields: + - name: WWDG1 + description: WWDG1 stop in debug mode + bit_offset: 6 + bit_size: 1 +fieldset/APB4FZ1: + description: APB4 peripheral freeze register + fields: + - name: I2C4 + description: I2C4 SMBUS timeout stop in debug mode + bit_offset: 7 + bit_size: 1 + - name: LPTIM2 + description: LPTIM2 stop in debug mode + bit_offset: 9 + bit_size: 1 + - name: LPTIM3 + description: LPTIM3 stop in debug mode + bit_offset: 10 + bit_size: 1 + - name: LPTIM4 + description: LPTIM4 stop in debug mode + bit_offset: 11 + bit_size: 1 + - name: LPTIM5 + description: LPTIM5 stop in debug mode + bit_offset: 12 + bit_size: 1 + - name: RTC + description: RTC stop in debug mode + bit_offset: 16 + bit_size: 1 + - name: IWDG1 + description: Independent watchdog for D1 stop in debug mode + bit_offset: 18 + bit_size: 1 +fieldset/CR: + description: Configuration register + fields: + - name: DBGSLEEP_D1 + description: Allow debug in D1 Sleep mode + bit_offset: 0 + bit_size: 1 + - name: DBGSTOP_D1 + description: Allow debug in D1 Stop mode + bit_offset: 1 + bit_size: 1 + - name: DBGSTBY_D1 + description: Allow debug in D1 Standby mode + bit_offset: 2 + bit_size: 1 + - name: TRACECLKEN + description: Trace clock enable enable + bit_offset: 20 + bit_size: 1 + - name: D1DBGCKEN + description: D1 debug clock enable enable + bit_offset: 21 + bit_size: 1 + - name: D3DBGCKEN + description: D3 debug clock enable enable + bit_offset: 22 + bit_size: 1 + - name: TRGOEN + description: External trigger output enable + bit_offset: 28 + bit_size: 1 +fieldset/IDC: + description: Identity code + fields: + - name: DEV_ID + description: Device ID + bit_offset: 0 + bit_size: 12 + - name: REV_ID + description: Revision ID + bit_offset: 16 + bit_size: 16 diff --git a/parse.py b/parse.py index b9f43a0..b2e3cc7 100644 --- a/parse.py +++ b/parse.py @@ -243,6 +243,7 @@ perimap = [ ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'), ('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'), ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), + ('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'), ] @@ -434,6 +435,17 @@ def parse_chips(): flash_peri['block'] = block peris['FLASH'] = flash_peri + # DBGMCU is not in the cubedb XMLs + if addr := h['defines'].get('DBGMCU_BASE'): + kind = 'DBGMCU:' + chip_name[:7] + '_dbgmcu_v1_0' + dbg_peri = OrderedDict({ + 'address': addr, + 'kind': kind, + }) + if block := match_peri(kind): + dbg_peri['block'] = block + peris['DBGMCU'] = dbg_peri + chip['peripherals'] = peris with open('data/chips/'+chip_name+'.yaml', 'w') as f: