From 846847b9d574e065c7fee163a040910bf73111bd Mon Sep 17 00:00:00 2001
From: Jensenn <neilgithub@jensenet.com>
Date: Tue, 10 May 2022 13:53:11 -0600
Subject: [PATCH] Split LCD peripheral into v1, v2

---
 data/registers/lcd_v1.yaml |   4 -
 data/registers/lcd_v2.yaml | 145 +++++++++++++++++++++++++++++++++++++
 stm32data/__main__.py      |   4 +-
 3 files changed, 148 insertions(+), 5 deletions(-)
 create mode 100644 data/registers/lcd_v2.yaml

diff --git a/data/registers/lcd_v1.yaml b/data/registers/lcd_v1.yaml
index 365993e..63a9f81 100644
--- a/data/registers/lcd_v1.yaml
+++ b/data/registers/lcd_v1.yaml
@@ -60,10 +60,6 @@ fieldset/CR:
       description: Mux segment enable
       bit_offset: 7
       bit_size: 1
-    - name: BUFEN
-      description: Voltage output buffer enable
-      bit_offset: 8
-      bit_size: 1
 fieldset/FCR:
   description: frame control register
   fields:
diff --git a/data/registers/lcd_v2.yaml b/data/registers/lcd_v2.yaml
new file mode 100644
index 0000000..365993e
--- /dev/null
+++ b/data/registers/lcd_v2.yaml
@@ -0,0 +1,145 @@
+---
+block/LCD:
+  description: Liquid crystal display controller
+  items:
+    - name: CR
+      description: control register
+      byte_offset: 0
+      fieldset: CR
+    - name: FCR
+      description: frame control register
+      byte_offset: 4
+      fieldset: FCR
+    - name: SR
+      description: status register
+      byte_offset: 8
+      fieldset: SR
+    - name: CLR
+      description: clear register
+      byte_offset: 12
+      access: Write
+      fieldset: CLR
+    - name: RAM_COM
+      description: display memory
+      array:
+        len: 8
+        stride: 8
+      byte_offset: 20
+      block: RAM_COM
+fieldset/CLR:
+  description: clear register
+  fields:
+    - name: SOFC
+      description: Start of frame flag clear
+      bit_offset: 1
+      bit_size: 1
+    - name: UDDC
+      description: Update display done clear
+      bit_offset: 3
+      bit_size: 1
+fieldset/CR:
+  description: control register
+  fields:
+    - name: LCDEN
+      description: LCD controller enable
+      bit_offset: 0
+      bit_size: 1
+    - name: VSEL
+      description: Voltage source selection
+      bit_offset: 1
+      bit_size: 1
+    - name: DUTY
+      description: Duty selection
+      bit_offset: 2
+      bit_size: 3
+    - name: BIAS
+      description: Bias selector
+      bit_offset: 5
+      bit_size: 2
+    - name: MUX_SEG
+      description: Mux segment enable
+      bit_offset: 7
+      bit_size: 1
+    - name: BUFEN
+      description: Voltage output buffer enable
+      bit_offset: 8
+      bit_size: 1
+fieldset/FCR:
+  description: frame control register
+  fields:
+    - name: HD
+      description: High drive enable
+      bit_offset: 0
+      bit_size: 1
+    - name: SOFIE
+      description: Start of frame interrupt enable
+      bit_offset: 1
+      bit_size: 1
+    - name: UDDIE
+      description: Update display done interrupt enable
+      bit_offset: 3
+      bit_size: 1
+    - name: PON
+      description: Pulse ON duration
+      bit_offset: 4
+      bit_size: 3
+    - name: DEAD
+      description: Dead time duration
+      bit_offset: 7
+      bit_size: 3
+    - name: CC
+      description: Contrast control
+      bit_offset: 10
+      bit_size: 3
+    - name: BLINKF
+      description: Blink frequency selection
+      bit_offset: 13
+      bit_size: 3
+    - name: BLINK
+      description: Blink mode selection
+      bit_offset: 16
+      bit_size: 2
+    - name: DIV
+      description: DIV clock divider
+      bit_offset: 18
+      bit_size: 4
+    - name: PS
+      description: PS 16-bit prescaler
+      bit_offset: 22
+      bit_size: 4
+fieldset/SR:
+  description: status register
+  fields:
+    - name: ENS
+      description: LCD enabled status
+      bit_offset: 0
+      bit_size: 1
+    - name: SOF
+      description: Start of frame flag
+      bit_offset: 1
+      bit_size: 1
+    - name: UDR
+      description: Update display request
+      bit_offset: 2
+      bit_size: 1
+    - name: UDD
+      description: Update Display Done
+      bit_offset: 3
+      bit_size: 1
+    - name: RDY
+      description: Ready flag
+      bit_offset: 4
+      bit_size: 1
+    - name: FCRSF
+      description: LCD Frame Control Register Synchronization flag
+      bit_offset: 5
+      bit_size: 1
+block/RAM_COM:
+  description: "display memory"
+  items:
+    - name: LOW
+      description: display memory low word
+      byte_offset: 0
+    - name: HIGH
+      description: display memory high word
+      byte_offset: 4
diff --git a/stm32data/__main__.py b/stm32data/__main__.py
index edd47fe..3badcb7 100755
--- a/stm32data/__main__.py
+++ b/stm32data/__main__.py
@@ -298,7 +298,9 @@ perimap = [
     ('.*:CRC:integtest1_v2_0', ('crc', 'v2', 'CRC')),
     ('.*:CRC:integtest1_v2_2', ('crc', 'v3', 'CRC')),
 
-    ('.*:LCD:lcdc1_v1.*', ('lcd', 'v1', 'LCD')),
+    ('.*:LCD:lcdc1_v1.0.*', ('lcd', 'v1', 'LCD')),
+    ('.*:LCD:lcdc1_v1.2.*', ('lcd', 'v2', 'LCD')),
+    ('.*:LCD:lcdc1_v1.3.*', ('lcd', 'v2', 'LCD')),
 ]
 
 peri_rename = {