diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml
index 154bef6..28db16d 100644
--- a/data/registers/timer_v1.yaml
+++ b/data/registers/timer_v1.yaml
@@ -1,11 +1,262 @@
+block/TIM_1CH:
+  description: 1-channel timers
+  items:
+  - name: CR1
+    description: control register 1
+    byte_offset: 0
+    fieldset: CR1_1CH
+  - name: DIER
+    description: DMA/Interrupt enable register
+    byte_offset: 12
+    fieldset: DIER_1CH
+  - name: SR
+    description: status register
+    byte_offset: 16
+    fieldset: SR_1CH
+  - name: EGR
+    description: event generation register
+    byte_offset: 20
+    access: Write
+    fieldset: EGR_1CH
+  - name: CCMR_Input
+    description: capture/compare mode register 1 (input mode)
+    array:
+      len: 1
+      stride: 4
+    byte_offset: 24
+    fieldset: CCMR_Input_1CH
+  - name: CCMR_Output
+    description: capture/compare mode register 1 (output mode)
+    array:
+      len: 1
+      stride: 4
+    byte_offset: 24
+    fieldset: CCMR_Output_1CH
+  - name: CCER
+    description: capture/compare enable register
+    byte_offset: 32
+    fieldset: CCER_1CH
+  - name: CNT
+    description: counter
+    byte_offset: 36
+    fieldset: CNT_BASIC
+  - name: PSC
+    description: prescaler
+    byte_offset: 40
+    fieldset: PSC_BASIC
+  - name: ARR
+    description: auto-reload register (Dither mode disabled)
+    byte_offset: 44
+    fieldset: ARR_BASIC
+  - name: ARR_DITHER
+    description: auto-reload register (Dither mode enabled)
+    byte_offset: 44
+    fieldset: ARR_DITHER_BASIC
+  - name: CCR
+    description: capture/compare register x (x=1) (Dither mode disabled)
+    array:
+      len: 1
+      stride: 4
+    byte_offset: 52
+    fieldset: CCR_GP16
+  - name: CCR_DITHER
+    description: capture/compare register x (x=1) (Dither mode enabled)
+    array:
+      len: 1
+      stride: 4
+    byte_offset: 52
+    fieldset: CCR_DITHER_GP16
+  - name: TISEL
+    description: input selection register
+    byte_offset: 92
+    fieldset: TISEL_1CH
+block/TIM_1CH_CMP:
+  extends: TIM_1CH
+  description: 1-channel with one complementary output timers
+  items:
+  - name: CR2
+    description: control register 2
+    byte_offset: 4
+    fieldset: CR2_1CH_CMP
+  - name: DIER
+    description: DMA/Interrupt enable register
+    byte_offset: 12
+    fieldset: DIER_1CH_CMP
+  - name: SR
+    description: status register
+    byte_offset: 16
+    fieldset: SR_1CH_CMP
+  - name: EGR
+    description: event generation register
+    byte_offset: 20
+    access: Write
+    fieldset: EGR_1CH_CMP
+  - name: CCER
+    description: capture/compare enable register
+    byte_offset: 32
+    fieldset: CCER_1CH_CMP
+  - name: RCR
+    description: repetition counter register
+    byte_offset: 48
+    fieldset: RCR_1CH_CMP
+  - name: BDTR
+    description: break and dead-time register
+    byte_offset: 68
+    fieldset: BDTR_1CH_CMP
+  - name: DTR2
+    description: break and dead-time register
+    byte_offset: 84
+    fieldset: DTR2_ADV
+  - name: AF1
+    description: alternate function register 1
+    byte_offset: 96
+    fieldset: AF1_1CH_CMP
+  - name: AF2
+    description: alternate function register 2
+    byte_offset: 100
+    fieldset: AF2_GP16
+  - name: DCR
+    description: DMA control register
+    byte_offset: 988
+    fieldset: DCR_GP16
+  - name: DMAR
+    description: DMA address for full transfer
+    byte_offset: 992
+    fieldset: DMAR_GP16
+block/TIM_2CH:
+  extends: TIM_1CH
+  description: 2-channel timers
+  items:
+  - name: CR2
+    description: control register 2
+    byte_offset: 4
+    fieldset: CR2_2CH
+  - name: SMCR
+    description: slave mode control register
+    byte_offset: 8
+    fieldset: SMCR_2CH
+  - name: DIER
+    description: DMA/Interrupt enable register
+    byte_offset: 12
+    fieldset: DIER_2CH
+  - name: SR
+    description: status register
+    byte_offset: 16
+    fieldset: SR_2CH
+  - name: EGR
+    description: event generation register
+    byte_offset: 20
+    access: Write
+    fieldset: EGR_2CH
+  - name: CCMR_Input
+    description: capture/compare mode register 1 (input mode)
+    array:
+      len: 1
+      stride: 4
+    byte_offset: 24
+    fieldset: CCMR_Input_2CH
+  - name: CCMR_Output
+    description: capture/compare mode register 1 (output mode)
+    array:
+      len: 1
+      stride: 4
+    byte_offset: 24
+    fieldset: CCMR_Output_2CH
+  - name: CCER
+    description: capture/compare enable register
+    byte_offset: 32
+    fieldset: CCER_2CH
+  - name: CCR
+    description: capture/compare register x (x=1-2) (Dither mode disabled)
+    array:
+      len: 2
+      stride: 4
+    byte_offset: 52
+    fieldset: CCR_GP16
+  - name: CCR_DITHER
+    description: capture/compare register x (x=1-2) (Dither mode enabled)
+    array:
+      len: 2
+      stride: 4
+    byte_offset: 52
+    fieldset: CCR_DITHER_GP16
+  - name: TISEL
+    description: input selection register
+    byte_offset: 92
+    fieldset: TISEL_2CH
+block/TIM_2CH_CMP:
+  extends: TIM_2CH
+  description: 2-channel with one complementary output timers
+  items:
+  - name: CR2
+    description: control register 2
+    byte_offset: 4
+    fieldset: CR2_2CH_CMP
+  - name: SMCR
+    description: slave mode control register
+    byte_offset: 8
+    fieldset: SMCR_2CH_CMP
+  - name: DIER
+    description: DMA/Interrupt enable register
+    byte_offset: 12
+    fieldset: DIER_2CH_CMP
+  - name: SR
+    description: status register
+    byte_offset: 16
+    fieldset: SR_1CH_CMP
+  - name: EGR
+    description: event generation register
+    byte_offset: 20
+    access: Write
+    fieldset: EGR_1CH_CMP
+  - name: CCER
+    description: capture/compare enable register
+    byte_offset: 32
+    fieldset: CCER_2CH_CMP
+  - name: RCR
+    description: repetition counter register
+    byte_offset: 48
+    fieldset: RCR_1CH_CMP
+  - name: BDTR
+    description: break and dead-time register
+    byte_offset: 68
+    fieldset: BDTR_1CH_CMP
+  - name: DTR2
+    description: break and dead-time register
+    byte_offset: 84
+    fieldset: DTR2_ADV
+  - name: TISEL
+    description: input selection register
+    byte_offset: 92
+    fieldset: TISEL_2CH
+  - name: AF1
+    description: alternate function register 1
+    byte_offset: 96
+    fieldset: AF1_1CH_CMP
+  - name: AF2
+    description: alternate function register 2
+    byte_offset: 100
+    fieldset: AF2_GP16
+  - name: DCR
+    description: DMA control register
+    byte_offset: 988
+    fieldset: DCR_GP16
+  - name: DMAR
+    description: DMA address for full transfer
+    byte_offset: 992
+    fieldset: DMAR_GP16
 block/TIM_ADV:
   extends: TIM_GP16
-  description: Advanced-timers
+  description: Advanced Control timers
   items:
   - name: CR2
     description: control register 2
     byte_offset: 4
     fieldset: CR2_ADV
+  - name: SMCR
+    description: slave mode control register
+    byte_offset: 8
+    fieldset: SMCR_ADV
   - name: DIER
     description: DMA/Interrupt enable register
     byte_offset: 12
@@ -26,13 +277,45 @@ block/TIM_ADV:
   - name: RCR
     description: repetition counter register
     byte_offset: 48
-    fieldset: RCR
+    fieldset: RCR_ADV
   - name: BDTR
     description: break and dead-time register
     byte_offset: 68
-    fieldset: BDTR
+    fieldset: BDTR_ADV
+  - name: CCR5
+    description: capture/compare register 5 (Dither mode disabled)
+    byte_offset: 72
+    fieldset: CCR5_ADV
+  - name: CCR5_DITHER
+    description: capture/compare register 5 (Dither mode enabled)
+    byte_offset: 72
+    fieldset: CCR5_DITHER_ADV
+  - name: CCR6
+    description: capture/compare register 6 (Dither mode disabled)
+    byte_offset: 76
+    fieldset: CCR_GP16
+  - name: CCR6_DITHER
+    description: capture/compare register 6 (Dither mode enabled)
+    byte_offset: 76
+    fieldset: CCR_DITHER_GP16
+  - name: CCMR3
+    description: capture/compare mode register 3
+    byte_offset: 80
+    fieldset: CCMR3_ADV
+  - name: DTR2
+    description: break and dead-time register
+    byte_offset: 84
+    fieldset: DTR2_ADV
+  - name: AF1
+    description: alternate function register 1
+    byte_offset: 96
+    fieldset: AF1_ADV
+  - name: AF2
+    description: alternate function register 2
+    byte_offset: 100
+    fieldset: AF2_ADV
 block/TIM_BASIC:
-  description: Basic timer
+  description: Basic timers
   items:
   - name: CR1
     description: control register 1
@@ -58,115 +341,272 @@ block/TIM_BASIC:
   - name: CNT
     description: counter
     byte_offset: 36
-    fieldset: CNT_16
+    fieldset: CNT_BASIC
   - name: PSC
     description: prescaler
     byte_offset: 40
-    fieldset: PSC
+    fieldset: PSC_BASIC
   - name: ARR
-    description: auto-reload register
+    description: auto-reload register (Dither mode disabled)
     byte_offset: 44
-    fieldset: ARR_16
+    fieldset: ARR_BASIC
+  - name: ARR_DITHER
+    description: auto-reload register (Dither mode enabled)
+    byte_offset: 44
+    fieldset: ARR_DITHER_BASIC
 block/TIM_GP16:
   extends: TIM_BASIC
-  description: General purpose 16-bit timer
+  description: General purpose 16-bit timers
   items:
   - name: CR1
     description: control register 1
     byte_offset: 0
-    fieldset: CR1_GP
+    fieldset: CR1_GP16
   - name: CR2
     description: control register 2
     byte_offset: 4
-    fieldset: CR2_GP
+    fieldset: CR2_GP16
   - name: SMCR
     description: slave mode control register
     byte_offset: 8
-    fieldset: SMCR
+    fieldset: SMCR_GP16
   - name: DIER
     description: DMA/Interrupt enable register
     byte_offset: 12
-    fieldset: DIER_GP
+    fieldset: DIER_GP16
   - name: SR
     description: status register
     byte_offset: 16
-    fieldset: SR_GP
+    fieldset: SR_GP16
   - name: EGR
     description: event generation register
     byte_offset: 20
     access: Write
-    fieldset: EGR_GP
+    fieldset: EGR_GP16
   - name: CCMR_Input
-    description: capture/compare mode register 1 (input mode)
+    description: capture/compare mode register 1-2 (input mode)
     array:
       len: 2
       stride: 4
     byte_offset: 24
-    fieldset: CCMR_Input
+    fieldset: CCMR_Input_GP16
   - name: CCMR_Output
-    description: capture/compare mode register 1 (output mode)
+    description: capture/compare mode register 1-2 (output mode)
     array:
       len: 2
       stride: 4
     byte_offset: 24
-    fieldset: CCMR_Output
+    fieldset: CCMR_Output_GP16
   - name: CCER
     description: capture/compare enable register
     byte_offset: 32
-    fieldset: CCER_GP
-  - name: PSC
-    description: prescaler
-    byte_offset: 40
-    fieldset: PSC
+    fieldset: CCER_GP16
   - name: CCR
-    description: capture/compare register
+    description: capture/compare register x (x=1-4) (Dither mode disabled)
     array:
       len: 4
       stride: 4
     byte_offset: 52
-    fieldset: CCR_16
+    fieldset: CCR_GP16
+  - name: CCR_DITHER
+    description: capture/compare register x (x=1-4) (Dither mode enabled)
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 52
+    fieldset: CCR_DITHER_GP16
+  - name: ECR
+    description: encoder control register
+    byte_offset: 88
+    fieldset: ECR_GP16
+  - name: TISEL
+    description: input selection register
+    byte_offset: 92
+    fieldset: TISEL_GP16
+  - name: AF1
+    description: alternate function register 1
+    byte_offset: 96
+    fieldset: AF1_GP16
+  - name: AF2
+    description: alternate function register 2
+    byte_offset: 100
+    fieldset: AF2_GP16
   - name: DCR
     description: DMA control register
-    byte_offset: 72
-    fieldset: DCR
+    byte_offset: 988
+    fieldset: DCR_GP16
   - name: DMAR
     description: DMA address for full transfer
-    byte_offset: 76
-    fieldset: DMAR
+    byte_offset: 992
+    fieldset: DMAR_GP16
 block/TIM_GP32:
   extends: TIM_GP16
-  description: General purpose 32-bit timer
+  description: General purpose 32-bit timers
   items:
   - name: CNT
-    description: counter
+    description: counter (Dither mode disabled)
     byte_offset: 36
-    fieldset: CNT_32
+    fieldset: CNT_GP32
+  - name: CNT_DITHER
+    description: counter (Dither mode enbled)
+    byte_offset: 36
+    fieldset: CNT_DITHER_GP32
   - name: ARR
-    description: auto-reload register
+    description: auto-reload register (Dither mode disabled)
     byte_offset: 44
-    fieldset: ARR_32
+    fieldset: ARR_GP32
+  - name: ARR_DITHER
+    description: auto-reload register (Dither mode enabled)
+    byte_offset: 44
+    fieldset: ARR_DITHER_GP32
   - name: CCR
-    description: capture/compare register
+    description: capture/compare register x (x=1-4) (Dither mode disabled)
     array:
       len: 4
       stride: 4
     byte_offset: 52
-    fieldset: CCR_32
-fieldset/ARR_16:
-  description: auto-reload register
+    fieldset: CCR_GP32
+  - name: CCR_DITHER
+    description: capture/compare register x (x=1-4) (Dither mode enabled)
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 52
+    fieldset: CCR_DITHER_GP32
+fieldset/AF1_1CH_CMP:
+  description: alternate function register 1
+  fields:
+  - name: BKINE
+    description: TIMx_BKIN input enable
+    bit_offset: 0
+    bit_size: 1
+  - name: BKCMPE
+    description: TIM_BRK_CMPx (x=1-8) enable
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+  - name: BKINP
+    description: TIMx_BKIN input polarity
+    bit_offset: 9
+    bit_size: 1
+    enum: BKINP
+  - name: BKCMPP
+    description: TIM_BRK_CMPx (x=1-4) input polarity
+    bit_offset: 10
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+    enum: BKINP
+fieldset/AF1_ADV:
+  extends: AF1_GP16
+  description: alternate function register 1
+  fields:
+  - name: BKINE
+    description: TIMx_BKIN input enable
+    bit_offset: 0
+    bit_size: 1
+  - name: BKCMPE
+    description: TIM_BRK_CMPx (x=1-8) enable
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+  - name: BKINP
+    description: TIMx_BKIN input polarity
+    bit_offset: 9
+    bit_size: 1
+    enum: BKINP
+  - name: BKCMPP
+    description: TIM_BRK_CMPx (x=1-4) input polarity
+    bit_offset: 10
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+    enum: BKINP
+fieldset/AF1_GP16:
+  description: alternate function register 1
+  fields:
+  - name: ETRSEL
+    description: etr_in source selection
+    bit_offset: 14
+    bit_size: 4
+fieldset/AF2_ADV:
+  extends: AF2_GP16
+  description: alternate function register 2
+  fields:
+  - name: BK2INE
+    description: TIMx_BKIN2 input enable
+    bit_offset: 0
+    bit_size: 1
+  - name: BK2CMPE
+    description: TIM_BRK2_CMPx (x=1-8) enable
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 1
+      stride: 8
+  - name: BK2INP
+    description: TIMx_BK2IN input polarity
+    bit_offset: 9
+    bit_size: 1
+    enum: BKINP
+  - name: BK2CMPP
+    description: TIM_BRK2_CMPx (x=1-4) input polarity
+    bit_offset: 10
+    bit_size: 1
+    array:
+      len: 1
+      stride: 4
+    enum: BKINP
+fieldset/AF2_GP16:
+  description: alternate function register 2
+  fields:
+  - name: OCRSEL
+    description: ocref_clr source selection
+    bit_offset: 16
+    bit_size: 3
+fieldset/ARR_BASIC:
+  description: auto-reload register (Dither mode disabled)
   fields:
   - name: ARR
     description: Auto-reload value
     bit_offset: 0
     bit_size: 16
-fieldset/ARR_32:
-  description: auto-reload register
+fieldset/ARR_DITHER_BASIC:
+  description: auto-reload register (Dither mode enabled)
+  fields:
+  - name: DITHER
+    description: Dither value
+    bit_offset: 0
+    bit_size: 4
+  - name: ARR
+    description: Auto-reload value
+    bit_offset: 4
+    bit_size: 16
+fieldset/ARR_DITHER_GP32:
+  description: auto-reload register (Dither mode enabled)
+  fields:
+  - name: DITHER
+    description: Dither value
+    bit_offset: 0
+    bit_size: 4
+  - name: ARR
+    description: Auto-reload value
+    bit_offset: 4
+    bit_size: 28
+fieldset/ARR_GP32:
+  description: auto-reload register (Dither mode disabled)
   fields:
   - name: ARR
     description: Auto-reload value
     bit_offset: 0
     bit_size: 32
-fieldset/BDTR:
+fieldset/BDTR_1CH_CMP:
   description: break and dead-time register
   fields:
   - name: DTG
@@ -177,6 +617,7 @@ fieldset/BDTR:
     description: Lock configuration
     bit_offset: 8
     bit_size: 2
+    enum: LOCK
   - name: OSSI
     description: Off-state selection for Idle mode
     bit_offset: 10
@@ -188,13 +629,20 @@ fieldset/BDTR:
     bit_size: 1
     enum: OSSR
   - name: BKE
-    description: Break enable
+    description: Break x (x=1) enable
     bit_offset: 12
     bit_size: 1
+    array:
+      len: 1
+      stride: 12
   - name: BKP
-    description: Break polarity
+    description: Break x (x=1) polarity
     bit_offset: 13
     bit_size: 1
+    array:
+      len: 1
+      stride: 12
+    enum: BKP
   - name: AOE
     description: Automatic output enable
     bit_offset: 14
@@ -203,94 +651,238 @@ fieldset/BDTR:
     description: Main output enable
     bit_offset: 15
     bit_size: 1
-fieldset/CCER_ADV:
-  extends: CCER_GP
+  - name: BKF
+    description: Break x (x=1) filter
+    bit_offset: 16
+    bit_size: 4
+    array:
+      len: 1
+      stride: 4
+    enum: FilterValue
+  - name: BKDSRM
+    description: Break x (x=1) Disarm
+    bit_offset: 26
+    bit_size: 1
+    array:
+      len: 1
+      stride: 1
+    enum: BKDSRM
+  - name: BKBID
+    description: Break x (x=1) bidirectional
+    bit_offset: 28
+    bit_size: 1
+    array:
+      len: 1
+      stride: 1
+    enum: BKBID
+fieldset/BDTR_ADV:
+  description: break and dead-time register
+  fields:
+  - name: DTG
+    description: Dead-time generator setup
+    bit_offset: 0
+    bit_size: 8
+  - name: LOCK
+    description: Lock configuration
+    bit_offset: 8
+    bit_size: 2
+    enum: LOCK
+  - name: OSSI
+    description: Off-state selection for Idle mode
+    bit_offset: 10
+    bit_size: 1
+    enum: OSSI
+  - name: OSSR
+    description: Off-state selection for Run mode
+    bit_offset: 11
+    bit_size: 1
+    enum: OSSR
+  - name: BKE
+    description: Break x (x=1,2) enable
+    bit_offset: 12
+    bit_size: 1
+    array:
+      len: 2
+      stride: 12
+  - name: BKP
+    description: Break x (x=1,2) polarity
+    bit_offset: 13
+    bit_size: 1
+    array:
+      len: 2
+      stride: 12
+    enum: BKP
+  - name: AOE
+    description: Automatic output enable
+    bit_offset: 14
+    bit_size: 1
+  - name: MOE
+    description: Main output enable
+    bit_offset: 15
+    bit_size: 1
+  - name: BKF
+    description: Break x (x=1,2) filter
+    bit_offset: 16
+    bit_size: 4
+    array:
+      len: 2
+      stride: 4
+    enum: FilterValue
+  - name: BKDSRM
+    description: Break x (x=1,2) Disarm
+    bit_offset: 26
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+    enum: BKDSRM
+  - name: BKBID
+    description: Break x (x=1,2) bidirectional
+    bit_offset: 28
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+    enum: BKBID
+fieldset/CCER_1CH:
+  description: capture/compare enable register
+  fields:
+  - name: CCE
+    description: Capture/Compare x (x=1) output enable
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 1
+      stride: 4
+  - name: CCP
+    description: Capture/Compare x (x=1) output Polarity
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 1
+      stride: 4
+  - name: CCNP
+    description: Capture/Compare x (x=1) output Polarity
+    bit_offset: 3
+    bit_size: 1
+    array:
+      len: 1
+      stride: 4
+fieldset/CCER_1CH_CMP:
+  extends: CCER_1CH
   description: capture/compare enable register
   fields:
   - name: CCNE
-    description: Capture/Compare 1 complementary output enable
+    description: Capture/Compare x (x=1) complementary output enable
+    bit_offset: 2
+    bit_size: 1
+    array:
+      len: 1
+      stride: 4
+fieldset/CCER_2CH:
+  extends: CCER_1CH
+  description: capture/compare enable register
+  fields:
+  - name: CCE
+    description: Capture/Compare x (x=1-2) output enable
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 2
+      stride: 4
+  - name: CCP
+    description: Capture/Compare x (x=1-2) output Polarity
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 2
+      stride: 4
+  - name: CCNP
+    description: Capture/Compare x (x=1-2) output Polarity
+    bit_offset: 3
+    bit_size: 1
+    array:
+      len: 2
+      stride: 4
+fieldset/CCER_2CH_CMP:
+  extends: CCER_2CH
+  description: capture/compare enable register
+  fields:
+  - name: CCNE
+    description: Capture/Compare x (x=1) complementary output enable
+    bit_offset: 2
+    bit_size: 1
+    array:
+      len: 1
+      stride: 4
+fieldset/CCER_ADV:
+  extends: CCER_GP16
+  description: capture/compare enable register
+  fields:
+  - name: CCE
+    description: Capture/Compare x (x=1-6) output enable
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 6
+      stride: 4
+  - name: CCP
+    description: Capture/Compare x (x=1-6) output Polarity
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 6
+      stride: 4
+  - name: CCNE
+    description: Capture/Compare x (x=1-4) complementary output enable
     bit_offset: 2
     bit_size: 1
     array:
       len: 4
       stride: 4
-fieldset/CCER_GP:
+fieldset/CCER_GP16:
   description: capture/compare enable register
   fields:
   - name: CCE
-    description: Capture/Compare 1 output enable
+    description: Capture/Compare x (x=1-4) output enable
     bit_offset: 0
     bit_size: 1
     array:
       len: 4
       stride: 4
   - name: CCP
-    description: Capture/Compare 1 output Polarity
+    description: Capture/Compare x (x=1-4) output Polarity
     bit_offset: 1
     bit_size: 1
     array:
       len: 4
       stride: 4
   - name: CCNP
-    description: Capture/Compare 1 output Polarity
+    description: Capture/Compare x (x=1-4) output Polarity
     bit_offset: 3
     bit_size: 1
     array:
       len: 4
       stride: 4
-fieldset/CCMR_Input:
-  description: capture/compare mode register 1 (input mode)
+fieldset/CCMR3_ADV:
+  description: capture/compare mode register 3
   fields:
-  - name: CCS
-    description: Capture/Compare 1 selection
-    bit_offset: 0
-    bit_size: 2
-    array:
-      len: 2
-      stride: 8
-    enum: CCMR_Input_CCS
-  - name: ICPSC
-    description: Input capture 1 prescaler
-    bit_offset: 2
-    bit_size: 2
-    array:
-      len: 2
-      stride: 8
-  - name: ICF
-    description: Input capture 1 filter
-    bit_offset: 4
-    bit_size: 4
-    array:
-      len: 2
-      stride: 8
-    enum: ICF
-fieldset/CCMR_Output:
-  description: capture/compare mode register 2 (output mode)
-  fields:
-  - name: CCS
-    description: Capture/Compare 3 selection
-    bit_offset: 0
-    bit_size: 2
-    array:
-      len: 2
-      stride: 8
-    enum: CCMR_Output_CCS
   - name: OCFE
-    description: Output compare 3 fast enable
+    description: Output compare x (x=5,6) fast enable
     bit_offset: 2
     bit_size: 1
     array:
       len: 2
       stride: 8
   - name: OCPE
-    description: Output compare 3 preload enable
+    description: Output compare x (x=5,6) preload enable
     bit_offset: 3
     bit_size: 1
     array:
       len: 2
       stride: 8
   - name: OCM
-    description: Output compare 3 mode
+    description: Output compare x (x=5,6) mode
     bit_offset: 4
     bit_size: 3
     array:
@@ -298,40 +890,324 @@ fieldset/CCMR_Output:
       stride: 8
     enum: OCM
   - name: OCCE
-    description: Output compare 3 clear enable
+    description: Output compare x (x=5,6) clear enable
     bit_offset: 7
     bit_size: 1
     array:
       len: 2
       stride: 8
-fieldset/CCR_16:
-  description: capture/compare register 1
+fieldset/CCMR_Input_1CH:
+  description: capture/compare mode register x (x=1) (input mode)
+  fields:
+  - name: CCS
+    description: Capture/Compare y selection
+    bit_offset: 0
+    bit_size: 2
+    array:
+      len: 1
+      stride: 8
+    enum: CCMR_Input_CCS
+  - name: ICPSC
+    description: Input capture y prescaler
+    bit_offset: 2
+    bit_size: 2
+    array:
+      len: 1
+      stride: 8
+  - name: ICF
+    description: Input capture y filter
+    bit_offset: 4
+    bit_size: 4
+    array:
+      len: 1
+      stride: 8
+    enum: FilterValue
+fieldset/CCMR_Input_2CH:
+  extends: CCMR_Input_1CH
+  description: capture/compare mode register x (x=1) (input mode)
+  fields:
+  - name: CCS
+    description: Capture/Compare y selection
+    bit_offset: 0
+    bit_size: 2
+    array:
+      len: 2
+      stride: 8
+    enum: CCMR_Input_CCS
+  - name: ICPSC
+    description: Input capture y prescaler
+    bit_offset: 2
+    bit_size: 2
+    array:
+      len: 2
+      stride: 8
+  - name: ICF
+    description: Input capture y filter
+    bit_offset: 4
+    bit_size: 4
+    array:
+      len: 2
+      stride: 8
+    enum: FilterValue
+fieldset/CCMR_Input_GP16:
+  description: capture/compare mode register x (x=1-2) (input mode)
+  fields:
+  - name: CCS
+    description: Capture/Compare y selection
+    bit_offset: 0
+    bit_size: 2
+    array:
+      len: 2
+      stride: 8
+    enum: CCMR_Input_CCS
+  - name: ICPSC
+    description: Input capture y prescaler
+    bit_offset: 2
+    bit_size: 2
+    array:
+      len: 2
+      stride: 8
+  - name: ICF
+    description: Input capture y filter
+    bit_offset: 4
+    bit_size: 4
+    array:
+      len: 2
+      stride: 8
+    enum: FilterValue
+fieldset/CCMR_Output_1CH:
+  description: capture/compare mode register x (x=1) (output mode)
+  fields:
+  - name: CCS
+    description: Capture/Compare y selection
+    bit_offset: 0
+    bit_size: 2
+    array:
+      len: 1
+      stride: 8
+    enum: CCMR_Output_CCS
+  - name: OCFE
+    description: Output compare y fast enable
+    bit_offset: 2
+    bit_size: 1
+    array:
+      len: 1
+      stride: 8
+  - name: OCPE
+    description: Output compare y preload enable
+    bit_offset: 3
+    bit_size: 1
+    array:
+      len: 1
+      stride: 8
+  - name: OCM
+    description: Output compare y mode
+    bit_offset: 4
+    bit_size: 3
+    array:
+      len: 1
+      stride: 8
+    enum: OCM
+fieldset/CCMR_Output_2CH:
+  extends: CCMR_Output_1CH
+  description: capture/compare mode register x (x=1) (output mode)
+  fields:
+  - name: CCS
+    description: Capture/Compare y selection
+    bit_offset: 0
+    bit_size: 2
+    array:
+      len: 2
+      stride: 8
+    enum: CCMR_Output_CCS
+  - name: OCFE
+    description: Output compare y fast enable
+    bit_offset: 2
+    bit_size: 1
+    array:
+      len: 2
+      stride: 8
+  - name: OCPE
+    description: Output compare y preload enable
+    bit_offset: 3
+    bit_size: 1
+    array:
+      len: 2
+      stride: 8
+  - name: OCM
+    description: Output compare y mode
+    bit_offset: 4
+    bit_size: 3
+    array:
+      len: 2
+      stride: 8
+    enum: OCM
+fieldset/CCMR_Output_GP16:
+  description: capture/compare mode register x (x=1-3) (output mode)
+  fields:
+  - name: CCS
+    description: Capture/Compare y selection
+    bit_offset: 0
+    bit_size: 2
+    array:
+      len: 2
+      stride: 8
+    enum: CCMR_Output_CCS
+  - name: OCFE
+    description: Output compare y fast enable
+    bit_offset: 2
+    bit_size: 1
+    array:
+      len: 2
+      stride: 8
+  - name: OCPE
+    description: Output compare y preload enable
+    bit_offset: 3
+    bit_size: 1
+    array:
+      len: 2
+      stride: 8
+  - name: OCM
+    description: Output compare y mode
+    bit_offset: 4
+    bit_size: 3
+    array:
+      len: 2
+      stride: 8
+    enum: OCM
+  - name: OCCE
+    description: Output compare y clear enable
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 2
+      stride: 8
+fieldset/CCR5_ADV:
+  extends: CCR_GP16
+  description: capture/compare register 5 (Dither mode disabled)
+  fields:
+  - name: GC5C
+    description: Group channel 5 and channel x (x=1-3)
+    bit_offset: 29
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+    enum: GC5C
+fieldset/CCR5_DITHER_ADV:
+  extends: CCR_DITHER_GP16
+  description: capture/compare register 5 (Dither mode enabled)
+  fields:
+  - name: GC5C
+    description: Group channel 5 and channel x (x=1-3)
+    bit_offset: 29
+    bit_size: 1
+    array:
+      len: 3
+      stride: 1
+    enum: GC5C
+fieldset/CCR_DITHER_GP16:
+  description: capture/compare register x (x=1-4,6) (Dither mode enabled)
+  fields:
+  - name: DITHER
+    description: capture/compare x (x=1-4,6) value
+    bit_offset: 0
+    bit_size: 4
+  - name: CCR
+    description: capture/compare x (x=1-4,6) value
+    bit_offset: 4
+    bit_size: 16
+fieldset/CCR_DITHER_GP32:
+  description: capture/compare register x (x=1-4,6) (Dither mode enabled)
+  fields:
+  - name: DITHER
+    description: Dither value
+    bit_offset: 0
+    bit_size: 4
+  - name: CCR
+    description: capture/compare x (x=1-4,6) value
+    bit_offset: 4
+    bit_size: 28
+fieldset/CCR_GP16:
+  description: capture/compare register x (x=1-4,6) (Dither mode disabled)
   fields:
   - name: CCR
-    description: Capture/Compare 1 value
+    description: capture/compare x (x=1-4,6) value
     bit_offset: 0
     bit_size: 16
-fieldset/CCR_32:
-  description: capture/compare register 1
+fieldset/CCR_GP32:
+  description: capture/compare register x (x=1-4,6) (Dither mode disabled)
   fields:
   - name: CCR
-    description: Capture/Compare 1 value
+    description: capture/compare x (x=1-4,6) value
     bit_offset: 0
     bit_size: 32
-fieldset/CNT_16:
+fieldset/CNT_BASIC:
   description: counter
   fields:
   - name: CNT
     description: counter value
     bit_offset: 0
     bit_size: 16
-fieldset/CNT_32:
-  description: counter
+  - name: UIFCPY
+    description: UIF copy
+    bit_offset: 31
+    bit_size: 1
+fieldset/CNT_DITHER_GP32:
+  description: counter (Dither mode enabled)
+  fields:
+  - name: CNT
+    description: counter value
+    bit_offset: 0
+    bit_size: 31
+  - name: UIFCPY
+    description: UIF copy
+    bit_offset: 31
+    bit_size: 1
+fieldset/CNT_GP32:
+  description: counter (Dither mode disabled)
   fields:
   - name: CNT
     description: counter value
     bit_offset: 0
     bit_size: 32
+fieldset/CR1_1CH:
+  description: control register 1
+  fields:
+  - name: CEN
+    description: Counter enable
+    bit_offset: 0
+    bit_size: 1
+  - name: UDIS
+    description: Update disable
+    bit_offset: 1
+    bit_size: 1
+  - name: URS
+    description: Update request source
+    bit_offset: 2
+    bit_size: 1
+    enum: URS
+  - name: OPM
+    description: One-pulse mode enbaled
+    bit_offset: 3
+    bit_size: 1
+  - name: ARPE
+    description: Auto-reload preload enable
+    bit_offset: 7
+    bit_size: 1
+  - name: CKD
+    description: Clock division
+    bit_offset: 8
+    bit_size: 2
+    enum: CKD
+  - name: UIFREMAP
+    description: UIF status bit remapping enable
+    bit_offset: 11
+    bit_size: 1
+  - name: DITHEN
+    description: Dithering enable
+    bit_offset: 12
+    bit_size: 1
 fieldset/CR1_BASIC:
   description: control register 1
   fields:
@@ -356,7 +1232,15 @@ fieldset/CR1_BASIC:
     description: Auto-reload preload enable
     bit_offset: 7
     bit_size: 1
-fieldset/CR1_GP:
+  - name: UIFREMAP
+    description: UIF status bit remapping enable
+    bit_offset: 11
+    bit_size: 1
+  - name: DITHEN
+    description: Dithering enable
+    bit_offset: 12
+    bit_size: 1
+fieldset/CR1_GP16:
   extends: CR1_BASIC
   description: control register 1
   fields:
@@ -375,8 +1259,82 @@ fieldset/CR1_GP:
     bit_offset: 8
     bit_size: 2
     enum: CKD
+fieldset/CR2_1CH_CMP:
+  description: control register 2
+  fields:
+  - name: CCPC
+    description: Capture/compare preloaded control
+    bit_offset: 0
+    bit_size: 1
+  - name: CCUS
+    description: Capture/compare control update selection
+    bit_offset: 2
+    bit_size: 1
+  - name: CCDS
+    description: Capture/compare DMA selection
+    bit_offset: 3
+    bit_size: 1
+    enum: CCDS
+  - name: OIS
+    description: Output Idle state x (x=1)
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 1
+      stride: 2
+  - name: OISN
+    description: Output Idle state x (x=1)
+    bit_offset: 9
+    bit_size: 1
+    array:
+      len: 1
+      stride: 2
+fieldset/CR2_2CH:
+  description: control register 2
+  fields:
+  - name: MMS
+    description: Master mode selection
+    bit_offset: 4
+    bit_size: 3
+    enum: MMS
+  - name: TI1S
+    description: TI1 selection
+    bit_offset: 7
+    bit_size: 1
+    enum: TI1S
+fieldset/CR2_2CH_CMP:
+  extends: CR2_2CH
+  description: control register 2
+  fields:
+  - name: CCPC
+    description: Capture/compare preloaded control
+    bit_offset: 0
+    bit_size: 1
+  - name: CCUS
+    description: Capture/compare control update selection
+    bit_offset: 2
+    bit_size: 1
+  - name: CCDS
+    description: Capture/compare DMA selection
+    bit_offset: 3
+    bit_size: 1
+    enum: CCDS
+  - name: OIS
+    description: Output Idle state x (x=1,2)
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 2
+      stride: 2
+  - name: OISN
+    description: Output Idle state x (x=1)
+    bit_offset: 9
+    bit_size: 1
+    array:
+      len: 1
+      stride: 2
 fieldset/CR2_ADV:
-  extends: CR2_GP
+  extends: CR2_GP16
   description: control register 2
   fields:
   - name: CCPC
@@ -388,24 +1346,24 @@ fieldset/CR2_ADV:
     bit_offset: 2
     bit_size: 1
   - name: OIS
-    description: Output Idle state 1
+    description: Output Idle state x (x=1-6)
     bit_offset: 8
     bit_size: 1
+    array:
+      len: 6
+      stride: 2
+  - name: OISN
+    description: Output Idle state x N x (x=1-4)
+    bit_offset: 9
+    bit_size: 1
     array:
       len: 4
       stride: 2
-  - name: OIS1N
-    description: Output Idle state 1
-    bit_offset: 9
-    bit_size: 1
-  - name: OIS2N
-    description: Output Idle state 2
-    bit_offset: 11
-    bit_size: 1
-  - name: OIS3N
-    description: Output Idle state 3
-    bit_offset: 13
-    bit_size: 1
+  - name: MMS2
+    description: Master mode selection 2
+    bit_offset: 20
+    bit_size: 4
+    enum: MMS2
 fieldset/CR2_BASIC:
   description: control register 2
   fields:
@@ -414,7 +1372,7 @@ fieldset/CR2_BASIC:
     bit_offset: 4
     bit_size: 3
     enum: MMS
-fieldset/CR2_GP:
+fieldset/CR2_GP16:
   extends: CR2_BASIC
   description: control register 2
   fields:
@@ -427,8 +1385,8 @@ fieldset/CR2_GP:
     description: TI1 selection
     bit_offset: 7
     bit_size: 1
-    enum: TIS
-fieldset/DCR:
+    enum: TI1S
+fieldset/DCR_GP16:
   description: DMA control register
   fields:
   - name: DBA
@@ -439,8 +1397,77 @@ fieldset/DCR:
     description: DMA burst length
     bit_offset: 8
     bit_size: 5
+  - name: DBSS
+    description: DMA burst source selection
+    bit_offset: 16
+    bit_size: 4
+    enum: DBSS
+fieldset/DIER_1CH:
+  description: DMA/Interrupt enable register
+  fields:
+  - name: UIE
+    description: Update interrupt enable
+    bit_offset: 0
+    bit_size: 1
+  - name: CCIE
+    description: Capture/Compare x (x=1) interrupt enable
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 1
+      stride: 1
+fieldset/DIER_1CH_CMP:
+  extends: DIER_1CH
+  description: DMA/Interrupt enable register
+  fields:
+  - name: COMIE
+    description: COM interrupt enable
+    bit_offset: 5
+    bit_size: 1
+  - name: BIE
+    description: Break interrupt enable
+    bit_offset: 7
+    bit_size: 1
+  - name: UDE
+    description: Update DMA request enable
+    bit_offset: 8
+    bit_size: 1
+  - name: CCDE
+    description: Capture/Compare x (x=1) DMA request enable
+    bit_offset: 9
+    bit_size: 1
+    array:
+      len: 1
+      stride: 1
+fieldset/DIER_2CH:
+  extends: DIER_1CH
+  description: DMA/Interrupt enable register
+  fields:
+  - name: CCIE
+    description: Capture/Compare x (x=1-2) interrupt enable
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+  - name: TIE
+    description: Trigger interrupt enable
+    bit_offset: 6
+    bit_size: 1
+fieldset/DIER_2CH_CMP:
+  extends: DIER_1CH_CMP
+  description: DMA/Interrupt enable register
+  fields:
+  - name: COMDE
+    description: COM DMA request enable
+    bit_offset: 13
+    bit_size: 1
+  - name: TDE
+    description: Trigger DMA request enable
+    bit_offset: 14
+    bit_size: 1
 fieldset/DIER_ADV:
-  extends: DIER_GP
+  extends: DIER_GP16
   description: DMA/Interrupt enable register
   fields:
   - name: COMIE
@@ -466,12 +1493,12 @@ fieldset/DIER_BASIC:
     description: Update DMA request enable
     bit_offset: 8
     bit_size: 1
-fieldset/DIER_GP:
+fieldset/DIER_GP16:
   extends: DIER_BASIC
   description: DMA/Interrupt enable register
   fields:
   - name: CCIE
-    description: Capture/Compare 1 interrupt enable
+    description: Capture/Compare x (x=1-4) interrupt enable
     bit_offset: 1
     bit_size: 1
     array:
@@ -481,8 +1508,12 @@ fieldset/DIER_GP:
     description: Trigger interrupt enable
     bit_offset: 6
     bit_size: 1
+  - name: BIE
+    description: Break interrupt enable
+    bit_offset: 7
+    bit_size: 1
   - name: CCDE
-    description: Capture/Compare 1 DMA request enable
+    description: Capture/Compare x (x=1-4) DMA request enable
     bit_offset: 9
     bit_size: 1
     array:
@@ -492,15 +1523,95 @@ fieldset/DIER_GP:
     description: Trigger DMA request enable
     bit_offset: 14
     bit_size: 1
-fieldset/DMAR:
+  - name: IDXIE
+    description: Index interrupt enable
+    bit_offset: 20
+    bit_size: 1
+  - name: DIRIE
+    description: Direction change interrupt enable
+    bit_offset: 21
+    bit_size: 1
+  - name: IERRIE
+    description: Index error interrupt enable
+    bit_offset: 22
+    bit_size: 1
+  - name: TERRIE
+    description: Transition error interrupt enable
+    bit_offset: 23
+    bit_size: 1
+fieldset/DMAR_GP16:
   description: DMA address for full transfer
   fields:
   - name: DMAB
     description: DMA register for burst accesses
     bit_offset: 0
-    bit_size: 16
-fieldset/EGR_ADV:
-  extends: EGR_GP
+    bit_size: 32
+fieldset/DTR2_ADV:
+  description: deadtime register 2
+  fields:
+  - name: DTGF
+    description: Dead-time falling edge generator setup
+    bit_offset: 0
+    bit_size: 8
+  - name: DTAE
+    description: Deadtime asymmetric enable
+    bit_offset: 16
+    bit_size: 1
+    enum: DTAE
+  - name: DTPE
+    description: Deadtime preload enable
+    bit_offset: 17
+    bit_size: 1
+fieldset/ECR_GP16:
+  description: encoder control register
+  fields:
+  - name: IE
+    description: Index enable
+    bit_offset: 0
+    bit_size: 1
+  - name: IDIR
+    description: Index direction
+    bit_offset: 1
+    bit_size: 2
+    enum: IDIR
+  - name: IBLK
+    description: Index blanking
+    bit_offset: 3
+    bit_size: 2
+    enum: IBLK
+  - name: FIDX
+    description: First index
+    bit_offset: 5
+    bit_size: 1
+    enum: FIDX
+  - name: IPOS
+    description: Index positioning
+    bit_offset: 6
+    bit_size: 2
+  - name: PW
+    description: Pulse width
+    bit_offset: 16
+    bit_size: 8
+  - name: PWPRSC
+    description: Pulse width prescaler
+    bit_offset: 24
+    bit_size: 2
+fieldset/EGR_1CH:
+  description: event generation register
+  fields:
+  - name: UG
+    description: Update generation
+    bit_offset: 0
+    bit_size: 1
+  - name: CCG
+    description: Capture/compare x (x=1) generation
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 1
+      stride: 1
+fieldset/EGR_1CH_CMP:
+  extends: EGR_1CH
   description: event generation register
   fields:
   - name: COMG
@@ -508,9 +1619,42 @@ fieldset/EGR_ADV:
     bit_offset: 5
     bit_size: 1
   - name: BG
-    description: Break generation
+    description: Break x (x=1) generation
     bit_offset: 7
     bit_size: 1
+    array:
+      len: 1
+      stride: 1
+fieldset/EGR_2CH:
+  extends: EGR_1CH
+  description: event generation register
+  fields:
+  - name: CCG
+    description: Capture/compare x (x=1-2) generation
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+  - name: TG
+    description: Trigger generation
+    bit_offset: 6
+    bit_size: 1
+fieldset/EGR_ADV:
+  extends: EGR_GP16
+  description: event generation register
+  fields:
+  - name: COMG
+    description: Capture/Compare control update generation
+    bit_offset: 5
+    bit_size: 1
+  - name: BG
+    description: Break x (x=1-2) generation
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
 fieldset/EGR_BASIC:
   description: event generation register
   fields:
@@ -518,44 +1662,78 @@ fieldset/EGR_BASIC:
     description: Update generation
     bit_offset: 0
     bit_size: 1
-fieldset/EGR_GP:
+fieldset/EGR_GP16:
   extends: EGR_BASIC
   description: event generation register
   fields:
   - name: CCG
-    description: Capture/compare 1 generation
+    description: Capture/compare x (x=1-4) generation
     bit_offset: 1
     bit_size: 1
     array:
       len: 4
       stride: 1
-  - name: COMG
-    description: Capture/Compare control update generation
-    bit_offset: 5
-    bit_size: 1
   - name: TG
     description: Trigger generation
     bit_offset: 6
     bit_size: 1
-  - name: BG
-    description: Break generation
-    bit_offset: 7
-    bit_size: 1
-fieldset/PSC:
+fieldset/PSC_BASIC:
   description: prescaler
   fields:
   - name: PSC
     description: Prescaler value
     bit_offset: 0
     bit_size: 16
-fieldset/RCR:
+fieldset/RCR_1CH_CMP:
   description: repetition counter register
   fields:
   - name: REP
     description: Repetition counter value
     bit_offset: 0
     bit_size: 8
-fieldset/SMCR:
+fieldset/RCR_ADV:
+  description: repetition counter register
+  fields:
+  - name: REP
+    description: Repetition counter value
+    bit_offset: 0
+    bit_size: 16
+fieldset/SMCR_2CH:
+  description: slave mode control register
+  fields:
+  - name: SMS
+    description: Slave mode selection
+    bit_offset: 0
+    bit_size: 3
+    enum: SMS
+  - name: TS
+    description: Trigger selection
+    bit_offset: 4
+    bit_size: 3
+    enum: TS
+  - name: MSM
+    description: Master/Slave mode
+    bit_offset: 7
+    bit_size: 1
+    enum: MSM
+fieldset/SMCR_2CH_CMP:
+  extends: SMCR_2CH
+  description: slave mode control register
+  fields:
+  - name: SMSPE
+    description: SMS preload enable
+    bit_offset: 24
+    bit_size: 1
+fieldset/SMCR_ADV:
+  extends: SMCR_GP16
+  description: slave mode control register
+  fields:
+  - name: OCCS
+    description: OCREF clear selection
+    bit_offset: 3
+    bit_size: 1
+    enum: OCCS
+fieldset/SMCR_GP16:
   description: slave mode control register
   fields:
   - name: SMS
@@ -577,7 +1755,7 @@ fieldset/SMCR:
     description: External trigger filter
     bit_offset: 8
     bit_size: 4
-    enum: ETF
+    enum: FilterValue
   - name: ETPS
     description: External trigger prescaler
     bit_offset: 12
@@ -592,8 +1770,38 @@ fieldset/SMCR:
     bit_offset: 15
     bit_size: 1
     enum: ETP
-fieldset/SR_ADV:
-  extends: SR_GP
+  - name: SMSPE
+    description: SMS preload enable
+    bit_offset: 24
+    bit_size: 1
+  - name: SMSPS
+    description: SMS preload source
+    bit_offset: 25
+    bit_size: 1
+    enum: SMSPS
+fieldset/SR_1CH:
+  description: status register
+  fields:
+  - name: UIF
+    description: Update interrupt flag
+    bit_offset: 0
+    bit_size: 1
+  - name: CCIF
+    description: Capture/compare x (x=1) interrupt flag
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 1
+      stride: 1
+  - name: CCOF
+    description: Capture/Compare x (x=1) overcapture flag
+    bit_offset: 9
+    bit_size: 1
+    array:
+      len: 1
+      stride: 1
+fieldset/SR_1CH_CMP:
+  extends: SR_1CH
   description: status register
   fields:
   - name: COMIF
@@ -601,9 +1809,57 @@ fieldset/SR_ADV:
     bit_offset: 5
     bit_size: 1
   - name: BIF
-    description: Break interrupt flag
+    description: Break x (x=1) interrupt flag
     bit_offset: 7
     bit_size: 1
+    array:
+      len: 1
+      stride: 1
+fieldset/SR_2CH:
+  extends: SR_1CH
+  description: status register
+  fields:
+  - name: CCIF
+    description: Capture/compare x (x=1-2) interrupt flag
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+  - name: TIF
+    description: Trigger interrupt flag
+    bit_offset: 6
+    bit_size: 1
+  - name: CCOF
+    description: Capture/Compare x (x=1-2) overcapture flag
+    bit_offset: 9
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+fieldset/SR_ADV:
+  extends: SR_GP16
+  description: status register
+  fields:
+  - name: COMIF
+    description: COM interrupt flag
+    bit_offset: 5
+    bit_size: 1
+  - name: BIF
+    description: Break x (x=1,2) interrupt flag
+    bit_offset: 7
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+  - name: CCIF5
+    description: Capture/compare 5 interrupt flag
+    bit_offset: 16
+    bit_size: 1
+  - name: CCIF6
+    description: Capture/compare 6 interrupt flag
+    bit_offset: 17
+    bit_size: 1
 fieldset/SR_BASIC:
   description: status register
   fields:
@@ -611,36 +1867,111 @@ fieldset/SR_BASIC:
     description: Update interrupt flag
     bit_offset: 0
     bit_size: 1
-fieldset/SR_GP:
+fieldset/SR_GP16:
   extends: SR_BASIC
   description: status register
   fields:
   - name: CCIF
-    description: Capture/compare 1 interrupt flag
+    description: Capture/compare x (x=1-4) interrupt flag
     bit_offset: 1
     bit_size: 1
     array:
       len: 4
       stride: 1
-  - name: COMIF
-    description: COM interrupt flag
-    bit_offset: 5
-    bit_size: 1
   - name: TIF
     description: Trigger interrupt flag
     bit_offset: 6
     bit_size: 1
-  - name: BIF
-    description: Break interrupt flag
-    bit_offset: 7
-    bit_size: 1
   - name: CCOF
-    description: Capture/Compare 1 overcapture flag
+    description: Capture/Compare x (x=1-4) overcapture flag
     bit_offset: 9
     bit_size: 1
     array:
       len: 4
       stride: 1
+  - name: IDXIF
+    description: Index interrupt flag
+    bit_offset: 20
+    bit_size: 1
+  - name: DIRIF
+    description: Direction change interrupt flag
+    bit_offset: 21
+    bit_size: 1
+  - name: IERRIF
+    description: Index error interrupt flag
+    bit_offset: 22
+    bit_size: 1
+  - name: TERRIF
+    description: Transition error interrupt flag
+    bit_offset: 23
+    bit_size: 1
+fieldset/TISEL_1CH:
+  description: input selection register
+  fields:
+  - name: TISEL
+    description: Selects TIM_TIx (x=1) input
+    bit_offset: 0
+    bit_size: 4
+    array:
+      len: 1
+      stride: 8
+fieldset/TISEL_2CH:
+  extends: TISEL_1CH
+  description: input selection register
+  fields:
+  - name: TISEL
+    description: Selects TIM_TIx (x=1-2) input
+    bit_offset: 0
+    bit_size: 4
+    array:
+      len: 2
+      stride: 8
+fieldset/TISEL_GP16:
+  description: input selection register
+  fields:
+  - name: TISEL
+    description: Selects TIM_TIx (x=1-4) input
+    bit_offset: 0
+    bit_size: 4
+    array:
+      len: 4
+      stride: 8
+enum/BKBID:
+  bit_size: 1
+  variants:
+  - name: Input
+    description: Break input tim_brk in input mode
+    value: 0
+  - name: Bidirectional
+    description: Break input tim_brk in bidirectional mode
+    value: 1
+enum/BKDSRM:
+  bit_size: 1
+  variants:
+  - name: Armed
+    description: Break input tim_brk is armed
+    value: 0
+  - name: Disarmed
+    description: Break input tim_brk is disarmed
+    value: 1
+enum/BKINP:
+  bit_size: 1
+  variants:
+  - name: NotInverted
+    description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1)
+    value: 0
+  - name: Inverted
+    description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1)
+    value: 1
+enum/BKP:
+  bit_size: 1
+  variants:
+  - name: ActiveLow
+    description: Break input tim_brk is active low
+    value: 0
+  - name: ActiveHigh
+    description: Break input tim_brk is active high
+    value: 1
 enum/CCDS:
   bit_size: 1
   variants:
@@ -695,6 +2026,30 @@ enum/CMS:
   - name: CenterAligned3
     description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
     value: 3
+enum/DBSS:
+  bit_size: 4
+  variants:
+  - name: Update
+    description: Update
+    value: 1
+  - name: CC1
+    description: CC1
+    value: 2
+  - name: CC2
+    description: CC2
+    value: 3
+  - name: CC3
+    description: CC3
+    value: 4
+  - name: CC4
+    description: CC4
+    value: 5
+  - name: COM
+    description: COM
+    value: 6
+  - name: Trigger
+    description: Trigger
+    value: 7
 enum/DIR:
   bit_size: 1
   variants:
@@ -704,57 +2059,15 @@ enum/DIR:
   - name: Down
     description: Counter used as downcounter
     value: 1
-enum/ETF:
-  bit_size: 4
+enum/DTAE:
+  bit_size: 1
   variants:
-  - name: NoFilter
-    description: No filter, sampling is done at fDTS
+  - name: Identical
+    description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register
     value: 0
-  - name: FCK_INT_N2
-    description: fSAMPLING=fCK_INT, N=2
+  - name: Distinct
+    description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits.
     value: 1
-  - name: FCK_INT_N4
-    description: fSAMPLING=fCK_INT, N=4
-    value: 2
-  - name: FCK_INT_N8
-    description: fSAMPLING=fCK_INT, N=8
-    value: 3
-  - name: FDTS_Div2_N6
-    description: fSAMPLING=fDTS/2, N=6
-    value: 4
-  - name: FDTS_Div2_N8
-    description: fSAMPLING=fDTS/2, N=8
-    value: 5
-  - name: FDTS_Div4_N6
-    description: fSAMPLING=fDTS/4, N=6
-    value: 6
-  - name: FDTS_Div4_N8
-    description: fSAMPLING=fDTS/4, N=8
-    value: 7
-  - name: FDTS_Div8_N6
-    description: fSAMPLING=fDTS/8, N=6
-    value: 8
-  - name: FDTS_Div8_N8
-    description: fSAMPLING=fDTS/8, N=8
-    value: 9
-  - name: FDTS_Div16_N5
-    description: fSAMPLING=fDTS/16, N=5
-    value: 10
-  - name: FDTS_Div16_N6
-    description: fSAMPLING=fDTS/16, N=6
-    value: 11
-  - name: FDTS_Div16_N8
-    description: fSAMPLING=fDTS/16, N=8
-    value: 12
-  - name: FDTS_Div32_N5
-    description: fSAMPLING=fDTS/32, N=5
-    value: 13
-  - name: FDTS_Div32_N6
-    description: fSAMPLING=fDTS/32, N=6
-    value: 14
-  - name: FDTS_Div32_N8
-    description: fSAMPLING=fDTS/32, N=8
-    value: 15
 enum/ETP:
   bit_size: 1
   variants:
@@ -779,7 +2092,16 @@ enum/ETPS:
   - name: Div8
     description: ETRP frequency divided by 8
     value: 3
-enum/ICF:
+enum/FIDX:
+  bit_size: 1
+  variants:
+  - name: AlwaysActive
+    description: Index is always active
+    value: 0
+  - name: FirstOnly
+    description: the first Index only resets the counter
+    value: 1
+enum/FilterValue:
   bit_size: 4
   variants:
   - name: NoFilter
@@ -830,6 +2152,54 @@ enum/ICF:
   - name: FDTS_Div32_N8
     description: fSAMPLING=fDTS/32, N=8
     value: 15
+enum/GC5C:
+  bit_size: 1
+  variants:
+  - name: NoEffect
+    description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3)
+    value: 0
+  - name: LogicalAND
+    description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF
+    value: 1
+enum/IBLK:
+  bit_size: 2
+  variants:
+  - name: AlwaysActive
+    description: Index always active
+    value: 0
+  - name: CC3P
+    description: Index disabled when tim_ti3 input is active, as per CC3P bitfield
+    value: 1
+  - name: CC4P
+    description: Index disabled when tim_ti4 input is active, as per CC4P bitfield
+    value: 2
+enum/IDIR:
+  bit_size: 2
+  variants:
+  - name: Both
+    description: Index resets the counter whatever the direction
+    value: 0
+  - name: Up
+    description: Index resets the counter when up-counting only
+    value: 1
+  - name: Down
+    description: Index resets the counter when down-counting only
+    value: 2
+enum/LOCK:
+  bit_size: 2
+  variants:
+  - name: Disabled
+    description: No bit is write protected
+    value: 0
+  - name: Level1
+    description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
+    value: 1
+  - name: Level2
+    description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
+    value: 2
+  - name: Level3
+    description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
+    value: 3
 enum/MMS:
   bit_size: 3
   variants:
@@ -857,6 +2227,57 @@ enum/MMS:
   - name: CompareOC4
     description: OC4REF signal is used as trigger output
     value: 7
+enum/MMS2:
+  bit_size: 4
+  variants:
+  - name: Reset
+    description: The UG bit from the TIMx_EGR register is used as TRGO2
+    value: 0
+  - name: Enable
+    description: The counter enable signal, CNT_EN, is used as TRGO2
+    value: 1
+  - name: Update
+    description: The update event is selected as TRGO2
+    value: 2
+  - name: ComparePulse
+    description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
+    value: 3
+  - name: CompareOC1
+    description: OC1REF signal is used as TRGO2
+    value: 4
+  - name: CompareOC2
+    description: OC2REF signal is used as TRGO2
+    value: 5
+  - name: CompareOC3
+    description: OC3REF signal is used as TRGO2
+    value: 6
+  - name: CompareOC4
+    description: OC4REF signal is used as TRGO2
+    value: 7
+  - name: CompareOC5
+    description: OC5REF signal is used as TRGO2
+    value: 8
+  - name: CompareOC6
+    description: OC6REF signal is used as TRGO2
+    value: 9
+  - name: ComparePulse_OC4
+    description: OC4REF rising or falling edges generate pulses on TRGO2
+    value: 10
+  - name: ComparePulse_OC6
+    description: OC6REF rising or falling edges generate pulses on TRGO2
+    value: 11
+  - name: ComparePulse_OC4_Or_OC6_Rising
+    description: OC4REF or OC6REF rising edges generate pulses on TRGO2
+    value: 12
+  - name: ComparePulse_OC4_Rising_Or_OC6_Falling
+    description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2
+    value: 13
+  - name: ComparePulse_OC5_Or_OC6_Rising
+    description: OC5REF or OC6REF rising edges generate pulses on TRGO2
+    value: 14
+  - name: ComparePulse_OC5_Rising_Or_OC6_Falling
+    description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2
+    value: 15
 enum/MSM:
   bit_size: 1
   variants:
@@ -866,6 +2287,15 @@ enum/MSM:
   - name: Sync
     description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
     value: 1
+enum/OCCS:
+  bit_size: 1
+  variants:
+  - name: Input
+    description: tim_ocref_clr_int is connected to the tim_ocref_clr input
+    value: 0
+  - name: ETRF
+    description: tim_ocref_clr_int is connected to tim_etrf
+    value: 1
 enum/OCM:
   bit_size: 3
   variants:
@@ -938,7 +2368,16 @@ enum/SMS:
   - name: Ext_Clock_Mode
     description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
     value: 7
-enum/TIS:
+enum/SMSPS:
+  bit_size: 1
+  variants:
+  - name: Update
+    description: The transfer is triggered by the Timer’s Update event
+    value: 0
+  - name: Index
+    description: The transfer is triggered by the Index event
+    value: 1
+enum/TI1S:
   bit_size: 1
   variants:
   - name: Normal