From 8402040d17cff5bea092a5ca944049727679dcf1 Mon Sep 17 00:00:00 2001 From: Matous Hybl Date: Wed, 8 Dec 2021 20:01:57 +0100 Subject: [PATCH] Fix generation of FMC peripheral in chip yamls. Add FMC registers. --- data/registers/fmc_h7.yaml | 1581 ++++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 3 + 2 files changed, 1584 insertions(+) create mode 100644 data/registers/fmc_h7.yaml diff --git a/data/registers/fmc_h7.yaml b/data/registers/fmc_h7.yaml new file mode 100644 index 0000000..4b1b235 --- /dev/null +++ b/data/registers/fmc_h7.yaml @@ -0,0 +1,1581 @@ +block/FMC: + description: FMC + items: + - byte_offset: 0 + description: This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories. + fieldset: BCR1 + name: BCR1 + - byte_offset: 4 + description: 'This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for write and read access, + that is, 2 registers are available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx registers).' + fieldset: BTR1 + name: BTR1 + - byte_offset: 8 + description: This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories. + fieldset: BCR2 + name: BCR2 + - byte_offset: 12 + description: 'This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for write and read access, + that is, 2 registers are available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx registers).' + fieldset: BTR2 + name: BTR2 + - byte_offset: 16 + description: This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories. + fieldset: BCR3 + name: BCR3 + - byte_offset: 20 + description: 'This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for write and read access, + that is, 2 registers are available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx registers).' + fieldset: BTR3 + name: BTR3 + - byte_offset: 24 + description: This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories. + fieldset: BCR4 + name: BCR4 + - byte_offset: 28 + description: 'This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the + FMC_BCRx register, then this register is partitioned for write and read access, + that is, 2 registers are available: one to configure read accesses (this register) + and one to configure write accesses (FMC_BWTRx registers).' + fieldset: BTR4 + name: BTR4 + - byte_offset: 128 + description: NAND Flash control registers + fieldset: PCR + name: PCR + - byte_offset: 132 + description: This register contains information about the FIFO status and interrupt. + The FMC features a FIFO that is used when writing to memories to transfer up + to 16 words of data.This is used to quickly write to the FIFO and free the AXI + bus for transactions to peripherals other than the FMC, while the FMC is draining + its FIFO into the memory. One of these register bits indicates the status of + the FIFO, for ECC purposes.The ECC is calculated while the data are written + to the memory. To read the correct ECC, the software must consequently wait + until the FIFO is empty. + fieldset: SR + name: SR + - byte_offset: 136 + description: The FMC_PMEM read/write register contains the timing information + for NAND Flash memory bank. This information is used to access either the common + memory space of the NAND Flash for command, address write access and data read/write + access. + fieldset: PMEM + name: PMEM + - byte_offset: 140 + description: 'The FMC_PATT read/write register contains the timing information + for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory + space of the NAND Flash for the last address write access if the timing must + differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: + NAND Flash prewait feature).' + fieldset: PATT + name: PATT + - access: Read + byte_offset: 148 + description: 'This register contain the current error correction code value computed + by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes + the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: + Computation of the error correction code (ECC) in NAND Flash memory), the data + read/written from/to the NAND Flash memory are processed automatically by the + ECC computation module. When X bytes have been read (according to the ECCPS + field in the FMC_PCR registers), the CPU must read the computed ECC value from + the FMC_ECC registers. It then verifies if these computed parity data are the + same as the parity value recorded in the spare area, to determine whether a + page is valid, and, to correct it otherwise. The FMC_ECCR register should be + cleared after being read by setting the ECCEN bit to 0. To compute a new data + block, the ECCEN bit must be set to 1.' + fieldset: ECCR + name: ECCR + - byte_offset: 260 + description: This register contains the control information of each memory bank. + It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is + set in the FMC_BCRx register, then this register is active for write access. + fieldset: BWTR1 + name: BWTR1 + - byte_offset: 268 + description: This register contains the control information of each memory bank. + It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is + set in the FMC_BCRx register, then this register is active for write access. + fieldset: BWTR2 + name: BWTR2 + - byte_offset: 276 + description: This register contains the control information of each memory bank. + It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is + set in the FMC_BCRx register, then this register is active for write access. + fieldset: BWTR3 + name: BWTR3 + - byte_offset: 284 + description: This register contains the control information of each memory bank. + It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is + set in the FMC_BCRx register, then this register is active for write access. + fieldset: BWTR4 + name: BWTR4 + - array: + len: 2 + stride: 4 + block: SDBANK + byte_offset: 320 + description: Cluster SDBANK%s, containing SDTR?, SDCR? + name: SDBANK + - byte_offset: 336 + description: This register contains the command issued when the SDRAM device is + accessed. This register is used to initialize the SDRAM device, and to activate + the Self-refresh and the Power-down modes. As soon as the MODE field is written, + the command will be issued only to one or to both SDRAM banks according to CTB1 + and CTB2 command bits. This register is the same for both SDRAM banks. + fieldset: SDCMR + name: SDCMR + - byte_offset: 340 + description: This register sets the refresh rate in number of SDCLK clock cycles + between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere + 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM + clock cycles (as in the above example) to obtain a safe margin if an internal + refresh request occurs when a read request has been accepted. It corresponds + to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a + timer which is decremented using the SDRAM clock. This timer generates a refresh + pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM + clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts + counting. If the value programmed in the register is 0, no refresh is carried + out. This register must not be reprogrammed after the initialization procedure + to avoid modifying the refresh rate.Each time a refresh pulse is generated, + this 13-bit COUNT field is reloaded into the counter.If a memory access is in + progress, the Auto-refresh request is delayed. However, if the memory access + and Auto-refresh requests are generated simultaneously, the Auto-refresh takes + precedence. If the memory access occurs during a refresh operation, the request + is buffered to be processed when the refresh is complete.This register is common + to SDRAM bank 1 and bank 2. + fieldset: SDRTR + name: SDRTR + - access: Read + byte_offset: 344 + description: SDRAM Status register + fieldset: SDSR + name: SDSR +block/SDBANK: + description: Cluster SDBANK%s, containing SDTR?, SDCR? + items: + - byte_offset: 0 + description: This register contains the control parameters for each SDRAM memory + bank + fieldset: SDCR + name: SDCR + - byte_offset: 8 + description: This register contains the timing parameters of each SDRAM bank + fieldset: SDTR + name: SDTR +fieldset/BCR1: + description: This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories. + fields: + - bit_offset: 0 + bit_size: 1 + description: Memory bank enable bit This bit enables the memory bank. After reset + Bank1 is enabled, all others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + name: MBKEN + - bit_offset: 1 + bit_size: 1 + description: 'Address/data multiplexing enable bit When this bit is set, the address + and data values are multiplexed on the data bus, valid only with NOR and PSRAM + memories:' + name: MUXEN + - bit_offset: 2 + bit_size: 2 + description: 'Memory type These bits define the type of external memory attached + to the corresponding memory bank:' + name: MTYP + - bit_offset: 4 + bit_size: 2 + description: Memory data bus width Defines the external memory device width, valid + for all type of memories. + name: MWID + - bit_offset: 6 + bit_size: 1 + description: Flash access enable This bit enables NOR Flash memory access operations. + name: FACCEN + - bit_offset: 8 + bit_size: 1 + description: 'Burst enable bit This bit enables/disables synchronous accesses + during read operations. It is valid only for synchronous memories operating + in Burst mode:' + name: BURSTEN + - bit_offset: 9 + bit_size: 1 + description: 'Wait signal polarity bit This bit defines the polarity of the wait + signal from memory used for either in synchronous or asynchronous mode:' + name: WAITPOL + - bit_offset: 11 + bit_size: 1 + description: 'Wait timing configuration The NWAIT signal indicates whether the + data from the memory are valid or if a wait state must be inserted when accessing + the memory in synchronous mode. This configuration bit determines if NWAIT is + asserted by the memory one clock cycle before the wait state or during the wait + state:' + name: WAITCFG + - bit_offset: 12 + bit_size: 1 + description: 'Write enable bit This bit indicates whether write operations are + enabled/disabled in the bank by the FMC:' + name: WREN + - bit_offset: 13 + bit_size: 1 + description: Wait enable bit This bit enables/disables wait-state insertion via + the NWAIT signal when accessing the memory in synchronous mode. + name: WAITEN + - bit_offset: 14 + bit_size: 1 + description: 'Extended mode enable. This bit enables the FMC to program the write + timings for asynchronous accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. Note: When the extended + mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode + 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 + or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected + (MTYP = 0x10).' + name: EXTMOD + - bit_offset: 15 + bit_size: 1 + description: Wait signal during asynchronous transfers This bit enables/disables + the FMC to use the wait signal even during an asynchronous protocol. + name: ASYNCWAIT + - bit_offset: 16 + bit_size: 3 + description: 'CRAM Page Size These are used for Cellular RAM 1.5 which does not + allow burst access to cross the address boundaries between pages. When these + bits are configured, the FMC controller splits automatically the burst access + when the memory page size is reached (refer to memory datasheet for page size). + Other configuration: reserved.' + name: CPSIZE + - bit_offset: 19 + bit_size: 1 + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the + bit enables synchronous accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + name: CBURSTRW + - bit_offset: 20 + bit_size: 1 + description: 'Continuous Clock Enable This bit enables the FMC_CLK clock output + to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers + is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must + be configured in synchronous mode to generate the FMC_CLK continuous clock. + If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in + the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous memories connected to other + banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 + and FMC_BWTR2..4 registers for other banks has no effect.)' + name: CCLKEN + - bit_offset: 21 + bit_size: 1 + description: 'Write FIFO Disable This bit disables the Write FIFO used by the + FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 register.' + name: WFDIS + - bit_offset: 24 + bit_size: 2 + description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 + or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP + bits of the FMC_BCR2..4 registers are dont care. It is only enabled through + the FMC_BCR1 register.' + name: BMAP + - bit_offset: 31 + bit_size: 1 + description: 'FMC controller Enable This bit enables/disables the FMC controller. + Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled + through the FMC_BCR1 register.' + name: FMCEN +fieldset/BCR2: + description: This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories. + fields: + - bit_offset: 0 + bit_size: 1 + description: Memory bank enable bit This bit enables the memory bank. After reset + Bank1 is enabled, all others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + name: MBKEN + - bit_offset: 1 + bit_size: 1 + description: 'Address/data multiplexing enable bit When this bit is set, the address + and data values are multiplexed on the data bus, valid only with NOR and PSRAM + memories:' + name: MUXEN + - bit_offset: 2 + bit_size: 2 + description: 'Memory type These bits define the type of external memory attached + to the corresponding memory bank:' + name: MTYP + - bit_offset: 4 + bit_size: 2 + description: Memory data bus width Defines the external memory device width, valid + for all type of memories. + name: MWID + - bit_offset: 6 + bit_size: 1 + description: Flash access enable This bit enables NOR Flash memory access operations. + name: FACCEN + - bit_offset: 8 + bit_size: 1 + description: 'Burst enable bit This bit enables/disables synchronous accesses + during read operations. It is valid only for synchronous memories operating + in Burst mode:' + name: BURSTEN + - bit_offset: 9 + bit_size: 1 + description: 'Wait signal polarity bit This bit defines the polarity of the wait + signal from memory used for either in synchronous or asynchronous mode:' + name: WAITPOL + - bit_offset: 11 + bit_size: 1 + description: 'Wait timing configuration The NWAIT signal indicates whether the + data from the memory are valid or if a wait state must be inserted when accessing + the memory in synchronous mode. This configuration bit determines if NWAIT is + asserted by the memory one clock cycle before the wait state or during the wait + state:' + name: WAITCFG + - bit_offset: 12 + bit_size: 1 + description: 'Write enable bit This bit indicates whether write operations are + enabled/disabled in the bank by the FMC:' + name: WREN + - bit_offset: 13 + bit_size: 1 + description: Wait enable bit This bit enables/disables wait-state insertion via + the NWAIT signal when accessing the memory in synchronous mode. + name: WAITEN + - bit_offset: 14 + bit_size: 1 + description: 'Extended mode enable. This bit enables the FMC to program the write + timings for asynchronous accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. Note: When the extended + mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode + 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 + or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected + (MTYP = 0x10).' + name: EXTMOD + - bit_offset: 15 + bit_size: 1 + description: Wait signal during asynchronous transfers This bit enables/disables + the FMC to use the wait signal even during an asynchronous protocol. + name: ASYNCWAIT + - bit_offset: 16 + bit_size: 3 + description: 'CRAM Page Size These are used for Cellular RAM 1.5 which does not + allow burst access to cross the address boundaries between pages. When these + bits are configured, the FMC controller splits automatically the burst access + when the memory page size is reached (refer to memory datasheet for page size). + Other configuration: reserved.' + name: CPSIZE + - bit_offset: 19 + bit_size: 1 + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the + bit enables synchronous accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + name: CBURSTRW + - bit_offset: 20 + bit_size: 1 + description: 'Continuous Clock Enable This bit enables the FMC_CLK clock output + to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers + is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must + be configured in synchronous mode to generate the FMC_CLK continuous clock. + If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in + the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous memories connected to other + banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 + and FMC_BWTR2..4 registers for other banks has no effect.)' + name: CCLKEN + - bit_offset: 21 + bit_size: 1 + description: 'Write FIFO Disable This bit disables the Write FIFO used by the + FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 register.' + name: WFDIS + - bit_offset: 24 + bit_size: 2 + description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 + or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP + bits of the FMC_BCR2..4 registers are dont care. It is only enabled through + the FMC_BCR1 register.' + name: BMAP + - bit_offset: 31 + bit_size: 1 + description: 'FMC controller Enable This bit enables/disables the FMC controller. + Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled + through the FMC_BCR1 register.' + name: FMCEN +fieldset/BCR3: + description: This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories. + fields: + - bit_offset: 0 + bit_size: 1 + description: Memory bank enable bit This bit enables the memory bank. After reset + Bank1 is enabled, all others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + name: MBKEN + - bit_offset: 1 + bit_size: 1 + description: 'Address/data multiplexing enable bit When this bit is set, the address + and data values are multiplexed on the data bus, valid only with NOR and PSRAM + memories:' + name: MUXEN + - bit_offset: 2 + bit_size: 2 + description: 'Memory type These bits define the type of external memory attached + to the corresponding memory bank:' + name: MTYP + - bit_offset: 4 + bit_size: 2 + description: Memory data bus width Defines the external memory device width, valid + for all type of memories. + name: MWID + - bit_offset: 6 + bit_size: 1 + description: Flash access enable This bit enables NOR Flash memory access operations. + name: FACCEN + - bit_offset: 8 + bit_size: 1 + description: 'Burst enable bit This bit enables/disables synchronous accesses + during read operations. It is valid only for synchronous memories operating + in Burst mode:' + name: BURSTEN + - bit_offset: 9 + bit_size: 1 + description: 'Wait signal polarity bit This bit defines the polarity of the wait + signal from memory used for either in synchronous or asynchronous mode:' + name: WAITPOL + - bit_offset: 11 + bit_size: 1 + description: 'Wait timing configuration The NWAIT signal indicates whether the + data from the memory are valid or if a wait state must be inserted when accessing + the memory in synchronous mode. This configuration bit determines if NWAIT is + asserted by the memory one clock cycle before the wait state or during the wait + state:' + name: WAITCFG + - bit_offset: 12 + bit_size: 1 + description: 'Write enable bit This bit indicates whether write operations are + enabled/disabled in the bank by the FMC:' + name: WREN + - bit_offset: 13 + bit_size: 1 + description: Wait enable bit This bit enables/disables wait-state insertion via + the NWAIT signal when accessing the memory in synchronous mode. + name: WAITEN + - bit_offset: 14 + bit_size: 1 + description: 'Extended mode enable. This bit enables the FMC to program the write + timings for asynchronous accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. Note: When the extended + mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode + 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 + or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected + (MTYP = 0x10).' + name: EXTMOD + - bit_offset: 15 + bit_size: 1 + description: Wait signal during asynchronous transfers This bit enables/disables + the FMC to use the wait signal even during an asynchronous protocol. + name: ASYNCWAIT + - bit_offset: 16 + bit_size: 3 + description: 'CRAM Page Size These are used for Cellular RAM 1.5 which does not + allow burst access to cross the address boundaries between pages. When these + bits are configured, the FMC controller splits automatically the burst access + when the memory page size is reached (refer to memory datasheet for page size). + Other configuration: reserved.' + name: CPSIZE + - bit_offset: 19 + bit_size: 1 + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the + bit enables synchronous accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + name: CBURSTRW + - bit_offset: 20 + bit_size: 1 + description: 'Continuous Clock Enable This bit enables the FMC_CLK clock output + to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers + is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must + be configured in synchronous mode to generate the FMC_CLK continuous clock. + If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in + the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous memories connected to other + banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 + and FMC_BWTR2..4 registers for other banks has no effect.)' + name: CCLKEN + - bit_offset: 21 + bit_size: 1 + description: 'Write FIFO Disable This bit disables the Write FIFO used by the + FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 register.' + name: WFDIS + - bit_offset: 24 + bit_size: 2 + description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 + or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP + bits of the FMC_BCR2..4 registers are dont care. It is only enabled through + the FMC_BCR1 register.' + name: BMAP + - bit_offset: 31 + bit_size: 1 + description: 'FMC controller Enable This bit enables/disables the FMC controller. + Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled + through the FMC_BCR1 register.' + name: FMCEN +fieldset/BCR4: + description: This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories. + fields: + - bit_offset: 0 + bit_size: 1 + description: Memory bank enable bit This bit enables the memory bank. After reset + Bank1 is enabled, all others are disabled. Accessing a disabled bank causes + an ERROR on AXI bus. + name: MBKEN + - bit_offset: 1 + bit_size: 1 + description: 'Address/data multiplexing enable bit When this bit is set, the address + and data values are multiplexed on the data bus, valid only with NOR and PSRAM + memories:' + name: MUXEN + - bit_offset: 2 + bit_size: 2 + description: 'Memory type These bits define the type of external memory attached + to the corresponding memory bank:' + name: MTYP + - bit_offset: 4 + bit_size: 2 + description: Memory data bus width Defines the external memory device width, valid + for all type of memories. + name: MWID + - bit_offset: 6 + bit_size: 1 + description: Flash access enable This bit enables NOR Flash memory access operations. + name: FACCEN + - bit_offset: 8 + bit_size: 1 + description: 'Burst enable bit This bit enables/disables synchronous accesses + during read operations. It is valid only for synchronous memories operating + in Burst mode:' + name: BURSTEN + - bit_offset: 9 + bit_size: 1 + description: 'Wait signal polarity bit This bit defines the polarity of the wait + signal from memory used for either in synchronous or asynchronous mode:' + name: WAITPOL + - bit_offset: 11 + bit_size: 1 + description: 'Wait timing configuration The NWAIT signal indicates whether the + data from the memory are valid or if a wait state must be inserted when accessing + the memory in synchronous mode. This configuration bit determines if NWAIT is + asserted by the memory one clock cycle before the wait state or during the wait + state:' + name: WAITCFG + - bit_offset: 12 + bit_size: 1 + description: 'Write enable bit This bit indicates whether write operations are + enabled/disabled in the bank by the FMC:' + name: WREN + - bit_offset: 13 + bit_size: 1 + description: Wait enable bit This bit enables/disables wait-state insertion via + the NWAIT signal when accessing the memory in synchronous mode. + name: WAITEN + - bit_offset: 14 + bit_size: 1 + description: 'Extended mode enable. This bit enables the FMC to program the write + timings for asynchronous accesses inside the FMC_BWTR register, thus resulting + in different timings for read and write operations. Note: When the extended + mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode + 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 + or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected + (MTYP = 0x10).' + name: EXTMOD + - bit_offset: 15 + bit_size: 1 + description: Wait signal during asynchronous transfers This bit enables/disables + the FMC to use the wait signal even during an asynchronous protocol. + name: ASYNCWAIT + - bit_offset: 16 + bit_size: 3 + description: 'CRAM Page Size These are used for Cellular RAM 1.5 which does not + allow burst access to cross the address boundaries between pages. When these + bits are configured, the FMC controller splits automatically the burst access + when the memory page size is reached (refer to memory datasheet for page size). + Other configuration: reserved.' + name: CPSIZE + - bit_offset: 19 + bit_size: 1 + description: Write burst enable For PSRAM (CRAM) operating in Burst mode, the + bit enables synchronous accesses during write operations. The enable bit for + synchronous read accesses is the BURSTEN bit in the FMC_BCRx register. + name: CBURSTRW + - bit_offset: 20 + bit_size: 1 + description: 'Continuous Clock Enable This bit enables the FMC_CLK clock output + to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers + is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must + be configured in synchronous mode to generate the FMC_CLK continuous clock. + If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in + the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous + mode is used and CCLKEN bit is set, the synchronous memories connected to other + banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 + and FMC_BWTR2..4 registers for other banks has no effect.)' + name: CCLKEN + - bit_offset: 21 + bit_size: 1 + description: 'Write FIFO Disable This bit disables the Write FIFO used by the + FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. + It is only enabled through the FMC_BCR1 register.' + name: WFDIS + - bit_offset: 24 + bit_size: 2 + description: 'FMC bank mapping These bits allows different to remap SDRAM bank2 + or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP + bits of the FMC_BCR2..4 registers are dont care. It is only enabled through + the FMC_BCR1 register.' + name: BMAP + - bit_offset: 31 + bit_size: 1 + description: 'FMC controller Enable This bit enables/disables the FMC controller. + Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled + through the FMC_BCR1 register.' + name: FMCEN +fieldset/BTR1: + description: 'This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx + register, then this register is partitioned for write and read access, that is, + 2 registers are available: one to configure read accesses (this register) and + one to configure write accesses (FMC_BWTRx registers).' + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Address setup phase duration These bits are written by software + to define the duration of the address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address + setup phase duration, please refer to the respective figure (refer to Figure81 + to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed + mode or Mode D, the minimum value for ADDSET is 1.' + name: ADDSET + - bit_offset: 4 + bit_size: 4 + description: 'Address-hold phase duration These bits are written by software to + define the duration of the address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each access mode address-hold phase + duration, please refer to the respective figure (Figure81 to Figure93). Note: + In synchronous accesses, this value is not used, the address hold phase is always + 1 memory clock period duration.' + name: ADDHLD + - bit_offset: 8 + bit_size: 8 + description: 'Data-phase duration These bits are written by software to define + the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous + accesses: For each memory type and access mode data-phase duration, please refer + to the respective figure (Figure81 to Figure93). Example: Mode1, write access, + DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous + accesses, this value is dont care.' + name: DATAST + - bit_offset: 16 + bit_size: 4 + description: 'Bus turnaround phase duration These bits are written by software + to add a delay at the end of a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between an asynchronous read (in + muxed or mode D) or write transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation is performed, the bank + can be the same or a different one, whereas it must be different in case of + write operation to the bank, except in muxed mode or mode D. In some cases, + whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted between two consecutive asynchronous + write transfers to the same static memory bank except in muxed mode and mode + D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive + asynchronous read transfers to the same static memory bank except for modes + muxed and D. An asynchronous read to an asynchronous or synchronous write to + any static bank or dynamic bank except in modes muxed and D mode. There is a + bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or read transfer to or from + static memory bank (the bank can be the same or a different one in case of a + read operation. Two consecutive synchronous read operations (in Burst or Single + mode) followed by any synchronous/asynchronous read or write from/to another + static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in Burst or Single mode) to different + static banks. A synchronous write access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus turnaround delay allows to match + the minimum time between consecutive transactions (tEHEL from NEx high to NEx + low) and the maximum time required by the memory to free the data bus after + a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ...' + name: BUSTURN + - bit_offset: 20 + bit_size: 4 + description: 'Clock divide ratio (for FMC_CLK signal) These bits define the period + of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous + NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio formula)' + name: CLKDIV + - bit_offset: 24 + bit_size: 4 + description: Data latency for synchronous memory For synchronous access with read + write burst mode enabled these bits define the number of memory clock cycles + name: DATLAT + - bit_offset: 28 + bit_size: 2 + description: Access mode These bits specify the asynchronous access modes as shown + in the timing diagrams. They are taken into account only when the EXTMOD bit + in the FMC_BCRx register is 1. + name: ACCMOD +fieldset/BTR2: + description: 'This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx + register, then this register is partitioned for write and read access, that is, + 2 registers are available: one to configure read accesses (this register) and + one to configure write accesses (FMC_BWTRx registers).' + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Address setup phase duration These bits are written by software + to define the duration of the address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address + setup phase duration, please refer to the respective figure (refer to Figure81 + to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed + mode or Mode D, the minimum value for ADDSET is 1.' + name: ADDSET + - bit_offset: 4 + bit_size: 4 + description: 'Address-hold phase duration These bits are written by software to + define the duration of the address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each access mode address-hold phase + duration, please refer to the respective figure (Figure81 to Figure93). Note: + In synchronous accesses, this value is not used, the address hold phase is always + 1 memory clock period duration.' + name: ADDHLD + - bit_offset: 8 + bit_size: 8 + description: 'Data-phase duration These bits are written by software to define + the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous + accesses: For each memory type and access mode data-phase duration, please refer + to the respective figure (Figure81 to Figure93). Example: Mode1, write access, + DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous + accesses, this value is dont care.' + name: DATAST + - bit_offset: 16 + bit_size: 4 + description: 'Bus turnaround phase duration These bits are written by software + to add a delay at the end of a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between an asynchronous read (in + muxed or mode D) or write transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation is performed, the bank + can be the same or a different one, whereas it must be different in case of + write operation to the bank, except in muxed mode or mode D. In some cases, + whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted between two consecutive asynchronous + write transfers to the same static memory bank except in muxed mode and mode + D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive + asynchronous read transfers to the same static memory bank except for modes + muxed and D. An asynchronous read to an asynchronous or synchronous write to + any static bank or dynamic bank except in modes muxed and D mode. There is a + bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or read transfer to or from + static memory bank (the bank can be the same or a different one in case of a + read operation. Two consecutive synchronous read operations (in Burst or Single + mode) followed by any synchronous/asynchronous read or write from/to another + static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in Burst or Single mode) to different + static banks. A synchronous write access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus turnaround delay allows to match + the minimum time between consecutive transactions (tEHEL from NEx high to NEx + low) and the maximum time required by the memory to free the data bus after + a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 1. ...' + name: BUSTURN + - bit_offset: 20 + bit_size: 4 + description: 'Clock divide ratio (for FMC_CLK signal) These bits define the period + of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous + NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio formula)' + name: CLKDIV + - bit_offset: 24 + bit_size: 4 + description: Data latency for synchronous memory For synchronous access with read + write burst mode enabled these bits define the number of memory clock cycles + name: DATLAT + - bit_offset: 28 + bit_size: 2 + description: Access mode These bits specify the asynchronous access modes as shown + in the timing diagrams. They are taken into account only when the EXTMOD bit + in the FMC_BCRx register is 1. + name: ACCMOD +fieldset/BTR3: + description: 'This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx + register, then this register is partitioned for write and read access, that is, + 2 registers are available: one to configure read accesses (this register) and + one to configure write accesses (FMC_BWTRx registers).' + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Address setup phase duration These bits are written by software + to define the duration of the address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address + setup phase duration, please refer to the respective figure (refer to Figure81 + to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed + mode or Mode D, the minimum value for ADDSET is 1.' + name: ADDSET + - bit_offset: 4 + bit_size: 4 + description: 'Address-hold phase duration These bits are written by software to + define the duration of the address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each access mode address-hold phase + duration, please refer to the respective figure (Figure81 to Figure93). Note: + In synchronous accesses, this value is not used, the address hold phase is always + 1 memory clock period duration.' + name: ADDHLD + - bit_offset: 8 + bit_size: 8 + description: 'Data-phase duration These bits are written by software to define + the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous + accesses: For each memory type and access mode data-phase duration, please refer + to the respective figure (Figure81 to Figure93). Example: Mode1, write access, + DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous + accesses, this value is dont care.' + name: DATAST + - bit_offset: 16 + bit_size: 4 + description: 'Bus turnaround phase duration These bits are written by software + to add a delay at the end of a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between an asynchronous read (in + muxed or mode D) or write transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation is performed, the bank + can be the same or a different one, whereas it must be different in case of + write operation to the bank, except in muxed mode or mode D. In some cases, + whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted between two consecutive asynchronous + write transfers to the same static memory bank except in muxed mode and mode + D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive + asynchronous read transfers to the same static memory bank except for modes + muxed and D. An asynchronous read to an asynchronous or synchronous write to + any static bank or dynamic bank except in modes muxed and D mode. There is a + bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or read transfer to or from + static memory bank (the bank can be the same or a different one in case of a + read operation. Two consecutive synchronous read operations (in Burst or Single + mode) followed by any synchronous/asynchronous read or write from/to another + static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in Burst or Single mode) to different + static banks. A synchronous write access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus turnaround delay allows to match + the minimum time between consecutive transactions (tEHEL from NEx high to NEx + low) and the maximum time required by the memory to free the data bus after + a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. ...' + name: BUSTURN + - bit_offset: 20 + bit_size: 4 + description: 'Clock divide ratio (for FMC_CLK signal) These bits define the period + of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous + NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio formula)' + name: CLKDIV + - bit_offset: 24 + bit_size: 4 + description: Data latency for synchronous memory For synchronous access with read + write burst mode enabled these bits define the number of memory clock cycles + name: DATLAT + - bit_offset: 28 + bit_size: 2 + description: Access mode These bits specify the asynchronous access modes as shown + in the timing diagrams. They are taken into account only when the EXTMOD bit + in the FMC_BCRx register is 1. + name: ACCMOD +fieldset/BTR4: + description: 'This register contains the control information of each memory bank, + used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx + register, then this register is partitioned for write and read access, that is, + 2 registers are available: one to configure read accesses (this register) and + one to configure write accesses (FMC_BWTRx registers).' + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Address setup phase duration These bits are written by software + to define the duration of the address setup phase (refer to Figure81 to Figure93), + used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address + setup phase duration, please refer to the respective figure (refer to Figure81 + to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed + mode or Mode D, the minimum value for ADDSET is 1.' + name: ADDSET + - bit_offset: 4 + bit_size: 4 + description: 'Address-hold phase duration These bits are written by software to + define the duration of the address hold phase (refer to Figure81 to Figure93), + used in mode D or multiplexed accesses: For each access mode address-hold phase + duration, please refer to the respective figure (Figure81 to Figure93). Note: + In synchronous accesses, this value is not used, the address hold phase is always + 1 memory clock period duration.' + name: ADDHLD + - bit_offset: 8 + bit_size: 8 + description: 'Data-phase duration These bits are written by software to define + the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous + accesses: For each memory type and access mode data-phase duration, please refer + to the respective figure (Figure81 to Figure93). Example: Mode1, write access, + DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous + accesses, this value is dont care.' + name: DATAST + - bit_offset: 16 + bit_size: 4 + description: 'Bus turnaround phase duration These bits are written by software + to add a delay at the end of a write-to-read or read-to write transaction. The + programmed bus turnaround delay is inserted between an asynchronous read (in + muxed or mode D) or write transaction and any other asynchronous /synchronous + read/write from/to a static bank. If a read operation is performed, the bank + can be the same or a different one, whereas it must be different in case of + write operation to the bank, except in muxed mode or mode D. In some cases, + whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as + follows: The bus turnaround delay is not inserted between two consecutive asynchronous + write transfers to the same static memory bank except in muxed mode and mode + D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive + asynchronous read transfers to the same static memory bank except for modes + muxed and D. An asynchronous read to an asynchronous or synchronous write to + any static bank or dynamic bank except in modes muxed and D mode. There is a + bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous + write operations (in Burst or Single mode) to the same bank. A synchronous write + (burst or single) access and an asynchronous write or read transfer to or from + static memory bank (the bank can be the same or a different one in case of a + read operation. Two consecutive synchronous read operations (in Burst or Single + mode) followed by any synchronous/asynchronous read or write from/to another + static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: + Two consecutive synchronous write operations (in Burst or Single mode) to different + static banks. A synchronous write access (in Burst or Single mode) and a synchronous + read from the same or a different bank. The bus turnaround delay allows to match + the minimum time between consecutive transactions (tEHEL from NEx high to NEx + low) and the maximum time required by the memory to free the data bus after + a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period + ≥ max (tEHELmin, tEHQZmax) if EXTMOD =1. ...' + name: BUSTURN + - bit_offset: 20 + bit_size: 4 + description: 'Clock divide ratio (for FMC_CLK signal) These bits define the period + of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous + NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: + Synchronous transactions for FMC_CLK divider ratio formula)' + name: CLKDIV + - bit_offset: 24 + bit_size: 4 + description: Data latency for synchronous memory For synchronous access with read + write burst mode enabled these bits define the number of memory clock cycles + name: DATLAT + - bit_offset: 28 + bit_size: 2 + description: Access mode These bits specify the asynchronous access modes as shown + in the timing diagrams. They are taken into account only when the EXTMOD bit + in the FMC_BCRx register is 1. + name: ACCMOD +fieldset/BWTR1: + description: This register contains the control information of each memory bank. + It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active for write access. + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Address setup phase duration. These bits are written by software + to define the duration of the address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous + accesses, this value is not used, the address setup phase is always 1 Flash + clock period duration. In muxed mode, the minimum ADDSET value is 1.' + name: ADDSET + - bit_offset: 4 + bit_size: 4 + description: 'Address-hold phase duration. These bits are written by software + to define the duration of the address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash + accesses, this value is not used, the address hold phase is always 1 Flash clock + period duration.' + name: ADDHLD + - bit_offset: 8 + bit_size: 8 + description: 'Data-phase duration. These bits are written by software to define + the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous + SRAM, PSRAM and NOR Flash memory accesses:' + name: DATAST + - bit_offset: 16 + bit_size: 4 + description: 'Bus turnaround phase duration These bits are written by software + to add a delay at the end of a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC + period ≥ tEHELmin. The programmed bus turnaround delay is inserted between + a an asynchronous write transfer and any other asynchronous /synchronous read + or write transfer to or from a static bank. If a read operation is performed, + the bank can be the same or a different one, whereas it must be different in + case of write operation to the bank, except in muxed mode or mode D. In some + cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed + as follows: The bus turnaround delay is not inserted between two consecutive + asynchronous write transfers to the same static memory bank except for muxed + mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: + Two consecutive synchronous write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous + write or read transfer to or from static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive synchronous write operations + (in Burst or Single mode) to different static banks. A synchronous write transfer + (in Burst or Single mode) and a synchronous read from the same or a different + bank. ...' + name: BUSTURN + - bit_offset: 28 + bit_size: 2 + description: Access mode. These bits specify the asynchronous access modes as + shown in the next timing diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is 1. + name: ACCMOD +fieldset/BWTR2: + description: This register contains the control information of each memory bank. + It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active for write access. + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Address setup phase duration. These bits are written by software + to define the duration of the address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous + accesses, this value is not used, the address setup phase is always 1 Flash + clock period duration. In muxed mode, the minimum ADDSET value is 1.' + name: ADDSET + - bit_offset: 4 + bit_size: 4 + description: 'Address-hold phase duration. These bits are written by software + to define the duration of the address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash + accesses, this value is not used, the address hold phase is always 1 Flash clock + period duration.' + name: ADDHLD + - bit_offset: 8 + bit_size: 8 + description: 'Data-phase duration. These bits are written by software to define + the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous + SRAM, PSRAM and NOR Flash memory accesses:' + name: DATAST + - bit_offset: 16 + bit_size: 4 + description: 'Bus turnaround phase duration These bits are written by software + to add a delay at the end of a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC + period ≥ tEHELmin. The programmed bus turnaround delay is inserted between + a an asynchronous write transfer and any other asynchronous /synchronous read + or write transfer to or from a static bank. If a read operation is performed, + the bank can be the same or a different one, whereas it must be different in + case of write operation to the bank, except in muxed mode or mode D. In some + cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed + as follows: The bus turnaround delay is not inserted between two consecutive + asynchronous write transfers to the same static memory bank except for muxed + mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: + Two consecutive synchronous write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous + write or read transfer to or from static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive synchronous write operations + (in Burst or Single mode) to different static banks. A synchronous write transfer + (in Burst or Single mode) and a synchronous read from the same or a different + bank. ...' + name: BUSTURN + - bit_offset: 28 + bit_size: 2 + description: Access mode. These bits specify the asynchronous access modes as + shown in the next timing diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is 1. + name: ACCMOD +fieldset/BWTR3: + description: This register contains the control information of each memory bank. + It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active for write access. + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Address setup phase duration. These bits are written by software + to define the duration of the address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous + accesses, this value is not used, the address setup phase is always 1 Flash + clock period duration. In muxed mode, the minimum ADDSET value is 1.' + name: ADDSET + - bit_offset: 4 + bit_size: 4 + description: 'Address-hold phase duration. These bits are written by software + to define the duration of the address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash + accesses, this value is not used, the address hold phase is always 1 Flash clock + period duration.' + name: ADDHLD + - bit_offset: 8 + bit_size: 8 + description: 'Data-phase duration. These bits are written by software to define + the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous + SRAM, PSRAM and NOR Flash memory accesses:' + name: DATAST + - bit_offset: 16 + bit_size: 4 + description: 'Bus turnaround phase duration These bits are written by software + to add a delay at the end of a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC + period ≥ tEHELmin. The programmed bus turnaround delay is inserted between + a an asynchronous write transfer and any other asynchronous /synchronous read + or write transfer to or from a static bank. If a read operation is performed, + the bank can be the same or a different one, whereas it must be different in + case of write operation to the bank, except in muxed mode or mode D. In some + cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed + as follows: The bus turnaround delay is not inserted between two consecutive + asynchronous write transfers to the same static memory bank except for muxed + mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: + Two consecutive synchronous write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous + write or read transfer to or from static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive synchronous write operations + (in Burst or Single mode) to different static banks. A synchronous write transfer + (in Burst or Single mode) and a synchronous read from the same or a different + bank. ...' + name: BUSTURN + - bit_offset: 28 + bit_size: 2 + description: Access mode. These bits specify the asynchronous access modes as + shown in the next timing diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is 1. + name: ACCMOD +fieldset/BWTR4: + description: This register contains the control information of each memory bank. + It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set + in the FMC_BCRx register, then this register is active for write access. + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Address setup phase duration. These bits are written by software + to define the duration of the address setup phase in KCK_FMC cycles (refer to + Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous + accesses, this value is not used, the address setup phase is always 1 Flash + clock period duration. In muxed mode, the minimum ADDSET value is 1.' + name: ADDSET + - bit_offset: 4 + bit_size: 4 + description: 'Address-hold phase duration. These bits are written by software + to define the duration of the address hold phase (refer to Figure81 to Figure93), + used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash + accesses, this value is not used, the address hold phase is always 1 Flash clock + period duration.' + name: ADDHLD + - bit_offset: 8 + bit_size: 8 + description: 'Data-phase duration. These bits are written by software to define + the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous + SRAM, PSRAM and NOR Flash memory accesses:' + name: DATAST + - bit_offset: 16 + bit_size: 4 + description: 'Bus turnaround phase duration These bits are written by software + to add a delay at the end of a write transaction to match the minimum time between + consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC + period ≥ tEHELmin. The programmed bus turnaround delay is inserted between + a an asynchronous write transfer and any other asynchronous /synchronous read + or write transfer to or from a static bank. If a read operation is performed, + the bank can be the same or a different one, whereas it must be different in + case of write operation to the bank, except in muxed mode or mode D. In some + cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed + as follows: The bus turnaround delay is not inserted between two consecutive + asynchronous write transfers to the same static memory bank except for muxed + mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: + Two consecutive synchronous write operations (in Burst or Single mode) to the + same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous + write or read transfer to or from static memory bank. There is a bus turnaround + delay of 3 FMC clock cycle between: Two consecutive synchronous write operations + (in Burst or Single mode) to different static banks. A synchronous write transfer + (in Burst or Single mode) and a synchronous read from the same or a different + bank. ...' + name: BUSTURN + - bit_offset: 28 + bit_size: 2 + description: Access mode. These bits specify the asynchronous access modes as + shown in the next timing diagrams.These bits are taken into account only when + the EXTMOD bit in the FMC_BCRx register is 1. + name: ACCMOD +fieldset/ECCR: + description: 'This register contain the current error correction code value computed + by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes + the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: + Computation of the error correction code (ECC) in NAND Flash memory), the data + read/written from/to the NAND Flash memory are processed automatically by the + ECC computation module. When X bytes have been read (according to the ECCPS field + in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC + registers. It then verifies if these computed parity data are the same as the + parity value recorded in the spare area, to determine whether a page is valid, + and, to correct it otherwise. The FMC_ECCR register should be cleared after being + read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit + must be set to 1.' + fields: + - bit_offset: 0 + bit_size: 32 + description: ECC result This field contains the value computed by the ECC computation + logic. Table167 describes the contents of these bit fields. + name: ECC +fieldset/PATT: + description: 'The FMC_PATT read/write register contains the timing information for + NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory + space of the NAND Flash for the last address write access if the timing must differ + from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: + NAND Flash prewait feature).' + fields: + - bit_offset: 0 + bit_size: 8 + description: 'Attribute memory setup time These bits define the number of KCK_FMC + (+1) clock cycles to set up address before the command assertion (NWE, NOE), + for NAND Flash read or write access to attribute memory space:' + name: ATTSET + - bit_offset: 8 + bit_size: 8 + description: 'Attribute memory wait time These bits define the minimum number + of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash + read or write access to attribute memory space. The duration for command assertion + is extended if the wait signal (NWAIT) is active (low) at the end of the programmed + value of KCK_FMC:' + name: ATTWAIT + - bit_offset: 16 + bit_size: 8 + description: 'Attribute memory hold time These bits define the number of KCK_FMC + clock cycles during which the address is held (and data for write access) after + the command de-assertion (NWE, NOE), for NAND Flash read or write access to + attribute memory space:' + name: ATTHOLD + - bit_offset: 24 + bit_size: 8 + description: 'Attribute memory data bus Hi-Z time These bits define the number + of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the + start of a NAND Flash write access to attribute memory space on socket. Only + valid for writ transaction:' + name: ATTHIZ +fieldset/PCR: + description: NAND Flash control registers + fields: + - bit_offset: 1 + bit_size: 1 + description: 'Wait feature enable bit. This bit enables the Wait feature for the + NAND Flash memory bank:' + name: PWAITEN + - bit_offset: 2 + bit_size: 1 + description: NAND Flash memory bank enable bit. This bit enables the memory bank. + Accessing a disabled memory bank causes an ERROR on AXI bus + name: PBKEN + - bit_offset: 4 + bit_size: 2 + description: Data bus width. These bits define the external memory device width. + name: PWID + - bit_offset: 6 + bit_size: 1 + description: ECC computation logic enable bit + name: ECCEN + - bit_offset: 9 + bit_size: 4 + description: 'CLE to RE delay. These bits set time from CLE low to RE low in number + of KCK_FMC clock cycles. The time is give by the following formula: t_clr = + (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set + is MEMSET or ATTSET according to the addressed space.' + name: TCLR + - bit_offset: 13 + bit_size: 4 + description: 'ALE to RE delay. These bits set time from ALE low to RE low in number + of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC + is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed + space.' + name: TAR + - bit_offset: 17 + bit_size: 3 + description: 'ECC page size. These bits define the page size for the extended + ECC:' + name: ECCPS +fieldset/PMEM: + description: The FMC_PMEM read/write register contains the timing information for + NAND Flash memory bank. This information is used to access either the common memory + space of the NAND Flash for command, address write access and data read/write + access. + fields: + - bit_offset: 0 + bit_size: 8 + description: 'Common memory x setup time These bits define the number of KCK_FMC + (+1) clock cycles to set up the address before the command assertion (NWE, NOE), + for NAND Flash read or write access to common memory space:' + name: MEMSET + - bit_offset: 8 + bit_size: 8 + description: 'Common memory wait time These bits define the minimum number of + KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read + or write access to common memory space. The duration of command assertion is + extended if the wait signal (NWAIT) is active (low) at the end of the programmed + value of KCK_FMC:' + name: MEMWAIT + - bit_offset: 16 + bit_size: 8 + description: 'Common memory hold time These bits define the number of KCK_FMC + clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses + during which the address is held (and data for write accesses) after the command + is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory + space:' + name: MEMHOLD + - bit_offset: 24 + bit_size: 8 + description: 'Common memory x data bus Hi-Z time These bits define the number + of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start + of a NAND Flash write access to common memory space. This is only valid for + write transactions:' + name: MEMHIZ +fieldset/SDCMR: + description: This register contains the command issued when the SDRAM device is + accessed. This register is used to initialize the SDRAM device, and to activate + the Self-refresh and the Power-down modes. As soon as the MODE field is written, + the command will be issued only to one or to both SDRAM banks according to CTB1 + and CTB2 command bits. This register is the same for both SDRAM banks. + fields: + - bit_offset: 0 + bit_size: 3 + description: 'Command mode These bits define the command issued to the SDRAM device. + Note: When a command is issued, at least one Command Target Bank bit ( CTB1 + or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM + banks are used, the Auto-refresh and PALL command must be issued simultaneously + to the two devices with CTB1 and CTB2 bits set otherwise the command will be + ignored. Note: If only one SDRAM bank is used and a command is issued with its + associated CTB bit set, the other CTB bit of the unused bank must be kept to + 0.' + name: MODE + - bit_offset: 3 + bit_size: 1 + description: Command Target Bank 2 This bit indicates whether the command will + be issued to SDRAM Bank 2 or not. + name: CTB2 + - bit_offset: 4 + bit_size: 1 + description: Command Target Bank 1 This bit indicates whether the command will + be issued to SDRAM Bank 1 or not. + name: CTB1 + - bit_offset: 5 + bit_size: 4 + description: Number of Auto-refresh These bits define the number of consecutive + Auto-refresh commands issued when MODE = 011. .... + name: NRFS + - bit_offset: 9 + bit_size: 14 + description: Mode Register definition This 14-bit field defines the SDRAM Mode + Register content. The Mode Register is programmed using the Load Mode Register + command. The MRD[13:0] bits are also used to program the extended mode register + for mobile SDRAM. + name: MRD +fieldset/SDCR: + description: This register contains the control parameters for each SDRAM memory + bank + fields: + - bit_offset: 0 + bit_size: 2 + description: Number of column address bits These bits define the number of bits + of a column address. + name: NC + - bit_offset: 2 + bit_size: 2 + description: Number of row address bits These bits define the number of bits of + a row address. + name: NR + - bit_offset: 4 + bit_size: 2 + description: Memory data bus width. These bits define the memory device width. + name: MWID + - bit_offset: 6 + bit_size: 1 + description: Number of internal banks This bit sets the number of internal banks. + name: NB + - bit_offset: 7 + bit_size: 2 + description: CAS Latency This bits sets the SDRAM CAS latency in number of memory + clock cycles + name: CAS + - bit_offset: 9 + bit_size: 1 + description: Write protection This bit enables write mode access to the SDRAM + bank. + name: WP + - bit_offset: 10 + bit_size: 2 + description: 'SDRAM clock configuration These bits define the SDRAM clock period + for both SDRAM banks and allow disabling the clock before changing the frequency. + In this case the SDRAM must be re-initialized. Note: The corresponding bits + in the FMC_SDCR2 register is read only.' + name: SDCLK + - bit_offset: 12 + bit_size: 1 + description: 'Burst read This bit enables burst read mode. The SDRAM controller + anticipates the next read commands during the CAS latency and stores data in + the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read + only.' + name: RBURST + - bit_offset: 13 + bit_size: 2 + description: 'Read pipe These bits define the delay, in KCK_FMC clock cycles, + for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 + register is read only.' + name: RPIPE +fieldset/SDRTR: + description: This register sets the refresh rate in number of SDCLK clock cycles + between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere + 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM + clock cycles (as in the above example) to obtain a safe margin if an internal + refresh request occurs when a read request has been accepted. It corresponds to + a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer + which is decremented using the SDRAM clock. This timer generates a refresh pulse + when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As + soon as the FMC_SDRTR register is programmed, the timer starts counting. If the + value programmed in the register is 0, no refresh is carried out. This register + must not be reprogrammed after the initialization procedure to avoid modifying + the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field + is reloaded into the counter.If a memory access is in progress, the Auto-refresh + request is delayed. However, if the memory access and Auto-refresh requests are + generated simultaneously, the Auto-refresh takes precedence. If the memory access + occurs during a refresh operation, the request is buffered to be processed when + the refresh is complete.This register is common to SDRAM bank 1 and bank 2. + fields: + - bit_offset: 0 + bit_size: 1 + description: Clear Refresh error flag This bit is used to clear the Refresh Error + Flag (RE) in the Status Register. + name: CRE + - bit_offset: 1 + bit_size: 13 + description: Refresh Timer Count This 13-bit field defines the refresh rate of + the SDRAM device. It is expressed in number of memory clock cycles. It must + be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) + x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20 + name: COUNT + - bit_offset: 14 + bit_size: 1 + description: RES Interrupt Enable + name: REIE +fieldset/SDSR: + description: SDRAM Status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Refresh error flag An interrupt is generated if REIE = 1 and RE = + 1 + name: RE + - bit_offset: 1 + bit_size: 2 + description: Status Mode for Bank 1 These bits define the Status Mode of SDRAM + Bank 1. + name: MODES1 + - bit_offset: 3 + bit_size: 2 + description: Status Mode for Bank 2 These bits define the Status Mode of SDRAM + Bank 2. + name: MODES2 +fieldset/SDTR: + description: This register contains the timing parameters of each SDRAM bank + fields: + - bit_offset: 0 + bit_size: 4 + description: Load Mode Register to Active These bits define the delay between + a Load Mode Register command and an Active or Refresh command in number of memory + clock cycles. .... + name: TMRD + - bit_offset: 4 + bit_size: 4 + description: 'Exit Self-refresh delay These bits define the delay from releasing + the Self-refresh command to issuing the Activate command in number of memory + clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 + must be programmed with the same TXSR timing corresponding to the slowest SDRAM + device.' + name: TXSR + - bit_offset: 8 + bit_size: 4 + description: Self refresh time These bits define the minimum Self-refresh period + in number of memory clock cycles. .... + name: TRAS + - bit_offset: 12 + bit_size: 4 + description: 'Row cycle delay These bits define the delay between the Refresh + command and the Activate command, as well as the delay between two consecutive + Refresh commands. It is expressed in number of memory clock cycles. The TRC + timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are + used, the TRC must be programmed with the timings of the slowest device. .... + Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined + in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 + register are dont care.' + name: TRC + - bit_offset: 16 + bit_size: 4 + description: 'Recovery delay These bits define the delay between a Write and a + Precharge command in number of memory clock cycles. .... Note: TWR must be programmed + to match the write recovery time (tWR) defined in the SDRAM datasheet, and to + guarantee that: TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP Example: + TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be programmed + to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed + with the same TWR timing corresponding to the slowest SDRAM device.' + name: TWR + - bit_offset: 20 + bit_size: 4 + description: 'Row precharge delay These bits define the delay between a Precharge + command and another command in number of memory clock cycles. The TRP timing + is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, + the TRP must be programmed with the timing of the slowest device. .... Note: + The corresponding bits in the FMC_SDTR2 register are dont care.' + name: TRP + - bit_offset: 24 + bit_size: 4 + description: Row to column delay These bits define the delay between the Activate + command and a Read/Write command in number of memory clock cycles. .... + name: TRCD +fieldset/SR: + description: This register contains information about the FIFO status and interrupt. + The FMC features a FIFO that is used when writing to memories to transfer up to + 16 words of data.This is used to quickly write to the FIFO and free the AXI bus + for transactions to peripherals other than the FMC, while the FMC is draining + its FIFO into the memory. One of these register bits indicates the status of the + FIFO, for ECC purposes.The ECC is calculated while the data are written to the + memory. To read the correct ECC, the software must consequently wait until the + FIFO is empty. + fields: + - bit_offset: 0 + bit_size: 1 + description: 'Interrupt rising edge status The flag is set by hardware and reset + by software. Note: If this bit is written by software to 1 it will be set.' + name: IRS + - bit_offset: 1 + bit_size: 1 + description: Interrupt high-level status The flag is set by hardware and reset + by software. + name: ILS + - bit_offset: 2 + bit_size: 1 + description: 'Interrupt falling edge status The flag is set by hardware and reset + by software. Note: If this bit is written by software to 1 it will be set.' + name: IFS + - bit_offset: 3 + bit_size: 1 + description: Interrupt rising edge detection enable bit + name: IREN + - bit_offset: 4 + bit_size: 1 + description: Interrupt high-level detection enable bit + name: ILEN + - bit_offset: 5 + bit_size: 1 + description: Interrupt falling edge detection enable bit + name: IFEN + - bit_offset: 6 + bit_size: 1 + description: FIFO empty. Read-only bit that provides the status of the FIFO + name: FEMPT diff --git a/stm32data/__main__.py b/stm32data/__main__.py index e4c413e..fdfa51c 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -205,6 +205,8 @@ perimap = [ ('STM32F7.*:ETH:ETH:ethermac110_v2_0', 'eth_v1c/ETH'), ('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'), + ('STM32H7.*:FMC:.*', 'fmc_h7/FMC'), + ('.*LPTIM\d.*:G0xx_lptimer1_v1_4', 'lptim_g0/LPTIM'), ('STM32H7.*:TIM1:.*', 'timer_v1/TIM_ADV'), @@ -279,6 +281,7 @@ alt_peri_defines = { 'FLASH': ['FLASH_R_BASE'], 'ADC_COMMON': ['ADC_COMMON', 'ADC1_COMMON', 'ADC12_COMMON', 'ADC123_COMMON'], 'CAN': ['CAN_BASE', 'CAN1_BASE'], + 'FMC': ['FMC_BASE', 'FMC_R_BASE'] } # Device address overrides, in case of missing from headers