From 3dd39de9461995f473eeef467c15894e89658831 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Wed, 20 Apr 2022 13:49:09 +0200 Subject: [PATCH 1/4] Add flash for stm32wl --- data/registers/flash_wl55.yaml | 559 +++++++++++++++++++++++++++++++++ stm32data/__main__.py | 1 + 2 files changed, 560 insertions(+) create mode 100644 data/registers/flash_wl55.yaml diff --git a/data/registers/flash_wl55.yaml b/data/registers/flash_wl55.yaml new file mode 100644 index 0000000..da253b4 --- /dev/null +++ b/data/registers/flash_wl55.yaml @@ -0,0 +1,559 @@ +--- +block/FLASH: + description: Flash + items: + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: KEYR + description: Flash key register + byte_offset: 8 + access: Write + fieldset: KEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 12 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 16 + fieldset: SR + - name: CR + description: Flash control register + byte_offset: 20 + fieldset: CR + - name: ECCR + description: Flash ECC register + byte_offset: 24 + fieldset: ECCR + - name: OPTR + description: Flash option register + byte_offset: 32 + fieldset: OPTR + - name: PCROP1ASR + description: Flash Bank 1 PCROP Start address zone A register + byte_offset: 36 + fieldset: PCROP1ASR + - name: PCROP1AER + description: Flash Bank 1 PCROP End address zone A register + byte_offset: 40 + fieldset: PCROP1AER + - name: WRP1AR + description: Flash Bank 1 WRP area A address register + byte_offset: 44 + fieldset: WRP1AR + - name: WRP1BR + description: Flash Bank 1 WRP area B address register + byte_offset: 48 + fieldset: WRP1BR + - name: PCROP1BSR + description: Flash Bank 1 PCROP Start address area B register + byte_offset: 52 + fieldset: PCROP1BSR + - name: PCROP1BER + description: Flash Bank 1 PCROP End address area B register + byte_offset: 56 + fieldset: PCROP1BER + - name: IPCCBR + description: IPCC mailbox data buffer address register + byte_offset: 60 + fieldset: IPCCBR + - name: C2ACR + description: CPU2 cortex M0 access control register + byte_offset: 92 + fieldset: C2ACR + - name: C2SR + description: CPU2 cortex M0 status register + byte_offset: 96 + fieldset: C2SR + - name: C2CR + description: CPU2 cortex M0 control register + byte_offset: 100 + fieldset: C2CR + - name: SFR + description: Secure flash start address register + byte_offset: 128 + fieldset: SFR + - name: SRRVR + description: Secure SRAM2 start address and cortex M0 reset vector register + byte_offset: 132 + fieldset: SRRVR +fieldset/ACR: + description: Access control register + fields: + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 3 + - name: PRFTEN + description: Prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: Instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: DCEN + description: Data cache enable + bit_offset: 10 + bit_size: 1 + - name: ICRST + description: Instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: DCRST + description: Data cache reset + bit_offset: 12 + bit_size: 1 + - name: PES + description: CPU1 CortexM4 program erase suspend request + bit_offset: 15 + bit_size: 1 + - name: EMPTY + description: Flash User area empty + bit_offset: 16 + bit_size: 1 +fieldset/C2ACR: + description: CPU2 cortex M0 access control register + fields: + - name: PRFTEN + description: CPU2 cortex M0 prefetch enable + bit_offset: 8 + bit_size: 1 + - name: ICEN + description: CPU2 cortex M0 instruction cache enable + bit_offset: 9 + bit_size: 1 + - name: ICRST + description: CPU2 cortex M0 instruction cache reset + bit_offset: 11 + bit_size: 1 + - name: PES + description: CPU2 cortex M0 program erase suspend request + bit_offset: 15 + bit_size: 1 +fieldset/C2CR: + description: CPU2 cortex M0 control register + fields: + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: Masse erase + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page Number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 +fieldset/C2SR: + description: CPU2 cortex M0 status register + fields: + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: write protection error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISSERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 +fieldset/CR: + description: Flash control register + fields: + - name: PG + description: Programming + bit_offset: 0 + bit_size: 1 + - name: PER + description: Page erase + bit_offset: 1 + bit_size: 1 + - name: MER + description: This bit triggers the mass erase (all user pages) when set + bit_offset: 2 + bit_size: 1 + - name: PNB + description: Page number selection + bit_offset: 3 + bit_size: 8 + - name: STRT + description: Start + bit_offset: 16 + bit_size: 1 + - name: OPTSTRT + description: Options modification start + bit_offset: 17 + bit_size: 1 + - name: FSTPG + description: Fast programming + bit_offset: 18 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable + bit_offset: 24 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable + bit_offset: 25 + bit_size: 1 + - name: RDERRIE + description: PCROP read error interrupt enable + bit_offset: 26 + bit_size: 1 + - name: OBL_LAUNCH + description: Force the option byte loading + bit_offset: 27 + bit_size: 1 + - name: OPTLOCK + description: Options Lock + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: FLASH_CR Lock + bit_offset: 31 + bit_size: 1 +fieldset/ECCR: + description: Flash ECC register + fields: + - name: ADDR_ECC + description: ECC fail address + bit_offset: 0 + bit_size: 17 + - name: SYSF_ECC + description: System Flash ECC fail + bit_offset: 20 + bit_size: 1 + - name: ECCCIE + description: ECC correction interrupt enable + bit_offset: 24 + bit_size: 1 + - name: CPUID + description: CPU identification + bit_offset: 26 + bit_size: 3 + - name: ECCC + description: ECC correction + bit_offset: 30 + bit_size: 1 + - name: ECCD + description: ECC detection + bit_offset: 31 + bit_size: 1 +fieldset/IPCCBR: + description: IPCC mailbox data buffer address register + fields: + - name: IPCCDBA + description: PCC mailbox data buffer base address + bit_offset: 0 + bit_size: 14 +fieldset/KEYR: + description: Flash key register + fields: + - name: KEYR + description: KEYR + bit_offset: 0 + bit_size: 32 +fieldset/OPTKEYR: + description: Option byte key register + fields: + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: Flash option register + fields: + - name: RDP + description: Read protection level + bit_offset: 0 + bit_size: 8 + - name: ESE + description: Security enabled + bit_offset: 8 + bit_size: 1 + - name: BOR_LEV + description: BOR reset Level + bit_offset: 9 + bit_size: 3 + - name: nRST_STOP + description: nRST_STOP + bit_offset: 12 + bit_size: 1 + - name: nRST_STDBY + description: nRST_STDBY + bit_offset: 13 + bit_size: 1 + - name: nRST_SHDW + description: nRST_SHDW + bit_offset: 14 + bit_size: 1 + - name: IDWG_SW + description: Independent watchdog selection + bit_offset: 16 + bit_size: 1 + - name: IWDG_STOP + description: Independent watchdog counter freeze in Stop mode + bit_offset: 17 + bit_size: 1 + - name: IWDG_STDBY + description: Independent watchdog counter freeze in Standby mode + bit_offset: 18 + bit_size: 1 + - name: WWDG_SW + description: Window watchdog selection + bit_offset: 19 + bit_size: 1 + - name: nBOOT1 + description: Boot configuration + bit_offset: 23 + bit_size: 1 + - name: SRAM2_PE + description: SRAM2 parity check enable + bit_offset: 24 + bit_size: 1 + - name: SRAM2_RST + description: SRAM2 Erase when system reset + bit_offset: 25 + bit_size: 1 + - name: nSWBOOT0 + description: Software Boot0 + bit_offset: 26 + bit_size: 1 + - name: nBOOT0 + description: nBoot0 option bit + bit_offset: 27 + bit_size: 1 + - name: AGC_TRIM + description: Radio Automatic Gain Control Trimming + bit_offset: 29 + bit_size: 3 +fieldset/PCROP1AER: + description: Flash Bank 1 PCROP End address zone A register + fields: + - name: PCROP1A_END + description: Bank 1 PCROP area end offset + bit_offset: 0 + bit_size: 9 + - name: PCROP_RDP + description: PCROP area preserved when RDP level decreased + bit_offset: 31 + bit_size: 1 +fieldset/PCROP1ASR: + description: Flash Bank 1 PCROP Start address zone A register + fields: + - name: PCROP1A_STRT + description: Bank 1 PCROPQ area start offset + bit_offset: 0 + bit_size: 9 +fieldset/PCROP1BER: + description: Flash Bank 1 PCROP End address area B register + fields: + - name: PCROP1B_END + description: Bank 1 PCROP area end area B offset + bit_offset: 0 + bit_size: 9 +fieldset/PCROP1BSR: + description: Flash Bank 1 PCROP Start address area B register + fields: + - name: PCROP1B_STRT + description: Bank 1 PCROP area B start offset + bit_offset: 0 + bit_size: 9 +fieldset/SFR: + description: Secure flash start address register + fields: + - name: SFSA + description: Secure flash start address + bit_offset: 0 + bit_size: 8 + - name: FSD + description: Flash security disable + bit_offset: 8 + bit_size: 1 + - name: DDS + description: Disable Cortex M0 debug access + bit_offset: 12 + bit_size: 1 +fieldset/SR: + description: Status register + fields: + - name: EOP + description: End of operation + bit_offset: 0 + bit_size: 1 + - name: OPERR + description: Operation error + bit_offset: 1 + bit_size: 1 + - name: PROGERR + description: Programming error + bit_offset: 3 + bit_size: 1 + - name: WRPERR + description: Write protected error + bit_offset: 4 + bit_size: 1 + - name: PGAERR + description: Programming alignment error + bit_offset: 5 + bit_size: 1 + - name: SIZERR + description: Size error + bit_offset: 6 + bit_size: 1 + - name: PGSERR + description: Programming sequence error + bit_offset: 7 + bit_size: 1 + - name: MISERR + description: Fast programming data miss error + bit_offset: 8 + bit_size: 1 + - name: FASTERR + description: Fast programming error + bit_offset: 9 + bit_size: 1 + - name: OPTNV + description: User Option OPTVAL indication + bit_offset: 13 + bit_size: 1 + - name: RDERR + description: PCROP read error + bit_offset: 14 + bit_size: 1 + - name: OPTVERR + description: Option validity error + bit_offset: 15 + bit_size: 1 + - name: BSY + description: Busy + bit_offset: 16 + bit_size: 1 + - name: CFGBSY + description: Programming or erase configuration busy + bit_offset: 18 + bit_size: 1 + - name: PESD + description: Programming or erase operation suspended + bit_offset: 19 + bit_size: 1 +fieldset/SRRVR: + description: Secure SRAM2 start address and cortex M0 reset vector register + fields: + - name: SBRV + description: cortex M0 access control register + bit_offset: 0 + bit_size: 18 + - name: SBRSA + description: Secure backup SRAM2a start address + bit_offset: 18 + bit_size: 5 + - name: BRSD + description: backup SRAM2a security disable + bit_offset: 23 + bit_size: 1 + - name: SNBRSA + description: Secure non backup SRAM2a start address + bit_offset: 25 + bit_size: 5 + - name: NBRSD + description: non-backup SRAM2b security disable + bit_offset: 30 + bit_size: 1 + - name: C2OPT + description: CPU2 cortex M0 boot reset vector memory selection + bit_offset: 31 + bit_size: 1 +fieldset/WRP1AR: + description: Flash Bank 1 WRP area A address register + fields: + - name: WRP1A_STRT + description: Bank 1 WRP first area A start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1A_END + description: Bank 1 WRP first area A end offset + bit_offset: 16 + bit_size: 8 +fieldset/WRP1BR: + description: Flash Bank 1 WRP area B address register + fields: + - name: WRP1B_END + description: Bank 1 WRP second area B start offset + bit_offset: 0 + bit_size: 8 + - name: WRP1B_STRT + description: Bank 1 WRP second area B end offset + bit_offset: 16 + bit_size: 8 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 0e5a878..e38f745 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -229,6 +229,7 @@ perimap = [ ('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')), ('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')), ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), + ('STM32WL.*:FLASH:.*', ('flash', 'wl55', 'FLASH')), ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')), ('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')), ('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')), From 004542bf86fd8a91c78d6193433e730af7f578b9 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Fri, 22 Apr 2022 09:39:42 +0200 Subject: [PATCH 2/4] Add l0 flash support --- data/registers/flash_l0.yaml | 630 +++++++++++++++++++++++++++++++++++ stm32data/__main__.py | 1 + 2 files changed, 631 insertions(+) create mode 100644 data/registers/flash_l0.yaml diff --git a/data/registers/flash_l0.yaml b/data/registers/flash_l0.yaml new file mode 100644 index 0000000..774a776 --- /dev/null +++ b/data/registers/flash_l0.yaml @@ -0,0 +1,630 @@ +--- +block/FLASH: + description: Flash + items: + - name: ACR + description: Access control register + byte_offset: 0 + fieldset: ACR + - name: PECR + description: Program/erase control register + byte_offset: 4 + fieldset: PECR + - name: PDKEYR + description: Power down key register + byte_offset: 8 + access: Write + fieldset: PDKEYR + - name: PEKEYR + description: Program/erase key register + byte_offset: 12 + access: Write + fieldset: PEKEYR + - name: PRGKEYR + description: Program memory key register + byte_offset: 16 + access: Write + fieldset: PRGKEYR + - name: OPTKEYR + description: Option byte key register + byte_offset: 20 + access: Write + fieldset: OPTKEYR + - name: SR + description: Status register + byte_offset: 24 + fieldset: SR + - name: OPTR + description: Option byte register + byte_offset: 28 + access: Read + fieldset: OPTR + - name: WRPROT1 + description: Write Protection Register 1 + byte_offset: 32 + access: Read + fieldset: WRPROT1 + - name: WRPROT2 + description: Write Protection Register 2 + byte_offset: 128 + access: Read + fieldset: WRPROT2 +fieldset/ACR: + description: Access control register + fields: + - name: LATENCY + description: Latency + bit_offset: 0 + bit_size: 1 + enum: LATENCY + - name: PRFTEN + description: Prefetch enable + bit_offset: 1 + bit_size: 1 + enum: PRFTEN + - name: SLEEP_PD + description: Flash mode during Sleep + bit_offset: 3 + bit_size: 1 + enum: SLEEP_PD + - name: RUN_PD + description: Flash mode during Run + bit_offset: 4 + bit_size: 1 + enum: RUN_PD + - name: DISAB_BUF + description: Disable Buffer + bit_offset: 5 + bit_size: 1 + enum: DISAB_BUF + - name: PRE_READ + description: Pre-read data address + bit_offset: 6 + bit_size: 1 + enum: PRE_READ +fieldset/OPTKEYR: + description: Option byte key register + fields: + - name: OPTKEYR + description: Option byte key + bit_offset: 0 + bit_size: 32 +fieldset/OPTR: + description: Option byte register + fields: + - name: RDPROT + description: Read protection + bit_offset: 0 + bit_size: 8 + enum: RDPROT + - name: WPRMOD + description: Selection of protection mode of WPR bits + bit_offset: 8 + bit_size: 1 + enum: WPRMOD + - name: BOR_LEV + description: BOR_LEV + bit_offset: 16 + bit_size: 4 + enum: BOR_LEV +fieldset/PDKEYR: + description: Power down key register + fields: + - name: PDKEYR + description: RUN_PD in FLASH_ACR key + bit_offset: 0 + bit_size: 32 +fieldset/PECR: + description: Program/erase control register + fields: + - name: PELOCK + description: FLASH_PECR and data EEPROM lock + bit_offset: 0 + bit_size: 1 + enum: PELOCK + - name: PRGLOCK + description: Program memory lock + bit_offset: 1 + bit_size: 1 + enum: PRGLOCK + - name: OPTLOCK + description: Option bytes block lock + bit_offset: 2 + bit_size: 1 + enum: OPTLOCK + - name: PROG + description: Program memory selection + bit_offset: 3 + bit_size: 1 + enum: PROG + - name: DATA + description: Data EEPROM selection + bit_offset: 4 + bit_size: 1 + enum: DATA + - name: FIX + description: "Fixed time data write for Byte, Half Word and Word programming" + bit_offset: 8 + bit_size: 1 + enum: FIX + - name: ERASE + description: Page or Double Word erase mode + bit_offset: 9 + bit_size: 1 + enum: ERASE + - name: FPRG + description: Half Page/Double Word programming mode + bit_offset: 10 + bit_size: 1 + enum: FPRG + - name: PARALLELBANK + description: Parallel bank mode + bit_offset: 15 + bit_size: 1 + enum: PARALLELBANK + - name: EOPIE + description: End of programming interrupt enable + bit_offset: 16 + bit_size: 1 + enum: EOPIE + - name: ERRIE + description: Error interrupt enable + bit_offset: 17 + bit_size: 1 + enum: ERRIE + - name: OBL_LAUNCH + description: Launch the option byte loading + bit_offset: 18 + bit_size: 1 + enum_read: OBL_LAUNCHR + enum_write: OBL_LAUNCHW +fieldset/PEKEYR: + description: Program/erase key register + fields: + - name: PEKEYR + description: FLASH_PEC and data EEPROM key + bit_offset: 0 + bit_size: 32 +fieldset/PRGKEYR: + description: Program memory key register + fields: + - name: PRGKEYR + description: Program memory key + bit_offset: 0 + bit_size: 32 +fieldset/SR: + description: Status register + fields: + - name: BSY + description: Write/erase operations in progress + bit_offset: 0 + bit_size: 1 + enum: BSY + - name: EOP + description: End of operation + bit_offset: 1 + bit_size: 1 + enum: EOP + - name: ENDHV + description: End of high voltage + bit_offset: 2 + bit_size: 1 + enum: ENDHV + - name: READY + description: Flash memory module ready after low power mode + bit_offset: 3 + bit_size: 1 + enum: READY + - name: WRPERR + description: Write protected error + bit_offset: 8 + bit_size: 1 + enum_read: WRPERRR + enum_write: WRPERRW + - name: PGAERR + description: Programming alignment error + bit_offset: 9 + bit_size: 1 + enum_read: PGAERRR + enum_write: PGAERRW + - name: SIZERR + description: Size error + bit_offset: 10 + bit_size: 1 + enum_read: SIZERRR + enum_write: SIZERRW + - name: OPTVERR + description: Option validity error + bit_offset: 11 + bit_size: 1 + enum_read: OPTVERRR + enum_write: OPTVERRW + - name: RDERR + description: RDERR + bit_offset: 14 + bit_size: 1 + enum_read: RDERRR + enum_write: RDERRW + - name: NOTZEROERR + description: NOTZEROERR + bit_offset: 16 + bit_size: 1 + enum_read: NOTZEROERRR + enum_write: NOTZEROERRW + - name: FWWERR + description: FWWERR + bit_offset: 17 + bit_size: 1 + enum_read: FWWERRR + enum_write: FWWERRW +fieldset/WRPROT1: + description: Write Protection Register 1 + fields: + - name: WRPROT + description: Write Protection + bit_offset: 0 + bit_size: 32 + array: + len: 1 + stride: 0 +fieldset/WRPROT2: + description: Write Protection Register 2 + fields: + - name: WRPROT + description: Write Protection + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 +enum/BOR_LEV: + bit_size: 4 + variants: + - name: BOR_Off + description: This is the reset threshold level for the 1.45 V - 1.55 V voltage range (power-down only) + value: 0 + - name: BOR_Level1 + description: Reset threshold level for VBOR0 (around 1.8 V) + value: 1 + - name: BOR_Level2 + description: Reset threshold level for VBOR1 (around 2.0 V) + value: 2 + - name: BOR_Level3 + description: Reset threshold level for VBOR2 (around 2.5 V) + value: 3 + - name: BOR_Level4 + description: Reset threshold level for VBOR3 (around 2.7 V) + value: 4 + - name: BOR_Level5 + description: Reset threshold level for VBOR4 (around 3.0 V) + value: 5 +enum/BSY: + bit_size: 1 + variants: + - name: Inactive + description: No write/erase operation is in progress + value: 0 + - name: Active + description: No write/erase operation is in progress + value: 1 +enum/DATA: + bit_size: 1 + variants: + - name: NotSelected + description: Data EEPROM not selected + value: 0 + - name: Selected + description: Data memory selected + value: 1 +enum/DISAB_BUF: + bit_size: 1 + variants: + - name: Enabled + description: The buffers are enabled + value: 0 + - name: Disabled + description: The buffers are disabled + value: 1 +enum/ENDHV: + bit_size: 1 + variants: + - name: Active + description: High voltage is executing a write/erase operation in the NVM + value: 0 + - name: Inactive + description: "High voltage is off, no write/erase operation is ongoing" + value: 1 +enum/EOP: + bit_size: 1 + variants: + - name: NoEvent + description: No EOP operation occurred + value: 0 + - name: Event + description: An EOP event occurred + value: 1 +enum/EOPIE: + bit_size: 1 + variants: + - name: Disabled + description: End of program interrupt disable + value: 0 + - name: Enabled + description: End of program interrupt enable + value: 1 +enum/ERASE: + bit_size: 1 + variants: + - name: NoErase + description: No erase operation requested + value: 0 + - name: Erase + description: Erase operation requested + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - name: Disabled + description: Error interrupt disable + value: 0 + - name: Enabled + description: Error interrupt enable + value: 1 +enum/FIX: + bit_size: 1 + variants: + - name: AutoErase + description: An erase phase is automatically performed + value: 0 + - name: PrelimErase + description: The program operation is always performed with a preliminary erase + value: 1 +enum/FPRG: + bit_size: 1 + variants: + - name: Disabled + description: Half Page programming disabled + value: 0 + - name: Enabled + description: Half Page programming enabled + value: 1 +enum/FWWERRR: + bit_size: 1 + variants: + - name: NoError + description: No write/erase operation aborted to perform a fetch + value: 0 + - name: Error + description: A write/erase operation aborted to perform a fetch + value: 1 +enum/FWWERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/LATENCY: + bit_size: 1 + variants: + - name: WS0 + description: Zero wait state is used to read a word in the NVM + value: 0 + - name: WS1 + description: One wait state is used to read a word in the NVM + value: 1 +enum/NOTZEROERRR: + bit_size: 1 + variants: + - name: NoEvent + description: The write operation is done in an erased region or the memory interface can apply an erase before a write + value: 0 + - name: Event + description: The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write + value: 1 +enum/NOTZEROERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/OBL_LAUNCHR: + bit_size: 1 + variants: + - name: Complete + description: Option byte loaded + value: 0 + - name: NotComplete + description: Option byte loading to be done + value: 1 +enum/OBL_LAUNCHW: + bit_size: 1 + variants: + - name: Reload + description: Reload option byte + value: 1 +enum/OPTLOCK: + bit_size: 1 + variants: + - name: Unlocked + description: The write and erase operations in the Option bytes area are disabled + value: 0 + - name: Locked + description: The write and erase operations in the Option bytes area are enabled + value: 1 +enum/OPTVERRR: + bit_size: 1 + variants: + - name: NoError + description: No error happened during the Option bytes loading + value: 0 + - name: Error + description: One or more errors happened during the Option bytes loading + value: 1 +enum/OPTVERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/PARALLELBANK: + bit_size: 1 + variants: + - name: Disabled + description: Parallel bank mode disabled + value: 0 + - name: Enabled + description: Parallel bank mode enabled + value: 1 +enum/PELOCK: + bit_size: 1 + variants: + - name: Unlocked + description: The FLASH_PECR register is unlocked + value: 0 + - name: Locked + description: The FLASH_PECR register is locked and no write/erase operation can start + value: 1 +enum/PGAERRR: + bit_size: 1 + variants: + - name: NoError + description: No alignment error happened + value: 0 + - name: Error + description: One alignment error happened + value: 1 +enum/PGAERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/PRE_READ: + bit_size: 1 + variants: + - name: Disabled + description: The pre-read is disabled + value: 0 + - name: Enabled + description: The pre-read is enabled + value: 1 +enum/PRFTEN: + bit_size: 1 + variants: + - name: Disabled + description: Prefetch is disabled + value: 0 + - name: Enabled + description: Prefetch is enabled + value: 1 +enum/PRGLOCK: + bit_size: 1 + variants: + - name: Unlocked + description: The write and erase operations in the Flash program memory are disabled + value: 0 + - name: Locked + description: The write and erase operations in the Flash program memory are enabled + value: 1 +enum/PROG: + bit_size: 1 + variants: + - name: NotSelected + description: The Flash program memory is not selected + value: 0 + - name: Selected + description: The Flash program memory is selected + value: 1 +enum/RDERRR: + bit_size: 1 + variants: + - name: NoError + description: No read protection error happened. + value: 0 + - name: Error + description: One read protection error happened + value: 1 +enum/RDERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/RDPROT: + bit_size: 8 + variants: + - name: Level1 + description: Level 1 + value: 0 + - name: Level0 + description: Level 0 + value: 170 + - name: Level2 + description: Level 2 + value: 204 +enum/READY: + bit_size: 1 + variants: + - name: NotReady + description: The NVM is not ready + value: 0 + - name: Ready + description: The NVM is ready + value: 1 +enum/RUN_PD: + bit_size: 1 + variants: + - name: NVMIdleMode + description: "When the device is in Run mode, the NVM is in Idle mode" + value: 0 + - name: NVMPwrDownMode + description: "When the device is in Run mode, the NVM is in power-down mode" + value: 1 +enum/SIZERRR: + bit_size: 1 + variants: + - name: NoError + description: No size error happened + value: 0 + - name: Error + description: One size error happened + value: 1 +enum/SIZERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 +enum/SLEEP_PD: + bit_size: 1 + variants: + - name: NVMIdleMode + description: "When the device is in Sleep mode, the NVM is in Idle mode" + value: 0 + - name: NVMPwrDownMode + description: "When the device is in Sleep mode, the NVM is in power-down mode" + value: 1 +enum/WPRMOD: + bit_size: 1 + variants: + - name: Disabled + description: PCROP disabled. The WRPROT bits are used as a write protection on a sector. + value: 0 + - name: Enabled + description: PCROP enabled. The WRPROT bits are used as a read protection on a sector. + value: 1 +enum/WRPERRR: + bit_size: 1 + variants: + - name: NoError + description: No protection error happened + value: 0 + - name: Error + description: One protection error happened + value: 1 +enum/WRPERRW: + bit_size: 1 + variants: + - name: Clear + description: Clear the flag + value: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index e38f745..f6414fb 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -224,6 +224,7 @@ perimap = [ ('STM32F3.*:FLASH:.*', ('flash', 'f3', 'FLASH')), ('STM32F4.*:FLASH:.*', ('flash', 'f4', 'FLASH')), ('STM32F7.*:FLASH:.*', ('flash', 'f7', 'FLASH')), + ('STM32L0[0-9]2.*:FLASH:.*', ('flash', 'l0', 'FLASH')), ('STM32L1.*:FLASH:.*', ('flash', 'l1', 'FLASH')), ('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')), ('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')), From 83544cfdfcdcc2d6546d0db4238145ac6ca22d7a Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 26 Apr 2022 14:53:40 +0200 Subject: [PATCH 3/4] Remove enums from l0 regs --- data/registers/flash_l0.yaml | 390 ----------------------------------- 1 file changed, 390 deletions(-) diff --git a/data/registers/flash_l0.yaml b/data/registers/flash_l0.yaml index 774a776..aa1b7d9 100644 --- a/data/registers/flash_l0.yaml +++ b/data/registers/flash_l0.yaml @@ -56,32 +56,26 @@ fieldset/ACR: description: Latency bit_offset: 0 bit_size: 1 - enum: LATENCY - name: PRFTEN description: Prefetch enable bit_offset: 1 bit_size: 1 - enum: PRFTEN - name: SLEEP_PD description: Flash mode during Sleep bit_offset: 3 bit_size: 1 - enum: SLEEP_PD - name: RUN_PD description: Flash mode during Run bit_offset: 4 bit_size: 1 - enum: RUN_PD - name: DISAB_BUF description: Disable Buffer bit_offset: 5 bit_size: 1 - enum: DISAB_BUF - name: PRE_READ description: Pre-read data address bit_offset: 6 bit_size: 1 - enum: PRE_READ fieldset/OPTKEYR: description: Option byte key register fields: @@ -96,17 +90,14 @@ fieldset/OPTR: description: Read protection bit_offset: 0 bit_size: 8 - enum: RDPROT - name: WPRMOD description: Selection of protection mode of WPR bits bit_offset: 8 bit_size: 1 - enum: WPRMOD - name: BOR_LEV description: BOR_LEV bit_offset: 16 bit_size: 4 - enum: BOR_LEV fieldset/PDKEYR: description: Power down key register fields: @@ -121,62 +112,50 @@ fieldset/PECR: description: FLASH_PECR and data EEPROM lock bit_offset: 0 bit_size: 1 - enum: PELOCK - name: PRGLOCK description: Program memory lock bit_offset: 1 bit_size: 1 - enum: PRGLOCK - name: OPTLOCK description: Option bytes block lock bit_offset: 2 bit_size: 1 - enum: OPTLOCK - name: PROG description: Program memory selection bit_offset: 3 bit_size: 1 - enum: PROG - name: DATA description: Data EEPROM selection bit_offset: 4 bit_size: 1 - enum: DATA - name: FIX description: "Fixed time data write for Byte, Half Word and Word programming" bit_offset: 8 bit_size: 1 - enum: FIX - name: ERASE description: Page or Double Word erase mode bit_offset: 9 bit_size: 1 - enum: ERASE - name: FPRG description: Half Page/Double Word programming mode bit_offset: 10 bit_size: 1 - enum: FPRG - name: PARALLELBANK description: Parallel bank mode bit_offset: 15 bit_size: 1 - enum: PARALLELBANK - name: EOPIE description: End of programming interrupt enable bit_offset: 16 bit_size: 1 - enum: EOPIE - name: ERRIE description: Error interrupt enable bit_offset: 17 bit_size: 1 - enum: ERRIE - name: OBL_LAUNCH description: Launch the option byte loading bit_offset: 18 bit_size: 1 - enum_read: OBL_LAUNCHR enum_write: OBL_LAUNCHW fieldset/PEKEYR: description: Program/erase key register @@ -199,64 +178,46 @@ fieldset/SR: description: Write/erase operations in progress bit_offset: 0 bit_size: 1 - enum: BSY - name: EOP description: End of operation bit_offset: 1 bit_size: 1 - enum: EOP - name: ENDHV description: End of high voltage bit_offset: 2 bit_size: 1 - enum: ENDHV - name: READY description: Flash memory module ready after low power mode bit_offset: 3 bit_size: 1 - enum: READY - name: WRPERR description: Write protected error bit_offset: 8 bit_size: 1 - enum_read: WRPERRR - enum_write: WRPERRW - name: PGAERR description: Programming alignment error bit_offset: 9 bit_size: 1 - enum_read: PGAERRR - enum_write: PGAERRW - name: SIZERR description: Size error bit_offset: 10 bit_size: 1 - enum_read: SIZERRR - enum_write: SIZERRW - name: OPTVERR description: Option validity error bit_offset: 11 bit_size: 1 - enum_read: OPTVERRR - enum_write: OPTVERRW - name: RDERR description: RDERR bit_offset: 14 bit_size: 1 - enum_read: RDERRR - enum_write: RDERRW - name: NOTZEROERR description: NOTZEROERR bit_offset: 16 bit_size: 1 - enum_read: NOTZEROERRR - enum_write: NOTZEROERRW - name: FWWERR description: FWWERR bit_offset: 17 bit_size: 1 - enum_read: FWWERRR - enum_write: FWWERRW fieldset/WRPROT1: description: Write Protection Register 1 fields: @@ -277,354 +238,3 @@ fieldset/WRPROT2: array: len: 1 stride: 0 -enum/BOR_LEV: - bit_size: 4 - variants: - - name: BOR_Off - description: This is the reset threshold level for the 1.45 V - 1.55 V voltage range (power-down only) - value: 0 - - name: BOR_Level1 - description: Reset threshold level for VBOR0 (around 1.8 V) - value: 1 - - name: BOR_Level2 - description: Reset threshold level for VBOR1 (around 2.0 V) - value: 2 - - name: BOR_Level3 - description: Reset threshold level for VBOR2 (around 2.5 V) - value: 3 - - name: BOR_Level4 - description: Reset threshold level for VBOR3 (around 2.7 V) - value: 4 - - name: BOR_Level5 - description: Reset threshold level for VBOR4 (around 3.0 V) - value: 5 -enum/BSY: - bit_size: 1 - variants: - - name: Inactive - description: No write/erase operation is in progress - value: 0 - - name: Active - description: No write/erase operation is in progress - value: 1 -enum/DATA: - bit_size: 1 - variants: - - name: NotSelected - description: Data EEPROM not selected - value: 0 - - name: Selected - description: Data memory selected - value: 1 -enum/DISAB_BUF: - bit_size: 1 - variants: - - name: Enabled - description: The buffers are enabled - value: 0 - - name: Disabled - description: The buffers are disabled - value: 1 -enum/ENDHV: - bit_size: 1 - variants: - - name: Active - description: High voltage is executing a write/erase operation in the NVM - value: 0 - - name: Inactive - description: "High voltage is off, no write/erase operation is ongoing" - value: 1 -enum/EOP: - bit_size: 1 - variants: - - name: NoEvent - description: No EOP operation occurred - value: 0 - - name: Event - description: An EOP event occurred - value: 1 -enum/EOPIE: - bit_size: 1 - variants: - - name: Disabled - description: End of program interrupt disable - value: 0 - - name: Enabled - description: End of program interrupt enable - value: 1 -enum/ERASE: - bit_size: 1 - variants: - - name: NoErase - description: No erase operation requested - value: 0 - - name: Erase - description: Erase operation requested - value: 1 -enum/ERRIE: - bit_size: 1 - variants: - - name: Disabled - description: Error interrupt disable - value: 0 - - name: Enabled - description: Error interrupt enable - value: 1 -enum/FIX: - bit_size: 1 - variants: - - name: AutoErase - description: An erase phase is automatically performed - value: 0 - - name: PrelimErase - description: The program operation is always performed with a preliminary erase - value: 1 -enum/FPRG: - bit_size: 1 - variants: - - name: Disabled - description: Half Page programming disabled - value: 0 - - name: Enabled - description: Half Page programming enabled - value: 1 -enum/FWWERRR: - bit_size: 1 - variants: - - name: NoError - description: No write/erase operation aborted to perform a fetch - value: 0 - - name: Error - description: A write/erase operation aborted to perform a fetch - value: 1 -enum/FWWERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/LATENCY: - bit_size: 1 - variants: - - name: WS0 - description: Zero wait state is used to read a word in the NVM - value: 0 - - name: WS1 - description: One wait state is used to read a word in the NVM - value: 1 -enum/NOTZEROERRR: - bit_size: 1 - variants: - - name: NoEvent - description: The write operation is done in an erased region or the memory interface can apply an erase before a write - value: 0 - - name: Event - description: The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write - value: 1 -enum/NOTZEROERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/OBL_LAUNCHR: - bit_size: 1 - variants: - - name: Complete - description: Option byte loaded - value: 0 - - name: NotComplete - description: Option byte loading to be done - value: 1 -enum/OBL_LAUNCHW: - bit_size: 1 - variants: - - name: Reload - description: Reload option byte - value: 1 -enum/OPTLOCK: - bit_size: 1 - variants: - - name: Unlocked - description: The write and erase operations in the Option bytes area are disabled - value: 0 - - name: Locked - description: The write and erase operations in the Option bytes area are enabled - value: 1 -enum/OPTVERRR: - bit_size: 1 - variants: - - name: NoError - description: No error happened during the Option bytes loading - value: 0 - - name: Error - description: One or more errors happened during the Option bytes loading - value: 1 -enum/OPTVERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/PARALLELBANK: - bit_size: 1 - variants: - - name: Disabled - description: Parallel bank mode disabled - value: 0 - - name: Enabled - description: Parallel bank mode enabled - value: 1 -enum/PELOCK: - bit_size: 1 - variants: - - name: Unlocked - description: The FLASH_PECR register is unlocked - value: 0 - - name: Locked - description: The FLASH_PECR register is locked and no write/erase operation can start - value: 1 -enum/PGAERRR: - bit_size: 1 - variants: - - name: NoError - description: No alignment error happened - value: 0 - - name: Error - description: One alignment error happened - value: 1 -enum/PGAERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/PRE_READ: - bit_size: 1 - variants: - - name: Disabled - description: The pre-read is disabled - value: 0 - - name: Enabled - description: The pre-read is enabled - value: 1 -enum/PRFTEN: - bit_size: 1 - variants: - - name: Disabled - description: Prefetch is disabled - value: 0 - - name: Enabled - description: Prefetch is enabled - value: 1 -enum/PRGLOCK: - bit_size: 1 - variants: - - name: Unlocked - description: The write and erase operations in the Flash program memory are disabled - value: 0 - - name: Locked - description: The write and erase operations in the Flash program memory are enabled - value: 1 -enum/PROG: - bit_size: 1 - variants: - - name: NotSelected - description: The Flash program memory is not selected - value: 0 - - name: Selected - description: The Flash program memory is selected - value: 1 -enum/RDERRR: - bit_size: 1 - variants: - - name: NoError - description: No read protection error happened. - value: 0 - - name: Error - description: One read protection error happened - value: 1 -enum/RDERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/RDPROT: - bit_size: 8 - variants: - - name: Level1 - description: Level 1 - value: 0 - - name: Level0 - description: Level 0 - value: 170 - - name: Level2 - description: Level 2 - value: 204 -enum/READY: - bit_size: 1 - variants: - - name: NotReady - description: The NVM is not ready - value: 0 - - name: Ready - description: The NVM is ready - value: 1 -enum/RUN_PD: - bit_size: 1 - variants: - - name: NVMIdleMode - description: "When the device is in Run mode, the NVM is in Idle mode" - value: 0 - - name: NVMPwrDownMode - description: "When the device is in Run mode, the NVM is in power-down mode" - value: 1 -enum/SIZERRR: - bit_size: 1 - variants: - - name: NoError - description: No size error happened - value: 0 - - name: Error - description: One size error happened - value: 1 -enum/SIZERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 -enum/SLEEP_PD: - bit_size: 1 - variants: - - name: NVMIdleMode - description: "When the device is in Sleep mode, the NVM is in Idle mode" - value: 0 - - name: NVMPwrDownMode - description: "When the device is in Sleep mode, the NVM is in power-down mode" - value: 1 -enum/WPRMOD: - bit_size: 1 - variants: - - name: Disabled - description: PCROP disabled. The WRPROT bits are used as a write protection on a sector. - value: 0 - - name: Enabled - description: PCROP enabled. The WRPROT bits are used as a read protection on a sector. - value: 1 -enum/WRPERRR: - bit_size: 1 - variants: - - name: NoError - description: No protection error happened - value: 0 - - name: Error - description: One protection error happened - value: 1 -enum/WRPERRW: - bit_size: 1 - variants: - - name: Clear - description: Clear the flag - value: 1 From afcd7a7d6973dd8d063d052b1e832243b482dcf4 Mon Sep 17 00:00:00 2001 From: Ulf Lilleengen Date: Tue, 26 Apr 2022 18:17:09 +0200 Subject: [PATCH 4/4] Rename flash_w[bl]55 flash_w[bl] --- data/registers/{flash_wb55.yaml => flash_wb.yaml} | 0 data/registers/{flash_wl55.yaml => flash_wl.yaml} | 0 stm32data/__main__.py | 4 ++-- 3 files changed, 2 insertions(+), 2 deletions(-) rename data/registers/{flash_wb55.yaml => flash_wb.yaml} (100%) rename data/registers/{flash_wl55.yaml => flash_wl.yaml} (100%) diff --git a/data/registers/flash_wb55.yaml b/data/registers/flash_wb.yaml similarity index 100% rename from data/registers/flash_wb55.yaml rename to data/registers/flash_wb.yaml diff --git a/data/registers/flash_wl55.yaml b/data/registers/flash_wl.yaml similarity index 100% rename from data/registers/flash_wl55.yaml rename to data/registers/flash_wl.yaml diff --git a/stm32data/__main__.py b/stm32data/__main__.py index f6414fb..6d77461 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -229,8 +229,8 @@ perimap = [ ('STM32L4.*:FLASH:.*', ('flash', 'l4', 'FLASH')), ('STM32L5.*:FLASH:.*', ('flash', 'l5', 'FLASH')), ('STM32U5.*:FLASH:.*', ('flash', 'u5', 'FLASH')), - ('STM32WB.*:FLASH:.*', ('flash', 'wb55', 'FLASH')), - ('STM32WL.*:FLASH:.*', ('flash', 'wl55', 'FLASH')), + ('STM32WB.*:FLASH:.*', ('flash', 'wb', 'FLASH')), + ('STM32WL.*:FLASH:.*', ('flash', 'wl', 'FLASH')), ('STM32G0.*:FLASH:.*', ('flash', 'g0', 'FLASH')), ('STM32F7.*:ETH:ETH:ethermac110_v2_0', ('eth', 'v1c', 'ETH')), ('.*ETH:ethermac110_v3_0', ('eth', 'v2', 'ETH')),