diff --git a/data/registers/lptim_g0.yaml b/data/registers/lptim_g0.yaml deleted file mode 100644 index 02dad0f..0000000 --- a/data/registers/lptim_g0.yaml +++ /dev/null @@ -1,291 +0,0 @@ -block/LPTIM: - description: Low power timer - items: - - name: ISR - description: Interrupt and Status Register - byte_offset: 0 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt Clear Register - byte_offset: 4 - access: Write - fieldset: ICR - - name: IER - description: Interrupt Enable Register - byte_offset: 8 - fieldset: IER - - name: CFGR - description: Configuration Register - byte_offset: 12 - fieldset: CFGR - - name: CR - description: Control Register - byte_offset: 16 - fieldset: CR - - name: CMP - description: Compare Register - byte_offset: 20 - fieldset: CMP - - name: ARR - description: Autoreload Register - byte_offset: 24 - fieldset: ARR - - name: CNT - description: Counter Register - byte_offset: 28 - access: Read - fieldset: CNT - - name: CFGR2 - description: LPTIM configuration register 2 - byte_offset: 36 - fieldset: CFGR2 -fieldset/ARR: - description: Autoreload Register - fields: - - name: ARR - description: Auto reload value - bit_offset: 0 - bit_size: 16 -fieldset/CFGR: - description: Configuration Register - fields: - - name: CKSEL - description: Clock selector - bit_offset: 0 - bit_size: 1 - enum: CKSEL - - name: CKPOL - description: Clock Polarity - bit_offset: 1 - bit_size: 2 - - name: CKFLT - description: Configurable digital filter for external clock - bit_offset: 3 - bit_size: 2 - - name: TRGFLT - description: Configurable digital filter for trigger - bit_offset: 6 - bit_size: 2 - - name: PRESC - description: Clock prescaler - bit_offset: 9 - bit_size: 3 - enum: PRESC - - name: TRIGSEL - description: Trigger selector - bit_offset: 13 - bit_size: 3 - - name: TRIGEN - description: Trigger enable and polarity - bit_offset: 17 - bit_size: 2 - enum: TRIGEN - - name: TIMOUT - description: Timeout enable - bit_offset: 19 - bit_size: 1 - - name: WAVE - description: Waveform shape - bit_offset: 20 - bit_size: 1 - - name: WAVPOL - description: Waveform shape polarity - bit_offset: 21 - bit_size: 1 - - name: PRELOAD - description: Registers update mode - bit_offset: 22 - bit_size: 1 - - name: COUNTMODE - description: counter mode enabled - bit_offset: 23 - bit_size: 1 - - name: ENC - description: Encoder mode enable - bit_offset: 24 - bit_size: 1 -fieldset/CFGR2: - description: LPTIM configuration register 2 - fields: - - name: IN1SEL - description: LPTIMx Input 1 selection - bit_offset: 0 - bit_size: 2 - - name: IN2SEL - description: LPTIM1 Input 2 selection - bit_offset: 4 - bit_size: 2 -fieldset/CMP: - description: Compare Register - fields: - - name: CMP - description: Compare value - bit_offset: 0 - bit_size: 16 -fieldset/CNT: - description: Counter Register - fields: - - name: CNT - description: Counter value - bit_offset: 0 - bit_size: 16 -fieldset/CR: - description: Control Register - fields: - - name: ENABLE - description: LPTIM Enable - bit_offset: 0 - bit_size: 1 - - name: SNGSTRT - description: LPTIM start in single mode - bit_offset: 1 - bit_size: 1 - - name: CNTSTRT - description: Timer start in continuous mode - bit_offset: 2 - bit_size: 1 - - name: COUNTRST - description: Counter reset - bit_offset: 3 - bit_size: 1 - - name: RSTARE - description: Reset after read enable - bit_offset: 4 - bit_size: 1 -fieldset/ICR: - description: Interrupt Clear Register - fields: - - name: CMPMCF - description: compare match Clear Flag - bit_offset: 0 - bit_size: 1 - - name: ARRMCF - description: Autoreload match Clear Flag - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGCF - description: External trigger valid edge Clear Flag - bit_offset: 2 - bit_size: 1 - - name: CMPOKCF - description: Compare register update OK Clear Flag - bit_offset: 3 - bit_size: 1 - - name: ARROKCF - description: Autoreload register update OK Clear Flag - bit_offset: 4 - bit_size: 1 - - name: UPCF - description: Direction change to UP Clear Flag - bit_offset: 5 - bit_size: 1 - - name: DOWNCF - description: Direction change to down Clear Flag - bit_offset: 6 - bit_size: 1 -fieldset/IER: - description: Interrupt Enable Register - fields: - - name: CMPMIE - description: Compare match Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: ARRMIE - description: Autoreload match Interrupt Enable - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGIE - description: External trigger valid edge Interrupt Enable - bit_offset: 2 - bit_size: 1 - - name: CMPOKIE - description: Compare register update OK Interrupt Enable - bit_offset: 3 - bit_size: 1 - - name: ARROKIE - description: Autoreload register update OK Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: UPIE - description: Direction change to UP Interrupt Enable - bit_offset: 5 - bit_size: 1 - - name: DOWNIE - description: Direction change to down Interrupt Enable - bit_offset: 6 - bit_size: 1 -fieldset/ISR: - description: Interrupt and Status Register - fields: - - name: CMPM - description: Compare match - bit_offset: 0 - bit_size: 1 - - name: ARRM - description: Autoreload match - bit_offset: 1 - bit_size: 1 - - name: EXTTRIG - description: External trigger edge event - bit_offset: 2 - bit_size: 1 - - name: CMPOK - description: Compare register update OK - bit_offset: 3 - bit_size: 1 - - name: ARROK - description: Autoreload register update OK - bit_offset: 4 - bit_size: 1 - - name: UP - description: Counter direction change down to up - bit_offset: 5 - bit_size: 1 - - name: DOWN - description: Counter direction change up to down - bit_offset: 6 - bit_size: 1 -enum/CKSEL: - bit_size: 1 - variants: - - name: INTERNAL - description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) - value: 0 - - name: EXTERNAL - description: LPTIM is clocked by an external clock source through the LPTIM external Input1 - value: 1 -enum/PRESC: - bit_size: 3 - variants: - - name: DIV_BY_1 - value: 0 - - name: DIV_BY_2 - value: 1 - - name: DIV_BY_4 - value: 2 - - name: DIV_BY_8 - value: 3 - - name: DIV_BY_16 - value: 4 - - name: DIV_BY_32 - value: 5 - - name: DIV_BY_64 - value: 6 - - name: DIV_BY_128 - value: 7 -enum/TRIGEN: - bit_size: 2 - variants: - - name: SOFTWARE - description: software trigger (counting start is initiated by software) - value: 0 - - name: RISING - description: rising edge is the active edge - value: 1 - - name: FALLING - description: rising edge is the active edge - value: 2 - - name: BOTH - description: both edges are active edges - value: 3 diff --git a/data/registers/opamp_f3.yaml b/data/registers/opamp_f3.yaml new file mode 100644 index 0000000..2dfcca1 --- /dev/null +++ b/data/registers/opamp_f3.yaml @@ -0,0 +1,213 @@ +--- +block/OPAMP: + description: Operational Amplifier + items: + - name: OPAMPCSR + description: OPAMP control register + byte_offset: 0 + fieldset: OPAMP_CSR +fieldset/OPAMP_CSR: + description: OPAMP control register + fields: + - name: OPAMPEN + description: OPAMP enable + bit_offset: 0 + bit_size: 1 + - name: FORCE_VP + description: FORCE_VP + bit_offset: 1 + bit_size: 1 + - name: VP_SEL + description: OPAMP Non inverting input selection + bit_offset: 2 + bit_size: 2 + - name: VM_SEL + description: OPAMP inverting input selection + bit_offset: 5 + bit_size: 2 + - name: TCM_EN + description: Timer controlled Mux mode enable + bit_offset: 7 + bit_size: 1 + - name: VMS_SEL + description: OPAMP inverting input secondary selection + bit_offset: 8 + bit_size: 1 + - name: VPS_SEL + description: OPAMP Non inverting input secondary selection + bit_offset: 9 + bit_size: 2 + - name: CALON + description: Calibration mode enable + bit_offset: 11 + bit_size: 1 + - name: CALSEL + description: Calibration selection + bit_offset: 12 + bit_size: 2 + - name: PGA_GAIN + description: Gain in PGA mode + bit_offset: 14 + bit_size: 4 + - name: USER_TRIM + description: User trimming enable + bit_offset: 18 + bit_size: 1 + - name: TRIMOFFSETP + description: Offset trimming value (PMOS) + bit_offset: 19 + bit_size: 5 + - name: TRIMOFFSETN + description: Offset trimming value (NMOS) + bit_offset: 24 + bit_size: 5 + - name: TSTREF + description: TSTREF + bit_offset: 29 + bit_size: 1 + - name: OUTCAL + description: OPAMP ouput status flag + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: OPAMP lock + bit_offset: 31 + bit_size: 1 +enum/CALSEL: + bit_size: 2 + variants: + - name: Percent3_3 + description: VREFOPAMP=3.3% VDDA + value: 0 + - name: Percent10 + description: VREFOPAMP=10% VDDA + value: 1 + - name: Percent50 + description: VREFOPAMP=50% VDDA + value: 2 + - name: Percent90 + description: VREFOPAMP=90% VDDA + value: 3 +enum/FORCE_VP: + bit_size: 1 + variants: + - name: Normal + description: Normal operating mode + value: 0 + - name: Calibration + description: Calibration mode. Non-inverting input connected to calibration reference + value: 1 +enum/LOCK: + bit_size: 1 + variants: + - name: Unlocked + description: Comparator CSR bits are read-write + value: 0 + - name: Locked + description: Comparator CSR bits are read-only + value: 1 +enum/OUTCAL: + bit_size: 1 + variants: + - name: Low + description: Non-inverting < inverting + value: 0 + - name: High + description: Non-inverting > inverting + value: 1 +enum/PGA_GAIN: + bit_size: 4 + variants: + - name: Gain2 + description: Gain 2 + value: 0 + - name: Gain4 + description: Gain 4 + value: 1 + - name: Gain8 + description: Gain 8 + value: 2 + - name: Gain16 + description: Gain 16 + value: 4 + - name: Gain2_VM0 + description: "Gain 2, feedback connected to VM0" + value: 8 + - name: Gain4_VM0 + description: "Gain 4, feedback connected to VM0" + value: 9 + - name: Gain8_VM0 + description: "Gain 8, feedback connected to VM0" + value: 10 + - name: Gain16_VM0 + description: "Gain 16, feedback connected to VM0" + value: 11 + - name: Gain2_VM1 + description: "Gain 2, feedback connected to VM1" + value: 12 + - name: Gain4_VM1 + description: "Gain 4, feedback connected to VM1" + value: 13 + - name: Gain8_VM1 + description: "Gain 8, feedback connected to VM1" + value: 14 + - name: Gain16_VM1 + description: "Gain 16, feedback connected to VM1" + value: 15 +enum/TSTREF: + bit_size: 1 + variants: + - name: Output + description: VREFOPAMP2 is output + value: 0 + - name: NotOutput + description: VREFOPAMP2 is not output + value: 1 +enum/VMS_SEL: + bit_size: 1 + variants: + - name: PC5 + description: PC5 (VM0) used as OPAMP2 inverting input when TCM_EN=1 + value: 0 + - name: PA5 + description: PA5 (VM1) used as OPAMP2 inverting input when TCM_EN=1 + value: 1 +enum/VM_SEL: + bit_size: 2 + variants: + - name: PC5 + description: PC5 (VM0) used as OPAMP2 inverting input + value: 0 + - name: PA5 + description: PA5 (VM1) used as OPAMP2 inverting input + value: 1 + - name: PGA + description: Resistor feedback output (PGA mode) + value: 2 + - name: Follower + description: Follower mode + value: 3 +enum/VPS_SEL: + bit_size: 2 + variants: + - name: PB14 + description: PB14 used as OPAMP2 non-inverting input when TCM_EN=1 + value: 1 + - name: PB0 + description: PB0 used as OPAMP2 non-inverting input when TCM_EN=1 + value: 2 + - name: PA7 + description: PA7 used as OPAMP2 non-inverting input when TCM_EN=1 + value: 3 +enum/VP_SEL: + bit_size: 2 + variants: + - name: PB14 + description: PB14 used as OPAMP2 non-inverting input + value: 1 + - name: PB0 + description: PB0 used as OPAMP2 non-inverting input + value: 2 + - name: PA7 + description: PA7 used as OPAMP2 non-inverting input + value: 3 diff --git a/data/registers/opamp_g4.yaml b/data/registers/opamp_g4.yaml new file mode 100644 index 0000000..5fc3544 --- /dev/null +++ b/data/registers/opamp_g4.yaml @@ -0,0 +1,298 @@ +--- +block/OPAMP: + description: Operational amplifiers + items: + - name: OPAMP_CSR + description: OPAMP control/status register + byte_offset: 0 + fieldset: OPAMP_CSR + - name: OPAMP_TCMR + description: OPAMP control/status register + byte_offset: 24 + fieldset: OPAMP_TCMR +fieldset/OPAMP_CSR: + description: OPAMP control/status register + fields: + - name: OPAEN + description: Operational amplifier Enable + bit_offset: 0 + bit_size: 1 + - name: FORCE_VP + description: FORCE_VP + bit_offset: 1 + bit_size: 1 + enum: OPAMP_CSR_FORCE_VP + - name: VP_SEL + description: VP_SEL + bit_offset: 2 + bit_size: 2 + enum: OPAMP_CSR_VP_SEL + - name: USERTRIM + description: USERTRIM + bit_offset: 4 + bit_size: 1 + enum: OPAMP_CSR_USERTRIM + - name: VM_SEL + description: VM_SEL + bit_offset: 5 + bit_size: 2 + enum: OPAMP_CSR_VM_SEL + - name: OPAHSM + description: OPAHSM + bit_offset: 7 + bit_size: 1 + enum: OPAMP_CSR_OPAHSM + - name: OPAINTOEN + description: OPAINTOEN + bit_offset: 8 + bit_size: 1 + enum: OPAMP_CSR_OPAINTOEN + - name: CALON + description: CALON + bit_offset: 11 + bit_size: 1 + - name: CALSEL + description: CALSEL + bit_offset: 12 + bit_size: 2 + enum: OPAMP_CSR_CALSEL + - name: PGA_GAIN + description: PGA_GAIN + bit_offset: 14 + bit_size: 5 + enum: OPAMP_CSR_PGA_GAIN + - name: TRIMOFFSETP + description: TRIMOFFSETP + bit_offset: 19 + bit_size: 5 + - name: TRIMOFFSETN + description: TRIMOFFSETN + bit_offset: 24 + bit_size: 5 + - name: CALOUT + description: CALOUT + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: LOCK + bit_offset: 31 + bit_size: 1 + enum: OPAMP_CSR_LOCK +fieldset/OPAMP_TCMR: + description: OPAMP timer controlled mode register + fields: + - name: VMS_SEL + description: VMS_SEL + bit_offset: 0 + bit_size: 1 + - name: VPS_SEL + description: VPS_SEL + bit_offset: 1 + bit_size: 2 + enum: OPAMP_TCMR_VPS_SEL + - name: T1CM_EN + description: T1CM_EN + bit_offset: 3 + bit_size: 1 + - name: T8CM_EN + description: T8CM_EN + bit_offset: 4 + bit_size: 1 + - name: T20CM_EN + description: T20CM_EN + bit_offset: 5 + bit_size: 1 + - name: LOCK + description: LOCK + bit_offset: 31 + bit_size: 1 + enum: OPAMP_TCMR_LOCK +enum/OPAMP_CSR_CALSEL: + bit_size: 2 + variants: + - name: Percent3_3 + description: 0.033*VDDA applied to OPAMP inputs during calibration + value: 0 + - name: Percent10 + description: 0.1*VDDA applied to OPAMP inputs during calibration + value: 1 + - name: Percent50 + description: 0.5*VDDA applied to OPAMP inputs during calibration + value: 2 + - name: Percent90 + description: 0.9*VDDA applied to OPAMP inputs during calibration + value: 3 +enum/OPAMP_CSR_FORCE_VP: + bit_size: 1 + variants: + - name: Normal + description: Non-inverting input connected configured inputs + value: 0 + - name: CalibrationVerification + description: Non-inverting input connected to calibration reference voltage + value: 1 +enum/OPAMP_CSR_LOCK: + bit_size: 1 + variants: + - name: ReadWrite + description: CSR is read-write + value: 0 + - name: ReadOnly + description: "CSR is read-only, can only be cleared by system reset" + value: 1 +enum/OPAMP_CSR_OPAHSM: + bit_size: 1 + variants: + - name: Normal + description: OpAmp in normal mode + value: 0 + - name: HighSpeed + description: OpAmp in high speed mode + value: 1 +enum/OPAMP_CSR_OPAINTOEN: + bit_size: 1 + variants: + - name: OutputPin + description: Output is connected to the output Pin + value: 0 + - name: ADCChannel + description: Output is connected internally to ADC channel + value: 1 +enum/OPAMP_CSR_PGA_GAIN: + bit_size: 5 + variants: + - name: Gain2 + description: Gain 2 + value: 0 + - name: Gain4 + description: Gain 4 + value: 1 + - name: Gain8 + description: Gain 8 + value: 2 + - name: Gain16 + description: Gain 16 + value: 3 + - name: Gain32 + description: Gain 32 + value: 4 + - name: Gain64 + description: Gain 64 + value: 5 + - name: Gain2_InputVINM0 + description: "Gain 2, input/bias connected to VINM0 or inverting gain" + value: 8 + - name: Gain4_InputVINM0 + description: "Gain 4, input/bias connected to VINM0 or inverting gain" + value: 9 + - name: Gain8_InputVINM0 + description: "Gain 8, input/bias connected to VINM0 or inverting gain" + value: 10 + - name: Gain16_InputVINM0 + description: "Gain 16, input/bias connected to VINM0 or inverting gain" + value: 11 + - name: Gain32_InputVINM0 + description: "Gain 32, input/bias connected to VINM0 or inverting gain" + value: 12 + - name: Gain64_InputVINM0 + description: "Gain 64, input/bias connected to VINM0 or inverting gain" + value: 13 + - name: Gain2_FilteringVINM0 + description: "Gain 2, with filtering on VINM0" + value: 16 + - name: Gain4_FilteringVINM0 + description: "Gain 4, with filtering on VINM0" + value: 17 + - name: Gain8_FilteringVINM0 + description: "Gain 8, with filtering on VINM0" + value: 18 + - name: Gain16_FilteringVINM0 + description: "Gain 16, with filtering on VINM0" + value: 19 + - name: Gain32_FilteringVINM0 + description: "Gain 32, with filtering on VINM0" + value: 20 + - name: Gain64_FilteringVINM0 + description: "Gain 64, with filtering on VINM0" + value: 21 + - name: Gain2_InputVINM0FilteringVINM1 + description: "Gain 2, input/bias connected to VINM0 with filtering on VINM1 or inverting gain" + value: 24 + - name: Gain4_InputVINM0FilteringVINM1 + description: "Gain 4, input/bias connected to VINM0 with filtering on VINM1 or inverting gain" + value: 25 + - name: Gain8_InputVINM0FilteringVINM1 + description: "Gain 8, input/bias connected to VINM0 with filtering on VINM1 or inverting gain" + value: 26 + - name: Gain16_InputVINM0FilteringVINM1 + description: "Gain 16, input/bias connected to VINM0 with filtering on VINM1 or inverting gain" + value: 27 + - name: Gain32_InputVINM0FilteringVINM1 + description: "Gain 32, input/bias connected to VINM0 with filtering on VINM1 or inverting gain" + value: 28 + - name: Gain64_InputVINM0FilteringVINM1 + description: "Gain 64, input/bias connected to VINM0 with filtering on VINM1 or inverting gain" + value: 29 +enum/OPAMP_CSR_USERTRIM: + bit_size: 1 + variants: + - name: Factory + description: Factory trim used + value: 0 + - name: User + description: User trim used + value: 1 +enum/OPAMP_CSR_VM_SEL: + bit_size: 2 + variants: + - name: VINM0 + description: VINM0 connected to VINM input + value: 0 + - name: VINM1 + description: VINM1 connected to VINM input + value: 1 + - name: PGA + description: Feedback resistor connected to VINM (PGA mode) + value: 2 + - name: Output + description: OpAmp output connected to VINM (Follower mode) + value: 3 +enum/OPAMP_CSR_VP_SEL: + bit_size: 2 + variants: + - name: VINP0 + description: VINP0 connected to VINP input + value: 0 + - name: VINP1 + description: VINP1 connected to VINP input + value: 1 + - name: VINP2 + description: VINP2 connected to VINP input + value: 2 + - name: DAC3_CH1 + description: DAC3_CH1 connected to VINP input + value: 3 +enum/OPAMP_TCMR_LOCK: + bit_size: 1 + variants: + - name: ReadWrite + description: TCMR is read-write + value: 0 + - name: ReadOnly + description: "TCMR is read-only, can only be cleared by system reset" + value: 1 +enum/OPAMP_TCMR_VPS_SEL: + bit_size: 2 + variants: + - name: VINP0 + description: VINP0 connected to VINP input + value: 0 + - name: VINP1 + description: VINP1 connected to VINP input + value: 1 + - name: VINP2 + description: VINP2 connected to VINP input + value: 2 + - name: DAC3_CH1 + description: DAC3_CH1 connected to VINP input + value: 3 diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index 6c66cd5..a8ee025 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -1110,10 +1110,12 @@ fieldset/CFGR: description: Microcontroller clock output bit_offset: 24 bit_size: 4 + enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: @@ -1483,6 +1485,57 @@ enum/HPRE: - name: Div512 description: hclk = SYSCLK divided by 256 value: 15 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: MSI + description: MSI oscillator clock selected + value: 2 + - name: HSI16 + description: HSI oscillator clock selected + value: 3 + - name: HSE32 + description: HSE32 oscillator clock selected + value: 4 + - name: PLLRCLK + description: Main PLLRCLK clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 8 + - name: PLLPCLK + description: Main PLLCLK oscillator clock selected + value: 13 + - name: PLLQCLK + description: Main PLLQCLK oscillator clock selected + value: 14 enum/PPRE: bit_size: 3 variants: diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index 393bc3b..17d34f8 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -740,10 +740,12 @@ fieldset/CFGR: description: Microcontroller clock output bit_offset: 24 bit_size: 4 + enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: @@ -1105,6 +1107,57 @@ enum/HPRE: - name: Div512 description: hclk = SYSCLK divided by 256 value: 15 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: MSI + description: MSI oscillator clock selected + value: 2 + - name: HSI16 + description: HSI oscillator clock selected + value: 3 + - name: HSE32 + description: HSE32 oscillator clock selected + value: 4 + - name: PLLRCLK + description: Main PLLRCLK clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 8 + - name: PLLPCLK + description: Main PLLCLK oscillator clock selected + value: 13 + - name: PLLQCLK + description: Main PLLQCLK oscillator clock selected + value: 14 enum/PPRE: bit_size: 3 variants: diff --git a/data/registers/sbs_h5.yaml b/data/registers/syscfg_h5.yaml similarity index 99% rename from data/registers/sbs_h5.yaml rename to data/registers/syscfg_h5.yaml index 2b9d3f5..3094aeb 100644 --- a/data/registers/sbs_h5.yaml +++ b/data/registers/syscfg_h5.yaml @@ -1,4 +1,4 @@ -block/SBS: +block/SYSCFG: description: SBS register block items: - name: HDPLCR diff --git a/data/registers/sbs_h50.yaml b/data/registers/syscfg_h50.yaml similarity index 99% rename from data/registers/sbs_h50.yaml rename to data/registers/syscfg_h50.yaml index 8328357..74107ad 100644 --- a/data/registers/sbs_h50.yaml +++ b/data/registers/syscfg_h50.yaml @@ -1,4 +1,4 @@ -block/SBS: +block/SYSCFG: description: System configuration, boot and security items: - name: HDPLCR diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 5f6a27f..e7152c9 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -189,6 +189,8 @@ impl PeriMatcher { (".*:ADC:aditf5_v2_2", ("adc", "v3", "ADC")), (".*:ADC:aditf5_v3_0", ("adc", "v4", "ADC")), (".*:ADC:aditf5_v3_1", ("adc", "v4", "ADC")), + ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")), + ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")), ("STM32G4.*:ADC:.*", ("adc", "v4", "ADC")), @@ -201,6 +203,8 @@ impl PeriMatcher { (".*:ADC3_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), ("STM32H7.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), ("STM32H7.*:ADC3_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), + ("STM32G4.*:OPAMP:G4_tsmc90_fastOpamp", ("opamp", "g4", "OPAMP")), + ("STM32F3.*:OPAMP:tsmc018_ull_opamp_v1_0", ("opamp", "f3", "OPAMP")), (".*:DCMI:.*", ("dcmi", "v1", "DCMI")), ("STM32C0.*:SYSCFG:.*", ("syscfg", "c0", "SYSCFG")), ("STM32F0.*:SYSCFG:.*", ("syscfg", "f0", "SYSCFG")), @@ -223,11 +227,9 @@ impl PeriMatcher { ("STM32WBA.*:SYSCFG:.*", ("syscfg", "wba", "SYSCFG")), ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")), ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")), - ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")), - ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")), - ("STM32H50.*:SBS:.*", ("sbs", "h50", "SBS")), - ("STM32H5.*:SBS:.*", ("sbs", "h5", "SBS")), + ("STM32H50.*:SBS:.*", ("syscfg", "h50", "SYSCFG")), + ("STM32H5.*:SBS:.*", ("syscfg", "h5", "SYSCFG")), (".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")), (".*:IWDG:iwdg1_v2_0", ("iwdg", "v2", "IWDG")), (".*:WWDG:wwdg1_v1_0", ("wwdg", "v1", "WWDG")), @@ -398,7 +400,9 @@ impl PeriMatcher { ("STM32G4.*:FSMC:.*", ("fsmc", "v4x1", "FSMC")), ("STM32L5.*:FSMC:.*", ("fsmc", "v4x1", "FSMC")), ("STM32U5.*:FSMC:.*", ("fsmc", "v5x1", "FSMC")), - (r".*LPTIM\d.*:G0xx_lptimer1_v1_4", ("lptim", "g0", "LPTIM")), + (r".*LPTIM\d.*:G0xx_lptimer1_v1_4", ("lptim", "v1", "LPTIM")), + ("STM32WB.*:LPTIM1:.*", ("lptim", "v1", "LPTIM")), + ("STM32WB.*:LPTIM2:.*", ("lptim", "v1", "LPTIM")), ("STM32F1.*:TIM(1|8):.*", ("timer", "v1", "TIM_ADV")), ("STM32F1.*:TIM(2|5):.*", ("timer", "v1", "TIM_GP16")), ("STM32F1.*:TIM(6|7):.*", ("timer", "v1", "TIM_BASIC")), @@ -942,7 +946,11 @@ fn process_core( }; let mut p = stm32_data_serde::chip::core::Peripheral { - name: pname.clone(), + name: if pname == "SBS" { + "SYSCFG".to_string() + } else { + pname.clone() + }, address: addr, registers: None, rcc: None,