diff --git a/data/registers/dac_v4.yaml b/data/registers/dac_v4.yaml
new file mode 100644
index 0000000..e7c7576
--- /dev/null
+++ b/data/registers/dac_v4.yaml
@@ -0,0 +1,475 @@
+block/DAC:
+  description: Digital-to-analog converter
+  items:
+  - name: CR
+    description: control register
+    byte_offset: 0
+    fieldset: CR
+  - name: SWTRIGR
+    description: software trigger register
+    byte_offset: 4
+    access: Write
+    fieldset: SWTRIGR
+  - name: DHR12R
+    description: channel 12-bit right-aligned data holding register
+    array:
+      len: 2
+      stride: 12
+    byte_offset: 8
+    fieldset: DHR12R
+  - name: DHR12L
+    description: channel 12-bit left-aligned data holding register
+    array:
+      len: 2
+      stride: 12
+    byte_offset: 12
+    fieldset: DHR12L
+  - name: DHR8R
+    description: channel 8-bit right-aligned data holding register
+    array:
+      len: 2
+      stride: 12
+    byte_offset: 16
+    fieldset: DHR8R
+  - name: DHR12RD
+    description: Dual DAC 12-bit right-aligned data holding register
+    byte_offset: 32
+    fieldset: DHR12RD
+  - name: DHR12LD
+    description: DUAL DAC 12-bit left aligned data holding register
+    byte_offset: 36
+    fieldset: DHR12LD
+  - name: DHR8RD
+    description: DUAL DAC 8-bit right aligned data holding register
+    byte_offset: 40
+    fieldset: DHR8RD
+  - name: DOR
+    description: channel data output register
+    array:
+      len: 2
+      stride: 4
+    byte_offset: 44
+    access: Read
+    fieldset: DOR
+  - name: SR
+    description: status register
+    byte_offset: 52
+    fieldset: SR
+  - name: CCR
+    description: calibration control register
+    byte_offset: 56
+    fieldset: CCR
+  - name: MCR
+    description: mode control register
+    byte_offset: 60
+    fieldset: MCR
+  - name: SHSR1
+    description: Sample and Hold sample time register
+    array:
+      len: 2
+      stride: 4
+    byte_offset: 64
+    fieldset: SHSR
+  - name: SHHR
+    description: Sample and Hold hold time register
+    byte_offset: 72
+    fieldset: SHHR
+  - name: SHRR
+    description: Sample and Hold refresh time register
+    byte_offset: 76
+    fieldset: SHRR
+  - name: STR
+    description: Sawtooth register
+    byte_offset: 88
+    fieldset: STR
+    array:
+      len: 2
+      stride: 4
+  - name: STMODR
+    description: Sawtooth Mode register
+    byte_offset: 96
+    fieldset: STMODR
+fieldset/CCR:
+  description: calibration control register
+  fields:
+  - name: OTRIM1
+    description: DAC Channel 1 offset trimming value
+    bit_offset: 0
+    bit_size: 5
+  - name: OTRIM2
+    description: DAC Channel 2 offset trimming value
+    bit_offset: 16
+    bit_size: 5
+fieldset/CR:
+  description: control register
+  fields:
+  - name: EN
+    description: DAC channel enable
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: TEN
+    description: DAC channel trigger enable
+    bit_offset: 1
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: TSEL
+    description: DAC channel 1 trigger selection
+    bit_offset: 2
+    bit_size: 4
+    enum: TSEL
+    array:
+      len: 2
+      stride: 16
+  - name: WAVE
+    description: DAC channel noise/triangle wave generation enable
+    bit_offset: 6
+    bit_size: 2
+    array:
+      len: 2
+      stride: 16
+    enum: WAVE
+  - name: MAMP
+    description: DAC channel mask/amplitude selector
+    bit_offset: 8
+    bit_size: 4
+    array:
+      len: 2
+      stride: 16
+  - name: DMAEN
+    description: DAC channel DMA enable
+    bit_offset: 12
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: DMAUDRIE
+    description: DAC channel DMA Underrun Interrupt enable
+    bit_offset: 13
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: CEN
+    description: DAC channel calibration enable
+    bit_offset: 14
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+fieldset/DHR12L:
+  description: channel 12-bit left-aligned data holding register
+  fields:
+  - name: DHR
+    description: DAC channel 12-bit left-aligned data
+    bit_offset: 4
+    bit_size: 12
+  - name: DHRB
+    description: DAC channel 12-bit left-aligned data B.
+    bit_offset: 20
+    bit_size: 12
+fieldset/DHR12LD:
+  description: DUAL DAC 12-bit left aligned data holding register
+  fields:
+  - name: DHR
+    description: DAC channel 12-bit left-aligned data
+    bit_offset: 4
+    bit_size: 12
+    array:
+      len: 2
+      stride: 16
+fieldset/DHR12R:
+  description: channel 12-bit right-aligned data holding register
+  fields:
+  - name: DHR
+    description: DAC channel 12-bit right-aligned data
+    bit_offset: 0
+    bit_size: 12
+  - name: DHRB
+    description: channel 12-bit right-aligned data B
+    bit_offset: 16
+    bit_size: 12
+fieldset/DHR12RD:
+  description: Dual DAC 12-bit right-aligned data holding register
+  fields:
+  - name: DHR
+    description: DAC channel 12-bit right-aligned data
+    bit_offset: 0
+    bit_size: 12
+    array:
+      len: 2
+      stride: 16
+fieldset/DHR8R:
+  description: channel 8-bit right-aligned data holding register
+  fields:
+  - name: DHR
+    description: DAC channel 8-bit right-aligned data
+    bit_offset: 0
+    bit_size: 8
+  - name: DHRB
+    description: DAC channel 8-bit right-aligned data B
+    bit_offset: 8
+    bit_size: 8
+fieldset/DHR8RD:
+  description: DUAL DAC 8-bit right aligned data holding register
+  fields:
+  - name: DHR
+    description: DAC channel 8-bit right-aligned data
+    bit_offset: 0
+    bit_size: 8
+    array:
+      len: 2
+      stride: 8
+fieldset/DOR:
+  description: channel data output register
+  fields:
+  - name: DOR
+    description: DAC channel data output
+    bit_offset: 0
+    bit_size: 12
+  - name: DORB
+    description: DAC channel data output B
+    bit_offset: 16
+    bit_size: 12
+fieldset/MCR:
+  description: mode control register
+  fields:
+  - name: MODE
+    description: DAC channel mode
+    bit_offset: 0
+    bit_size: 3
+    enum: MODE
+    array:
+      len: 2
+      stride: 16
+  - name: DMADOUBLE
+    description: DAC Channel1 DMA double data mode.
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: SINFORMAT
+    description: Enable signed format for DAC channel1.
+    bit_offset: 9
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: HFSEL
+    description: High frequency interface mode selection.
+    bit_offset: 14
+    bit_size: 2
+fieldset/SHHR:
+  description: Sample and Hold hold time register
+  fields:
+  - name: THOLD
+    description: DAC channel hold Time
+    bit_offset: 0
+    bit_size: 10
+    array:
+      len: 2
+      stride: 16
+fieldset/SHRR:
+  description: Sample and Hold refresh time register
+  fields:
+  - name: TREFRESH
+    description: DAC channel refresh Time
+    bit_offset: 0
+    bit_size: 8
+    array:
+      len: 2
+      stride: 16
+fieldset/SHSR:
+  description: Sample and Hold sample time register
+  fields:
+  - name: TSAMPLE
+    description: DAC channel sample Time
+    bit_offset: 0
+    bit_size: 10
+fieldset/SR:
+  description: status register
+  fields:
+  - name: DACRDY
+    description: DAC channel ready status bit.
+    bit_offset: 11
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: DORSTAT
+    description: DAC channel output register status bit.
+    bit_offset: 12
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: DMAUDR
+    description: DAC channel DMA underrun flag
+    bit_offset: 13
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: CAL_FLAG
+    description: DAC channel calibration offset status
+    bit_offset: 14
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+  - name: BWST
+    description: DAC channel busy writing sample time flag
+    bit_offset: 15
+    bit_size: 1
+    array:
+      len: 2
+      stride: 16
+fieldset/STMODR:
+  description: Sawtooth Mode register.
+  fields:
+  - name: STRSTTRIGSEL1
+    description: DAC Channel 1 Sawtooth Reset trigger selection.
+    bit_offset: 0
+    bit_size: 4
+  - name: STINCTRIGSEL1
+    description: DAC Channel 1 Sawtooth Increment trigger selection.
+    bit_offset: 8
+    bit_size: 4
+  - name: STRSTTRIGSEL2
+    description: DAC Channel 1 Sawtooth Reset trigger selection.
+    bit_offset: 16
+    bit_size: 4
+  - name: STINCTRIGSEL2
+    description: DAC Channel 2 Sawtooth Increment trigger selection.
+    bit_offset: 24
+    bit_size: 4
+fieldset/STR:
+  description: Sawtooth register.
+  fields:
+  - name: RSTDATA
+    description: DAC Channel Sawtooth reset value.
+    bit_offset: 0
+    bit_size: 12
+  - name: DIR
+    description: DAC Channel Sawtooth direction setting.
+    bit_offset: 12
+    bit_size: 1
+  - name: INCDATA
+    description: DAC Sawtooth increment value (12.4 bit format)
+    bit_offset: 16
+    bit_size: 16
+fieldset/SWTRIGR:
+  description: DAC software trigger register.
+  fields:
+  - name: SWTRIG
+    description: 'DAC channel software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DHR1 register value has been loaded into the DOR1 register.'
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+  - name: SWTRIGB
+    description: DAC channel software trigger B.
+    bit_offset: 16
+    bit_size: 1
+    array:
+      len: 2
+      stride: 1
+enum/MODE:
+  bit_size: 3
+  variants:
+    - name: NORMAL_EXT_BUFEN
+      description: Normal mode, external pin only, buffer enabled
+      value: 0
+    - name: NORMAL_EXT_INT_BUFEN
+      description: Normal mode, external pin and internal peripherals, buffer enabled
+      value: 1
+    - name: NORMAL_EXT_BUFDIS
+      description: Normal mode, external pin only, buffer disabled
+      value: 2
+    - name: NORMAL_INT_BUFDIS
+      description: Normal mode, internal peripherals only, buffer disabled
+      value: 3
+    - name: SAMPHOLD_EXT_BUFEN
+      description: Sample and hold mode, external pin only, buffer enabled
+      value: 4
+    - name: SAMPHOLD_EXT_INT_BUFEN
+      description: Sample and hold mode, external pin and internal peripherals, buffer enabled
+      value: 5
+    - name: SAMPHOLD_EXT_INT_BUFDIS
+      description: Sample and hold mode, external pin and internal peripherals, buffer disabled
+      value: 6
+    - name: SAMPHOLD_INT_BUFDIS
+      description: Sample and hold mode, internal peripherals only, buffer disabled
+      value: 7
+enum/TSEL:
+  bit_size: 4
+  variants:
+  - name: SOFTWARE
+    description: Software trigger
+    value: 0
+  - name: TIM8_TIM1_TRGO
+    description: TIM8 (DAC1/2/4) or TIM1 (DAC3) trigger output
+    value: 1
+  - name: TIM7_TRGO
+    description: TIM7 trigger output
+    value: 2
+  - name: TIM15_TRGO
+    description: TIM15 trigger output
+    value: 3
+  - name: TIM2_TRGO
+    description: TIM2 trigger otuput
+    value: 4
+  - name: TIM4_TRGO
+    description: TIM4 trigger output
+    value: 5
+  - name: EXTI9
+    description: external pin
+    value: 6
+  - name: TIM6_TRGO
+    description: TIM6 trigger output
+    value: 7
+  - name: TIM3_TRGO
+    description: TIM3 trigger output
+    value: 8
+  - name: HRTIM_DAC_RESET_TRG1
+    description: HRTIM dual channel DAC trigger 1
+    value: 9
+  - name: HRTIM_DAC_RESET_TRG2
+    description: HRTIM dual channel DAC trigger 2
+    value: 10
+  - name: HRTIM_DAC_RESET_TRG3
+    description: HRTIM dual channel DAC trigger 3
+    value: 11
+  - name: HRTIM_DAC_RESET_TRG4
+    description: HRTIM dual channel DAC trigger 4
+    value: 12
+  - name: HRTIM_DAC_RESET_TRG5
+    description: HRTIM dual channel DAC trigger 5
+    value: 13
+  - name: HRTIM_DAC_RESET_TRG6
+    description: HRTIM dual channel DAC trigger 6
+    value: 14
+  - name: HRTIM_DAC_TRG1_2_3
+    description: HRTIM DAC trigger 1 (DAC1/DAC4), 2 (DAC2), 3 (DAC3)
+    value: 15
+enum/WAVE:
+  bit_size: 2
+  variants:
+  - name: Disabled
+    description: Wave generation disabled
+    value: 0
+  - name: Noise
+    description: Noise wave generation enabled
+    value: 1
+  - name: Triangle
+    description: Triangle wave generation enabled
+    value: 2
+  - name: Sawtooth
+    description: Sawtooth wave generation enabled
+    value: 3
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index 82bb4e7..bf977ad 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -182,6 +182,7 @@ impl PeriMatcher {
             (".*:DAC:dacif_v2_0", ("dac", "v2", "DAC")),
             (".*:DAC:dacif_v3_0", ("dac", "v3", "DAC")),
             (".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")),
+            (".*:DAC:G4_dacif_v4_0", ("dac", "v4", "DAC")),
             (".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")),
             (".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")),
             (".*:ADC:aditf_v2_5", ("adc", "f3_v2", "ADC")),