diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml index a5d4b16..ec88bd2 100644 --- a/data/registers/rcc_f0.yaml +++ b/data/registers/rcc_f0.yaml @@ -411,12 +411,10 @@ fieldset/BDCR: description: External Low Speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: External Low Speed oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: LSEDRV description: LSE oscillator drive capability bit_offset: 3 @@ -544,117 +542,94 @@ fieldset/CIR: description: LSI Ready Interrupt flag bit_offset: 0 bit_size: 1 - enum_read: LSIRDYFR - name: LSERDYF description: LSE Ready Interrupt flag bit_offset: 1 bit_size: 1 - enum_read: LSIRDYFR - name: HSIRDYF description: HSI Ready Interrupt flag bit_offset: 2 bit_size: 1 - enum_read: LSIRDYFR - name: HSERDYF description: HSE Ready Interrupt flag bit_offset: 3 bit_size: 1 - enum_read: LSIRDYFR - name: PLLRDYF description: PLL Ready Interrupt flag bit_offset: 4 bit_size: 1 - enum_read: LSIRDYFR - name: HSI14RDYF description: HSI14 ready interrupt flag bit_offset: 5 bit_size: 1 - enum_read: LSIRDYFR - name: HSI48RDYF description: HSI48 ready interrupt flag bit_offset: 6 bit_size: 1 - enum_read: LSIRDYFR - name: CSSF description: Clock Security System Interrupt flag bit_offset: 7 bit_size: 1 - enum_read: CSSFR - name: LSIRDYIE description: LSI Ready Interrupt Enable bit_offset: 8 bit_size: 1 - enum: LSIRDYIE - name: LSERDYIE description: LSE Ready Interrupt Enable bit_offset: 9 bit_size: 1 - enum: LSIRDYIE - name: HSIRDYIE description: HSI Ready Interrupt Enable bit_offset: 10 bit_size: 1 - enum: LSIRDYIE - name: HSERDYIE description: HSE Ready Interrupt Enable bit_offset: 11 bit_size: 1 - enum: LSIRDYIE - name: PLLRDYIE description: PLL Ready Interrupt Enable bit_offset: 12 bit_size: 1 - enum: LSIRDYIE - name: HSI14RDYIE description: HSI14 ready interrupt enable bit_offset: 13 bit_size: 1 - enum: LSIRDYIE - name: HSI48RDYIE description: HSI48 ready interrupt enable bit_offset: 14 bit_size: 1 - enum: LSIRDYIE - name: LSIRDYC description: LSI Ready Interrupt Clear bit_offset: 16 bit_size: 1 - enum_write: LSIRDYCW - name: LSERDYC description: LSE Ready Interrupt Clear bit_offset: 17 bit_size: 1 - enum_write: LSIRDYCW - name: HSIRDYC description: HSI Ready Interrupt Clear bit_offset: 18 bit_size: 1 - enum_write: LSIRDYCW - name: HSERDYC description: HSE Ready Interrupt Clear bit_offset: 19 bit_size: 1 - enum_write: LSIRDYCW - name: PLLRDYC description: PLL Ready Interrupt Clear bit_offset: 20 bit_size: 1 - enum_write: LSIRDYCW - name: HSI14RDYC description: HSI 14 MHz Ready Interrupt Clear bit_offset: 21 bit_size: 1 - enum_write: LSIRDYCW - name: HSI48RDYC description: HSI48 Ready Interrupt Clear bit_offset: 22 bit_size: 1 - enum_write: LSIRDYCW - name: CSSC description: Clock security system interrupt clear bit_offset: 23 bit_size: 1 - enum_write: CSSCW fieldset/CR: description: Clock control register fields: @@ -666,7 +641,6 @@ fieldset/CR: description: Internal High Speed clock ready flag bit_offset: 1 bit_size: 1 - enum_read: HSIRDYR - name: HSITRIM description: Internal High Speed clock trimming bit_offset: 3 @@ -683,12 +657,10 @@ fieldset/CR: description: External High Speed clock ready flag bit_offset: 17 bit_size: 1 - enum_read: HSIRDYR - name: HSEBYP description: External High Speed clock Bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: CSSON description: Clock Security System enable bit_offset: 19 @@ -701,7 +673,6 @@ fieldset/CR: description: PLL clock ready flag bit_offset: 25 bit_size: 1 - enum_read: HSIRDYR fieldset/CR2: description: Clock control register 2 fields: @@ -713,12 +684,10 @@ fieldset/CR2: description: HR14 clock ready flag bit_offset: 1 bit_size: 1 - enum_read: HSIRDYR - name: HSI14DIS description: HSI14 clock request from ADC disable bit_offset: 2 bit_size: 1 - enum: HSIDIS - name: HSI14TRIM description: HSI14 clock trimming bit_offset: 3 @@ -735,7 +704,6 @@ fieldset/CR2: description: HSI48 clock ready flag bit_offset: 17 bit_size: 1 - enum_read: HSIRDYR - name: HSI48CAL description: HSI48 factory clock calibration bit_offset: 24 @@ -751,52 +719,42 @@ fieldset/CSR: description: Internal low speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR - name: V18PWRRSTF description: 1.8 V domain reset flag bit_offset: 23 bit_size: 1 - enum_read: OBLRSTFR - name: RMVF description: Remove reset flag bit_offset: 24 bit_size: 1 - enum_write: RMVFW - name: OBLRSTF description: Option byte loader reset flag bit_offset: 25 bit_size: 1 - enum_read: OBLRSTFR - name: PINRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 - enum_read: OBLRSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 - enum_read: OBLRSTFR - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - enum_read: OBLRSTFR - name: IWDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 - enum_read: OBLRSTFR - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - enum_read: OBLRSTFR - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 - enum_read: OBLRSTFR enum/CECSW: bit_size: 1 variants: @@ -806,21 +764,6 @@ enum/CECSW: - name: LSE description: LSE clock selected as CEC clock source value: 1 -enum/CSSCW: - bit_size: 1 - variants: - - name: Clear - description: Clear CSSF flag - value: 1 -enum/CSSFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Interrupted - description: Clock security interrupt caused by HSE clock failure - value: 1 enum/HPRE: bit_size: 4 variants: @@ -851,33 +794,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 -enum/HSIDIS: - bit_size: 1 - variants: - - name: Allow - description: ADC can turn on the HSI14 oscillator - value: 0 - - name: Disallow - description: ADC can not turn on the HSI14 oscillator - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: HSI48 oscillator ready - value: 0 - - name: Ready - description: HSI48 oscillator ready - value: 1 enum/ICSW: bit_size: 1 variants: @@ -887,15 +803,6 @@ enum/ICSW: - name: SYSCLK description: SYSCLK clock selected as I2C clock source value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 enum/LSEDRV: bit_size: 2 variants: @@ -911,48 +818,6 @@ enum/LSEDRV: - name: High description: High drive capacity value: 3 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSIRDYCW: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/LSIRDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/LSIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCO: bit_size: 3 variants: @@ -1010,15 +875,6 @@ enum/MCOPRE: - name: Div128 description: MCO is divided by 128 value: 7 -enum/OBLRSTFR: - bit_size: 1 - variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 enum/PLLMUL: bit_size: 4 variants: @@ -1172,12 +1028,6 @@ enum/PREDIV: - name: Div16 description: PREDIV input clock divided by 16 value: 15 -enum/RMVFW: - bit_size: 1 - variants: - - name: Clear - description: Clears the reset flag - value: 1 enum/RTCSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_f2.yaml b/data/registers/rcc_f2.yaml index 24e9588..662b06b 100644 --- a/data/registers/rcc_f2.yaml +++ b/data/registers/rcc_f2.yaml @@ -866,12 +866,10 @@ fieldset/BDCR: description: External low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: External low-speed oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: RTCSEL description: RTC clock source selection bit_offset: 8 @@ -949,102 +947,82 @@ fieldset/CIR: description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - enum_read: PLLISRDYFR - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - enum_read: PLLISRDYFR - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - enum_read: PLLISRDYFR - name: HSERDYF description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - enum_read: PLLISRDYFR - name: PLLRDYF description: Main PLL (PLL) ready interrupt flag bit_offset: 4 bit_size: 1 - enum_read: PLLISRDYFR - name: PLLI2SRDYF description: PLLI2S ready interrupt flag bit_offset: 5 bit_size: 1 - enum_read: PLLISRDYFR - name: CSSF description: Clock security system interrupt flag bit_offset: 7 bit_size: 1 - enum_read: CSSFR - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 8 bit_size: 1 - enum: PLLISRDYIE - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 9 bit_size: 1 - enum: PLLISRDYIE - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 10 bit_size: 1 - enum: PLLISRDYIE - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 11 bit_size: 1 - enum: PLLISRDYIE - name: PLLRDYIE description: Main PLL (PLL) ready interrupt enable bit_offset: 12 bit_size: 1 - enum: PLLISRDYIE - name: PLLI2SRDYIE description: PLLI2S ready interrupt enable bit_offset: 13 bit_size: 1 - enum: PLLISRDYIE - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 16 bit_size: 1 - enum_write: PLLISRDYCW - name: LSERDYC description: LSE ready interrupt clear bit_offset: 17 bit_size: 1 - enum_write: PLLISRDYCW - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 18 bit_size: 1 - enum_write: PLLISRDYCW - name: HSERDYC description: HSE ready interrupt clear bit_offset: 19 bit_size: 1 - enum_write: PLLISRDYCW - name: PLLRDYC description: Main PLL(PLL) ready interrupt clear bit_offset: 20 bit_size: 1 - enum_write: PLLISRDYCW - name: PLLI2SRDYC description: PLLI2S ready interrupt clear bit_offset: 21 bit_size: 1 - enum_write: PLLISRDYCW - name: CSSC description: Clock security system interrupt clear bit_offset: 23 bit_size: 1 - enum_write: CSSCW fieldset/CR: description: clock control register fields: @@ -1056,7 +1034,6 @@ fieldset/CR: description: Internal high-speed clock ready flag bit_offset: 1 bit_size: 1 - enum_read: PLLISRDYR - name: HSITRIM description: Internal high-speed clock trimming bit_offset: 3 @@ -1073,12 +1050,10 @@ fieldset/CR: description: HSE clock ready flag bit_offset: 17 bit_size: 1 - enum_read: PLLISRDYR - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: CSSON description: Clock security system enable bit_offset: 19 @@ -1091,7 +1066,6 @@ fieldset/CR: description: Main PLL (PLL) clock ready flag bit_offset: 25 bit_size: 1 - enum_read: PLLISRDYR - name: PLLI2SON description: PLLI2S enable bit_offset: 26 @@ -1100,7 +1074,6 @@ fieldset/CR: description: PLLI2S clock ready flag bit_offset: 27 bit_size: 1 - enum_read: PLLISRDYR fieldset/CSR: description: clock control & status register fields: @@ -1112,47 +1085,38 @@ fieldset/CSR: description: Internal low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR - name: RMVF description: Remove reset flag bit_offset: 24 bit_size: 1 - enum_write: RMVFW - name: BORRSTF description: BOR reset flag bit_offset: 25 bit_size: 1 - enum_read: LPWRRSTFR - name: PADRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 - enum_read: LPWRRSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 - enum_read: LPWRRSTFR - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - enum_read: LPWRRSTFR - name: WDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 - enum_read: LPWRRSTFR - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - enum_read: LPWRRSTFR - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 - enum_read: LPWRRSTFR fieldset/PLLCFGR: description: PLL configuration register fields: @@ -1209,21 +1173,6 @@ fieldset/SSCGR: description: Spread spectrum modulation enable bit_offset: 31 bit_size: 1 -enum/CSSCW: - bit_size: 1 - variants: - - name: Clear - description: Clear CSSF flag - value: 1 -enum/CSSFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Interrupted - description: Clock security interrupt caused by HSE clock failure - value: 1 enum/HPRE: bit_size: 4 variants: @@ -1254,15 +1203,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 enum/ISSRC: bit_size: 1 variants: @@ -1272,42 +1212,6 @@ enum/ISSRC: - name: CKIN description: External clock mapped on the I2S_CKIN pin used as I2S clock source value: 1 -enum/LPWRRSTFR: - bit_size: 1 - variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCO1: bit_size: 2 variants: @@ -1356,39 +1260,6 @@ enum/MCOPRE: - name: Div5 description: Division by 5 value: 7 -enum/PLLISRDYCW: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/PLLISRDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/PLLISRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/PLLISRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/PLLP: bit_size: 2 variants: @@ -1431,12 +1302,6 @@ enum/PPRE: - name: Div16 description: HCLK divided by 16 value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - name: Clear - description: Clears the reset flag - value: 1 enum/RTCSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index d16c396..844bcd5 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -547,12 +547,10 @@ fieldset/BDCR: description: External Low Speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: External Low Speed oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: LSEDRV description: LSE oscillator drive capability bit_offset: 3 @@ -767,87 +765,70 @@ fieldset/CIR: description: LSI Ready Interrupt flag bit_offset: 0 bit_size: 1 - enum_read: LSIRDYFR - name: LSERDYF description: LSE Ready Interrupt flag bit_offset: 1 bit_size: 1 - enum_read: LSIRDYFR - name: HSIRDYF description: HSI Ready Interrupt flag bit_offset: 2 bit_size: 1 - enum_read: LSIRDYFR - name: HSERDYF description: HSE Ready Interrupt flag bit_offset: 3 bit_size: 1 - enum_read: LSIRDYFR - name: PLLRDYF description: PLL Ready Interrupt flag bit_offset: 4 bit_size: 1 - enum_read: LSIRDYFR - name: CSSF description: Clock Security System Interrupt flag bit_offset: 7 bit_size: 1 - enum_read: CSSFR - name: LSIRDYIE description: LSI Ready Interrupt Enable bit_offset: 8 bit_size: 1 - enum: LSIRDYIE - name: LSERDYIE description: LSE Ready Interrupt Enable bit_offset: 9 bit_size: 1 - enum: LSIRDYIE - name: HSIRDYIE description: HSI Ready Interrupt Enable bit_offset: 10 bit_size: 1 - enum: LSIRDYIE - name: HSERDYIE description: HSE Ready Interrupt Enable bit_offset: 11 bit_size: 1 - enum: LSIRDYIE - name: PLLRDYIE description: PLL Ready Interrupt Enable bit_offset: 12 bit_size: 1 - enum: LSIRDYIE - name: LSIRDYC description: LSI Ready Interrupt Clear bit_offset: 16 bit_size: 1 - enum_write: LSIRDYCW - name: LSERDYC description: LSE Ready Interrupt Clear bit_offset: 17 bit_size: 1 - enum_write: LSIRDYCW - name: HSIRDYC description: HSI Ready Interrupt Clear bit_offset: 18 bit_size: 1 - enum_write: LSIRDYCW - name: HSERDYC description: HSE Ready Interrupt Clear bit_offset: 19 bit_size: 1 - enum_write: LSIRDYCW - name: PLLRDYC description: PLL Ready Interrupt Clear bit_offset: 20 bit_size: 1 - enum_write: LSIRDYCW - name: CSSC description: Clock security system interrupt clear bit_offset: 23 bit_size: 1 - enum_write: CSSCW fieldset/CR: description: Clock control register fields: @@ -859,7 +840,6 @@ fieldset/CR: description: Internal High Speed clock ready flag bit_offset: 1 bit_size: 1 - enum_read: HSIRDYR - name: HSITRIM description: Internal High Speed clock trimming bit_offset: 3 @@ -876,12 +856,10 @@ fieldset/CR: description: External High Speed clock ready flag bit_offset: 17 bit_size: 1 - enum_read: HSIRDYR - name: HSEBYP description: External High Speed clock Bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: CSSON description: Clock Security System enable bit_offset: 19 @@ -894,7 +872,6 @@ fieldset/CR: description: PLL clock ready flag bit_offset: 25 bit_size: 1 - enum_read: HSIRDYR fieldset/CSR: description: Control/status register (RCC_CSR) fields: @@ -906,7 +883,6 @@ fieldset/CSR: description: Internal low speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR - name: V18PWRRSTF description: Reset flag of the 1.8 V domain bit_offset: 23 @@ -915,7 +891,6 @@ fieldset/CSR: description: Remove reset flag bit_offset: 24 bit_size: 1 - enum_write: RMVFW - name: OBLRSTF description: Option byte loader reset flag bit_offset: 25 @@ -1010,21 +985,6 @@ enum/CECSW: - name: LSE description: LSE clock selected as CEC clock source value: 1 -enum/CSSCW: - bit_size: 1 - variants: - - name: Clear - description: Clear CSSF flag - value: 1 -enum/CSSFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Interrupted - description: Clock security interrupt caused by HSE clock failure - value: 1 enum/HPRE: bit_size: 4 variants: @@ -1055,24 +1015,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/ICSW: bit_size: 1 variants: @@ -1091,15 +1033,6 @@ enum/ISSRC: - name: CKIN description: External clock mapped on the I2S_CKIN pin used as I2S clock source value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 enum/LSEDRV: bit_size: 2 variants: @@ -1115,48 +1048,6 @@ enum/LSEDRV: - name: High description: High drive capacity value: 3 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSIRDYCW: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/LSIRDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/LSIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCO: bit_size: 3 variants: @@ -1358,12 +1249,6 @@ enum/PREDIV: - name: Div16 description: PREDIV input clock divided by 16 value: 15 -enum/RMVFW: - bit_size: 1 - variants: - - name: Clear - description: Clears the reset flag - value: 1 enum/RTCSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 7be0093..bbbbc59 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1190,12 +1190,10 @@ fieldset/BDCR: description: External low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: External low-speed oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: RTCSEL description: RTC clock source selection bit_offset: 8 @@ -1286,117 +1284,94 @@ fieldset/CIR: description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - enum_read: PLLISRDYFR - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - enum_read: PLLISRDYFR - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - enum_read: PLLISRDYFR - name: HSERDYF description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - enum_read: PLLISRDYFR - name: PLLRDYF description: Main PLL (PLL) ready interrupt flag bit_offset: 4 bit_size: 1 - enum_read: PLLISRDYFR - name: PLLI2SRDYF description: PLLI2S ready interrupt flag bit_offset: 5 bit_size: 1 - enum_read: PLLISRDYFR - name: CSSF description: Clock security system interrupt flag bit_offset: 7 bit_size: 1 - enum_read: CSSFR - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 8 bit_size: 1 - enum: PLLISRDYIE - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 9 bit_size: 1 - enum: PLLISRDYIE - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 10 bit_size: 1 - enum: PLLISRDYIE - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 11 bit_size: 1 - enum: PLLISRDYIE - name: PLLRDYIE description: Main PLL (PLL) ready interrupt enable bit_offset: 12 bit_size: 1 - enum: PLLISRDYIE - name: PLLI2SRDYIE description: PLLI2S ready interrupt enable bit_offset: 13 bit_size: 1 - enum: PLLISRDYIE - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 16 bit_size: 1 - enum_write: PLLISRDYCW - name: LSERDYC description: LSE ready interrupt clear bit_offset: 17 bit_size: 1 - enum_write: PLLISRDYCW - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 18 bit_size: 1 - enum_write: PLLISRDYCW - name: HSERDYC description: HSE ready interrupt clear bit_offset: 19 bit_size: 1 - enum_write: PLLISRDYCW - name: PLLRDYC description: Main PLL(PLL) ready interrupt clear bit_offset: 20 bit_size: 1 - enum_write: PLLISRDYCW - name: PLLI2SRDYC description: PLLI2S ready interrupt clear bit_offset: 21 bit_size: 1 - enum_write: PLLISRDYCW - name: CSSC description: Clock security system interrupt clear bit_offset: 23 bit_size: 1 - enum_write: CSSCW - name: PLLSAIRDYF description: PLLSAI ready interrupt flag bit_offset: 6 bit_size: 1 - enum_read: PLLSAIRDYFR - name: PLLSAIRDYIE description: PLLSAI Ready Interrupt Enable bit_offset: 14 bit_size: 1 - enum: PLLSAIRDYIE - name: PLLSAIRDYC description: PLLSAI Ready Interrupt Clear bit_offset: 22 bit_size: 1 - enum_write: PLLSAIRDYCW fieldset/CKGATENR: description: clocks gated enable register fields: @@ -1443,7 +1418,6 @@ fieldset/CR: description: Internal high-speed clock ready flag bit_offset: 1 bit_size: 1 - enum_read: PLLISRDYR - name: HSITRIM description: Internal high-speed clock trimming bit_offset: 3 @@ -1460,12 +1434,10 @@ fieldset/CR: description: HSE clock ready flag bit_offset: 17 bit_size: 1 - enum_read: PLLISRDYR - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: CSSON description: Clock security system enable bit_offset: 19 @@ -1478,7 +1450,6 @@ fieldset/CR: description: Main PLL (PLL) clock ready flag bit_offset: 25 bit_size: 1 - enum_read: PLLISRDYR - name: PLLI2SON description: PLLI2S enable bit_offset: 26 @@ -1487,7 +1458,6 @@ fieldset/CR: description: PLLI2S clock ready flag bit_offset: 27 bit_size: 1 - enum_read: PLLISRDYR - name: PLLSAION description: PLLSAI enable bit_offset: 28 @@ -1496,7 +1466,6 @@ fieldset/CR: description: PLLSAI clock ready flag bit_offset: 29 bit_size: 1 - enum_read: PLLISRDYR fieldset/CSR: description: clock control & status register fields: @@ -1508,47 +1477,38 @@ fieldset/CSR: description: Internal low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR - name: RMVF description: Remove reset flag bit_offset: 24 bit_size: 1 - enum_write: RMVFW - name: BORRSTF description: BOR reset flag bit_offset: 25 bit_size: 1 - enum_read: LPWRRSTFR - name: PADRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 - enum_read: LPWRRSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 - enum_read: LPWRRSTFR - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - enum_read: LPWRRSTFR - name: WDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 - enum_read: LPWRRSTFR - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - enum_read: LPWRRSTFR - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 - enum_read: LPWRRSTFR fieldset/DCKCFGR: description: Dedicated Clock Configuration Register fields: @@ -1818,21 +1778,6 @@ enum/CKMSEL: - name: PLLSAI description: 48MHz clock from PLLSAI is selected value: 1 -enum/CSSCW: - bit_size: 1 - variants: - - name: Clear - description: Clear CSSF flag - value: 1 -enum/CSSFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Interrupted - description: Clock security interrupt caused by HSE clock failure - value: 1 enum/DSISEL: bit_size: 1 variants: @@ -1884,24 +1829,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/I2S1SRC: bit_size: 2 variants: @@ -1950,24 +1877,6 @@ enum/LPTIMSEL: - name: LSE description: LSE clock is selected as LPTILM1 clock value: 3 -enum/LPWRRSTFR: - bit_size: 1 - variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 enum/LSEMOD: bit_size: 1 variants: @@ -1977,24 +1886,6 @@ enum/LSEMOD: - name: High description: LSE oscillator high drive mode selection value: 1 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCO1: bit_size: 2 variants: @@ -2355,39 +2246,6 @@ enum/PLLISP: - name: Div8 description: PLL*P=8 value: 3 -enum/PLLISRDYCW: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/PLLISRDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/PLLISRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/PLLISRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/PLLISSRC: bit_size: 1 variants: @@ -2541,30 +2399,6 @@ enum/PLLSAIP: - name: Div8 description: PLL*P=8 value: 3 -enum/PLLSAIRDYCW: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/PLLSAIRDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/PLLSAIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 enum/PLLSRC: bit_size: 1 variants: @@ -2592,12 +2426,6 @@ enum/PPRE: - name: Div16 description: HCLK divided by 16 value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - name: Clear - description: Clears the reset flag - value: 1 enum/RTCSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml index 34e6227..299afe2 100644 --- a/data/registers/rcc_f410.yaml +++ b/data/registers/rcc_f410.yaml @@ -476,12 +476,10 @@ fieldset/BDCR: description: External low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: External low-speed oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: RTCSEL description: RTC clock source selection bit_offset: 8 @@ -562,92 +560,74 @@ fieldset/CIR: description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - enum_read: PLLRDYFR - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - enum_read: PLLRDYFR - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - enum_read: PLLRDYFR - name: HSERDYF description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - enum_read: PLLRDYFR - name: PLLRDYF description: Main PLL (PLL) ready interrupt flag bit_offset: 4 bit_size: 1 - enum_read: PLLRDYFR - name: CSSF description: Clock security system interrupt flag bit_offset: 7 bit_size: 1 - enum_read: CSSFR - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 8 bit_size: 1 - enum: PLLRDYIE - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 9 bit_size: 1 - enum: PLLRDYIE - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 10 bit_size: 1 - enum: PLLRDYIE - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 11 bit_size: 1 - enum: PLLRDYIE - name: PLLRDYIE description: Main PLL (PLL) ready interrupt enable bit_offset: 12 bit_size: 1 - enum: PLLRDYIE - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 16 bit_size: 1 - enum_write: PLLISRDYCW - name: LSERDYC description: LSE ready interrupt clear bit_offset: 17 bit_size: 1 - enum_write: PLLISRDYCW - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 18 bit_size: 1 - enum_write: PLLISRDYCW - name: HSERDYC description: HSE ready interrupt clear bit_offset: 19 bit_size: 1 - enum_write: PLLISRDYCW - name: PLLRDYC description: Main PLL(PLL) ready interrupt clear bit_offset: 20 bit_size: 1 - enum_write: PLLISRDYCW - name: PLLI2SRDYC description: PLLI2S ready interrupt clear bit_offset: 21 bit_size: 1 - enum_write: PLLISRDYCW - name: CSSC description: Clock security system interrupt clear bit_offset: 23 bit_size: 1 - enum_write: CSSCW fieldset/CR: description: clock control register fields: @@ -659,7 +639,6 @@ fieldset/CR: description: Internal high-speed clock ready flag bit_offset: 1 bit_size: 1 - enum_read: PLLRDYR - name: HSITRIM description: Internal high-speed clock trimming bit_offset: 3 @@ -676,12 +655,10 @@ fieldset/CR: description: HSE clock ready flag bit_offset: 17 bit_size: 1 - enum_read: PLLRDYR - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: CSSON description: Clock security system enable bit_offset: 19 @@ -694,7 +671,6 @@ fieldset/CR: description: Main PLL (PLL) clock ready flag bit_offset: 25 bit_size: 1 - enum_read: PLLRDYR fieldset/CSR: description: clock control & status register fields: @@ -706,47 +682,38 @@ fieldset/CSR: description: Internal low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR - name: RMVF description: Remove reset flag bit_offset: 24 bit_size: 1 - enum_write: RMVFW - name: BORRSTF description: BOR reset flag bit_offset: 25 bit_size: 1 - enum_read: LPWRRSTFR - name: PADRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 - enum_read: LPWRRSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 - enum_read: LPWRRSTFR - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - enum_read: LPWRRSTFR - name: WDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 - enum_read: LPWRRSTFR - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - enum_read: LPWRRSTFR - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 - enum_read: LPWRRSTFR fieldset/DCKCFGR: description: DCKCFGR register fields: @@ -822,21 +789,6 @@ fieldset/SSCGR: description: Spread spectrum modulation enable bit_offset: 31 bit_size: 1 -enum/CSSCW: - bit_size: 1 - variants: - - name: Clear - description: Clear CSSF flag - value: 1 -enum/CSSFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Interrupted - description: Clock security interrupt caused by HSE clock failure - value: 1 enum/FMPICSEL: bit_size: 2 variants: @@ -879,15 +831,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 enum/ISSRC: bit_size: 2 variants: @@ -915,42 +858,6 @@ enum/LPTIMSEL: - name: LSE description: LSE clock is selected as LPTILM1 clock value: 3 -enum/LPWRRSTFR: - bit_size: 1 - variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCO1: bit_size: 2 variants: @@ -999,12 +906,6 @@ enum/MCOPRE: - name: Div5 description: Division by 5 value: 7 -enum/PLLISRDYCW: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 enum/PLLP: bit_size: 2 variants: @@ -1020,33 +921,6 @@ enum/PLLP: - name: Div8 description: PLLP=8 value: 3 -enum/PLLRDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/PLLRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/PLLRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/PLLSRC: bit_size: 1 variants: @@ -1074,12 +948,6 @@ enum/PPRE: - name: Div16 description: HCLK divided by 16 value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - name: Clear - description: Clears the reset flag - value: 1 enum/RTCSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index 59a9e85..748795e 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -1182,12 +1182,10 @@ fieldset/BDCR: description: External low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: External low-speed oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: LSEDRV description: LSE oscillator drive capability bit_offset: 3 @@ -1270,117 +1268,94 @@ fieldset/CIR: description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - enum_read: LSIRDYFR - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - enum_read: LSIRDYFR - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - enum_read: LSIRDYFR - name: HSERDYF description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - enum_read: LSIRDYFR - name: PLLRDYF description: Main PLL (PLL) ready interrupt flag bit_offset: 4 bit_size: 1 - enum_read: LSIRDYFR - name: PLLI2SRDYF description: PLLI2S ready interrupt flag bit_offset: 5 bit_size: 1 - enum_read: LSIRDYFR - name: PLLSAIRDYF description: PLLSAI ready interrupt flag bit_offset: 6 bit_size: 1 - enum_read: LSIRDYFR - name: CSSF description: Clock security system interrupt flag bit_offset: 7 bit_size: 1 - enum_read: CSSFR - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 8 bit_size: 1 - enum: LSIRDYIE - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 9 bit_size: 1 - enum: LSIRDYIE - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 10 bit_size: 1 - enum: LSIRDYIE - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 11 bit_size: 1 - enum: LSIRDYIE - name: PLLRDYIE description: Main PLL (PLL) ready interrupt enable bit_offset: 12 bit_size: 1 - enum: LSIRDYIE - name: PLLI2SRDYIE description: PLLI2S ready interrupt enable bit_offset: 13 bit_size: 1 - enum: LSIRDYIE - name: PLLSAIRDYIE description: PLLSAI Ready Interrupt Enable bit_offset: 14 bit_size: 1 - enum: LSIRDYIE - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 16 bit_size: 1 - enum_write: LSIRDYCW - name: LSERDYC description: LSE ready interrupt clear bit_offset: 17 bit_size: 1 - enum_write: LSIRDYCW - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 18 bit_size: 1 - enum_write: LSIRDYCW - name: HSERDYC description: HSE ready interrupt clear bit_offset: 19 bit_size: 1 - enum_write: LSIRDYCW - name: PLLRDYC description: Main PLL(PLL) ready interrupt clear bit_offset: 20 bit_size: 1 - enum_write: LSIRDYCW - name: PLLI2SRDYC description: PLLI2S ready interrupt clear bit_offset: 21 bit_size: 1 - enum_write: LSIRDYCW - name: PLLSAIRDYC description: PLLSAI Ready Interrupt Clear bit_offset: 22 bit_size: 1 - enum_write: LSIRDYCW - name: CSSC description: Clock security system interrupt clear bit_offset: 23 bit_size: 1 - enum_write: CSSCW fieldset/CR: description: clock control register fields: @@ -1392,7 +1367,6 @@ fieldset/CR: description: Internal high-speed clock ready flag bit_offset: 1 bit_size: 1 - enum_read: HSIRDYR - name: HSITRIM description: Internal high-speed clock trimming bit_offset: 3 @@ -1409,12 +1383,10 @@ fieldset/CR: description: HSE clock ready flag bit_offset: 17 bit_size: 1 - enum_read: HSIRDYR - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: CSSON description: Clock security system enable bit_offset: 19 @@ -1427,7 +1399,6 @@ fieldset/CR: description: Main PLL (PLL) clock ready flag bit_offset: 25 bit_size: 1 - enum_read: HSIRDYR - name: PLLI2SON description: PLLI2S enable bit_offset: 26 @@ -1436,7 +1407,6 @@ fieldset/CR: description: PLLI2S clock ready flag bit_offset: 27 bit_size: 1 - enum_read: HSIRDYR - name: PLLSAION description: PLLSAI enable bit_offset: 28 @@ -1445,7 +1415,6 @@ fieldset/CR: description: PLLSAI clock ready flag bit_offset: 29 bit_size: 1 - enum_read: HSIRDYR fieldset/CSR: description: clock control & status register fields: @@ -1457,47 +1426,38 @@ fieldset/CSR: description: Internal low-speed oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR - name: RMVF description: Remove reset flag bit_offset: 24 bit_size: 1 - enum_write: RMVFW - name: BORRSTF description: BOR reset flag bit_offset: 25 bit_size: 1 - enum_read: BORRSTFR - name: PADRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 - enum_read: BORRSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 - enum_read: BORRSTFR - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - enum_read: BORRSTFR - name: WDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 - enum_read: BORRSTFR - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - enum_read: BORRSTFR - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 - enum_read: BORRSTFR fieldset/DCKCFGR1: description: dedicated clocks configuration register fields: @@ -1732,15 +1692,6 @@ enum/ADFSDMSEL: - name: SAI2 description: SAI2 clock selected as DFSDM1 Audio clock source value: 1 -enum/BORRSTFR: - bit_size: 1 - variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 enum/CECSEL: bit_size: 1 variants: @@ -1759,21 +1710,6 @@ enum/CKMSEL: - name: PLLSAI description: 48MHz clock from PLLSAI is selected value: 1 -enum/CSSCW: - bit_size: 1 - variants: - - name: Clear - description: Clear CSSF flag - value: 1 -enum/CSSFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock security interrupt caused by HSE clock failure - value: 0 - - name: Interrupted - description: Clock security interrupt caused by HSE clock failure - value: 1 enum/DFSDMSEL: bit_size: 1 variants: @@ -1822,24 +1758,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/ICSEL: bit_size: 2 variants: @@ -1876,15 +1794,6 @@ enum/LPTIMSEL: - name: LSE description: LSE clock is selected as LPTILM1 clock value: 3 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 enum/LSEDRV: bit_size: 2 variants: @@ -1900,48 +1809,6 @@ enum/LSEDRV: - name: High description: High drive capacity value: 3 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSIRDYCW: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/LSIRDYFR: - bit_size: 1 - variants: - - name: NotInterrupted - description: No clock ready interrupt - value: 0 - - name: Interrupted - description: Clock ready interrupt - value: 1 -enum/LSIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCO1: bit_size: 2 variants: @@ -2275,12 +2142,6 @@ enum/PPRE: - name: Div16 description: HCLK divided by 16 value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - name: Clear - description: Clears the reset flag - value: 1 enum/RTCSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index 4fd26a1..59948dd 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -1034,17 +1034,6 @@ fieldset/CSR: description: Low-power reset flag bit_offset: 31 bit_size: 1 -fieldset/ICSCR: - description: Internal clock sources calibration register - fields: - - name: HSICAL - description: HSI16 clock calibration - bit_offset: 0 - bit_size: 8 - - name: HSITRIM - description: HSI16 clock trimming - bit_offset: 8 - bit_size: 7 fieldset/GPIOENR: description: GPIO clock enable register fields: @@ -1114,6 +1103,17 @@ fieldset/GPIOSMENR: description: I/O port F clock enable during Sleep mode bit_offset: 5 bit_size: 1 +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - name: HSICAL + description: HSI16 clock calibration + bit_offset: 0 + bit_size: 8 + - name: HSITRIM + description: HSI16 clock trimming + bit_offset: 8 + bit_size: 7 fieldset/PLLSYSCFGR: description: PLL configuration register fields: diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 1d1af97..f4ef2d6 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -1742,12 +1742,10 @@ fieldset/BDCR: description: LSE oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: LSE oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: LSEDRV description: LSE oscillator driving capability bit_offset: 3 @@ -1761,7 +1759,6 @@ fieldset/BDCR: description: LSE clock security system failure detection bit_offset: 6 bit_size: 1 - enum_read: LSECSSDR - name: RTCSEL description: RTC clock source selection bit_offset: 8 @@ -2716,57 +2713,46 @@ fieldset/C1_RSR: description: Remove reset flag bit_offset: 16 bit_size: 1 - enum: C_RSR_RMVF - name: CPURSTF description: CPU reset flag bit_offset: 17 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: D1RSTF description: D1 domain power switch reset flag bit_offset: 19 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: D2RSTF description: D2 domain power switch reset flag bit_offset: 20 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: BORRSTF description: BOR reset flag bit_offset: 21 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: PINRSTF description: Pin reset flag (NRST) bit_offset: 22 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 23 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: SFTRSTF description: System reset from CPU reset flag bit_offset: 24 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: IWDG1RSTF description: Independent Watchdog reset flag bit_offset: 26 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: WWDG1RSTF description: Window Watchdog reset flag bit_offset: 28 bit_size: 1 - enum_read: C_RSR_CPURSTFR - name: LPWRRSTF description: Reset due to illegal D1 DStandby or CPU CStop flag bit_offset: 30 bit_size: 1 - enum_read: C_RSR_CPURSTFR fieldset/CFGR: description: RCC Clock Configuration Register fields: @@ -2829,22 +2815,18 @@ fieldset/CICR: description: LSI ready Interrupt Clear bit_offset: 0 bit_size: 1 - enum: LSIRDYC - name: LSERDYC description: LSE ready Interrupt Clear bit_offset: 1 bit_size: 1 - enum: LSIRDYC - name: HSIRDYC description: HSI ready Interrupt Clear bit_offset: 2 bit_size: 1 - enum: LSIRDYC - name: HSERDYC description: HSE ready Interrupt Clear bit_offset: 3 bit_size: 1 - enum: LSIRDYC - name: HSE_ready_Interrupt_Clear description: CSI ready Interrupt Clear bit_offset: 4 @@ -2853,7 +2835,6 @@ fieldset/CICR: description: RC48 ready Interrupt Clear bit_offset: 5 bit_size: 1 - enum: LSIRDYC - name: PLLRDYC description: PLL1 ready Interrupt Clear bit_offset: 6 @@ -2861,17 +2842,14 @@ fieldset/CICR: array: len: 3 stride: 1 - enum: LSIRDYC - name: LSECSSC description: LSE clock security system Interrupt Clear bit_offset: 9 bit_size: 1 - enum: LSIRDYC - name: HSECSSC description: HSE clock security system Interrupt Clear bit_offset: 10 bit_size: 1 - enum: LSIRDYC fieldset/CIER: description: RCC Clock Source Interrupt Enable Register fields: @@ -2879,32 +2857,26 @@ fieldset/CIER: description: LSI ready Interrupt Enable bit_offset: 0 bit_size: 1 - enum: LSIRDYIE - name: LSERDYIE description: LSE ready Interrupt Enable bit_offset: 1 bit_size: 1 - enum: LSIRDYIE - name: HSIRDYIE description: HSI ready Interrupt Enable bit_offset: 2 bit_size: 1 - enum: LSIRDYIE - name: HSERDYIE description: HSE ready Interrupt Enable bit_offset: 3 bit_size: 1 - enum: LSIRDYIE - name: CSIRDYIE description: CSI ready Interrupt Enable bit_offset: 4 bit_size: 1 - enum: LSIRDYIE - name: HSI48RDYIE description: RC48 ready Interrupt Enable bit_offset: 5 bit_size: 1 - enum: LSIRDYIE - name: PLLRDYIE description: PLL1 ready Interrupt Enable bit_offset: 6 @@ -2912,12 +2884,10 @@ fieldset/CIER: array: len: 3 stride: 1 - enum: LSIRDYIE - name: LSECSSIE description: LSE clock security system Interrupt Enable bit_offset: 9 bit_size: 1 - enum: LSIRDYIE fieldset/CIFR: description: RCC Clock Source Interrupt Flag Register fields: @@ -2975,7 +2945,6 @@ fieldset/CR: description: HSI clock ready flag bit_offset: 2 bit_size: 1 - enum_read: HSIRDYR - name: HSIDIV description: HSI clock divider bit_offset: 3 @@ -2985,7 +2954,6 @@ fieldset/CR: description: HSI divider flag bit_offset: 5 bit_size: 1 - enum_read: HSIDIVFR - name: CSION description: CSI clock enable bit_offset: 7 @@ -2994,7 +2962,6 @@ fieldset/CR: description: CSI clock ready flag bit_offset: 8 bit_size: 1 - enum_read: HSIRDYR - name: CSIKERON description: CSI clock enable in Stop mode bit_offset: 9 @@ -3007,17 +2974,14 @@ fieldset/CR: description: RC48 clock ready flag bit_offset: 13 bit_size: 1 - enum_read: HSIRDYR - name: D1CKRDY description: D1 domain clocks ready flag bit_offset: 14 bit_size: 1 - enum_read: HSIRDYR - name: D2CKRDY description: D2 domain clocks ready flag bit_offset: 15 bit_size: 1 - enum_read: HSIRDYR - name: HSEON description: HSE clock enable bit_offset: 16 @@ -3026,12 +2990,10 @@ fieldset/CR: description: HSE clock ready flag bit_offset: 17 bit_size: 1 - enum_read: HSIRDYR - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: HSECSSON description: HSE Clock Security System enable bit_offset: 19 @@ -3050,7 +3012,6 @@ fieldset/CR: array: len: 3 stride: 2 - enum_read: HSIRDYR fieldset/CRRCR: description: RCC Clock Recovery RC Register fields: @@ -3080,7 +3041,6 @@ fieldset/CSR: description: LSI oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR fieldset/D1CCIPR: description: RCC Domain 1 Kernel Clock Configuration Register fields: @@ -3353,7 +3313,6 @@ fieldset/GCR: description: WWDG1 reset scope control bit_offset: 0 bit_size: 1 - enum: WWRSC - name: WW2RSC description: WWDG2 reset scope control bit_offset: 1 @@ -3549,52 +3508,42 @@ fieldset/RSR: description: CPU reset flag bit_offset: 17 bit_size: 1 - enum_read: RSR_CPURSTFR - name: D1RSTF description: D1 domain power switch reset flag bit_offset: 19 bit_size: 1 - enum_read: RSR_CPURSTFR - name: D2RSTF description: D2 domain power switch reset flag bit_offset: 20 bit_size: 1 - enum_read: RSR_CPURSTFR - name: BORRSTF description: BOR reset flag bit_offset: 21 bit_size: 1 - enum_read: RSR_CPURSTFR - name: PINRSTF description: Pin reset flag (NRST) bit_offset: 22 bit_size: 1 - enum_read: RSR_CPURSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 23 bit_size: 1 - enum_read: RSR_CPURSTFR - name: SFTRSTF description: System reset from CPU reset flag bit_offset: 24 bit_size: 1 - enum_read: RSR_CPURSTFR - name: IWDG1RSTF description: Independent Watchdog reset flag bit_offset: 26 bit_size: 1 - enum_read: RSR_CPURSTFR - name: WWDG1RSTF description: Window Watchdog reset flag bit_offset: 28 bit_size: 1 - enum_read: RSR_CPURSTFR - name: LPWRRSTF description: Reset due to illegal D1 DStandby or CPU CStop flag bit_offset: 30 bit_size: 1 - enum_read: RSR_CPURSTFR enum/ADCSEL: bit_size: 2 variants: @@ -3631,24 +3580,6 @@ enum/CKPERSEL: - name: HSE description: HSE selected as peripheral clock value: 2 -enum/C_RSR_CPURSTFR: - bit_size: 1 - variants: - - name: NoResetOccoured - description: No reset occoured for block - value: 0 - - name: ResetOccourred - description: Reset occoured for block - value: 1 -enum/C_RSR_RMVF: - bit_size: 1 - variants: - - name: NotActive - description: Not clearing the the reset flags - value: 0 - - name: Clear - description: Clear the reset flags - value: 1 enum/DFSDMSEL: bit_size: 1 variants: @@ -3940,15 +3871,6 @@ enum/HRTIMSEL: - name: C_CK description: The HRTIM prescaler clock source is the CPU clock (c_ck) value: 1 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 enum/HSIDIV: bit_size: 2 variants: @@ -3964,24 +3886,6 @@ enum/HSIDIV: - name: Div8 description: Division by 8 value: 3 -enum/HSIDIVFR: - bit_size: 1 - variants: - - name: NotPropagated - description: New HSIDIV ratio has not yet propagated to hsi_ck - value: 0 - - name: Propagated - description: HSIDIV ratio has propagated to hsi_ck - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/I2C1235SEL: bit_size: 2 variants: @@ -4075,24 +3979,6 @@ enum/LPUARTSEL: - name: LSE description: LSE selected as peripheral clock value: 5 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 -enum/LSECSSDR: - bit_size: 1 - variants: - - name: NoFailure - description: No failure detected on 32 kHz oscillator - value: 0 - - name: Failure - description: Failure detected on 32 kHz oscillator - value: 1 enum/LSEDRV: bit_size: 2 variants: @@ -4108,39 +3994,6 @@ enum/LSEDRV: - name: Highest description: Highest LSE oscillator driving capability value: 3 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSIRDYC: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/LSIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCO1: bit_size: 3 variants: @@ -4234,15 +4087,6 @@ enum/RNGSEL: - name: LSI description: LSI selected as peripheral clock value: 3 -enum/RSR_CPURSTFR: - bit_size: 1 - variants: - - name: NoResetOccoured - description: No reset occoured for block - value: 0 - - name: ResetOccourred - description: Reset occoured for block - value: 1 enum/RSR_RMVF: bit_size: 1 variants: @@ -4483,12 +4327,3 @@ enum/USBSEL: - name: HSI48 description: HSI48 selected as peripheral clock value: 3 -enum/WWRSC: - bit_size: 1 - variants: - - name: Clear - description: Clear WWDG1 scope control - value: 0 - - name: Set - description: Set WWDG1 scope control - value: 1 diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index 64c1a2f..97df91e 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -1454,12 +1454,10 @@ fieldset/BDCR: description: LSE oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: LSE oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: LSEDRV description: LSE oscillator driving capability bit_offset: 3 @@ -1473,7 +1471,6 @@ fieldset/BDCR: description: LSE clock security system failure detection bit_offset: 6 bit_size: 1 - enum_read: LSECSSDR - name: RTCSEL description: RTC clock source selection bit_offset: 8 @@ -1499,52 +1496,42 @@ fieldset/C1_RSR: description: CPU reset flag bit_offset: 17 bit_size: 1 - enum_read: CPURSTFR - name: D1RSTF description: D1 domain power switch reset flag bit_offset: 19 bit_size: 1 - enum_read: CPURSTFR - name: D2RSTF description: D2 domain power switch reset flag bit_offset: 20 bit_size: 1 - enum_read: CPURSTFR - name: BORRSTF description: BOR reset flag bit_offset: 21 bit_size: 1 - enum_read: CPURSTFR - name: PINRSTF description: Pin reset flag (NRST) bit_offset: 22 bit_size: 1 - enum_read: CPURSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 23 bit_size: 1 - enum_read: CPURSTFR - name: SFTRSTF description: System reset from CPU reset flag bit_offset: 24 bit_size: 1 - enum_read: CPURSTFR - name: IWDG1RSTF description: Independent Watchdog reset flag bit_offset: 26 bit_size: 1 - enum_read: CPURSTFR - name: WWDG1RSTF description: Window Watchdog reset flag bit_offset: 28 bit_size: 1 - enum_read: CPURSTFR - name: LPWRRSTF description: Reset due to illegal D1 DStandby or CPU CStop flag bit_offset: 30 bit_size: 1 - enum_read: CPURSTFR fieldset/CDCCIP1R: description: RCC Domain 2 Kernel Clock Configuration Register fields: @@ -1716,22 +1703,18 @@ fieldset/CICR: description: LSI ready Interrupt Clear bit_offset: 0 bit_size: 1 - enum: LSIRDYC - name: LSERDYC description: LSE ready Interrupt Clear bit_offset: 1 bit_size: 1 - enum: LSIRDYC - name: HSIRDYC description: HSI ready Interrupt Clear bit_offset: 2 bit_size: 1 - enum: LSIRDYC - name: HSERDYC description: HSE ready Interrupt Clear bit_offset: 3 bit_size: 1 - enum: LSIRDYC - name: HSE_ready_Interrupt_Clear description: CSI ready Interrupt Clear bit_offset: 4 @@ -1740,7 +1723,6 @@ fieldset/CICR: description: RC48 ready Interrupt Clear bit_offset: 5 bit_size: 1 - enum: LSIRDYC - name: PLLRDYC description: PLL1 ready Interrupt Clear bit_offset: 6 @@ -1748,17 +1730,14 @@ fieldset/CICR: array: len: 3 stride: 1 - enum: LSIRDYC - name: LSECSSC description: LSE clock security system Interrupt Clear bit_offset: 9 bit_size: 1 - enum: LSIRDYC - name: HSECSSC description: HSE clock security system Interrupt Clear bit_offset: 10 bit_size: 1 - enum: LSIRDYC fieldset/CIER: description: RCC Clock Source Interrupt Enable Register fields: @@ -1766,32 +1745,26 @@ fieldset/CIER: description: LSI ready Interrupt Enable bit_offset: 0 bit_size: 1 - enum: LSIRDYIE - name: LSERDYIE description: LSE ready Interrupt Enable bit_offset: 1 bit_size: 1 - enum: LSIRDYIE - name: HSIRDYIE description: HSI ready Interrupt Enable bit_offset: 2 bit_size: 1 - enum: LSIRDYIE - name: HSERDYIE description: HSE ready Interrupt Enable bit_offset: 3 bit_size: 1 - enum: LSIRDYIE - name: CSIRDYIE description: CSI ready Interrupt Enable bit_offset: 4 bit_size: 1 - enum: LSIRDYIE - name: HSI48RDYIE description: RC48 ready Interrupt Enable bit_offset: 5 bit_size: 1 - enum: LSIRDYIE - name: PLLRDYIE description: PLL1 ready Interrupt Enable bit_offset: 6 @@ -1799,12 +1772,10 @@ fieldset/CIER: array: len: 3 stride: 1 - enum: LSIRDYIE - name: LSECSSIE description: LSE clock security system Interrupt Enable bit_offset: 9 bit_size: 1 - enum: LSIRDYIE fieldset/CIFR: description: RCC Clock Source Interrupt Flag Register fields: @@ -1862,7 +1833,6 @@ fieldset/CR: description: HSI clock ready flag bit_offset: 2 bit_size: 1 - enum_read: HSIRDYR - name: HSIDIV description: HSI clock divider bit_offset: 3 @@ -1872,7 +1842,6 @@ fieldset/CR: description: HSI divider flag bit_offset: 5 bit_size: 1 - enum_read: HSIDIVFR - name: CSION description: CSI clock enable bit_offset: 7 @@ -1881,7 +1850,6 @@ fieldset/CR: description: CSI clock ready flag bit_offset: 8 bit_size: 1 - enum_read: HSIRDYR - name: CSIKERON description: CSI clock enable in Stop mode bit_offset: 9 @@ -1894,17 +1862,14 @@ fieldset/CR: description: RC48 clock ready flag bit_offset: 13 bit_size: 1 - enum_read: HSIRDYR - name: D1CKRDY description: D1 domain clocks ready flag bit_offset: 14 bit_size: 1 - enum_read: HSIRDYR - name: D2CKRDY description: D2 domain clocks ready flag bit_offset: 15 bit_size: 1 - enum_read: HSIRDYR - name: HSEON description: HSE clock enable bit_offset: 16 @@ -1913,12 +1878,10 @@ fieldset/CR: description: HSE clock ready flag bit_offset: 17 bit_size: 1 - enum_read: HSIRDYR - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: HSECSSON description: HSE Clock Security System enable bit_offset: 19 @@ -1937,7 +1900,6 @@ fieldset/CR: array: len: 3 stride: 2 - enum_read: HSIRDYR fieldset/CRRCR: description: RCC Clock Recovery RC Register fields: @@ -1967,7 +1929,6 @@ fieldset/CSR: description: LSI oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR fieldset/D1CFGR: description: RCC Domain 1 Clock Configuration Register fields: @@ -2077,7 +2038,6 @@ fieldset/GCR: description: WWDG1 reset scope control bit_offset: 0 bit_size: 1 - enum: WWRSC fieldset/HSICFGR: description: RCC HSI configuration register fields: @@ -2302,15 +2262,6 @@ enum/CKPERSEL: - name: HSE description: HSE selected as peripheral clock value: 2 -enum/CPURSTFR: - bit_size: 1 - variants: - - name: NoResetOccoured - description: No reset occoured for block - value: 0 - - name: ResetOccourred - description: Reset occoured for block - value: 1 enum/DFSDMSEL: bit_size: 1 variants: @@ -2602,15 +2553,6 @@ enum/HRTIMSEL: - name: C_CK description: The HRTIM prescaler clock source is the CPU clock (c_ck) value: 1 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 enum/HSIDIV: bit_size: 2 variants: @@ -2626,24 +2568,6 @@ enum/HSIDIV: - name: Div8 description: Division by 8 value: 3 -enum/HSIDIVFR: - bit_size: 1 - variants: - - name: NotPropagated - description: New HSIDIV ratio has not yet propagated to hsi_ck - value: 0 - - name: Propagated - description: HSIDIV ratio has propagated to hsi_ck - value: 1 -enum/HSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/I2C123SEL: bit_size: 2 variants: @@ -2737,24 +2661,6 @@ enum/LPUARTSEL: - name: LSE description: LSE selected as peripheral clock value: 5 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 -enum/LSECSSDR: - bit_size: 1 - variants: - - name: NoFailure - description: No failure detected on 32 kHz oscillator - value: 0 - - name: Failure - description: Failure detected on 32 kHz oscillator - value: 1 enum/LSEDRV: bit_size: 2 variants: @@ -2770,39 +2676,6 @@ enum/LSEDRV: - name: Highest description: Highest LSE oscillator driving capability value: 3 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSIRDYC: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag - value: 1 -enum/LSIRDYIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt disabled - value: 0 - - name: Enabled - description: Interrupt enabled - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCO1: bit_size: 3 variants: @@ -3136,12 +3009,3 @@ enum/USBSEL: - name: HSI48 description: HSI48 selected as peripheral clock value: 3 -enum/WWRSC: - bit_size: 1 - variants: - - name: Clear - description: Clear WWDG1 scope control - value: 0 - - name: Set - description: Set WWDG1 scope control - value: 1 diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index 1e73dea..2b990b1 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -880,30 +880,6 @@ fieldset/CSR: description: Low-power reset flag bit_offset: 31 bit_size: 1 -fieldset/ICSCR: - description: Internal clock sources calibration register - fields: - - name: HSI16CAL - description: nternal high speed clock calibration - bit_offset: 0 - bit_size: 8 - - name: HSI16TRIM - description: High speed internal clock trimming - bit_offset: 8 - bit_size: 5 - - name: MSIRANGE - description: MSI clock ranges - bit_offset: 13 - bit_size: 3 - enum: MSIRANGE - - name: MSICAL - description: MSI clock calibration - bit_offset: 16 - bit_size: 8 - - name: MSITRIM - description: MSI clock trimming - bit_offset: 24 - bit_size: 8 fieldset/GPIOENR: description: GPIO clock enable register fields: @@ -985,6 +961,30 @@ fieldset/GPIOSMEN: description: Port H clock enable during Sleep mode bit_offset: 7 bit_size: 1 +fieldset/ICSCR: + description: Internal clock sources calibration register + fields: + - name: HSI16CAL + description: nternal high speed clock calibration + bit_offset: 0 + bit_size: 8 + - name: HSI16TRIM + description: High speed internal clock trimming + bit_offset: 8 + bit_size: 5 + - name: MSIRANGE + description: MSI clock ranges + bit_offset: 13 + bit_size: 3 + enum: MSIRANGE + - name: MSICAL + description: MSI clock calibration + bit_offset: 16 + bit_size: 8 + - name: MSITRIM + description: MSI clock trimming + bit_offset: 24 + bit_size: 8 enum/HPRE: bit_size: 4 variants: @@ -1042,21 +1042,6 @@ enum/LPTIMSEL: - name: LSE description: LSE clock selected as Timer clock value: 3 -enum/UARTSEL: - bit_size: 2 - variants: - - name: APB - description: APB clock selected as peripheral clock - value: 0 - - name: SYSTEM - description: System clock selected as peripheral clock - value: 1 - - name: HSI16 - description: HSI16 clock selected as peripheral clock - value: 2 - - name: LSE - description: LSE clock selected as peripheral clock - value: 3 enum/LSEDRV: bit_size: 2 variants: @@ -1267,3 +1252,18 @@ enum/SW: - name: PLL description: PLL used as system clock value: 3 +enum/UARTSEL: + bit_size: 2 + variants: + - name: APB + description: APB clock selected as peripheral clock + value: 0 + - name: SYSTEM + description: System clock selected as peripheral clock + value: 1 + - name: HSI16 + description: HSI16 clock selected as peripheral clock + value: 2 + - name: LSE + description: LSE clock selected as peripheral clock + value: 3 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index b0e9094..49e426c 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1273,12 +1273,10 @@ fieldset/BDCR: description: LSE oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSERDYR - name: LSEBYP description: LSE oscillator bypass bit_offset: 2 bit_size: 1 - enum: LSEBYP - name: LSEDRV description: " SE oscillator drive capability " bit_offset: 3 @@ -1292,7 +1290,6 @@ fieldset/BDCR: description: LSECSSD bit_offset: 6 bit_size: 1 - enum_read: LSECSSDR - name: LSESYSEN description: LSESYSEN bit_offset: 7 @@ -1306,7 +1303,6 @@ fieldset/BDCR: description: LSESYSRDY bit_offset: 11 bit_size: 1 - enum_read: LSESYSRDYR - name: RTCEN description: RTC clock enable bit_offset: 15 @@ -1609,7 +1605,6 @@ fieldset/CR: description: MSI clock ready flag bit_offset: 1 bit_size: 1 - enum_read: PLLSAIRDYR - name: MSIPLLEN description: MSI clock PLL enable bit_offset: 2 @@ -1634,7 +1629,6 @@ fieldset/CR: description: HSI clock ready flag bit_offset: 10 bit_size: 1 - enum_read: PLLSAIRDYR - name: HSIASFS description: " HSI automatic start from Stop " bit_offset: 11 @@ -1647,12 +1641,10 @@ fieldset/CR: description: HSE clock ready flag bit_offset: 17 bit_size: 1 - enum_read: PLLSAIRDYR - name: HSEBYP description: " HSE crystal oscillator bypass " bit_offset: 18 bit_size: 1 - enum: HSEBYP - name: CSSON description: " Clock security system enable " bit_offset: 19 @@ -1665,7 +1657,6 @@ fieldset/CR: description: Main PLL clock ready flag bit_offset: 25 bit_size: 1 - enum_read: PLLSAIRDYR - name: PLLSAI1ON description: SAI1 PLL enable bit_offset: 26 @@ -1674,7 +1665,6 @@ fieldset/CR: description: SAI1 PLL clock ready flag bit_offset: 27 bit_size: 1 - enum_read: PLLSAIRDYR - name: PLLSAI2ON description: SAI2 PLL enable bit_offset: 28 @@ -1683,7 +1673,6 @@ fieldset/CR: description: SAI2 PLL clock ready flag bit_offset: 29 bit_size: 1 - enum_read: PLLSAIRDYR - name: PRIV description: PRIV bit_offset: 31 @@ -1714,7 +1703,6 @@ fieldset/CSR: description: LSI oscillator ready bit_offset: 1 bit_size: 1 - enum_read: LSIRDYR - name: LSIPREDIV description: LSIPREDIV bit_offset: 4 @@ -1727,42 +1715,34 @@ fieldset/CSR: description: Remove reset flag bit_offset: 23 bit_size: 1 - enum_write: RMVFW - name: OBLRSTF description: " Option byte loader reset flag " bit_offset: 25 bit_size: 1 - enum_read: LPWRSTFR - name: PINRSTF description: Pin reset flag bit_offset: 26 bit_size: 1 - enum_read: LPWRSTFR - name: BORRSTF description: BOR flag bit_offset: 27 bit_size: 1 - enum_read: LPWRSTFR - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - enum_read: LPWRSTFR - name: IWWDGRSTF description: " Independent window watchdog reset flag " bit_offset: 29 bit_size: 1 - enum_read: LPWRSTFR - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - enum_read: LPWRSTFR - name: LPWRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 - enum_read: LPWRSTFR fieldset/ICSCR: description: " Internal clock sources calibration register " fields: @@ -2035,24 +2015,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/HSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: HSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: HSE crystal oscillator bypassed with external clock - value: 1 -enum/LPWRSTFR: - bit_size: 1 - variants: - - name: NoReset - description: No reset has occured - value: 0 - - name: Reset - description: A reset has occured - value: 1 enum/LSCOSEL: bit_size: 1 variants: @@ -2062,24 +2024,6 @@ enum/LSCOSEL: - name: LSE description: LSE clock selected value: 1 -enum/LSEBYP: - bit_size: 1 - variants: - - name: NotBypassed - description: LSE crystal oscillator not bypassed - value: 0 - - name: Bypassed - description: LSE crystal oscillator bypassed with external clock - value: 1 -enum/LSECSSDR: - bit_size: 1 - variants: - - name: NoFailure - description: No failure detected on LSE (32 kHz oscillator) - value: 0 - - name: Failure - description: Failure detected on LSE (32 kHz oscillator) - value: 1 enum/LSEDRV: bit_size: 2 variants: @@ -2095,33 +2039,6 @@ enum/LSEDRV: - name: Higher description: "'Xtal mode' higher driving capability" value: 3 -enum/LSERDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSE oscillator not ready - value: 0 - - name: Ready - description: LSE oscillator ready - value: 1 -enum/LSESYSRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSESYS clock not ready - value: 0 - - name: Ready - description: LSESYS clock ready - value: 1 -enum/LSIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: LSI oscillator not ready - value: 0 - - name: Ready - description: LSI oscillator ready - value: 1 enum/MCOPRE: bit_size: 3 variants: @@ -2170,15 +2087,6 @@ enum/MCOSEL: - name: HSI48 description: Internal HSI48 clock selected value: 8 -enum/PLLSAIRDYR: - bit_size: 1 - variants: - - name: NotReady - description: Clock not ready - value: 0 - - name: Ready - description: Clock ready - value: 1 enum/PPRE: bit_size: 3 variants: @@ -2197,12 +2105,6 @@ enum/PPRE: - name: Div16 description: HCLK divided by 16 value: 7 -enum/RMVFW: - bit_size: 1 - variants: - - name: Clear - description: Clears the reset flag - value: 1 enum/RTCSEL: bit_size: 2 variants: