From 5ec0ad4387790f97d1e7338b4895c99386be176e Mon Sep 17 00:00:00 2001 From: chemicstry Date: Tue, 31 May 2022 20:14:33 +0300 Subject: [PATCH 01/11] Add RTC registers for all chips --- data/registers/rtc_f0.yaml | 556 ++++++++ data/registers/rtc_f1.yaml | 148 ++ data/registers/rtc_f2.yaml | 504 +++++++ data/registers/rtc_f3.yaml | 1270 +++++++++++++++++ data/registers/rtc_f4.yaml | 1135 ++++++++++++++++ data/registers/{rtc_v2.yaml => rtc_f7.yaml} | 92 +- data/registers/rtc_gx.yaml | 645 +++++++++ data/registers/rtc_h7.yaml | 1201 ++++++++++++++++ data/registers/rtc_l0.yaml | 1319 ++++++++++++++++++ data/registers/rtc_l1.yaml | 649 +++++++++ data/registers/rtc_l4.yaml | 681 ++++++++++ data/registers/rtc_l41x-l42x.yaml | 645 +++++++++ data/registers/rtc_l5.yaml | 755 ++++++++++ data/registers/rtc_u5.yaml | 813 +++++++++++ data/registers/rtc_wl.yaml | 1360 +++++++++++++++++++ stm32data/__main__.py | 18 +- 16 files changed, 11754 insertions(+), 37 deletions(-) create mode 100644 data/registers/rtc_f0.yaml create mode 100644 data/registers/rtc_f1.yaml create mode 100644 data/registers/rtc_f2.yaml create mode 100644 data/registers/rtc_f3.yaml create mode 100644 data/registers/rtc_f4.yaml rename data/registers/{rtc_v2.yaml => rtc_f7.yaml} (95%) create mode 100644 data/registers/rtc_gx.yaml create mode 100644 data/registers/rtc_h7.yaml create mode 100644 data/registers/rtc_l0.yaml create mode 100644 data/registers/rtc_l1.yaml create mode 100644 data/registers/rtc_l4.yaml create mode 100644 data/registers/rtc_l41x-l42x.yaml create mode 100644 data/registers/rtc_l5.yaml create mode 100644 data/registers/rtc_u5.yaml create mode 100644 data/registers/rtc_wl.yaml diff --git a/data/registers/rtc_f0.yaml b/data/registers/rtc_f0.yaml new file mode 100644 index 0000000..c97b18a --- /dev/null +++ b/data/registers/rtc_f0.yaml @@ -0,0 +1,556 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: "initialization and status register" + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMAR + description: alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: time-stamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: "tamper and alternate function configuration register" + byte_offset: 64 + fieldset: TAFCR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: BKPR + description: backup register + array: + len: 5 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: "Second units in BCD format." + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: "Minute units in BCD format." + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD format." + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format. + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: "Use a 16-second calibration cycle period" + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: "Use a 8-second calibration cycle period" + bit_offset: 14 + bit_size: 1 + - name: CALP + description: "Increase frequency of RTC by 488.5 ppm" + bit_offset: 15 + bit_size: 1 +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: "Time-stamp event active edge" + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: "RTC_REFIN reference clock detection enable (50 or 60 Hz)" + bit_offset: 4 + bit_size: 1 + - name: BYPSHAD + description: "Bypass the shadow registers" + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: "Wakeup timer interrupt enable" + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: "Time-stamp interrupt enable" + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: "Add 1 hour (summer time change)" + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: "Subtract 1 hour (winter time change)" + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: "Calibration output selection" + bit_offset: 19 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: "initialization and status register" + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: "Registers synchronization flag" + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMP1F + description: RTC_TAMP1 detection flag + bit_offset: 13 + bit_size: 1 + - name: TAMP2F + description: RTC_TAMP2 detection flag + bit_offset: 14 + bit_size: 1 + - name: TAMP3F + description: RTC_TAMP3 detection flag + bit_offset: 15 + bit_size: 1 + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: "Synchronous prescaler factor" + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: "Asynchronous prescaler factor" + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: "Subtract a fraction of a second" + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAFCR: + description: "tamper and alternate function configuration register" + fields: + - name: TAMP1E + description: "RTC_TAMP1 input detection enable" + bit_offset: 0 + bit_size: 1 + - name: TAMP1TRG + description: "Active level for RTC_TAMP1 input" + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP2E + description: "RTC_TAMP2 input detection enable" + bit_offset: 3 + bit_size: 1 + - name: TAMP2TRG + description: "Active level for RTC_TAMP2 input" + bit_offset: 4 + bit_size: 1 + - name: TAMP3E + description: "RTC_TAMP3 input detection enable" + bit_offset: 5 + bit_size: 1 + - name: TAMP3TRG + description: "Active level for RTC_TAMP3 input" + bit_offset: 6 + bit_size: 1 + - name: TAMPTS + description: "Activate timestamp on tamper detection event" + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + - name: TAMPFLT + description: RTC_TAMPx filter count + bit_offset: 11 + bit_size: 2 + - name: TAMP_PRCH + description: "RTC_TAMPx precharge duration" + bit_offset: 13 + bit_size: 2 + - name: TAMP_PUDIS + description: RTC_TAMPx pull-up disable + bit_offset: 15 + bit_size: 1 + - name: PC13VALUE + description: "RTC_ALARM output type/PC13 value" + bit_offset: 18 + bit_size: 1 + - name: PC13MODE + description: PC13 mode + bit_offset: 19 + bit_size: 1 + - name: PC14VALUE + description: PC14 value + bit_offset: 20 + bit_size: 1 + - name: PC14MODE + description: PC14 mode + bit_offset: 21 + bit_size: 1 + - name: PC15VALUE + description: PC15 value + bit_offset: 22 + bit_size: 1 + - name: PC15MODE + description: PC15 mode + bit_offset: 23 + bit_size: 1 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/TSDR: + description: timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: time-stamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: timestamp time register + fields: + - name: SU + description: "Second units in BCD format." + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MNU + description: "Minute units in BCD format." + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 diff --git a/data/registers/rtc_f1.yaml b/data/registers/rtc_f1.yaml new file mode 100644 index 0000000..cdc4f28 --- /dev/null +++ b/data/registers/rtc_f1.yaml @@ -0,0 +1,148 @@ +--- +block/RTC: + description: Real time clock + items: + - name: CRH + description: RTC Control Register High + byte_offset: 0 + fieldset: CRH + - name: CRL + description: RTC Control Register Low + byte_offset: 4 + fieldset: CRL + - name: PRLH + description: "RTC Prescaler Load Register High" + byte_offset: 8 + access: Write + fieldset: PRLH + - name: PRLL + description: "RTC Prescaler Load Register Low" + byte_offset: 12 + access: Write + fieldset: PRLL + - name: DIVH + description: "RTC Prescaler Divider Register High" + byte_offset: 16 + access: Read + fieldset: DIVH + - name: DIVL + description: "RTC Prescaler Divider Register Low" + byte_offset: 20 + access: Read + fieldset: DIVL + - name: CNTH + description: RTC Counter Register High + byte_offset: 24 + fieldset: CNTH + - name: CNTL + description: RTC Counter Register Low + byte_offset: 28 + fieldset: CNTL + - name: ALRH + description: RTC Alarm Register High + byte_offset: 32 + access: Write + fieldset: ALRH + - name: ALRL + description: RTC Alarm Register Low + byte_offset: 36 + access: Write + fieldset: ALRL +fieldset/ALRH: + description: RTC Alarm Register High + fields: + - name: ALRH + description: RTC alarm register high + bit_offset: 0 + bit_size: 16 +fieldset/ALRL: + description: RTC Alarm Register Low + fields: + - name: ALRL + description: RTC alarm register low + bit_offset: 0 + bit_size: 16 +fieldset/CNTH: + description: RTC Counter Register High + fields: + - name: CNTH + description: RTC counter register high + bit_offset: 0 + bit_size: 16 +fieldset/CNTL: + description: RTC Counter Register Low + fields: + - name: CNTL + description: RTC counter register Low + bit_offset: 0 + bit_size: 16 +fieldset/CRH: + description: RTC Control Register High + fields: + - name: SECIE + description: Second interrupt Enable + bit_offset: 0 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt Enable + bit_offset: 1 + bit_size: 1 + - name: OWIE + description: Overflow interrupt Enable + bit_offset: 2 + bit_size: 1 +fieldset/CRL: + description: RTC Control Register Low + fields: + - name: SECF + description: Second Flag + bit_offset: 0 + bit_size: 1 + - name: ALRF + description: Alarm Flag + bit_offset: 1 + bit_size: 1 + - name: OWF + description: Overflow Flag + bit_offset: 2 + bit_size: 1 + - name: RSF + description: "Registers Synchronized Flag" + bit_offset: 3 + bit_size: 1 + - name: CNF + description: Configuration Flag + bit_offset: 4 + bit_size: 1 + - name: RTOFF + description: RTC operation OFF + bit_offset: 5 + bit_size: 1 +fieldset/DIVH: + description: "RTC Prescaler Divider Register High" + fields: + - name: DIVH + description: "RTC prescaler divider register high" + bit_offset: 0 + bit_size: 4 +fieldset/DIVL: + description: "RTC Prescaler Divider Register Low" + fields: + - name: DIVL + description: "RTC prescaler divider register Low" + bit_offset: 0 + bit_size: 16 +fieldset/PRLH: + description: "RTC Prescaler Load Register High" + fields: + - name: PRLH + description: "RTC Prescaler Load Register High" + bit_offset: 0 + bit_size: 4 +fieldset/PRLL: + description: "RTC Prescaler Load Register Low" + fields: + - name: PRLL + description: "RTC Prescaler Divider Register Low" + bit_offset: 0 + bit_size: 16 diff --git a/data/registers/rtc_f2.yaml b/data/registers/rtc_f2.yaml new file mode 100644 index 0000000..bf12574 --- /dev/null +++ b/data/registers/rtc_f2.yaml @@ -0,0 +1,504 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: "initialization and status register" + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMAR + description: alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: alarm B register + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TAFCR + description: "tamper and alternate function configuration register" + byte_offset: 64 + fieldset: TAFCR + - name: BKPR + description: backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 +fieldset/BKPR: + description: backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALIBR: + description: calibration register + fields: + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: "Time-stamp event active edge" + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: "Reference clock detection enable (50 or 60 Hz)" + bit_offset: 4 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: DCE + description: "Coarse digital calibration enable" + bit_offset: 7 + bit_size: 1 + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + - name: WUTIE + description: "Wakeup timer interrupt enable" + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: "Time-stamp interrupt enable" + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: "Add 1 hour (summer time change)" + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: "Subtract 1 hour (winter time change)" + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: "initialization and status register" + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: "Registers synchronization flag" + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + - name: ALRBF + description: Alarm B flag + bit_offset: 9 + bit_size: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMP1F + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: "Synchronous prescaler factor" + bit_offset: 0 + bit_size: 13 + - name: PREDIV_A + description: "Asynchronous prescaler factor" + bit_offset: 16 + bit_size: 7 +fieldset/TAFCR: + description: "tamper and alternate function configuration register" + fields: + - name: TAMP1E + description: Tamper 1 detection enable + bit_offset: 0 + bit_size: 1 + - name: TAMP1TRG + description: Active level for tamper 1 + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP1INSEL + description: TAMPER1 mapping + bit_offset: 16 + bit_size: 1 + - name: TSINSEL + description: TIMESTAMP mapping + bit_offset: 17 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSTR: + description: time stamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: "Wakeup auto-reload value bits" + bit_offset: 0 + bit_size: 16 diff --git a/data/registers/rtc_f3.yaml b/data/registers/rtc_f3.yaml new file mode 100644 index 0000000..c0a718f --- /dev/null +++ b/data/registers/rtc_f3.yaml @@ -0,0 +1,1270 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: "initialization and status register" + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMAR + description: alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: alarm B register + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: "tamper and alternate function configuration register" + byte_offset: 64 + fieldset: TAFCR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 72 + fieldset: ALRMBSSR + - name: BKPR + description: backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMAR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMAR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMAR_MSK1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMBR_PM + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMBR_WDSEL + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMBR_MSK1 +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: "Use a 16-second calibration cycle period" + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: "Use an 8-second calibration cycle period" + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: "Increase frequency of RTC by 488.5 ppm" + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: "Time-stamp event active edge" + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: "Reference clock detection enable (50 or 60 Hz)" + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: "Bypass the shadow registers" + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + enum: ALRAE + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + enum: ALRBE + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + enum: WUTE + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + enum: TSE + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + enum: ALRAIE + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + enum: ALRBIE + - name: WUTIE + description: "Wakeup timer interrupt enable" + bit_offset: 14 + bit_size: 1 + enum: WUTIE + - name: TSIE + description: "Time-stamp interrupt enable" + bit_offset: 15 + bit_size: 1 + enum: TSIE + - name: ADD1H + description: "Add 1 hour (summer time change)" + bit_offset: 16 + bit_size: 1 + enum_write: ADD1HW + - name: SUB1H + description: "Subtract 1 hour (winter time change)" + bit_offset: 17 + bit_size: 1 + enum_write: SUB1HW + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + enum: BKP + - name: COSEL + description: "Calibration output selection" + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + enum: COE +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: "initialization and status register" + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + enum_read: ALRAWFR + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + enum_read: ALRAWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: "Registers synchronization flag" + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + enum_read: ALRAFR + enum_write: ALRAFW + - name: ALRBF + description: Alarm B flag + bit_offset: 9 + bit_size: 1 + enum_read: ALRBFR + enum_write: ALRBFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMP1F + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: TAMP2F + description: RTC_TAMP2 detection flag + bit_offset: 14 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: TAMP3F + description: RTC_TAMP3 detection flag + bit_offset: 15 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: "Synchronous prescaler factor" + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: "Asynchronous prescaler factor" + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: "Subtract a fraction of a second" + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 + enum_write: ADD1SW +fieldset/SSR: + description: sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAFCR: + description: "tamper and alternate function configuration register" + fields: + - name: TAMP1E + description: Tamper 1 detection enable + bit_offset: 0 + bit_size: 1 + enum: TAMP1E + - name: TAMP1TRG + description: Active level for tamper 1 + bit_offset: 1 + bit_size: 1 + enum: TAMP1TRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + enum: TAMPIE + - name: TAMP2E + description: Tamper 2 detection enable + bit_offset: 3 + bit_size: 1 + enum: TAMP1E + - name: TAMP2TRG + description: Active level for tamper 2 + bit_offset: 4 + bit_size: 1 + enum: TAMP1TRG + - name: TAMPTS + description: "Activate timestamp on tamper detection event" + bit_offset: 7 + bit_size: 1 + enum: TAMPTS + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: TAMPER pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: PC13VALUE + description: PC13 value + bit_offset: 18 + bit_size: 1 + enum: PC13VALUE + - name: PC13MODE + description: PC13 mode + bit_offset: 19 + bit_size: 1 + enum: PC13MODE + - name: PC14VALUE + description: PC14 value + bit_offset: 20 + bit_size: 1 + enum: PC13VALUE + - name: PC14MODE + description: PC 14 mode + bit_offset: 21 + bit_size: 1 + enum: PC13MODE + - name: PC15VALUE + description: PC15 value + bit_offset: 22 + bit_size: 1 + enum: PC13VALUE + - name: PC15MODE + description: PC15 mode + bit_offset: 23 + bit_size: 1 + enum: PC13MODE +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: TR_PM +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: time stamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: "Wakeup auto-reload value bits" + bit_offset: 0 + bit_size: 16 +enum/ADD1HW: + bit_size: 1 + variants: + - name: Add1 + description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + value: 1 +enum/ADD1SW: + bit_size: 1 + variants: + - name: Add1 + description: Add one second to the clock/calendar + value: 1 +enum/ALRAE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A disabled + value: 0 + - name: Enabled + description: Alarm A enabled + value: 1 +enum/ALRAFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRAFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRAIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A interrupt disabled + value: 0 + - name: Enabled + description: Alarm A interrupt enabled + value: 1 +enum/ALRAWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRBE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B disabled + value: 0 + - name: Enabled + description: Alarm B enabled + value: 1 +enum/ALRBFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + value: 1 +enum/ALRBFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRBIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B Interrupt disabled + value: 0 + - name: Enabled + description: Alarm B Interrupt enabled + value: 1 +enum/ALRMAR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMAR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMAR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMBR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMBR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMBR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: DST_Not_Changed + description: Daylight Saving Time change has not been performed + value: 0 + - name: DST_Changed + description: Daylight Saving Time change has been performed + value: 1 +enum/BYPSHAD: + bit_size: 1 + variants: + - name: ShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" + value: 0 + - name: BypassShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COE: + bit_size: 1 + variants: + - name: Disabled + description: Calibration output disabled + value: 0 + - name: Enabled + description: Calibration output enabled + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/PC13MODE: + bit_size: 1 + variants: + - name: Floating + description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + value: 0 + - name: PushPull + description: PCx is forced to push-pull output if LSE is disabled + value: 1 +enum/PC13VALUE: + bit_size: 1 + variants: + - name: Low + description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low" + value: 0 + - name: High + description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high" + value: 1 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SUB1HW: + bit_size: 1 + variants: + - name: Sub1 + description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + value: 1 +enum/TAMP1E: + bit_size: 1 + variants: + - name: Disabled + description: RTC_TAMPx input detection disabled + value: 0 + - name: Enabled + description: RTC_TAMPx input detection enabled + value: 1 +enum/TAMP1FR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMP1FW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMP1TRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPIE: + bit_size: 1 + variants: + - name: Disabled + description: Tamper interrupt disabled + value: 0 + - name: Enabled + description: Tamper interrupt enabled + value: 1 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/TAMPTS: + bit_size: 1 + variants: + - name: NoSave + description: Tamper detection event does not cause a timestamp to be saved + value: 0 + - name: Save + description: Save timestamp on tamper detection event + value: 1 +enum/TR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSE: + bit_size: 1 + variants: + - name: Disabled + description: Timestamp disabled + value: 0 + - name: Enabled + description: Timestamp enabled + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSIE: + bit_size: 1 + variants: + - name: Disabled + description: Time-stamp Interrupt disabled + value: 0 + - name: Enabled + description: Time-stamp Interrupt enabled + value: 1 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer disabled + value: 0 + - name: Enabled + description: Wakeup timer enabled + value: 1 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTIE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer interrupt disabled + value: 0 + - name: Enabled + description: Wakeup timer interrupt enabled + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_f4.yaml b/data/registers/rtc_f4.yaml new file mode 100644 index 0000000..ecde10c --- /dev/null +++ b/data/registers/rtc_f4.yaml @@ -0,0 +1,1135 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: "initialization and status register" + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMAR + description: alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: alarm B register + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: "tamper and alternate function configuration register" + byte_offset: 64 + fieldset: TAFCR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 72 + fieldset: ALRMBSSR + - name: BKPR + description: backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMAR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMAR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMAR_MSK1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMBR_PM + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMBR_WDSEL + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMBR_MSK1 +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALIBR: + description: calibration register + fields: + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: "Use a 16-second calibration cycle period" + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: "Use an 8-second calibration cycle period" + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: "Increase frequency of RTC by 488.5 ppm" + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: "Time-stamp event active edge" + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: "Reference clock detection enable (50 or 60 Hz)" + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: "Bypass the shadow registers" + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: DCE + description: "Coarse digital calibration enable" + bit_offset: 7 + bit_size: 1 + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + enum: ALRAE + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + enum: ALRBE + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + enum: WUTE + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + enum: TSE + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + enum: ALRAIE + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + enum: ALRBIE + - name: WUTIE + description: "Wakeup timer interrupt enable" + bit_offset: 14 + bit_size: 1 + enum: WUTIE + - name: TSIE + description: "Time-stamp interrupt enable" + bit_offset: 15 + bit_size: 1 + enum: TSIE + - name: ADD1H + description: "Add 1 hour (summer time change)" + bit_offset: 16 + bit_size: 1 + enum_write: ADD1HW + - name: SUB1H + description: "Subtract 1 hour (winter time change)" + bit_offset: 17 + bit_size: 1 + enum_write: SUB1HW + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + enum: BKP + - name: COSEL + description: "Calibration Output selection" + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + enum: COE +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: "initialization and status register" + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + enum_read: ALRAWFR + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + enum_read: ALRAWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: "Registers synchronization flag" + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + enum_read: ALRAFR + enum_write: ALRAFW + - name: ALRBF + description: Alarm B flag + bit_offset: 9 + bit_size: 1 + enum_read: ALRBFR + enum_write: ALRBFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMP1F + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: TAMP2F + description: TAMPER2 detection flag + bit_offset: 14 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: "Synchronous prescaler factor" + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: "Asynchronous prescaler factor" + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: "Subtract a fraction of a second" + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 + enum_write: ADD1SW +fieldset/SSR: + description: sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAFCR: + description: "tamper and alternate function configuration register" + fields: + - name: TAMP1E + description: Tamper 1 detection enable + bit_offset: 0 + bit_size: 1 + - name: TAMP1TRG + description: Active level for tamper 1 + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP2E + description: Tamper 2 detection enable + bit_offset: 3 + bit_size: 1 + - name: TAMP2TRG + description: Active level for tamper 2 + bit_offset: 4 + bit_size: 1 + - name: TAMPTS + description: "Activate timestamp on tamper detection event" + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + - name: TAMPPUDIS + description: TAMPER pull-up disable + bit_offset: 15 + bit_size: 1 + - name: TAMP1INSEL + description: TAMPER1 mapping + bit_offset: 16 + bit_size: 1 + - name: TSINSEL + description: TIMESTAMP mapping + bit_offset: 17 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: TR_PM +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: time stamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: "Wakeup auto-reload value bits" + bit_offset: 0 + bit_size: 16 +enum/ADD1HW: + bit_size: 1 + variants: + - name: Add1 + description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + value: 1 +enum/ADD1SW: + bit_size: 1 + variants: + - name: Add1 + description: Add one second to the clock/calendar + value: 1 +enum/ALRAE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A disabled + value: 0 + - name: Enabled + description: Alarm A enabled + value: 1 +enum/ALRAFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRAFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRAIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A interrupt disabled + value: 0 + - name: Enabled + description: Alarm A interrupt enabled + value: 1 +enum/ALRAWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRBE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B disabled + value: 0 + - name: Enabled + description: Alarm B enabled + value: 1 +enum/ALRBFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + value: 1 +enum/ALRBFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRBIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B Interrupt disabled + value: 0 + - name: Enabled + description: Alarm B Interrupt enabled + value: 1 +enum/ALRMAR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMAR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMAR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMBR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMBR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMBR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: DST_Not_Changed + description: Daylight Saving Time change has not been performed + value: 0 + - name: DST_Changed + description: Daylight Saving Time change has been performed + value: 1 +enum/BYPSHAD: + bit_size: 1 + variants: + - name: ShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" + value: 0 + - name: BypassShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COE: + bit_size: 1 + variants: + - name: Disabled + description: Calibration output disabled + value: 0 + - name: Enabled + description: Calibration output enabled + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SUB1HW: + bit_size: 1 + variants: + - name: Sub1 + description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + value: 1 +enum/TAMP1FR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMP1FW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSE: + bit_size: 1 + variants: + - name: Disabled + description: Timestamp disabled + value: 0 + - name: Enabled + description: Timestamp enabled + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSIE: + bit_size: 1 + variants: + - name: Disabled + description: Time-stamp Interrupt disabled + value: 0 + - name: Enabled + description: Time-stamp Interrupt enabled + value: 1 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer disabled + value: 0 + - name: Enabled + description: Wakeup timer enabled + value: 1 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTIE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer interrupt disabled + value: 0 + - name: Enabled + description: Wakeup timer interrupt enabled + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2.yaml b/data/registers/rtc_f7.yaml similarity index 95% rename from data/registers/rtc_v2.yaml rename to data/registers/rtc_f7.yaml index 20ada52..1f76e62 100644 --- a/data/registers/rtc_v2.yaml +++ b/data/registers/rtc_f7.yaml @@ -102,14 +102,11 @@ fieldset/ALRMAR: description: Second tens in BCD format bit_offset: 4 bit_size: 3 - - name: MSK + - name: MSK1 description: Alarm A seconds mask bit_offset: 7 bit_size: 1 - array: - len: 4 - stride: 8 - enum: ALRMAR_MSK + enum: ALRMAR_MSK1 - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -118,6 +115,11 @@ fieldset/ALRMAR: description: Minute tens in BCD format bit_offset: 12 bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMAR_MSK1 - name: HU description: Hour units in BCD format bit_offset: 16 @@ -131,6 +133,11 @@ fieldset/ALRMAR: bit_offset: 22 bit_size: 1 enum: ALRMAR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMAR_MSK1 - name: DU description: Date units or day in BCD format bit_offset: 24 @@ -144,6 +151,11 @@ fieldset/ALRMAR: bit_offset: 30 bit_size: 1 enum: ALRMAR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMAR_MSK1 fieldset/ALRMASSR: description: alarm A sub second register fields: @@ -166,14 +178,11 @@ fieldset/ALRMBR: description: Second tens in BCD format bit_offset: 4 bit_size: 3 - - name: MSK + - name: MSK1 description: Alarm B seconds mask bit_offset: 7 bit_size: 1 - array: - len: 4 - stride: 8 - enum: ALRMBR_MSK + enum: ALRMBR_MSK1 - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -182,6 +191,11 @@ fieldset/ALRMBR: description: Minute tens in BCD format bit_offset: 12 bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMBR_MSK1 - name: HU description: Hour units in BCD format bit_offset: 16 @@ -195,6 +209,11 @@ fieldset/ALRMBR: bit_offset: 22 bit_size: 1 enum: ALRMBR_PM + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMBR_MSK1 - name: DU description: Date units or day in BCD format bit_offset: 24 @@ -208,6 +227,11 @@ fieldset/ALRMBR: bit_offset: 30 bit_size: 1 enum: ALRMBR_WDSEL + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMBR_MSK1 fieldset/ALRMBSSR: description: alarm B sub second register fields: @@ -233,14 +257,16 @@ fieldset/CALR: description: Calibration minus bit_offset: 0 bit_size: 9 - - name: CALW + - name: CALW16 description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 - array: - len: 2 - stride: 1 enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 - name: CALP description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 @@ -318,12 +344,12 @@ fieldset/CR: description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - enum_write: ADDHW + enum_write: ADD1HW - name: SUB1H description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - enum_write: SUBHW + enum_write: SUB1HW - name: BKP description: Backup bit_offset: 18 @@ -462,36 +488,32 @@ fieldset/ISR: description: Tamper detection flag bit_offset: 13 bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW + enum_read: TAMP1FR + enum_write: TAMP1FW - name: TAMP2F description: RTC_TAMP2 detection flag bit_offset: 14 bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW + enum_read: TAMP1FR + enum_write: TAMP1FW - name: TAMP3F description: RTC_TAMP3 detection flag bit_offset: 15 bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW + enum_read: TAMP1FR + enum_write: TAMP1FW - name: RECALPF description: Recalibration pending Flag bit_offset: 16 bit_size: 1 enum_read: RECALPFR - name: ITSF - description: Internal tTime-stamp flag + description: Internal time-stamp flag bit_offset: 17 bit_size: 1 fieldset/OR: description: option register fields: - - name: RTC_OUT_RMP - description: RTC_OUT remap - bit_offset: 1 - bit_size: 1 - name: TSINSEL description: TIMESTAMP mapping bit_offset: 1 @@ -522,7 +544,7 @@ fieldset/SHIFTR: description: Add one second bit_offset: 31 bit_size: 1 - enum_write: ADDSW + enum_write: ADD1SW fieldset/SSR: description: sub second register fields: @@ -724,13 +746,13 @@ fieldset/WUTR: description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ADDHW: +enum/ADD1HW: bit_size: 1 variants: - name: Add1 description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode value: 1 -enum/ADDSW: +enum/ADD1SW: bit_size: 1 variants: - name: Add1 @@ -805,7 +827,7 @@ enum/ALRBIE: - name: Enabled description: Alarm B Interrupt enabled value: 1 -enum/ALRMAR_MSK: +enum/ALRMAR_MSK1: bit_size: 1 variants: - name: Mask @@ -832,7 +854,7 @@ enum/ALRMAR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care." value: 1 -enum/ALRMBR_MSK: +enum/ALRMBR_MSK1: bit_size: 1 variants: - name: Mask @@ -1015,19 +1037,19 @@ enum/SHPFR: - name: ShiftPending description: A shift operation is pending value: 1 -enum/SUBHW: +enum/SUB1HW: bit_size: 1 variants: - name: Sub1 description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode value: 1 -enum/TAMPFR: +enum/TAMP1FR: bit_size: 1 variants: - name: Tampered description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input value: 1 -enum/TAMPFW: +enum/TAMP1FW: bit_size: 1 variants: - name: Clear diff --git a/data/registers/rtc_gx.yaml b/data/registers/rtc_gx.yaml new file mode 100644 index 0000000..fec8a49 --- /dev/null +++ b/data/registers/rtc_gx.yaml @@ -0,0 +1,645 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: initialization and status register + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: control register + byte_offset: 24 + fieldset: CR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMAR + description: alarm A register + byte_offset: 64 + fieldset: ALRMAR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBR + description: alarm B register + byte_offset: 72 + fieldset: ALRMBR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 76 + fieldset: ALRMBSSR + - name: SR + description: status register + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: status register + byte_offset: 84 + access: Read + fieldset: MISR + - name: SCR + description: status register + byte_offset: 92 + access: Write + fieldset: SCR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: Time-stamp event active edge + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Time-stamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: timestamp on internal event enable + bit_offset: 24 + bit_size: 1 + - name: TAMPTS + description: TAMPTS + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: TAMPOE + bit_offset: 26 + bit_size: 1 + - name: TAMPALRM_PU + description: TAMPALRM_PU + bit_offset: 29 + bit_size: 1 + - name: TAMPALRM_TYPE + description: TAMPALRM_TYPE + bit_offset: 30 + bit_size: 1 + - name: OUT2EN + description: OUT2EN + bit_offset: 31 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ICSR: + description: initialization and status register + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 +fieldset/MISR: + description: status register + fields: + - name: ALRAMF + description: ALRAMF + bit_offset: 0 + bit_size: 1 + - name: ALRBMF + description: ALRBMF + bit_offset: 1 + bit_size: 1 + - name: WUTMF + description: WUTMF + bit_offset: 2 + bit_size: 1 + - name: TSMF + description: TSMF + bit_offset: 3 + bit_size: 1 + - name: TSOVMF + description: TSOVMF + bit_offset: 4 + bit_size: 1 + - name: ITSMF + description: ITSMF + bit_offset: 5 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SCR: + description: status register + fields: + - name: CALRAF + description: CALRAF + bit_offset: 0 + bit_size: 1 + - name: CALRBF + description: CALRBF + bit_offset: 1 + bit_size: 1 + - name: CWUTF + description: CWUTF + bit_offset: 2 + bit_size: 1 + - name: CTSF + description: CTSF + bit_offset: 3 + bit_size: 1 + - name: CTSOVF + description: CTSOVF + bit_offset: 4 + bit_size: 1 + - name: CITSF + description: CITSF + bit_offset: 5 + bit_size: 1 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SR: + description: status register + fields: + - name: ALRAF + description: ALRAF + bit_offset: 0 + bit_size: 1 + - name: ALRBF + description: ALRBF + bit_offset: 1 + bit_size: 1 + - name: WUTF + description: WUTF + bit_offset: 2 + bit_size: 1 + - name: TSF + description: TSF + bit_offset: 3 + bit_size: 1 + - name: TSOVF + description: TSOVF + bit_offset: 4 + bit_size: 1 + - name: ITSF + description: ITSF + bit_offset: 5 + bit_size: 1 +fieldset/SSR: + description: sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: time stamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 diff --git a/data/registers/rtc_h7.yaml b/data/registers/rtc_h7.yaml new file mode 100644 index 0000000..89b2e34 --- /dev/null +++ b/data/registers/rtc_h7.yaml @@ -0,0 +1,1201 @@ +--- +block/RTC: + description: RTC + items: + - name: TR + description: "The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." + byte_offset: 0 + fieldset: TR + - name: DR + description: "The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." + byte_offset: 4 + fieldset: DR + - name: CR + description: RTC control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: "This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9." + byte_offset: 12 + fieldset: ISR + - name: PRER + description: "This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9." + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: "This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9." + byte_offset: 20 + fieldset: WUTR + - name: ALRMAR + description: "This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: "This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: RTC write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: RTC sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: "This register is write protected. The write access procedure is described in RTC register write protection on page9." + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: "The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset." + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: "This register is write protected. The write access procedure is described in RTC register write protection on page9." + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: "RTC tamper and alternate function configuration register" + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMASSR + description: "This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9" + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBSSR + description: "This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection." + byte_offset: 72 + fieldset: ALRMBSSR + - name: OR + description: RTC option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: RTC backup registers + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMAR: + description: "This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." + fields: + - name: SU + description: "Second units in BCD format." + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: MNU + description: "Minute units in BCD format." + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMAR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: DU + description: "Date units or day in BCD format." + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format. + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMAR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMAR_MSK1 +fieldset/ALRMASSR: + description: "This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9" + fields: + - name: SS + description: "Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared." + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation." + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: "This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMBR_PM + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMBR_WDSEL + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMBR_MSK1 +fieldset/ALRMBSSR: + description: "This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection." + fields: + - name: SS + description: "Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared." + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation." + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: RTC backup registers + fields: + - name: BKP + description: "The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: "This register is write protected. The write access procedure is described in RTC register write protection on page9." + fields: + - name: CALM + description: "Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section24.3.12: RTC smooth digital calibration on page13." + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: "Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM[0] is stuck at 0 when CALW16= 1. Refer to Section24.3.12: RTC smooth digital calibration." + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: "Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00; when CALW8= 1. Refer to Section24.3.12: RTC smooth digital calibration." + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: "Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section24.3.12: RTC smooth digital calibration." + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: RTC control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: "Time-stamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting." + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: "RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF." + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: "Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1." + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + enum: ALRAE + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + enum: ALRBE + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + enum: WUTE + - name: TSE + description: timestamp enable + bit_offset: 11 + bit_size: 1 + enum: TSE + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + enum: ALRAIE + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + enum: ALRBIE + - name: WUTIE + description: "Wakeup timer interrupt enable" + bit_offset: 14 + bit_size: 1 + enum: WUTIE + - name: TSIE + description: "Time-stamp interrupt enable" + bit_offset: 15 + bit_size: 1 + enum: TSIE + - name: ADD1H + description: "Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0." + bit_offset: 16 + bit_size: 1 + enum_write: ADD1HW + - name: SUB1H + description: "Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0." + bit_offset: 17 + bit_size: 1 + enum_write: SUB1HW + - name: BKP + description: "Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not." + bit_offset: 18 + bit_size: 1 + enum: BKP + - name: COSEL + description: "Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section24.3.15: Calibration clock output" + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: "Output polarity This bit is used to configure the polarity of RTC_ALARM output" + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: "Output selection These bits are used to select the flag to be routed to RTC_ALARM output" + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: "Calibration output enable This bit enables the RTC_CALIB output" + bit_offset: 23 + bit_size: 1 + enum: COE + - name: ITSE + description: "timestamp on internal event enable" + bit_offset: 24 + bit_size: 1 + enum: ITSE +fieldset/DR: + description: "The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: "This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9." + fields: + - name: ALRAWF + description: "Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode." + bit_offset: 0 + bit_size: 1 + enum_read: ALRAWFR + - name: ALRBWF + description: "Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode." + bit_offset: 1 + bit_size: 1 + enum_read: ALRAWFR + - name: WUTWF + description: "Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set." + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: "Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect." + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: INITS + description: "Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state)." + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: "Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode." + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: "Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated." + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRAF + description: "Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0." + bit_offset: 8 + bit_size: 1 + enum_read: ALRAFR + enum_write: ALRAFW + - name: ALRBF + description: "Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0." + bit_offset: 9 + bit_size: 1 + enum_read: ALRBFR + enum_write: ALRBFW + - name: WUTF + description: "Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again." + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: "Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0." + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: "Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-stamp event occurs immediately before the TSF bit is cleared." + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMP1F + description: "RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0" + bit_offset: 13 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: TAMP2F + description: "RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0" + bit_offset: 14 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: TAMP3F + description: "RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0" + bit_offset: 15 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: RECALPF + description: "Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly." + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR + - name: ITSF + description: Internal tTime-stamp flag + bit_offset: 17 + bit_size: 1 + enum_read: ITSFR + enum_write: ITSFW +fieldset/OR: + description: RTC option register + fields: + - name: RTC_ALARM_TYPE + description: "RTC_ALARM output type on PC13" + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 +fieldset/PRER: + description: "This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9." + fields: + - name: PREDIV_S + description: "Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)" + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: "Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)" + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: "This register is write protected. The write access procedure is described in RTC register write protection on page9." + fields: + - name: SUBFS + description: "Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time." + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: "Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation." + bit_offset: 31 + bit_size: 1 + enum_write: ADD1SW +fieldset/SSR: + description: RTC sub second register + fields: + - name: SS + description: "Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR." + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: "RTC tamper and alternate function configuration register" + fields: + - name: TAMP1E + description: "RTC_TAMP1 input detection enable" + bit_offset: 0 + bit_size: 1 + - name: TAMP1TRG + description: "Active level for RTC_TAMP1 input If TAMPFLT != 00 if TAMPFLT = 00:" + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP2E + description: "RTC_TAMP2 input detection enable" + bit_offset: 3 + bit_size: 1 + - name: TAMP2TRG + description: "Active level for RTC_TAMP2 input if TAMPFLT != 00: if TAMPFLT = 00:" + bit_offset: 4 + bit_size: 1 + - name: TAMP3E + description: RTC_TAMP3 detection enable + bit_offset: 5 + bit_size: 1 + - name: TAMP3TRG + description: "Active level for RTC_TAMP3 input if TAMPFLT != 00: if TAMPFLT = 00:" + bit_offset: 6 + bit_size: 1 + - name: TAMPTS + description: "Activate timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register." + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: "Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled." + bit_offset: 8 + bit_size: 3 + - name: TAMPFLT + description: "RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs." + bit_offset: 11 + bit_size: 2 + - name: TAMPPRCH + description: "RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs." + bit_offset: 13 + bit_size: 2 + - name: TAMPPUDIS + description: "RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample." + bit_offset: 15 + bit_size: 1 + - name: TAMP1IE + description: Tamper 1 interrupt enable + bit_offset: 16 + bit_size: 1 + - name: TAMP1NOERASE + description: Tamper 1 no erase + bit_offset: 17 + bit_size: 1 + - name: TAMP1MF + description: Tamper 1 mask flag + bit_offset: 18 + bit_size: 1 + - name: TAMP2IE + description: Tamper 2 interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TAMP2NOERASE + description: Tamper 2 no erase + bit_offset: 20 + bit_size: 1 + - name: TAMP2MF + description: Tamper 2 mask flag + bit_offset: 21 + bit_size: 1 + - name: TAMP3IE + description: Tamper 3 interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TAMP3NOERASE + description: Tamper 3 no erase + bit_offset: 23 + bit_size: 1 + - name: TAMP3MF + description: Tamper 3 mask flag + bit_offset: 24 + bit_size: 1 +fieldset/TR: + description: "The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: TR_PM +fieldset/TSDR: + description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: "The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset." + fields: + - name: SS + description: "Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred." + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." + fields: + - name: SU + description: "Second units in BCD format." + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MNU + description: "Minute units in BCD format." + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: RTC write protection register + fields: + - name: KEY + description: "Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection." + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: "This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9." + fields: + - name: WUT + description: "Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden." + bit_offset: 0 + bit_size: 16 +enum/ADD1HW: + bit_size: 1 + variants: + - name: Add1 + description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + value: 1 +enum/ADD1SW: + bit_size: 1 + variants: + - name: Add1 + description: Add one second to the clock/calendar + value: 1 +enum/ALRAE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A disabled + value: 0 + - name: Enabled + description: Alarm A enabled + value: 1 +enum/ALRAFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRAFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRAIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A interrupt disabled + value: 0 + - name: Enabled + description: Alarm A interrupt enabled + value: 1 +enum/ALRAWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRBE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B disabled + value: 0 + - name: Enabled + description: Alarm B enabled + value: 1 +enum/ALRBFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + value: 1 +enum/ALRBFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRBIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B Interrupt disabled + value: 0 + - name: Enabled + description: Alarm B Interrupt enabled + value: 1 +enum/ALRMAR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMAR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMAR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMBR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMBR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMBR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: DST_Not_Changed + description: Daylight Saving Time change has not been performed + value: 0 + - name: DST_Changed + description: Daylight Saving Time change has been performed + value: 1 +enum/BYPSHAD: + bit_size: 1 + variants: + - name: ShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" + value: 0 + - name: BypassShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COE: + bit_size: 1 + variants: + - name: Disabled + description: Calibration output disabled + value: 0 + - name: Enabled + description: Calibration output enabled + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/ITSE: + bit_size: 1 + variants: + - name: Disabled + description: Internal event timestamp is disabled + value: 0 + - name: Enabled + description: Internal event timestamp is enabled + value: 1 +enum/ITSFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when a time-stamp on the internal event occurs + value: 1 +enum/ITSFW: + bit_size: 1 + variants: + - name: Clear + description: "This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits" + value: 0 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SUB1HW: + bit_size: 1 + variants: + - name: Sub1 + description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + value: 1 +enum/TAMP1FR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMP1FW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSE: + bit_size: 1 + variants: + - name: Disabled + description: Timestamp disabled + value: 0 + - name: Enabled + description: Timestamp enabled + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSIE: + bit_size: 1 + variants: + - name: Disabled + description: Time-stamp Interrupt disabled + value: 0 + - name: Enabled + description: Time-stamp Interrupt enabled + value: 1 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer disabled + value: 0 + - name: Enabled + description: Wakeup timer enabled + value: 1 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTIE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer interrupt disabled + value: 0 + - name: Enabled + description: Wakeup timer interrupt enabled + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_l0.yaml b/data/registers/rtc_l0.yaml new file mode 100644 index 0000000..7c340c7 --- /dev/null +++ b/data/registers/rtc_l0.yaml @@ -0,0 +1,1319 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: RTC time register + byte_offset: 0 + fieldset: TR + - name: DR + description: RTC date register + byte_offset: 4 + fieldset: DR + - name: CR + description: RTC control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: RTC initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: RTC prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: RTC wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMAR + description: RTC alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: RTC alarm B register + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: RTC sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: RTC shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: RTC timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: RTC timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: RTC time-stamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: RTC calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: RTC tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMASSR + description: RTC alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBSSR + description: RTC alarm B sub second register + byte_offset: 72 + fieldset: ALRMBSSR + - name: OR + description: option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: RTC backup registers + array: + len: 5 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMAR: + description: RTC alarm A register + fields: + - name: SU + description: Second units in BCD format. + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: MNU + description: Minute units in BCD format. + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMAR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: DU + description: Date units or day in BCD format. + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format. + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMAR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMAR_MSK1 +fieldset/ALRMASSR: + description: RTC alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: RTC alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMBR_PM + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMBR_WDSEL + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMBR_MSK1 +fieldset/ALRMBSSR: + description: RTC alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: RTC backup registers + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: RTC calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: RTC control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Time-stamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: RTC_REFIN reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + enum: ALRAE + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + enum: ALRBE + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + enum: WUTE + - name: TSE + description: timestamp enable + bit_offset: 11 + bit_size: 1 + enum: TSE + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + enum: ALRAIE + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + enum: ALRBIE + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + enum: WUTIE + - name: TSIE + description: Time-stamp interrupt enable + bit_offset: 15 + bit_size: 1 + enum: TSIE + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + enum_write: ADD1HW + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + enum_write: SUB1HW + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + enum: BKP + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + enum: COE +fieldset/DR: + description: RTC date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: RTC initialization and status register + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + enum_read: ALRAWFR + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + enum_read: ALRAWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + enum_read: ALRAFR + enum_write: ALRAFW + - name: ALRBF + description: Alarm B flag + bit_offset: 9 + bit_size: 1 + enum_read: ALRBFR + enum_write: ALRBFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMP1F + description: RTC_TAMP1 detection flag + bit_offset: 13 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: TAMP2F + description: RTC_TAMP2 detection flag + bit_offset: 14 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: TAMP3F + description: RTC_TAMP3 detection flag + bit_offset: 15 + bit_size: 1 + enum_read: TAMP1FR + enum_write: TAMP1FW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/OR: + description: option register + fields: + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_ALARM on PC13 output type + bit_offset: 1 + bit_size: 1 +fieldset/PRER: + description: RTC prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 16 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: RTC shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 + enum_write: ADD1SW +fieldset/SSR: + description: RTC sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: RTC tamper configuration register + fields: + - name: TAMP1E + description: RTC_TAMP1 input detection enable + bit_offset: 0 + bit_size: 1 + enum: TAMP1E + - name: TAMP1TRG + description: Active level for RTC_TAMP1 input + bit_offset: 1 + bit_size: 1 + enum: TAMP1TRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + enum: TAMPIE + - name: TAMP2E + description: RTC_TAMP2 input detection enable + bit_offset: 3 + bit_size: 1 + enum: TAMP1E + - name: TAMP2TRG + description: Active level for RTC_TAMP2 input + bit_offset: 4 + bit_size: 1 + enum: TAMP1TRG + - name: TAMP3E + description: RTC_TAMP3 detection enable + bit_offset: 5 + bit_size: 1 + enum: TAMP1E + - name: TAMP3TRG + description: Active level for RTC_TAMP3 input + bit_offset: 6 + bit_size: 1 + enum: TAMP1TRG + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + enum: TAMPTS + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: RTC_TAMPx filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: RTC_TAMPx precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: RTC_TAMPx pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMP1IE + description: Tamper 1 interrupt enable + bit_offset: 16 + bit_size: 1 + enum: TAMP1IE + - name: TAMP1NOERASE + description: Tamper 1 no erase + bit_offset: 17 + bit_size: 1 + enum: TAMP1NOERASE + - name: TAMP1MF + description: Tamper 1 mask flag + bit_offset: 18 + bit_size: 1 + enum: TAMP1MF + - name: TAMP2IE + description: Tamper 2 interrupt enable + bit_offset: 19 + bit_size: 1 + enum: TAMP1IE + - name: TAMP2NOERASE + description: Tamper 2 no erase + bit_offset: 20 + bit_size: 1 + enum: TAMP1NOERASE + - name: TAMP2MF + description: Tamper 2 mask flag + bit_offset: 21 + bit_size: 1 + enum: TAMP1MF + - name: TAMP3IE + description: Tamper 3 interrupt enable + bit_offset: 22 + bit_size: 1 + enum: TAMP1IE + - name: TAMP3NOERASE + description: Tamper 3 no erase + bit_offset: 23 + bit_size: 1 + enum: TAMP1NOERASE + - name: TAMP3MF + description: Tamper 3 mask flag + bit_offset: 24 + bit_size: 1 + enum: TAMP1MF +fieldset/TR: + description: RTC time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: TR_PM +fieldset/TSDR: + description: RTC timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: RTC time-stamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: RTC timestamp time register + fields: + - name: SU + description: Second units in BCD format. + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format. + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: RTC wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ADD1HW: + bit_size: 1 + variants: + - name: Add1 + description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + value: 1 +enum/ADD1SW: + bit_size: 1 + variants: + - name: Add1 + description: Add one second to the clock/calendar + value: 1 +enum/ALRAE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A disabled + value: 0 + - name: Enabled + description: Alarm A enabled + value: 1 +enum/ALRAFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRAFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRAIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A interrupt disabled + value: 0 + - name: Enabled + description: Alarm A interrupt enabled + value: 1 +enum/ALRAWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRBE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B disabled + value: 0 + - name: Enabled + description: Alarm B enabled + value: 1 +enum/ALRBFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + value: 1 +enum/ALRBFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRBIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B Interrupt disabled + value: 0 + - name: Enabled + description: Alarm B Interrupt enabled + value: 1 +enum/ALRMAR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMAR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMAR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMBR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMBR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMBR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: DST_Not_Changed + description: Daylight Saving Time change has not been performed + value: 0 + - name: DST_Changed + description: Daylight Saving Time change has been performed + value: 1 +enum/BYPSHAD: + bit_size: 1 + variants: + - name: ShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" + value: 0 + - name: BypassShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COE: + bit_size: 1 + variants: + - name: Disabled + description: Calibration output disabled + value: 0 + - name: Enabled + description: Calibration output enabled + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SUB1HW: + bit_size: 1 + variants: + - name: Sub1 + description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + value: 1 +enum/TAMP1E: + bit_size: 1 + variants: + - name: Disabled + description: RTC_TAMPx input detection disabled + value: 0 + - name: Enabled + description: RTC_TAMPx input detection enabled + value: 1 +enum/TAMP1FR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMP1FW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMP1IE: + bit_size: 1 + variants: + - name: Disabled + description: Tamper x interrupt is disabled if TAMPIE = 0 + value: 0 + - name: Enabled + description: Tamper x interrupt enabled + value: 1 +enum/TAMP1MF: + bit_size: 1 + variants: + - name: NotMasked + description: Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection + value: 0 + - name: Masked + description: Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. + value: 1 +enum/TAMP1NOERASE: + bit_size: 1 + variants: + - name: Erase + description: Tamper x event erases the backup registers + value: 0 + - name: NoErase + description: Tamper x event does not erase the backup registers + value: 1 +enum/TAMP1TRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPIE: + bit_size: 1 + variants: + - name: Disabled + description: Tamper interrupt disabled + value: 0 + - name: Enabled + description: Tamper interrupt enabled + value: 1 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/TAMPTS: + bit_size: 1 + variants: + - name: NoSave + description: Tamper detection event does not cause a timestamp to be saved + value: 0 + - name: Save + description: Save timestamp on tamper detection event + value: 1 +enum/TR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSE: + bit_size: 1 + variants: + - name: Disabled + description: Timestamp disabled + value: 0 + - name: Enabled + description: Timestamp enabled + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSIE: + bit_size: 1 + variants: + - name: Disabled + description: Time-stamp Interrupt disabled + value: 0 + - name: Enabled + description: Time-stamp Interrupt enabled + value: 1 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer disabled + value: 0 + - name: Enabled + description: Wakeup timer enabled + value: 1 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTIE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer interrupt disabled + value: 0 + - name: Enabled + description: Wakeup timer interrupt enabled + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_l1.yaml b/data/registers/rtc_l1.yaml new file mode 100644 index 0000000..0fbf5f4 --- /dev/null +++ b/data/registers/rtc_l1.yaml @@ -0,0 +1,649 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: "initialization and status register" + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMAR + description: alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: alarm B register + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: TSTR + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: "tamper and alternate function configuration register" + byte_offset: 64 + fieldset: TAFCR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 72 + fieldset: ALRMBSSR + - name: BKPR + description: backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: "Second units in BCD format." + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: "Minute units in BCD format." + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD format." + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format. + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALIBR: + description: calibration register + fields: + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: CALW16 + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: "Use a 16-second calibration cycle period" + bit_offset: 14 + bit_size: 1 + - name: CALP + description: "Use an 8-second calibration cycle period" + bit_offset: 15 + bit_size: 1 +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: "Time-stamp event active edge" + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: "Reference clock detection enable" + bit_offset: 4 + bit_size: 1 + - name: BYPSHAD + description: "Bypass the shadow registers" + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: DCE + description: "Coarse digital calibration enable" + bit_offset: 7 + bit_size: 1 + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + - name: WUTIE + description: "Wakeup timer interrupt enable" + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: "Time-stamp interrupt enable" + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: "Calibration output selection" + bit_offset: 19 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: "initialization and status register" + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: "Registers synchronization flag" + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + - name: ALRBF + description: Alarm B flag + bit_offset: 9 + bit_size: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMP1F + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + - name: TAMP2F + description: TAMPER2 detection flag + bit_offset: 14 + bit_size: 1 + - name: TAMP3F + description: TAMPER3 detection flag + bit_offset: 15 + bit_size: 1 + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: "Synchronous prescaler factor" + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: "Asynchronous prescaler factor" + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: "Subtract a fraction of a second" + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: ADD1S + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAFCR: + description: "tamper and alternate function configuration register" + fields: + - name: TAMP1E + description: Tamper 1 detection enable + bit_offset: 0 + bit_size: 1 + - name: TAMP1ETRG + description: Active level for tamper 1 + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP2E + description: Tamper 2 detection enable + bit_offset: 3 + bit_size: 1 + - name: TAMP2TRG + description: Active level for tamper 2 + bit_offset: 4 + bit_size: 1 + - name: TAMP3E + description: TIMESTAMP mapping + bit_offset: 5 + bit_size: 1 + - name: TAMP3TRG + description: TAMPER1 mapping + bit_offset: 6 + bit_size: 1 + - name: TAMPTS + description: "Activate timestamp on tamper detection event" + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + - name: TAMPPUDIS + description: TAMPER pull-up disable + bit_offset: 15 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: "RTC timestamp subsecond field" + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: TSTR + fields: + - name: SU + description: "Second units in BCD format." + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MNU + description: "Minute units in BCD format." + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: "Wakeup auto-reload value bits" + bit_offset: 0 + bit_size: 16 diff --git a/data/registers/rtc_l4.yaml b/data/registers/rtc_l4.yaml new file mode 100644 index 0000000..27090d5 --- /dev/null +++ b/data/registers/rtc_l4.yaml @@ -0,0 +1,681 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: "initialization and status\r register" + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMAR + description: alarm A register + byte_offset: 28 + fieldset: ALRMAR + - name: ALRMBR + description: alarm B register + byte_offset: 32 + fieldset: ALRMBR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 72 + fieldset: ALRMBSSR + - name: OR + description: option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD\r format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting\r at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD\r format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting\r at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: "Use a 16-second calibration cycle\r period" + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: "Use an 8-second calibration cycle\r period" + bit_offset: 14 + bit_size: 1 + - name: CALP + description: "Increase frequency of RTC by 488.5\r ppm" + bit_offset: 15 + bit_size: 1 +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: "Time-stamp event active\r edge" + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: "Reference clock detection enable (50 or\r 60 Hz)" + bit_offset: 4 + bit_size: 1 + - name: BYPSHAD + description: "Bypass the shadow\r registers" + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + - name: WUTIE + description: "Wakeup timer interrupt\r enable" + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: "Time-stamp interrupt\r enable" + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: "Add 1 hour (summer time\r change)" + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: "Subtract 1 hour (winter time\r change)" + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: "Calibration output\r selection" + bit_offset: 19 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: "timestamp on internal event\r enable" + bit_offset: 24 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: "initialization and status\r register" + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: "Registers synchronization\r flag" + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: ALRAF + description: Alarm A flag + bit_offset: 8 + bit_size: 1 + - name: ALRBF + description: Alarm B flag + bit_offset: 9 + bit_size: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + - name: TAMP1F + description: Tamper detection flag + bit_offset: 13 + bit_size: 1 + - name: TAMP2F + description: RTC_TAMP2 detection flag + bit_offset: 14 + bit_size: 1 + - name: TAMP3F + description: RTC_TAMP3 detection flag + bit_offset: 15 + bit_size: 1 + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 +fieldset/OR: + description: option register + fields: + - name: RTC_ALARM_TYPE + description: "RTC_ALARM on PC13 output\r type" + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: "Synchronous prescaler\r factor" + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: "Asynchronous prescaler\r factor" + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: "Subtract a fraction of a\r second" + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: tamper configuration register + fields: + - name: TAMP1E + description: Tamper 1 detection enable + bit_offset: 0 + bit_size: 1 + - name: TAMP1TRG + description: Active level for tamper 1 + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP2E + description: Tamper 2 detection enable + bit_offset: 3 + bit_size: 1 + - name: TAMP2TRG + description: Active level for tamper 2 + bit_offset: 4 + bit_size: 1 + - name: TAMP3E + description: Tamper 3 detection enable + bit_offset: 5 + bit_size: 1 + - name: TAMP3TRG + description: Active level for tamper 3 + bit_offset: 6 + bit_size: 1 + - name: TAMPTS + description: "Activate timestamp on tamper detection\r event" + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + - name: TAMPPUDIS + description: TAMPER pull-up disable + bit_offset: 15 + bit_size: 1 + - name: TAMP1IE + description: Tamper 1 interrupt enable + bit_offset: 16 + bit_size: 1 + - name: TAMP1NOERASE + description: Tamper 1 no erase + bit_offset: 17 + bit_size: 1 + - name: TAMP1MF + description: Tamper 1 mask flag + bit_offset: 18 + bit_size: 1 + - name: TAMP2IE + description: Tamper 2 interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TAMP2NOERASE + description: Tamper 2 no erase + bit_offset: 20 + bit_size: 1 + - name: TAMP2MF + description: Tamper 2 mask flag + bit_offset: 21 + bit_size: 1 + - name: TAMP3IE + description: Tamper 3 interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TAMP3NOERASE + description: Tamper 3 no erase + bit_offset: 23 + bit_size: 1 + - name: TAMP3MF + description: Tamper 3 mask flag + bit_offset: 24 + bit_size: 1 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: time stamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: "Wakeup auto-reload value\r bits" + bit_offset: 0 + bit_size: 16 diff --git a/data/registers/rtc_l41x-l42x.yaml b/data/registers/rtc_l41x-l42x.yaml new file mode 100644 index 0000000..198d9cb --- /dev/null +++ b/data/registers/rtc_l41x-l42x.yaml @@ -0,0 +1,645 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: RTC initialization control and status register + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: control register + byte_offset: 24 + fieldset: CR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMAR + description: alarm A register + byte_offset: 64 + fieldset: ALRMAR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBR + description: alarm B register + byte_offset: 72 + fieldset: ALRMBR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 76 + fieldset: ALRMBSSR + - name: SR + description: RTC status register + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: RTC masked interrupt status register + byte_offset: 84 + access: Read + fieldset: MISR + - name: SCR + description: RTC status clear register + byte_offset: 92 + access: Write + fieldset: SCR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD\r format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting\r at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD\r format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting\r at this bit" + bit_offset: 24 + bit_size: 4 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: LPCAL + description: Calibration low-power mode + bit_offset: 12 + bit_size: 1 + - name: CALW16 + description: "Use a 16-second calibration cycle\r period" + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: "Use an 8-second calibration cycle\r period" + bit_offset: 14 + bit_size: 1 + - name: CALP + description: "Increase frequency of RTC by 488.5\r ppm" + bit_offset: 15 + bit_size: 1 +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: "Time-stamp event active\r edge" + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: "Reference clock detection enable (50 or\r 60 Hz)" + bit_offset: 4 + bit_size: 1 + - name: BYPSHAD + description: "Bypass the shadow\r registers" + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Time stamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + - name: WUTIE + description: "Wakeup timer interrupt\r enable" + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: "Time-stamp interrupt\r enable" + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: "Add 1 hour (summer time\r change)" + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: "Subtract 1 hour (winter time\r change)" + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: "Calibration output\r selection" + bit_offset: 19 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: "timestamp on internal event\r enable" + bit_offset: 24 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: Tamper detection output enable on TAMPALRM + bit_offset: 26 + bit_size: 1 + - name: TAMPALRM_PU + description: TAMPALRM pull-up enable + bit_offset: 29 + bit_size: 1 + - name: TAMPALRM_TYPE + description: TAMPALRM output type + bit_offset: 30 + bit_size: 1 + - name: OUT2EN + description: RTC_OUT2 output enable + bit_offset: 31 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ICSR: + description: RTC initialization control and status register + fields: + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 +fieldset/MISR: + description: RTC masked interrupt status register + fields: + - name: ALRAMF + description: Alarm A masked flag + bit_offset: 0 + bit_size: 1 + - name: ALRBMF + description: Alarm B masked flag + bit_offset: 1 + bit_size: 1 + - name: WUTMF + description: Wakeup timer masked flag + bit_offset: 2 + bit_size: 1 + - name: TSMF + description: Timestamp masked flag + bit_offset: 3 + bit_size: 1 + - name: TSOVMF + description: Timestamp overflow masked flag + bit_offset: 4 + bit_size: 1 + - name: ITSMF + description: Internal timestamp masked flag + bit_offset: 5 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: "Synchronous prescaler\r factor" + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: "Asynchronous prescaler\r factor" + bit_offset: 16 + bit_size: 7 +fieldset/SCR: + description: RTC status clear register + fields: + - name: CALRAF + description: Clear alarm A flag + bit_offset: 0 + bit_size: 1 + - name: CALRBF + description: Clear alarm B flag + bit_offset: 1 + bit_size: 1 + - name: CWUTF + description: Clear wakeup timer flag + bit_offset: 2 + bit_size: 1 + - name: CTSF + description: Clear timestamp flag + bit_offset: 3 + bit_size: 1 + - name: CTSOVF + description: Clear timestamp overflow flag + bit_offset: 4 + bit_size: 1 + - name: CITSF + description: Clear internal timestamp flag + bit_offset: 5 + bit_size: 1 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: "Subtract a fraction of a\r second" + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SR: + description: RTC status register + fields: + - name: ALRAF + description: Alarm A flag + bit_offset: 0 + bit_size: 1 + - name: ALRBF + description: Alarm B flag + bit_offset: 1 + bit_size: 1 + - name: WUTF + description: Wakeup timer flag + bit_offset: 2 + bit_size: 1 + - name: TSF + description: Timestamp flag + bit_offset: 3 + bit_size: 1 + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 4 + bit_size: 1 + - name: ITSF + description: Internal timestamp flag + bit_offset: 5 + bit_size: 1 +fieldset/SSR: + description: sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: time stamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: "Wakeup auto-reload value\r bits" + bit_offset: 0 + bit_size: 16 + - name: WUTOCLR + description: Wakeup auto-reload output clear value + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/rtc_l5.yaml b/data/registers/rtc_l5.yaml new file mode 100644 index 0000000..894f9f7 --- /dev/null +++ b/data/registers/rtc_l5.yaml @@ -0,0 +1,755 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: RTC sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: " RTC initialization control and status register " + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: RTC control register + byte_offset: 24 + fieldset: CR + - name: PRIVCR + description: " RTC privilege mode control register " + byte_offset: 28 + fieldset: PRIVCR + - name: SMCR + description: " RTC secure mode control register " + byte_offset: 32 + fieldset: SMCR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMAR + description: alarm A register + byte_offset: 64 + fieldset: ALRMAR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBR + description: alarm B register + byte_offset: 72 + fieldset: ALRMBR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 76 + fieldset: ALRMBSSR + - name: SR + description: RTC status register + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: " RTC non-secure masked interrupt status register " + byte_offset: 84 + access: Read + fieldset: MISR + - name: SMISR + description: " RTC secure masked interrupt status register " + byte_offset: 88 + access: Read + fieldset: SMISR + - name: SCR + description: RTC status clear register + byte_offset: 92 + access: Write + fieldset: SCR +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: " Date units or day in BCD format " + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: " Mask the most-significant bits starting at this bit " + bit_offset: 24 + bit_size: 4 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: " Date units or day in BCD format " + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: " Mask the most-significant bits starting at this bit " + bit_offset: 24 + bit_size: 4 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: LPCAL + description: LPCAL + bit_offset: 12 + bit_size: 1 + - name: CALW16 + description: " Use a 16-second calibration cycle period " + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: " Use an 8-second calibration cycle period " + bit_offset: 14 + bit_size: 1 + - name: CALP + description: " Increase frequency of RTC by 488.5 ppm " + bit_offset: 15 + bit_size: 1 +fieldset/CR: + description: RTC control register + fields: + - name: WUCKSEL + description: WUCKSEL + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: TSEDGE + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: REFCKON + bit_offset: 4 + bit_size: 1 + - name: BYPSHAD + description: BYPSHAD + bit_offset: 5 + bit_size: 1 + - name: FMT + description: FMT + bit_offset: 6 + bit_size: 1 + - name: ALRAE + description: ALRAE + bit_offset: 8 + bit_size: 1 + - name: ALRBE + description: ALRBE + bit_offset: 9 + bit_size: 1 + - name: WUTE + description: WUTE + bit_offset: 10 + bit_size: 1 + - name: TSE + description: TSE + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: ALRAIE + bit_offset: 12 + bit_size: 1 + - name: ALRBIE + description: ALRBIE + bit_offset: 13 + bit_size: 1 + - name: WUTIE + description: WUTIE + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: TSIE + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: ADD1H + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: SUB1H + bit_offset: 17 + bit_size: 1 + - name: BKP + description: BKP + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: COSEL + bit_offset: 19 + bit_size: 1 + - name: POL + description: POL + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: OSEL + bit_offset: 21 + bit_size: 2 + - name: COE + description: COE + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: ITSE + bit_offset: 24 + bit_size: 1 + - name: TAMPTS + description: TAMPTS + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: TAMPOE + bit_offset: 26 + bit_size: 1 + - name: TAMPALRM_PU + description: TAMPALRM_PU + bit_offset: 29 + bit_size: 1 + - name: TAMPALRM_TYPE + description: TAMPALRM_TYPE + bit_offset: 30 + bit_size: 1 + - name: OUT2EN + description: OUT2EN + bit_offset: 31 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ICSR: + description: " RTC initialization control and status register " + fields: + - name: ALRAWF + description: Alarm A write flag + bit_offset: 0 + bit_size: 1 + - name: ALRBWF + description: Alarm B write flag + bit_offset: 1 + bit_size: 1 + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: " Registers synchronization flag " + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 +fieldset/MISR: + description: " RTC non-secure masked interrupt status register " + fields: + - name: ALRAMF + description: ALRAMF + bit_offset: 0 + bit_size: 1 + - name: ALRBMF + description: ALRBMF + bit_offset: 1 + bit_size: 1 + - name: WUTMF + description: WUTMF + bit_offset: 2 + bit_size: 1 + - name: TSMF + description: TSMF + bit_offset: 3 + bit_size: 1 + - name: TSOVMF + description: TSOVMF + bit_offset: 4 + bit_size: 1 + - name: ITSMF + description: ITSMF + bit_offset: 5 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: " Synchronous prescaler factor " + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: " Asynchronous prescaler factor " + bit_offset: 16 + bit_size: 7 +fieldset/PRIVCR: + description: " RTC privilege mode control register " + fields: + - name: ALRAPRIV + description: ALRAPRIV + bit_offset: 0 + bit_size: 1 + - name: ALRBPRIV + description: ALRBPRIV + bit_offset: 1 + bit_size: 1 + - name: WUTPRIV + description: WUTPRIV + bit_offset: 2 + bit_size: 1 + - name: TSPRIV + description: TSPRIV + bit_offset: 3 + bit_size: 1 + - name: CALPRIV + description: CALPRIV + bit_offset: 13 + bit_size: 1 + - name: INITPRIV + description: INITPRIV + bit_offset: 14 + bit_size: 1 + - name: PRIV + description: PRIV + bit_offset: 15 + bit_size: 1 +fieldset/SCR: + description: RTC status clear register + fields: + - name: CALRAF + description: CALRAF + bit_offset: 0 + bit_size: 1 + - name: CALRBF + description: CALRBF + bit_offset: 1 + bit_size: 1 + - name: CWUTF + description: CWUTF + bit_offset: 2 + bit_size: 1 + - name: CTSF + description: CTSF + bit_offset: 3 + bit_size: 1 + - name: CTSOVF + description: CTSOVF + bit_offset: 4 + bit_size: 1 + - name: CITSF + description: CITSF + bit_offset: 5 + bit_size: 1 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: " Subtract a fraction of a second " + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SMCR: + description: " RTC secure mode control register " + fields: + - name: ALRADPROT + description: ALRADPROT + bit_offset: 0 + bit_size: 1 + - name: ALRBDPROT + description: ALRBDPROT + bit_offset: 1 + bit_size: 1 + - name: WUTDPROT + description: WUTDPROT + bit_offset: 2 + bit_size: 1 + - name: TSDPROT + description: TSDPROT + bit_offset: 3 + bit_size: 1 + - name: CALDPROT + description: CALDPROT + bit_offset: 13 + bit_size: 1 + - name: INITDPROT + description: INITDPROT + bit_offset: 14 + bit_size: 1 + - name: DECPROT + description: DECPROT + bit_offset: 15 + bit_size: 1 +fieldset/SMISR: + description: " RTC secure masked interrupt status register " + fields: + - name: ALRAMF + description: ALRAMF + bit_offset: 0 + bit_size: 1 + - name: ALRBMF + description: ALRBMF + bit_offset: 1 + bit_size: 1 + - name: WUTMF + description: WUTMF + bit_offset: 2 + bit_size: 1 + - name: TSMF + description: TSMF + bit_offset: 3 + bit_size: 1 + - name: TSOVMF + description: TSOVMF + bit_offset: 4 + bit_size: 1 + - name: ITSMF + description: ITSMF + bit_offset: 5 + bit_size: 1 +fieldset/SR: + description: RTC status register + fields: + - name: ALRAF + description: ALRAF + bit_offset: 0 + bit_size: 1 + - name: ALRBF + description: ALRBF + bit_offset: 1 + bit_size: 1 + - name: WUTF + description: WUTF + bit_offset: 2 + bit_size: 1 + - name: TSF + description: TSF + bit_offset: 3 + bit_size: 1 + - name: TSOVF + description: TSOVF + bit_offset: 4 + bit_size: 1 + - name: ITSF + description: ITSF + bit_offset: 5 + bit_size: 1 +fieldset/SSR: + description: RTC sub second register + fields: + - name: SS + description: SS + bit_offset: 0 + bit_size: 16 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: time stamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: " Wakeup auto-reload value bits " + bit_offset: 0 + bit_size: 16 + - name: WUTOCLR + description: WUTOCLR + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/rtc_u5.yaml b/data/registers/rtc_u5.yaml new file mode 100644 index 0000000..b81ee9f --- /dev/null +++ b/data/registers/rtc_u5.yaml @@ -0,0 +1,813 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: RTC sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: "RTC initialization control and status register" + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: RTC control register + byte_offset: 24 + fieldset: CR + - name: PRIVCR + description: "RTC privilege mode control register" + byte_offset: 28 + fieldset: PRIVCR + - name: SECCFGR + description: "RTC secure mode control register" + byte_offset: 32 + fieldset: SECCFGR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: time stamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: time stamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMAR + description: alarm A register + byte_offset: 64 + fieldset: ALRMAR + - name: ALRMASSR + description: alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBR + description: alarm B register + byte_offset: 72 + fieldset: ALRMBR + - name: ALRMBSSR + description: alarm B sub second register + byte_offset: 76 + fieldset: ALRMBSSR + - name: SR + description: RTC status register + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: "RTC non-secure masked interrupt status register" + byte_offset: 84 + access: Read + fieldset: MISR + - name: SMISR + description: "RTC secure masked interrupt status register" + byte_offset: 88 + access: Read + fieldset: SMISR + - name: SCR + description: RTC status clear register + byte_offset: 92 + access: Write + fieldset: SCR + - name: ALRABINR + description: RTC alarm A binary mode register + byte_offset: 112 + fieldset: ALRABINR + - name: ALRBBINR + description: RTC alarm B binary mode register + byte_offset: 116 + fieldset: ALRBBINR +fieldset/ALRABINR: + description: RTC alarm A binary mode register + fields: + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 +fieldset/ALRBBINR: + description: RTC alarm B binary mode register + fields: + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 +fieldset/ALRMAR: + description: alarm A register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 6 + - name: SSCLR + description: SSCLR + bit_offset: 31 + bit_size: 1 +fieldset/ALRMBR: + description: alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: "Date units or day in BCD format" + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: "Mask the most-significant bits starting at this bit" + bit_offset: 24 + bit_size: 6 + - name: SSCLR + description: SSCLR + bit_offset: 31 + bit_size: 1 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: LPCAL + description: LPCAL + bit_offset: 12 + bit_size: 1 + - name: CALW16 + description: "Use a 16-second calibration cycle period" + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: "Use an 8-second calibration cycle period" + bit_offset: 14 + bit_size: 1 + - name: CALP + description: "Increase frequency of RTC by 488.5 ppm" + bit_offset: 15 + bit_size: 1 +fieldset/CR: + description: RTC control register + fields: + - name: WUCKSEL + description: WUCKSEL + bit_offset: 0 + bit_size: 3 + - name: TSEDGE + description: TSEDGE + bit_offset: 3 + bit_size: 1 + - name: REFCKON + description: REFCKON + bit_offset: 4 + bit_size: 1 + - name: BYPSHAD + description: BYPSHAD + bit_offset: 5 + bit_size: 1 + - name: FMT + description: FMT + bit_offset: 6 + bit_size: 1 + - name: SSRUIE + description: SSRUIE + bit_offset: 7 + bit_size: 1 + - name: ALRAE + description: ALRAE + bit_offset: 8 + bit_size: 1 + - name: ALRBE + description: ALRBE + bit_offset: 9 + bit_size: 1 + - name: WUTE + description: WUTE + bit_offset: 10 + bit_size: 1 + - name: TSE + description: TSE + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: ALRAIE + bit_offset: 12 + bit_size: 1 + - name: ALRBIE + description: ALRBIE + bit_offset: 13 + bit_size: 1 + - name: WUTIE + description: WUTIE + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: TSIE + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: ADD1H + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: SUB1H + bit_offset: 17 + bit_size: 1 + - name: BKP + description: BKP + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: COSEL + bit_offset: 19 + bit_size: 1 + - name: POL + description: POL + bit_offset: 20 + bit_size: 1 + - name: OSEL + description: OSEL + bit_offset: 21 + bit_size: 2 + - name: COE + description: COE + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: ITSE + bit_offset: 24 + bit_size: 1 + - name: TAMPTS + description: TAMPTS + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: TAMPOE + bit_offset: 26 + bit_size: 1 + - name: ALRAFCLR + description: ALRAFCLR + bit_offset: 27 + bit_size: 1 + - name: ALRBFCLR + description: ALRBFCLR + bit_offset: 28 + bit_size: 1 + - name: TAMPALRM_PU + description: TAMPALRM_PU + bit_offset: 29 + bit_size: 1 + - name: TAMPALRM_TYPE + description: TAMPALRM_TYPE + bit_offset: 30 + bit_size: 1 + - name: OUT2EN + description: OUT2EN + bit_offset: 31 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ICSR: + description: "RTC initialization control and status register" + fields: + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + - name: RSF + description: "Registers synchronization flag" + bit_offset: 5 + bit_size: 1 + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + - name: BIN + description: BIN + bit_offset: 8 + bit_size: 2 + - name: BCDU + description: BCDU + bit_offset: 10 + bit_size: 3 + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 +fieldset/MISR: + description: "RTC non-secure masked interrupt status register" + fields: + - name: ALRAMF + description: ALRAMF + bit_offset: 0 + bit_size: 1 + - name: ALRBMF + description: ALRBMF + bit_offset: 1 + bit_size: 1 + - name: WUTMF + description: WUTMF + bit_offset: 2 + bit_size: 1 + - name: TSMF + description: TSMF + bit_offset: 3 + bit_size: 1 + - name: TSOVMF + description: TSOVMF + bit_offset: 4 + bit_size: 1 + - name: ITSMF + description: ITSMF + bit_offset: 5 + bit_size: 1 + - name: SSRUMF + description: SSRUMF + bit_offset: 6 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: "Synchronous prescaler factor" + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: "Asynchronous prescaler factor" + bit_offset: 16 + bit_size: 7 +fieldset/PRIVCR: + description: "RTC privilege mode control register" + fields: + - name: ALRAPRIV + description: ALRAPRIV + bit_offset: 0 + bit_size: 1 + - name: ALRBPRIV + description: ALRBPRIV + bit_offset: 1 + bit_size: 1 + - name: WUTPRIV + description: WUTPRIV + bit_offset: 2 + bit_size: 1 + - name: TSPRIV + description: TSPRIV + bit_offset: 3 + bit_size: 1 + - name: CALPRIV + description: CALPRIV + bit_offset: 13 + bit_size: 1 + - name: INITPRIV + description: INITPRIV + bit_offset: 14 + bit_size: 1 + - name: PRIV + description: PRIV + bit_offset: 15 + bit_size: 1 +fieldset/SCR: + description: RTC status clear register + fields: + - name: CALRAF + description: CALRAF + bit_offset: 0 + bit_size: 1 + - name: CALRBF + description: CALRBF + bit_offset: 1 + bit_size: 1 + - name: CWUTF + description: CWUTF + bit_offset: 2 + bit_size: 1 + - name: CTSF + description: CTSF + bit_offset: 3 + bit_size: 1 + - name: CTSOVF + description: CTSOVF + bit_offset: 4 + bit_size: 1 + - name: CITSF + description: CITSF + bit_offset: 5 + bit_size: 1 + - name: CSSRUF + description: CSSRUF + bit_offset: 6 + bit_size: 1 +fieldset/SECCFGR: + description: "RTC secure mode control register" + fields: + - name: ALRASEC + description: ALRASEC + bit_offset: 0 + bit_size: 1 + - name: ALRBSEC + description: ALRBSEC + bit_offset: 1 + bit_size: 1 + - name: WUTSEC + description: WUTSEC + bit_offset: 2 + bit_size: 1 + - name: TSSEC + description: TSSEC + bit_offset: 3 + bit_size: 1 + - name: CALSEC + description: CALSEC + bit_offset: 13 + bit_size: 1 + - name: INITSEC + description: INITSEC + bit_offset: 14 + bit_size: 1 + - name: SEC + description: SEC + bit_offset: 15 + bit_size: 1 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: "Subtract a fraction of a second" + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SMISR: + description: "RTC secure masked interrupt status register" + fields: + - name: ALRAMF + description: ALRAMF + bit_offset: 0 + bit_size: 1 + - name: ALRBMF + description: ALRBMF + bit_offset: 1 + bit_size: 1 + - name: WUTMF + description: WUTMF + bit_offset: 2 + bit_size: 1 + - name: TSMF + description: TSMF + bit_offset: 3 + bit_size: 1 + - name: TSOVMF + description: TSOVMF + bit_offset: 4 + bit_size: 1 + - name: ITSMF + description: ITSMF + bit_offset: 5 + bit_size: 1 + - name: SSRUMF + description: SSRUMF + bit_offset: 6 + bit_size: 1 +fieldset/SR: + description: RTC status register + fields: + - name: ALRAF + description: ALRAF + bit_offset: 0 + bit_size: 1 + - name: ALRBF + description: ALRBF + bit_offset: 1 + bit_size: 1 + - name: WUTF + description: WUTF + bit_offset: 2 + bit_size: 1 + - name: TSF + description: TSF + bit_offset: 3 + bit_size: 1 + - name: TSOVF + description: TSOVF + bit_offset: 4 + bit_size: 1 + - name: ITSF + description: ITSF + bit_offset: 5 + bit_size: 1 + - name: SSRUF + description: SSRUF + bit_offset: 6 + bit_size: 1 +fieldset/SSR: + description: RTC sub second register + fields: + - name: SS + description: SS + bit_offset: 0 + bit_size: 32 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/TSDR: + description: time stamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 32 +fieldset/TSTR: + description: time stamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: "Wakeup auto-reload value bits" + bit_offset: 0 + bit_size: 16 + - name: WUTOCLR + description: WUTOCLR + bit_offset: 16 + bit_size: 16 diff --git a/data/registers/rtc_wl.yaml b/data/registers/rtc_wl.yaml new file mode 100644 index 0000000..b1d315b --- /dev/null +++ b/data/registers/rtc_wl.yaml @@ -0,0 +1,1360 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: Sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: Initialization control and status register + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: Pre-scaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: Control register + byte_offset: 24 + fieldset: CR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: Calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMAR + description: Alarm A register + byte_offset: 64 + fieldset: ALRMAR + - name: ALRMASSR + description: Alarm A sub second register + byte_offset: 68 + fieldset: ALRMASSR + - name: ALRMBR + description: Alarm B register + byte_offset: 72 + fieldset: ALRMBR + - name: ALRMBSSR + description: Alarm B sub second register + byte_offset: 76 + fieldset: ALRMBSSR + - name: SR + description: Status register (interrupts) + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: Masked interrupt status register + byte_offset: 84 + access: Read + fieldset: MISR + - name: SCR + description: Status clear register (interrupts) + byte_offset: 92 + access: Write + fieldset: SCR + - name: ALRABINR + description: RTC alarm A binary mode register + byte_offset: 112 + fieldset: ALRABINR + - name: ALRBBINR + description: RTC alarm B binary mode register + byte_offset: 116 + fieldset: ALRBBINR +fieldset/ALRABINR: + description: RTC alarm A binary mode register + fields: + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 +fieldset/ALRBBINR: + description: RTC alarm B binary mode register + fields: + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 +fieldset/ALRMAR: + description: Alarm A register + fields: + - name: SU + description: Second units in BCD format. + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMAR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMAR_MSK1 + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMAR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMAR_MSK1 +fieldset/ALRMASSR: + description: Alarm A sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 6 + - name: SSCLR + description: Clear synchronous counter on alarm (Binary mode only) + bit_offset: 31 + bit_size: 1 + enum: ALRMASSR_SSCLR +fieldset/ALRMBR: + description: Alarm B register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm B seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm B minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMBR_PM + - name: MSK3 + description: Alarm B hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMBR_MSK1 + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMBR_WDSEL + - name: MSK4 + description: Alarm B date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMBR_MSK1 +fieldset/ALRMBSSR: + description: Alarm B sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 6 + - name: SSCLR + description: Clear synchronous counter on alarm (Binary mode only) + bit_offset: 31 + bit_size: 1 + enum: ALRMBSSR_SSCLR +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: LPCAL + description: Calibration low-power mode + bit_offset: 12 + bit_size: 1 + enum: LPCAL + - name: CALW16 + description: CALW16 + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use a 16-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Use an 8-second calibration cycle period + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: RTC_REFIN reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: SSRUIE + description: SSR underflow interrupt enable + bit_offset: 7 + bit_size: 1 + enum: SSRUIE + - name: ALRAE + description: Alarm A enable + bit_offset: 8 + bit_size: 1 + enum: ALRAE + - name: ALRBE + description: Alarm B enable + bit_offset: 9 + bit_size: 1 + enum: ALRBE + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + enum: WUTE + - name: TSE + description: timestamp enable + bit_offset: 11 + bit_size: 1 + enum: TSE + - name: ALRAIE + description: Alarm A interrupt enable + bit_offset: 12 + bit_size: 1 + enum: ALRAIE + - name: ALRBIE + description: Alarm B interrupt enable + bit_offset: 13 + bit_size: 1 + enum: ALRBIE + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + enum: WUTIE + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + enum: TSIE + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + enum_write: ADD1HW + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + enum_write: SUB1HW + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + enum: BKP + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + enum: COE + - name: ITSE + description: timestamp on internal event enable + bit_offset: 24 + bit_size: 1 + enum: ITSE + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 25 + bit_size: 1 + enum: TAMPTS + - name: TAMPOE + description: Tamper detection output enable on TAMPALRM + bit_offset: 26 + bit_size: 1 + enum: TAMPOE + - name: TAMPALRM_PU + description: TAMPALRM pull-up enable + bit_offset: 29 + bit_size: 1 + enum: TAMPALRM_PU + - name: TAMPALRM_TYPE + description: TAMPALRM output type + bit_offset: 30 + bit_size: 1 + enum: TAMPALRM_TYPE + - name: OUT2EN + description: RTC_OUT2 output enable + bit_offset: 31 + bit_size: 1 + enum: OUT2EN +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ICSR: + description: Initialization control and status register + fields: + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: BIN + description: Binary mode + bit_offset: 8 + bit_size: 2 + enum: BIN + - name: BCDU + description: BCD update + bit_offset: 10 + bit_size: 3 + enum: BCDU + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/MISR: + description: Masked interrupt status register + fields: + - name: ALRAMF + description: Alarm A masked flag + bit_offset: 0 + bit_size: 1 + enum: ALRAMF + - name: ALRBMF + description: Alarm B masked flag + bit_offset: 1 + bit_size: 1 + enum: ALRBMF + - name: WUTMF + description: Wakeup timer masked flag + bit_offset: 2 + bit_size: 1 + enum: WUTMF + - name: TSMF + description: Timestamp masked flag + bit_offset: 3 + bit_size: 1 + enum: TSMF + - name: TSOVMF + description: Timestamp overflow masked flag + bit_offset: 4 + bit_size: 1 + enum: TSOVMF + - name: ITSMF + description: Internal timestamp masked flag + bit_offset: 5 + bit_size: 1 + enum: ITSMF + - name: SSRUMF + description: SSR underflow masked flag + bit_offset: 6 + bit_size: 1 + enum: SSRUMF +fieldset/PRER: + description: Pre-scaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SCR: + description: Status clear register (interrupts) + fields: + - name: CALRAF + description: Clear alarm A flag + bit_offset: 0 + bit_size: 1 + enum: CALRAF + - name: CALRBF + description: Clear alarm B flag + bit_offset: 1 + bit_size: 1 + enum: CALRAF + - name: CWUTF + description: Clear wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: CALRAF + - name: CTSF + description: Clear timestamp flag + bit_offset: 3 + bit_size: 1 + enum: CALRAF + - name: CTSOVF + description: Clear timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: CALRAF + - name: CITSF + description: Clear internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: CALRAF + - name: CSSRUF + description: Clear SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: CALRAF +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 + enum_write: ADD1SW +fieldset/SR: + description: Status register (interrupts) + fields: + - name: ALRAF + description: Alarm A flag + bit_offset: 0 + bit_size: 1 + enum: ALRAF + - name: ALRBF + description: Alarm B flag + bit_offset: 1 + bit_size: 1 + enum: ALRBF + - name: WUTF + description: Wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: WUTF + - name: TSF + description: Timestamp flag + bit_offset: 3 + bit_size: 1 + enum: TSF + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: TSOVF + - name: ITSF + description: Internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: ITSF + - name: SSRUF + description: SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: SSRUF +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Synchronous binary counter + bit_offset: 0 + bit_size: 32 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: TR_PM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 32 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format. + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format. + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format. + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format. + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format. + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format. + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 + enum: KEY +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 + - name: WUTOCLR + description: Wakeup auto-reload output clear value + bit_offset: 16 + bit_size: 16 +enum/ADD1HW: + bit_size: 1 + variants: + - name: Add1 + description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + value: 1 +enum/ADD1SW: + bit_size: 1 + variants: + - name: Add1 + description: Add one second to the clock/calendar + value: 1 +enum/ALRAE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A disabled + value: 0 + - name: Enabled + description: Alarm A enabled + value: 1 +enum/ALRAF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRAIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A interrupt disabled + value: 0 + - name: Enabled + description: Alarm A interrupt enabled + value: 1 +enum/ALRAMF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRBE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B disabled + value: 0 + - name: Enabled + description: Alarm B enabled + value: 1 +enum/ALRBF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + value: 1 +enum/ALRBIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B Interrupt disabled + value: 0 + - name: Enabled + description: Alarm B Interrupt enabled + value: 1 +enum/ALRBMF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + value: 1 +enum/ALRMAR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMAR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMAR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMASSR_SSCLR: + bit_size: 1 + variants: + - name: FreeRunning + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" + value: 0 + - name: ALRMBINR + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" + value: 1 +enum/ALRMBR_MSK1: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMBR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMBR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMBSSR_SSCLR: + bit_size: 1 + variants: + - name: FreeRunning + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" + value: 0 + - name: ALRMBINR + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" + value: 1 +enum/BCDU: + bit_size: 3 + variants: + - name: Bit7 + description: "1s increment each time SS[7:0]=0" + value: 0 + - name: Bit8 + description: "1s increment each time SS[8:0]=0" + value: 1 + - name: Bit9 + description: "1s increment each time SS[9:0]=0" + value: 2 + - name: Bit10 + description: "1s increment each time SS[10:0]=0" + value: 3 + - name: Bit11 + description: "1s increment each time SS[11:0]=0" + value: 4 + - name: Bit12 + description: "1s increment each time SS[12:0]=0" + value: 5 + - name: Bit13 + description: "1s increment each time SS[13:0]=0" + value: 6 + - name: Bit14 + description: "1s increment each time SS[14:0]=0" + value: 7 +enum/BIN: + bit_size: 2 + variants: + - name: BCD + description: Free running BCD calendar mode (Binary mode disabled) + value: 0 + - name: Binary + description: Free running Binary mode (BCD mode disabled) + value: 1 + - name: BinBCD + description: Free running BCD calendar and Binary modes + value: 2 + - name: BinBCD2 + description: Free running BCD calendar and Binary modes + value: 3 +enum/BKP: + bit_size: 1 + variants: + - name: DSTNotChanged + description: Daylight Saving Time change has not been performed + value: 0 + - name: DSTChanged + description: Daylight Saving Time change has been performed + value: 1 +enum/BYPSHAD: + bit_size: 1 + variants: + - name: ShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" + value: 0 + - name: BypassShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALRAF: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag by writing 1 + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: SixteenSeconds + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: EightSeconds + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COE: + bit_size: 1 + variants: + - name: Disabled + description: Calibration output disabled + value: 0 + - name: Enabled + description: Calibration output enabled + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: TwentyFourHour + description: 24 hour/day format + value: 0 + - name: AmPm + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/ITSE: + bit_size: 1 + variants: + - name: Disabled + description: Internal event timestamp disabled + value: 0 + - name: Enabled + description: Internal event timestamp enabled + value: 1 +enum/ITSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/ITSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/KEY: + bit_size: 8 + variants: + - name: Activate + description: Activate write protection (any value that is not the keys) + value: 0 + - name: Deactivate2 + description: Key 2 + value: 83 + - name: Deactivate1 + description: Key 1 + value: 202 +enum/LPCAL: + bit_size: 1 + variants: + - name: RTCCLK + description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" + value: 0 + - name: CkApre + description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/OUT2EN: + bit_size: 1 + variants: + - name: Disabled + description: RTC output 2 disable + value: 0 + - name: Enabled + description: RTC output 2 enable + value: 1 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SSRUF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/SSRUIE: + bit_size: 1 + variants: + - name: Disabled + description: SSR underflow interrupt disabled + value: 0 + - name: Enabled + description: SSR underflow interrupt enabled + value: 1 +enum/SSRUMF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/SUB1HW: + bit_size: 1 + variants: + - name: Sub1 + description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + value: 1 +enum/TAMPALRM_PU: + bit_size: 1 + variants: + - name: NoPullUp + description: No pull-up is applied on TAMPALRM output + value: 0 + - name: PullUp + description: A pull-up is applied on TAMPALRM output + value: 1 +enum/TAMPALRM_TYPE: + bit_size: 1 + variants: + - name: PushPull + description: TAMPALRM is push-pull output + value: 0 + - name: OpenDrain + description: TAMPALRM is open-drain output + value: 1 +enum/TAMPOE: + bit_size: 1 + variants: + - name: Disabled + description: The tamper flag is not routed on TAMPALRM + value: 0 + - name: Enabled + description: "The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL" + value: 1 +enum/TAMPTS: + bit_size: 1 + variants: + - name: Disabled + description: Tamper detection event does not cause a RTC timestamp to be saved + value: 0 + - name: Enabled + description: Save RTC timestamp on tamper detection event + value: 1 +enum/TR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSE: + bit_size: 1 + variants: + - name: Disabled + description: Timestamp disabled + value: 0 + - name: Enabled + description: Timestamp enabled + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSIE: + bit_size: 1 + variants: + - name: Disabled + description: Time-stamp Interrupt disabled + value: 0 + - name: Enabled + description: Time-stamp Interrupt enabled + value: 1 +enum/TSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSOVF: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVMF: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer disabled + value: 0 + - name: Enabled + description: Wakeup timer enabled + value: 1 +enum/WUTF: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTIE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer interrupt disabled + value: 0 + - name: Enabled + description: Wakeup timer interrupt enabled + value: 1 +enum/WUTMF: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index d8856ca..99110b9 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -163,8 +163,22 @@ perimap = [ ('.*:MDIOS:mdios1_v1_0', ('mdios', 'v1', 'MDIOS')), ('.*:QUADSPI:quadspi1_v1_0', ('quadspi', 'v1', 'QUADSPI')), ('STM32F1.*:BKP.*', ('bkp', 'v1', 'BKP')), - ('.*:RTC:rtc2_v2_6', ('rtc', 'v2', 'RTC')), - ('.*:RTC:rtc2_v2_WB', ('rtc', 'wb', 'RTC')), + ('STM32F0.*:RTC:.*', ('rtc', 'f0', 'RTC')), + ('STM32F1.*:RTC:.*', ('rtc', 'f1', 'RTC')), + ('STM32F2.*:RTC:.*', ('rtc', 'f2', 'RTC')), + ('STM32F3.*:RTC:.*', ('rtc', 'f3', 'RTC')), + ('STM32F4.*:RTC:.*', ('rtc', 'f4', 'RTC')), + ('STM32F7.*:RTC:.*', ('rtc', 'f7', 'RTC')), + ('STM32G.*:RTC:.*', ('rtc', 'gx', 'RTC')), + ('STM32H7.*:RTC:.*', ('rtc', 'h7', 'RTC')), + ('STM32L0.*:RTC:.*', ('rtc', 'l0', 'RTC')), + ('STM32L1.*:RTC:.*', ('rtc', 'l1', 'RTC')), + ('STM32L41.*:RTC:.*', ('rtc', 'l41x-l42x', 'RTC')), + ('STM32L4.*:RTC:.*', ('rtc', 'l4', 'RTC')), + ('STM32L5.*:RTC:.*', ('rtc', 'l5', 'RTC')), + ('STM32U5.*:RTC:.*', ('rtc', 'u5', 'RTC')), + ('STM32WB.*:RTC:.*', ('rtc', 'wb', 'RTC')), + ('STM32WL.*:RTC:.*', ('rtc', 'wl', 'RTC')), ('.*:SAI:sai1_v1_1', ('sai', 'v1', 'SAI')), ('.*:SDIO:sdmmc_v1_2', ('sdmmc', 'v1', 'SDMMC')), ('.*:SDMMC:sdmmc_v1_3', ('sdmmc', 'v1', 'SDMMC')), From 82c3d2a485b567a73be469a59f65f3e6b206d3ae Mon Sep 17 00:00:00 2001 From: chemicstry Date: Tue, 31 May 2022 20:43:38 +0300 Subject: [PATCH 02/11] Group rtc regs by version --- data/registers/rtc_l41x-l42x.yaml | 645 -------- data/registers/rtc_l5.yaml | 755 --------- data/registers/{rtc_f1.yaml => rtc_v1.yaml} | 0 .../registers/{rtc_f0.yaml => rtc_v2-f0.yaml} | 0 .../registers/{rtc_f2.yaml => rtc_v2-f2.yaml} | 0 .../registers/{rtc_f3.yaml => rtc_v2-f3.yaml} | 0 .../registers/{rtc_f4.yaml => rtc_v2-f4.yaml} | 0 .../registers/{rtc_f7.yaml => rtc_v2-f7.yaml} | 0 .../registers/{rtc_h7.yaml => rtc_v2-h7.yaml} | 0 .../registers/{rtc_l0.yaml => rtc_v2-l0.yaml} | 0 .../registers/{rtc_l1.yaml => rtc_v2-l1.yaml} | 0 .../registers/{rtc_l4.yaml => rtc_v2-l4.yaml} | 0 .../registers/{rtc_u5.yaml => rtc_v2-u5.yaml} | 0 .../registers/{rtc_wb.yaml => rtc_v2-wb.yaml} | 0 data/registers/{rtc_gx.yaml => rtc_v3.yaml} | 0 data/registers/rtc_wl.yaml | 1360 ----------------- stm32data/__main__.py | 32 +- 17 files changed, 16 insertions(+), 2776 deletions(-) delete mode 100644 data/registers/rtc_l41x-l42x.yaml delete mode 100644 data/registers/rtc_l5.yaml rename data/registers/{rtc_f1.yaml => rtc_v1.yaml} (100%) rename data/registers/{rtc_f0.yaml => rtc_v2-f0.yaml} (100%) rename data/registers/{rtc_f2.yaml => rtc_v2-f2.yaml} (100%) rename data/registers/{rtc_f3.yaml => rtc_v2-f3.yaml} (100%) rename data/registers/{rtc_f4.yaml => rtc_v2-f4.yaml} (100%) rename data/registers/{rtc_f7.yaml => rtc_v2-f7.yaml} (100%) rename data/registers/{rtc_h7.yaml => rtc_v2-h7.yaml} (100%) rename data/registers/{rtc_l0.yaml => rtc_v2-l0.yaml} (100%) rename data/registers/{rtc_l1.yaml => rtc_v2-l1.yaml} (100%) rename data/registers/{rtc_l4.yaml => rtc_v2-l4.yaml} (100%) rename data/registers/{rtc_u5.yaml => rtc_v2-u5.yaml} (100%) rename data/registers/{rtc_wb.yaml => rtc_v2-wb.yaml} (100%) rename data/registers/{rtc_gx.yaml => rtc_v3.yaml} (100%) delete mode 100644 data/registers/rtc_wl.yaml diff --git a/data/registers/rtc_l41x-l42x.yaml b/data/registers/rtc_l41x-l42x.yaml deleted file mode 100644 index 198d9cb..0000000 --- a/data/registers/rtc_l41x-l42x.yaml +++ /dev/null @@ -1,645 +0,0 @@ ---- -block/RTC: - description: Real-time clock - items: - - name: TR - description: time register - byte_offset: 0 - fieldset: TR - - name: DR - description: date register - byte_offset: 4 - fieldset: DR - - name: SSR - description: sub second register - byte_offset: 8 - access: Read - fieldset: SSR - - name: ICSR - description: RTC initialization control and status register - byte_offset: 12 - fieldset: ICSR - - name: PRER - description: prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CR - description: control register - byte_offset: 24 - fieldset: CR - - name: WPR - description: write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: CALR - description: calibration register - byte_offset: 40 - fieldset: CALR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: time stamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: time stamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: ALRMAR - description: alarm A register - byte_offset: 64 - fieldset: ALRMAR - - name: ALRMASSR - description: alarm A sub second register - byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBR - description: alarm B register - byte_offset: 72 - fieldset: ALRMBR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 76 - fieldset: ALRMBSSR - - name: SR - description: RTC status register - byte_offset: 80 - access: Read - fieldset: SR - - name: MISR - description: RTC masked interrupt status register - byte_offset: 84 - access: Read - fieldset: MISR - - name: SCR - description: RTC status clear register - byte_offset: 92 - access: Write - fieldset: SCR -fieldset/ALRMAR: - description: alarm A register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: "Date units or day in BCD\r format" - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting\r at this bit" - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: "Date units or day in BCD\r format" - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting\r at this bit" - bit_offset: 24 - bit_size: 4 -fieldset/CALR: - description: calibration register - fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: LPCAL - description: Calibration low-power mode - bit_offset: 12 - bit_size: 1 - - name: CALW16 - description: "Use a 16-second calibration cycle\r period" - bit_offset: 13 - bit_size: 1 - - name: CALW8 - description: "Use an 8-second calibration cycle\r period" - bit_offset: 14 - bit_size: 1 - - name: CALP - description: "Increase frequency of RTC by 488.5\r ppm" - bit_offset: 15 - bit_size: 1 -fieldset/CR: - description: control register - fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - - name: TSEDGE - description: "Time-stamp event active\r edge" - bit_offset: 3 - bit_size: 1 - - name: REFCKON - description: "Reference clock detection enable (50 or\r 60 Hz)" - bit_offset: 4 - bit_size: 1 - - name: BYPSHAD - description: "Bypass the shadow\r registers" - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - - name: ALRAE - description: Alarm A enable - bit_offset: 8 - bit_size: 1 - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Time stamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRAIE - description: Alarm A interrupt enable - bit_offset: 12 - bit_size: 1 - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - - name: WUTIE - description: "Wakeup timer interrupt\r enable" - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: "Time-stamp interrupt\r enable" - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: "Add 1 hour (summer time\r change)" - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: "Subtract 1 hour (winter time\r change)" - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: "Calibration output\r selection" - bit_offset: 19 - bit_size: 1 - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: "timestamp on internal event\r enable" - bit_offset: 24 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 25 - bit_size: 1 - - name: TAMPOE - description: Tamper detection output enable on TAMPALRM - bit_offset: 26 - bit_size: 1 - - name: TAMPALRM_PU - description: TAMPALRM pull-up enable - bit_offset: 29 - bit_size: 1 - - name: TAMPALRM_TYPE - description: TAMPALRM output type - bit_offset: 30 - bit_size: 1 - - name: OUT2EN - description: RTC_OUT2 output enable - bit_offset: 31 - bit_size: 1 -fieldset/DR: - description: date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 -fieldset/ICSR: - description: RTC initialization control and status register - fields: - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 -fieldset/MISR: - description: RTC masked interrupt status register - fields: - - name: ALRAMF - description: Alarm A masked flag - bit_offset: 0 - bit_size: 1 - - name: ALRBMF - description: Alarm B masked flag - bit_offset: 1 - bit_size: 1 - - name: WUTMF - description: Wakeup timer masked flag - bit_offset: 2 - bit_size: 1 - - name: TSMF - description: Timestamp masked flag - bit_offset: 3 - bit_size: 1 - - name: TSOVMF - description: Timestamp overflow masked flag - bit_offset: 4 - bit_size: 1 - - name: ITSMF - description: Internal timestamp masked flag - bit_offset: 5 - bit_size: 1 -fieldset/PRER: - description: prescaler register - fields: - - name: PREDIV_S - description: "Synchronous prescaler\r factor" - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: "Asynchronous prescaler\r factor" - bit_offset: 16 - bit_size: 7 -fieldset/SCR: - description: RTC status clear register - fields: - - name: CALRAF - description: Clear alarm A flag - bit_offset: 0 - bit_size: 1 - - name: CALRBF - description: Clear alarm B flag - bit_offset: 1 - bit_size: 1 - - name: CWUTF - description: Clear wakeup timer flag - bit_offset: 2 - bit_size: 1 - - name: CTSF - description: Clear timestamp flag - bit_offset: 3 - bit_size: 1 - - name: CTSOVF - description: Clear timestamp overflow flag - bit_offset: 4 - bit_size: 1 - - name: CITSF - description: Clear internal timestamp flag - bit_offset: 5 - bit_size: 1 -fieldset/SHIFTR: - description: shift control register - fields: - - name: SUBFS - description: "Subtract a fraction of a\r second" - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 -fieldset/SR: - description: RTC status register - fields: - - name: ALRAF - description: Alarm A flag - bit_offset: 0 - bit_size: 1 - - name: ALRBF - description: Alarm B flag - bit_offset: 1 - bit_size: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 2 - bit_size: 1 - - name: TSF - description: Timestamp flag - bit_offset: 3 - bit_size: 1 - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 4 - bit_size: 1 - - name: ITSF - description: Internal timestamp flag - bit_offset: 5 - bit_size: 1 -fieldset/SSR: - description: sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 -fieldset/TR: - description: time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/TSDR: - description: time stamp date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 -fieldset/TSSSR: - description: timestamp sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 -fieldset/TSTR: - description: time stamp time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/WPR: - description: write protection register - fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 -fieldset/WUTR: - description: wakeup timer register - fields: - - name: WUT - description: "Wakeup auto-reload value\r bits" - bit_offset: 0 - bit_size: 16 - - name: WUTOCLR - description: Wakeup auto-reload output clear value - bit_offset: 16 - bit_size: 16 diff --git a/data/registers/rtc_l5.yaml b/data/registers/rtc_l5.yaml deleted file mode 100644 index 894f9f7..0000000 --- a/data/registers/rtc_l5.yaml +++ /dev/null @@ -1,755 +0,0 @@ ---- -block/RTC: - description: Real-time clock - items: - - name: TR - description: time register - byte_offset: 0 - fieldset: TR - - name: DR - description: date register - byte_offset: 4 - fieldset: DR - - name: SSR - description: RTC sub second register - byte_offset: 8 - access: Read - fieldset: SSR - - name: ICSR - description: " RTC initialization control and status register " - byte_offset: 12 - fieldset: ICSR - - name: PRER - description: prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CR - description: RTC control register - byte_offset: 24 - fieldset: CR - - name: PRIVCR - description: " RTC privilege mode control register " - byte_offset: 28 - fieldset: PRIVCR - - name: SMCR - description: " RTC secure mode control register " - byte_offset: 32 - fieldset: SMCR - - name: WPR - description: write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: CALR - description: calibration register - byte_offset: 40 - fieldset: CALR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: time stamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: time stamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: ALRMAR - description: alarm A register - byte_offset: 64 - fieldset: ALRMAR - - name: ALRMASSR - description: alarm A sub second register - byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBR - description: alarm B register - byte_offset: 72 - fieldset: ALRMBR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 76 - fieldset: ALRMBSSR - - name: SR - description: RTC status register - byte_offset: 80 - access: Read - fieldset: SR - - name: MISR - description: " RTC non-secure masked interrupt status register " - byte_offset: 84 - access: Read - fieldset: MISR - - name: SMISR - description: " RTC secure masked interrupt status register " - byte_offset: 88 - access: Read - fieldset: SMISR - - name: SCR - description: RTC status clear register - byte_offset: 92 - access: Write - fieldset: SCR -fieldset/ALRMAR: - description: alarm A register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: " Date units or day in BCD format " - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: " Mask the most-significant bits starting at this bit " - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: " Date units or day in BCD format " - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: " Mask the most-significant bits starting at this bit " - bit_offset: 24 - bit_size: 4 -fieldset/CALR: - description: calibration register - fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: LPCAL - description: LPCAL - bit_offset: 12 - bit_size: 1 - - name: CALW16 - description: " Use a 16-second calibration cycle period " - bit_offset: 13 - bit_size: 1 - - name: CALW8 - description: " Use an 8-second calibration cycle period " - bit_offset: 14 - bit_size: 1 - - name: CALP - description: " Increase frequency of RTC by 488.5 ppm " - bit_offset: 15 - bit_size: 1 -fieldset/CR: - description: RTC control register - fields: - - name: WUCKSEL - description: WUCKSEL - bit_offset: 0 - bit_size: 3 - - name: TSEDGE - description: TSEDGE - bit_offset: 3 - bit_size: 1 - - name: REFCKON - description: REFCKON - bit_offset: 4 - bit_size: 1 - - name: BYPSHAD - description: BYPSHAD - bit_offset: 5 - bit_size: 1 - - name: FMT - description: FMT - bit_offset: 6 - bit_size: 1 - - name: ALRAE - description: ALRAE - bit_offset: 8 - bit_size: 1 - - name: ALRBE - description: ALRBE - bit_offset: 9 - bit_size: 1 - - name: WUTE - description: WUTE - bit_offset: 10 - bit_size: 1 - - name: TSE - description: TSE - bit_offset: 11 - bit_size: 1 - - name: ALRAIE - description: ALRAIE - bit_offset: 12 - bit_size: 1 - - name: ALRBIE - description: ALRBIE - bit_offset: 13 - bit_size: 1 - - name: WUTIE - description: WUTIE - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: TSIE - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: ADD1H - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: SUB1H - bit_offset: 17 - bit_size: 1 - - name: BKP - description: BKP - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: COSEL - bit_offset: 19 - bit_size: 1 - - name: POL - description: POL - bit_offset: 20 - bit_size: 1 - - name: OSEL - description: OSEL - bit_offset: 21 - bit_size: 2 - - name: COE - description: COE - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: ITSE - bit_offset: 24 - bit_size: 1 - - name: TAMPTS - description: TAMPTS - bit_offset: 25 - bit_size: 1 - - name: TAMPOE - description: TAMPOE - bit_offset: 26 - bit_size: 1 - - name: TAMPALRM_PU - description: TAMPALRM_PU - bit_offset: 29 - bit_size: 1 - - name: TAMPALRM_TYPE - description: TAMPALRM_TYPE - bit_offset: 30 - bit_size: 1 - - name: OUT2EN - description: OUT2EN - bit_offset: 31 - bit_size: 1 -fieldset/DR: - description: date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 -fieldset/ICSR: - description: " RTC initialization control and status register " - fields: - - name: ALRAWF - description: Alarm A write flag - bit_offset: 0 - bit_size: 1 - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: " Registers synchronization flag " - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 -fieldset/MISR: - description: " RTC non-secure masked interrupt status register " - fields: - - name: ALRAMF - description: ALRAMF - bit_offset: 0 - bit_size: 1 - - name: ALRBMF - description: ALRBMF - bit_offset: 1 - bit_size: 1 - - name: WUTMF - description: WUTMF - bit_offset: 2 - bit_size: 1 - - name: TSMF - description: TSMF - bit_offset: 3 - bit_size: 1 - - name: TSOVMF - description: TSOVMF - bit_offset: 4 - bit_size: 1 - - name: ITSMF - description: ITSMF - bit_offset: 5 - bit_size: 1 -fieldset/PRER: - description: prescaler register - fields: - - name: PREDIV_S - description: " Synchronous prescaler factor " - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: " Asynchronous prescaler factor " - bit_offset: 16 - bit_size: 7 -fieldset/PRIVCR: - description: " RTC privilege mode control register " - fields: - - name: ALRAPRIV - description: ALRAPRIV - bit_offset: 0 - bit_size: 1 - - name: ALRBPRIV - description: ALRBPRIV - bit_offset: 1 - bit_size: 1 - - name: WUTPRIV - description: WUTPRIV - bit_offset: 2 - bit_size: 1 - - name: TSPRIV - description: TSPRIV - bit_offset: 3 - bit_size: 1 - - name: CALPRIV - description: CALPRIV - bit_offset: 13 - bit_size: 1 - - name: INITPRIV - description: INITPRIV - bit_offset: 14 - bit_size: 1 - - name: PRIV - description: PRIV - bit_offset: 15 - bit_size: 1 -fieldset/SCR: - description: RTC status clear register - fields: - - name: CALRAF - description: CALRAF - bit_offset: 0 - bit_size: 1 - - name: CALRBF - description: CALRBF - bit_offset: 1 - bit_size: 1 - - name: CWUTF - description: CWUTF - bit_offset: 2 - bit_size: 1 - - name: CTSF - description: CTSF - bit_offset: 3 - bit_size: 1 - - name: CTSOVF - description: CTSOVF - bit_offset: 4 - bit_size: 1 - - name: CITSF - description: CITSF - bit_offset: 5 - bit_size: 1 -fieldset/SHIFTR: - description: shift control register - fields: - - name: SUBFS - description: " Subtract a fraction of a second " - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 -fieldset/SMCR: - description: " RTC secure mode control register " - fields: - - name: ALRADPROT - description: ALRADPROT - bit_offset: 0 - bit_size: 1 - - name: ALRBDPROT - description: ALRBDPROT - bit_offset: 1 - bit_size: 1 - - name: WUTDPROT - description: WUTDPROT - bit_offset: 2 - bit_size: 1 - - name: TSDPROT - description: TSDPROT - bit_offset: 3 - bit_size: 1 - - name: CALDPROT - description: CALDPROT - bit_offset: 13 - bit_size: 1 - - name: INITDPROT - description: INITDPROT - bit_offset: 14 - bit_size: 1 - - name: DECPROT - description: DECPROT - bit_offset: 15 - bit_size: 1 -fieldset/SMISR: - description: " RTC secure masked interrupt status register " - fields: - - name: ALRAMF - description: ALRAMF - bit_offset: 0 - bit_size: 1 - - name: ALRBMF - description: ALRBMF - bit_offset: 1 - bit_size: 1 - - name: WUTMF - description: WUTMF - bit_offset: 2 - bit_size: 1 - - name: TSMF - description: TSMF - bit_offset: 3 - bit_size: 1 - - name: TSOVMF - description: TSOVMF - bit_offset: 4 - bit_size: 1 - - name: ITSMF - description: ITSMF - bit_offset: 5 - bit_size: 1 -fieldset/SR: - description: RTC status register - fields: - - name: ALRAF - description: ALRAF - bit_offset: 0 - bit_size: 1 - - name: ALRBF - description: ALRBF - bit_offset: 1 - bit_size: 1 - - name: WUTF - description: WUTF - bit_offset: 2 - bit_size: 1 - - name: TSF - description: TSF - bit_offset: 3 - bit_size: 1 - - name: TSOVF - description: TSOVF - bit_offset: 4 - bit_size: 1 - - name: ITSF - description: ITSF - bit_offset: 5 - bit_size: 1 -fieldset/SSR: - description: RTC sub second register - fields: - - name: SS - description: SS - bit_offset: 0 - bit_size: 16 -fieldset/TR: - description: time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/TSDR: - description: time stamp date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 -fieldset/TSSSR: - description: timestamp sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 -fieldset/TSTR: - description: time stamp time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/WPR: - description: write protection register - fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 -fieldset/WUTR: - description: wakeup timer register - fields: - - name: WUT - description: " Wakeup auto-reload value bits " - bit_offset: 0 - bit_size: 16 - - name: WUTOCLR - description: WUTOCLR - bit_offset: 16 - bit_size: 16 diff --git a/data/registers/rtc_f1.yaml b/data/registers/rtc_v1.yaml similarity index 100% rename from data/registers/rtc_f1.yaml rename to data/registers/rtc_v1.yaml diff --git a/data/registers/rtc_f0.yaml b/data/registers/rtc_v2-f0.yaml similarity index 100% rename from data/registers/rtc_f0.yaml rename to data/registers/rtc_v2-f0.yaml diff --git a/data/registers/rtc_f2.yaml b/data/registers/rtc_v2-f2.yaml similarity index 100% rename from data/registers/rtc_f2.yaml rename to data/registers/rtc_v2-f2.yaml diff --git a/data/registers/rtc_f3.yaml b/data/registers/rtc_v2-f3.yaml similarity index 100% rename from data/registers/rtc_f3.yaml rename to data/registers/rtc_v2-f3.yaml diff --git a/data/registers/rtc_f4.yaml b/data/registers/rtc_v2-f4.yaml similarity index 100% rename from data/registers/rtc_f4.yaml rename to data/registers/rtc_v2-f4.yaml diff --git a/data/registers/rtc_f7.yaml b/data/registers/rtc_v2-f7.yaml similarity index 100% rename from data/registers/rtc_f7.yaml rename to data/registers/rtc_v2-f7.yaml diff --git a/data/registers/rtc_h7.yaml b/data/registers/rtc_v2-h7.yaml similarity index 100% rename from data/registers/rtc_h7.yaml rename to data/registers/rtc_v2-h7.yaml diff --git a/data/registers/rtc_l0.yaml b/data/registers/rtc_v2-l0.yaml similarity index 100% rename from data/registers/rtc_l0.yaml rename to data/registers/rtc_v2-l0.yaml diff --git a/data/registers/rtc_l1.yaml b/data/registers/rtc_v2-l1.yaml similarity index 100% rename from data/registers/rtc_l1.yaml rename to data/registers/rtc_v2-l1.yaml diff --git a/data/registers/rtc_l4.yaml b/data/registers/rtc_v2-l4.yaml similarity index 100% rename from data/registers/rtc_l4.yaml rename to data/registers/rtc_v2-l4.yaml diff --git a/data/registers/rtc_u5.yaml b/data/registers/rtc_v2-u5.yaml similarity index 100% rename from data/registers/rtc_u5.yaml rename to data/registers/rtc_v2-u5.yaml diff --git a/data/registers/rtc_wb.yaml b/data/registers/rtc_v2-wb.yaml similarity index 100% rename from data/registers/rtc_wb.yaml rename to data/registers/rtc_v2-wb.yaml diff --git a/data/registers/rtc_gx.yaml b/data/registers/rtc_v3.yaml similarity index 100% rename from data/registers/rtc_gx.yaml rename to data/registers/rtc_v3.yaml diff --git a/data/registers/rtc_wl.yaml b/data/registers/rtc_wl.yaml deleted file mode 100644 index b1d315b..0000000 --- a/data/registers/rtc_wl.yaml +++ /dev/null @@ -1,1360 +0,0 @@ ---- -block/RTC: - description: Real-time clock - items: - - name: TR - description: Time register - byte_offset: 0 - fieldset: TR - - name: DR - description: Date register - byte_offset: 4 - fieldset: DR - - name: SSR - description: Sub second register - byte_offset: 8 - access: Read - fieldset: SSR - - name: ICSR - description: Initialization control and status register - byte_offset: 12 - fieldset: ICSR - - name: PRER - description: Pre-scaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: Wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CR - description: Control register - byte_offset: 24 - fieldset: CR - - name: WPR - description: Write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: CALR - description: Calibration register - byte_offset: 40 - fieldset: CALR - - name: SHIFTR - description: Shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: Timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: Timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: Timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: ALRMAR - description: Alarm A register - byte_offset: 64 - fieldset: ALRMAR - - name: ALRMASSR - description: Alarm A sub second register - byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBR - description: Alarm B register - byte_offset: 72 - fieldset: ALRMBR - - name: ALRMBSSR - description: Alarm B sub second register - byte_offset: 76 - fieldset: ALRMBSSR - - name: SR - description: Status register (interrupts) - byte_offset: 80 - access: Read - fieldset: SR - - name: MISR - description: Masked interrupt status register - byte_offset: 84 - access: Read - fieldset: MISR - - name: SCR - description: Status clear register (interrupts) - byte_offset: 92 - access: Write - fieldset: SCR - - name: ALRABINR - description: RTC alarm A binary mode register - byte_offset: 112 - fieldset: ALRABINR - - name: ALRBBINR - description: RTC alarm B binary mode register - byte_offset: 116 - fieldset: ALRBBINR -fieldset/ALRABINR: - description: RTC alarm A binary mode register - fields: - - name: SS - description: Synchronous counter alarm value in Binary mode - bit_offset: 0 - bit_size: 32 -fieldset/ALRBBINR: - description: RTC alarm B binary mode register - fields: - - name: SS - description: Synchronous counter alarm value in Binary mode - bit_offset: 0 - bit_size: 32 -fieldset/ALRMAR: - description: Alarm A register - fields: - - name: SU - description: Second units in BCD format. - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format. - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMAR_PM - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMAR_WDSEL - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMAR_MSK1 -fieldset/ALRMASSR: - description: Alarm A sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 6 - - name: SSCLR - description: Clear synchronous counter on alarm (Binary mode only) - bit_offset: 31 - bit_size: 1 - enum: ALRMASSR_SSCLR -fieldset/ALRMBR: - description: Alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMBR_PM - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMBR_WDSEL - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMBR_MSK1 -fieldset/ALRMBSSR: - description: Alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 6 - - name: SSCLR - description: Clear synchronous counter on alarm (Binary mode only) - bit_offset: 31 - bit_size: 1 - enum: ALRMBSSR_SSCLR -fieldset/CALR: - description: Calibration register - fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: LPCAL - description: Calibration low-power mode - bit_offset: 12 - bit_size: 1 - enum: LPCAL - - name: CALW16 - description: CALW16 - bit_offset: 13 - bit_size: 1 - enum: CALW16 - - name: CALW8 - description: Use a 16-second calibration cycle period - bit_offset: 14 - bit_size: 1 - enum: CALW8 - - name: CALP - description: Use an 8-second calibration cycle period - bit_offset: 15 - bit_size: 1 - enum: CALP -fieldset/CR: - description: Control register - fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Timestamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: RTC_REFIN reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - enum: BYPSHAD - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: SSRUIE - description: SSR underflow interrupt enable - bit_offset: 7 - bit_size: 1 - enum: SSRUIE - - name: ALRAE - description: Alarm A enable - bit_offset: 8 - bit_size: 1 - enum: ALRAE - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - enum: ALRBE - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - enum: WUTE - - name: TSE - description: timestamp enable - bit_offset: 11 - bit_size: 1 - enum: TSE - - name: ALRAIE - description: Alarm A interrupt enable - bit_offset: 12 - bit_size: 1 - enum: ALRAIE - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - enum: ALRBIE - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - enum: WUTIE - - name: TSIE - description: Timestamp interrupt enable - bit_offset: 15 - bit_size: 1 - enum: TSIE - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - enum_write: ADD1HW - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - enum_write: SUB1HW - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - enum: BKP - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - enum: COE - - name: ITSE - description: timestamp on internal event enable - bit_offset: 24 - bit_size: 1 - enum: ITSE - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 25 - bit_size: 1 - enum: TAMPTS - - name: TAMPOE - description: Tamper detection output enable on TAMPALRM - bit_offset: 26 - bit_size: 1 - enum: TAMPOE - - name: TAMPALRM_PU - description: TAMPALRM pull-up enable - bit_offset: 29 - bit_size: 1 - enum: TAMPALRM_PU - - name: TAMPALRM_TYPE - description: TAMPALRM output type - bit_offset: 30 - bit_size: 1 - enum: TAMPALRM_TYPE - - name: OUT2EN - description: RTC_OUT2 output enable - bit_offset: 31 - bit_size: 1 - enum: OUT2EN -fieldset/DR: - description: Date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 -fieldset/ICSR: - description: Initialization control and status register - fields: - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - enum_read: WUTWFR - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - enum_read: SHPFR - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - enum_read: INITSR - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - enum_read: RSFR - enum_write: RSFW - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - enum_read: INITFR - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: BIN - description: Binary mode - bit_offset: 8 - bit_size: 2 - enum: BIN - - name: BCDU - description: BCD update - bit_offset: 10 - bit_size: 3 - enum: BCDU - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - enum_read: RECALPFR -fieldset/MISR: - description: Masked interrupt status register - fields: - - name: ALRAMF - description: Alarm A masked flag - bit_offset: 0 - bit_size: 1 - enum: ALRAMF - - name: ALRBMF - description: Alarm B masked flag - bit_offset: 1 - bit_size: 1 - enum: ALRBMF - - name: WUTMF - description: Wakeup timer masked flag - bit_offset: 2 - bit_size: 1 - enum: WUTMF - - name: TSMF - description: Timestamp masked flag - bit_offset: 3 - bit_size: 1 - enum: TSMF - - name: TSOVMF - description: Timestamp overflow masked flag - bit_offset: 4 - bit_size: 1 - enum: TSOVMF - - name: ITSMF - description: Internal timestamp masked flag - bit_offset: 5 - bit_size: 1 - enum: ITSMF - - name: SSRUMF - description: SSR underflow masked flag - bit_offset: 6 - bit_size: 1 - enum: SSRUMF -fieldset/PRER: - description: Pre-scaler register - fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 -fieldset/SCR: - description: Status clear register (interrupts) - fields: - - name: CALRAF - description: Clear alarm A flag - bit_offset: 0 - bit_size: 1 - enum: CALRAF - - name: CALRBF - description: Clear alarm B flag - bit_offset: 1 - bit_size: 1 - enum: CALRAF - - name: CWUTF - description: Clear wakeup timer flag - bit_offset: 2 - bit_size: 1 - enum: CALRAF - - name: CTSF - description: Clear timestamp flag - bit_offset: 3 - bit_size: 1 - enum: CALRAF - - name: CTSOVF - description: Clear timestamp overflow flag - bit_offset: 4 - bit_size: 1 - enum: CALRAF - - name: CITSF - description: Clear internal timestamp flag - bit_offset: 5 - bit_size: 1 - enum: CALRAF - - name: CSSRUF - description: Clear SSR underflow flag - bit_offset: 6 - bit_size: 1 - enum: CALRAF -fieldset/SHIFTR: - description: Shift control register - fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 - enum_write: ADD1SW -fieldset/SR: - description: Status register (interrupts) - fields: - - name: ALRAF - description: Alarm A flag - bit_offset: 0 - bit_size: 1 - enum: ALRAF - - name: ALRBF - description: Alarm B flag - bit_offset: 1 - bit_size: 1 - enum: ALRBF - - name: WUTF - description: Wakeup timer flag - bit_offset: 2 - bit_size: 1 - enum: WUTF - - name: TSF - description: Timestamp flag - bit_offset: 3 - bit_size: 1 - enum: TSF - - name: TSOVF - description: Timestamp overflow flag - bit_offset: 4 - bit_size: 1 - enum: TSOVF - - name: ITSF - description: Internal timestamp flag - bit_offset: 5 - bit_size: 1 - enum: ITSF - - name: SSRUF - description: SSR underflow flag - bit_offset: 6 - bit_size: 1 - enum: SSRUF -fieldset/SSR: - description: Sub second register - fields: - - name: SS - description: Synchronous binary counter - bit_offset: 0 - bit_size: 32 -fieldset/TR: - description: Time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: TR_PM -fieldset/TSDR: - description: Timestamp date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 -fieldset/TSSSR: - description: Timestamp sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 32 -fieldset/TSTR: - description: Timestamp time register - fields: - - name: SU - description: Second units in BCD format. - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format. - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format. - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format. - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format. - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format. - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/WPR: - description: Write protection register - fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 - enum: KEY -fieldset/WUTR: - description: Wakeup timer register - fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 - - name: WUTOCLR - description: Wakeup auto-reload output clear value - bit_offset: 16 - bit_size: 16 -enum/ADD1HW: - bit_size: 1 - variants: - - name: Add1 - description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - value: 1 -enum/ADD1SW: - bit_size: 1 - variants: - - name: Add1 - description: Add one second to the clock/calendar - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A disabled - value: 0 - - name: Enabled - description: Alarm A enabled - value: 1 -enum/ALRAF: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRAIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A interrupt disabled - value: 0 - - name: Enabled - description: Alarm A interrupt enabled - value: 1 -enum/ALRAMF: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B disabled - value: 0 - - name: Enabled - description: Alarm B enabled - value: 1 -enum/ALRBF: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - value: 1 -enum/ALRBIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B Interrupt disabled - value: 0 - - name: Enabled - description: Alarm B Interrupt enabled - value: 1 -enum/ALRBMF: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - value: 1 -enum/ALRMAR_MSK1: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMAR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMAR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/ALRMASSR_SSCLR: - bit_size: 1 - variants: - - name: FreeRunning - description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" - value: 0 - - name: ALRMBINR - description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" - value: 1 -enum/ALRMBR_MSK1: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMBR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/ALRMBSSR_SSCLR: - bit_size: 1 - variants: - - name: FreeRunning - description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" - value: 0 - - name: ALRMBINR - description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" - value: 1 -enum/BCDU: - bit_size: 3 - variants: - - name: Bit7 - description: "1s increment each time SS[7:0]=0" - value: 0 - - name: Bit8 - description: "1s increment each time SS[8:0]=0" - value: 1 - - name: Bit9 - description: "1s increment each time SS[9:0]=0" - value: 2 - - name: Bit10 - description: "1s increment each time SS[10:0]=0" - value: 3 - - name: Bit11 - description: "1s increment each time SS[11:0]=0" - value: 4 - - name: Bit12 - description: "1s increment each time SS[12:0]=0" - value: 5 - - name: Bit13 - description: "1s increment each time SS[13:0]=0" - value: 6 - - name: Bit14 - description: "1s increment each time SS[14:0]=0" - value: 7 -enum/BIN: - bit_size: 2 - variants: - - name: BCD - description: Free running BCD calendar mode (Binary mode disabled) - value: 0 - - name: Binary - description: Free running Binary mode (BCD mode disabled) - value: 1 - - name: BinBCD - description: Free running BCD calendar and Binary modes - value: 2 - - name: BinBCD2 - description: Free running BCD calendar and Binary modes - value: 3 -enum/BKP: - bit_size: 1 - variants: - - name: DSTNotChanged - description: Daylight Saving Time change has not been performed - value: 0 - - name: DSTChanged - description: Daylight Saving Time change has been performed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - name: ShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" - value: 0 - - name: BypassShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" - value: 1 -enum/CALP: - bit_size: 1 - variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 -enum/CALRAF: - bit_size: 1 - variants: - - name: Clear - description: Clear interrupt flag by writing 1 - value: 1 -enum/CALW16: - bit_size: 1 - variants: - - name: SixteenSeconds - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 -enum/CALW8: - bit_size: 1 - variants: - - name: EightSeconds - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 -enum/COE: - bit_size: 1 - variants: - - name: Disabled - description: Calibration output disabled - value: 0 - - name: Enabled - description: Calibration output enabled - value: 1 -enum/COSEL: - bit_size: 1 - variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 -enum/FMT: - bit_size: 1 - variants: - - name: TwentyFourHour - description: 24 hour/day format - value: 0 - - name: AmPm - description: AM/PM hour format - value: 1 -enum/INIT: - bit_size: 1 - variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 -enum/INITFR: - bit_size: 1 - variants: - - name: NotAllowed - description: Calendar registers update is not allowed - value: 0 - - name: Allowed - description: Calendar registers update is allowed - value: 1 -enum/INITSR: - bit_size: 1 - variants: - - name: NotInitalized - description: Calendar has not been initialized - value: 0 - - name: Initalized - description: Calendar has been initialized - value: 1 -enum/ITSE: - bit_size: 1 - variants: - - name: Disabled - description: Internal event timestamp disabled - value: 0 - - name: Enabled - description: Internal event timestamp enabled - value: 1 -enum/ITSF: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a timestamp on the internal event occurs - value: 1 -enum/ITSMF: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a timestamp on the internal event occurs - value: 1 -enum/KEY: - bit_size: 8 - variants: - - name: Activate - description: Activate write protection (any value that is not the keys) - value: 0 - - name: Deactivate2 - description: Key 2 - value: 83 - - name: Deactivate1 - description: Key 1 - value: 202 -enum/LPCAL: - bit_size: 1 - variants: - - name: RTCCLK - description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" - value: 0 - - name: CkApre - description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" - value: 1 -enum/OSEL: - bit_size: 2 - variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 -enum/OUT2EN: - bit_size: 1 - variants: - - name: Disabled - description: RTC output 2 disable - value: 0 - - name: Enabled - description: RTC output 2 enable - value: 1 -enum/POL: - bit_size: 1 - variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 -enum/RECALPFR: - bit_size: 1 - variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 -enum/REFCKON: - bit_size: 1 - variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 -enum/SSRUF: - bit_size: 1 - variants: - - name: Underflow - description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - value: 1 -enum/SSRUIE: - bit_size: 1 - variants: - - name: Disabled - description: SSR underflow interrupt disabled - value: 0 - - name: Enabled - description: SSR underflow interrupt enabled - value: 1 -enum/SSRUMF: - bit_size: 1 - variants: - - name: Underflow - description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 - value: 1 -enum/SUB1HW: - bit_size: 1 - variants: - - name: Sub1 - description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode - value: 1 -enum/TAMPALRM_PU: - bit_size: 1 - variants: - - name: NoPullUp - description: No pull-up is applied on TAMPALRM output - value: 0 - - name: PullUp - description: A pull-up is applied on TAMPALRM output - value: 1 -enum/TAMPALRM_TYPE: - bit_size: 1 - variants: - - name: PushPull - description: TAMPALRM is push-pull output - value: 0 - - name: OpenDrain - description: TAMPALRM is open-drain output - value: 1 -enum/TAMPOE: - bit_size: 1 - variants: - - name: Disabled - description: The tamper flag is not routed on TAMPALRM - value: 0 - - name: Enabled - description: "The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL" - value: 1 -enum/TAMPTS: - bit_size: 1 - variants: - - name: Disabled - description: Tamper detection event does not cause a RTC timestamp to be saved - value: 0 - - name: Enabled - description: Save RTC timestamp on tamper detection event - value: 1 -enum/TR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/TSE: - bit_size: 1 - variants: - - name: Disabled - description: Timestamp disabled - value: 0 - - name: Enabled - description: Timestamp enabled - value: 1 -enum/TSEDGE: - bit_size: 1 - variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 -enum/TSF: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSIE: - bit_size: 1 - variants: - - name: Disabled - description: Time-stamp Interrupt disabled - value: 0 - - name: Enabled - description: Time-stamp Interrupt enabled - value: 1 -enum/TSMF: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSOVF: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set - value: 1 -enum/TSOVMF: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set - value: 1 -enum/WUCKSEL: - bit_size: 3 - variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 -enum/WUTE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer disabled - value: 0 - - name: Enabled - description: Wakeup timer enabled - value: 1 -enum/WUTF: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTIE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer interrupt disabled - value: 0 - - name: Enabled - description: Wakeup timer interrupt enabled - value: 1 -enum/WUTMF: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTWFR: - bit_size: 1 - variants: - - name: UpdateNotAllowed - description: Wakeup timer configuration update not allowed - value: 0 - - name: UpdateAllowed - description: Wakeup timer configuration update allowed - value: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 99110b9..c174420 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -163,22 +163,22 @@ perimap = [ ('.*:MDIOS:mdios1_v1_0', ('mdios', 'v1', 'MDIOS')), ('.*:QUADSPI:quadspi1_v1_0', ('quadspi', 'v1', 'QUADSPI')), ('STM32F1.*:BKP.*', ('bkp', 'v1', 'BKP')), - ('STM32F0.*:RTC:.*', ('rtc', 'f0', 'RTC')), - ('STM32F1.*:RTC:.*', ('rtc', 'f1', 'RTC')), - ('STM32F2.*:RTC:.*', ('rtc', 'f2', 'RTC')), - ('STM32F3.*:RTC:.*', ('rtc', 'f3', 'RTC')), - ('STM32F4.*:RTC:.*', ('rtc', 'f4', 'RTC')), - ('STM32F7.*:RTC:.*', ('rtc', 'f7', 'RTC')), - ('STM32G.*:RTC:.*', ('rtc', 'gx', 'RTC')), - ('STM32H7.*:RTC:.*', ('rtc', 'h7', 'RTC')), - ('STM32L0.*:RTC:.*', ('rtc', 'l0', 'RTC')), - ('STM32L1.*:RTC:.*', ('rtc', 'l1', 'RTC')), - ('STM32L41.*:RTC:.*', ('rtc', 'l41x-l42x', 'RTC')), - ('STM32L4.*:RTC:.*', ('rtc', 'l4', 'RTC')), - ('STM32L5.*:RTC:.*', ('rtc', 'l5', 'RTC')), - ('STM32U5.*:RTC:.*', ('rtc', 'u5', 'RTC')), - ('STM32WB.*:RTC:.*', ('rtc', 'wb', 'RTC')), - ('STM32WL.*:RTC:.*', ('rtc', 'wl', 'RTC')), + ('.*:RTC:rtc1_v1_1_Cube', ('rtc', 'v1', 'RTC')), + ('STM32F0.*:RTC:rtc2_.*', ('rtc', 'v2-f0', 'RTC')), + ('STM32F2.*:RTC:rtc2_.*', ('rtc', 'v2-f2', 'RTC')), + ('STM32F3.*:RTC:rtc2_.*', ('rtc', 'v2-f3', 'RTC')), + ('STM32F4.*:RTC:rtc2_.*', ('rtc', 'v2-f4', 'RTC')), + ('STM32F7.*:RTC:rtc2_.*', ('rtc', 'v2-f7', 'RTC')), + ('STM32H7.*:RTC:rtc2_.*', ('rtc', 'v2-h7', 'RTC')), + ('STM32L0.*:RTC:rtc2_.*', ('rtc', 'v2-l0', 'RTC')), + ('STM32L1.*:RTC:rtc2_.*', ('rtc', 'v2-l1', 'RTC')), + ('STM32L4.*:RTC:rtc2_.*', ('rtc', 'v2-l4', 'RTC')), + ('STM32U5.*:RTC:rtc2_.*', ('rtc', 'v2-u5', 'RTC')), + ('STM32WB.*:RTC:rtc2_.*', ('rtc', 'v2-wb', 'RTC')), + ('.*:RTC:rtc3_v1_0_Cube', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v1_1_Cube', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v2_0_Cube', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v3_0_Cube', ('rtc', 'v3', 'RTC')), ('.*:SAI:sai1_v1_1', ('sai', 'v1', 'SAI')), ('.*:SDIO:sdmmc_v1_2', ('sdmmc', 'v1', 'SDMMC')), ('.*:SDMMC:sdmmc_v1_3', ('sdmmc', 'v1', 'SDMMC')), From 82110c6686db4e558949abc7eb8342641b3947a0 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Tue, 31 May 2022 20:48:18 +0300 Subject: [PATCH 03/11] Fix control characters --- data/registers/rtc_v2-l4.yaml | 50 +++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/data/registers/rtc_v2-l4.yaml b/data/registers/rtc_v2-l4.yaml index 27090d5..80a64a7 100644 --- a/data/registers/rtc_v2-l4.yaml +++ b/data/registers/rtc_v2-l4.yaml @@ -15,7 +15,7 @@ block/RTC: byte_offset: 8 fieldset: CR - name: ISR - description: "initialization and status\r register" + description: "initialization and status register" byte_offset: 12 fieldset: ISR - name: PRER @@ -135,7 +135,7 @@ fieldset/ALRMAR: bit_offset: 23 bit_size: 1 - name: DU - description: "Date units or day in BCD\r format" + description: "Date units or day in BCD format" bit_offset: 24 bit_size: 4 - name: DT @@ -158,7 +158,7 @@ fieldset/ALRMASSR: bit_offset: 0 bit_size: 15 - name: MASKSS - description: "Mask the most-significant bits starting\r at this bit" + description: "Mask the most-significant bits starting at this bit" bit_offset: 24 bit_size: 4 fieldset/ALRMBR: @@ -205,7 +205,7 @@ fieldset/ALRMBR: bit_offset: 23 bit_size: 1 - name: DU - description: "Date units or day in BCD\r format" + description: "Date units or day in BCD format" bit_offset: 24 bit_size: 4 - name: DT @@ -228,7 +228,7 @@ fieldset/ALRMBSSR: bit_offset: 0 bit_size: 15 - name: MASKSS - description: "Mask the most-significant bits starting\r at this bit" + description: "Mask the most-significant bits starting at this bit" bit_offset: 24 bit_size: 4 fieldset/BKPR: @@ -246,15 +246,15 @@ fieldset/CALR: bit_offset: 0 bit_size: 9 - name: CALW16 - description: "Use a 16-second calibration cycle\r period" + description: "Use a 16-second calibration cycle period" bit_offset: 13 bit_size: 1 - name: CALW8 - description: "Use an 8-second calibration cycle\r period" + description: "Use an 8-second calibration cycle period" bit_offset: 14 bit_size: 1 - name: CALP - description: "Increase frequency of RTC by 488.5\r ppm" + description: "Increase frequency of RTC by 488.5 ppm" bit_offset: 15 bit_size: 1 fieldset/CR: @@ -265,15 +265,15 @@ fieldset/CR: bit_offset: 0 bit_size: 3 - name: TSEDGE - description: "Time-stamp event active\r edge" + description: "Time-stamp event active edge" bit_offset: 3 bit_size: 1 - name: REFCKON - description: "Reference clock detection enable (50 or\r 60 Hz)" + description: "Reference clock detection enable (50 or 60 Hz)" bit_offset: 4 bit_size: 1 - name: BYPSHAD - description: "Bypass the shadow\r registers" + description: "Bypass the shadow registers" bit_offset: 5 bit_size: 1 - name: FMT @@ -305,19 +305,19 @@ fieldset/CR: bit_offset: 13 bit_size: 1 - name: WUTIE - description: "Wakeup timer interrupt\r enable" + description: "Wakeup timer interrupt enable" bit_offset: 14 bit_size: 1 - name: TSIE - description: "Time-stamp interrupt\r enable" + description: "Time-stamp interrupt enable" bit_offset: 15 bit_size: 1 - name: ADD1H - description: "Add 1 hour (summer time\r change)" + description: "Add 1 hour (summer time change)" bit_offset: 16 bit_size: 1 - name: SUB1H - description: "Subtract 1 hour (winter time\r change)" + description: "Subtract 1 hour (winter time change)" bit_offset: 17 bit_size: 1 - name: BKP @@ -325,7 +325,7 @@ fieldset/CR: bit_offset: 18 bit_size: 1 - name: COSEL - description: "Calibration output\r selection" + description: "Calibration output selection" bit_offset: 19 bit_size: 1 - name: POL @@ -341,7 +341,7 @@ fieldset/CR: bit_offset: 23 bit_size: 1 - name: ITSE - description: "timestamp on internal event\r enable" + description: "timestamp on internal event enable" bit_offset: 24 bit_size: 1 fieldset/DR: @@ -376,7 +376,7 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: "initialization and status\r register" + description: "initialization and status register" fields: - name: ALRAWF description: Alarm A write flag @@ -399,7 +399,7 @@ fieldset/ISR: bit_offset: 4 bit_size: 1 - name: RSF - description: "Registers synchronization\r flag" + description: "Registers synchronization flag" bit_offset: 5 bit_size: 1 - name: INITF @@ -450,7 +450,7 @@ fieldset/OR: description: option register fields: - name: RTC_ALARM_TYPE - description: "RTC_ALARM on PC13 output\r type" + description: "RTC_ALARM on PC13 output type" bit_offset: 0 bit_size: 1 - name: RTC_OUT_RMP @@ -461,18 +461,18 @@ fieldset/PRER: description: prescaler register fields: - name: PREDIV_S - description: "Synchronous prescaler\r factor" + description: "Synchronous prescaler factor" bit_offset: 0 bit_size: 15 - name: PREDIV_A - description: "Asynchronous prescaler\r factor" + description: "Asynchronous prescaler factor" bit_offset: 16 bit_size: 7 fieldset/SHIFTR: description: shift control register fields: - name: SUBFS - description: "Subtract a fraction of a\r second" + description: "Subtract a fraction of a second" bit_offset: 0 bit_size: 15 - name: ADD1S @@ -518,7 +518,7 @@ fieldset/TAMPCR: bit_offset: 6 bit_size: 1 - name: TAMPTS - description: "Activate timestamp on tamper detection\r event" + description: "Activate timestamp on tamper detection event" bit_offset: 7 bit_size: 1 - name: TAMPFREQ @@ -676,6 +676,6 @@ fieldset/WUTR: description: wakeup timer register fields: - name: WUT - description: "Wakeup auto-reload value\r bits" + description: "Wakeup auto-reload value bits" bit_offset: 0 bit_size: 16 From 42cd969fcd0b34cc7eb53bfac1c13fbbca7507af Mon Sep 17 00:00:00 2001 From: chemicstry Date: Thu, 2 Jun 2022 22:35:27 +0300 Subject: [PATCH 04/11] WIP: merging RTCv2 registers --- data/registers/rtc_v2.yaml | 1786 ++++++++++++++++++++++++++++++++++++ 1 file changed, 1786 insertions(+) create mode 100644 data/registers/rtc_v2.yaml diff --git a/data/registers/rtc_v2.yaml b/data/registers/rtc_v2.yaml new file mode 100644 index 0000000..33f84b6 --- /dev/null +++ b/data/registers/rtc_v2.yaml @@ -0,0 +1,1786 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: time register + byte_offset: 0 + fieldset: TR + - name: DR + description: date register + byte_offset: 4 + fieldset: DR + - name: CR + description: control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: alarm register + array: + len: 1 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: TSTR + description: timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: alarm sub second register + array: + len: 1 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR +block/RTC_F0: + description: Real-time clock + extends: RTC_BASE + items: + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TAMPCR + description: tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR_F0 + - name: BKPR + description: backup register + array: + len: 5 + stride: 4 + byte_offset: 80 + fieldset: BKPR +block/RTC_F2: + description: Real-time clock + extends: RTC_BASE + items: + - name: CALIBR + description: calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: TAMPCR + description: tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR_F2 + - name: ALRMSSR + description: alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +block/RTC_F3: + description: Real-time clock + extends: RTC_BASE + items: + - name: ALRMR + description: alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TAMPCR + description: tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR_F0_F3 + - name: ALRMSSR + description: alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +block/RTC_F4: + description: Real-time clock + extends: RTC_BASE + items: + - name: CALIBR + description: calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TAMPCR + description: tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR_F4 + - name: ALRMSSR + description: alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR +block/RTC_F7_H7: + description: Real-time clock + extends: RTC_BASE + items: + - name: ALRMR + description: alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TAMPCR + description: tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAMPCR_F7 + - name: ALRMSSR + description: alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +block/RTC_L0: + description: Real-time clock + extends: RTC_BASE + items: + - name: ALRMR + description: alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TAMPCR + description: tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAMPCR_L0 + - name: ALRMSSR + description: alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: option register + byte_offset: 76 + fieldset: OR_L0 + - name: BKPR + description: backup register + array: + len: 5 + stride: 4 + byte_offset: 80 + fieldset: BKPR +block/RTC_L1: + description: Real-time clock + extends: RTC_BASE + items: + - name: CALIBR + description: calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: SSR + description: sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TAMPCR + description: tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAMPCR_L0 + - name: ALRMSSR + description: alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 +fieldset/ALRMSSR: + description: alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALIBR: + description: calibration register + fields: + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 +fieldset/CALR: + description: calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + - name: CALW8 + description: Use a 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Time-stamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 1 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum: ALRE + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + enum: WUTE + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + enum: TSE + - name: ALRIE + description: Alarm interrupt enable + array: + len: 1 + stride: 1 + bit_offset: 12 + bit_size: 1 + enum: ALRIE + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + enum: WUTIE + - name: TSIE + description: Time-stamp interrupt enable + bit_offset: 15 + bit_size: 1 + enum: TSIE + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + enum_write: ADDHW + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + enum_write: SUBHW + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + enum: BKP + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + enum: COE +fieldset/CR_F0: + extemds: CR + description: control register + fields: + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL +fieldset/CR_F2: + extemds: CR + description: control register + fields: + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum: ALRE + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + enum: ALRIE +fieldset/CR_F3: + extemds: CR + description: control register + fields: + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum: ALRE + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + enum: ALRIE + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL +fieldset/CR_F4: + extemds: CR + description: control register + fields: + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum: ALRE + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + enum: ALRIE + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL +fieldset/CR_F7_H7: + extemds: CR + description: control register + fields: + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum: ALRE + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + enum: ALRIE + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: ITSE + description: timestamp on internal event enable + bit_offset: 24 + bit_size: 1 +fieldset/CR_L0: + extemds: CR + description: control register + fields: + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + enum: BYPSHAD + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum: ALRE + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + enum: ALRIE + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL +fieldset/CR_L1: + extemds: CR + description: control register + fields: + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 +fieldset/DR: + description: date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 1 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 1 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Time-stamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Time-stamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 1 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW +fieldset/ISR_F0: + extedns: ISR + description: initialization and status register + fields: + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/ISR_F2: + extedns: ISR + description: initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW +fieldset/ISR_F3: + extedns: ISR + description: initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/ISR_F4: + extedns: ISR + description: initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/ISR_F7_H7: + extedns: ISR + description: initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR + - name: ITSF + description: Internal timestamp flag + bit_offset: 17 + bit_size: 1 +fieldset/ISR_L0: + extedns: ISR + description: initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + enum_read: SHPFR + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/OR_F7: + description: option register + fields: + - name: TSINSEL + description: TIMESTAMP mapping + bit_offset: 1 + bit_size: 2 + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 3 + bit_size: 1 +fieldset/OR_H7_L0: + description: option register + fields: + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 +fieldset/PRER: + description: prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/PRER_F2: + extends: PRER + description: prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 13 +fieldset/SHIFTR: + description: shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 + enum_write: ADDSW +fieldset/SSR: + description: sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: tamper configuration register + fields: + - name: TAMP1E + description: Tamper 1 detection enable + bit_offset: 0 + bit_size: 1 + - name: TAMP1TRG + description: Active level for tamper 1 + bit_offset: 1 + bit_size: 1 + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 +fieldset/TAMPCR_2: + extends: TAMPCR + description: tamper configuration register + fields: + - name: TAMP2E + description: Tamper 2 detection enable + bit_offset: 3 + bit_size: 1 + - name: TAMP2TRG + description: Active level for tamper 2 + bit_offset: 4 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 +fieldset/TAMPCR_3: + extends: TAMPCR_2 + description: tamper configuration register + fields: + - name: TAMP3E + description: Tamper 3 detection enable + bit_offset: 5 + bit_size: 1 + - name: TAMP3TRG + description: Active level for tamper 3 + bit_offset: 6 + bit_size: 1 +fieldset/TAFCR_F0_F3: + extedns: TAMPCR_3 + description: tamper and alternate function configuration register + fields: + - name: PC13VALUE + description: "RTC_ALARM output type/PC13 value" + bit_offset: 18 + bit_size: 1 + enum: PCVALUE + - name: PC13MODE + description: PC13 mode + bit_offset: 19 + bit_size: 1 + enum: PCMODE + - name: PC14VALUE + description: PC14 value + bit_offset: 20 + bit_size: 1 + enum: PCVALUE + - name: PC14MODE + description: PC14 mode + bit_offset: 21 + bit_size: 1 + enum: PCMODE + - name: PC15VALUE + description: PC15 value + bit_offset: 22 + bit_size: 1 + enum: PCVALUE + - name: PC15MODE + description: PC15 mode + bit_offset: 23 + bit_size: 1 + enum: PCMODE +fieldset/TAFCR_F2: + extedns: TAMPCR + description: tamper and alternate function configuration register + fields: + - name: TAMP1INSEL + description: TAMPER1 mapping + bit_offset: 16 + bit_size: 1 + - name: TSINSEL + description: TIMESTAMP mapping + bit_offset: 17 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 +fieldset/TAFCR_F4: + extedns: TAMPCR + description: tamper and alternate function configuration register + fields: + - name: TAMP1INSEL + description: TAMPER1 mapping + bit_offset: 16 + bit_size: 1 + - name: TSINSEL + description: TIMESTAMP mapping + bit_offset: 17 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 +fieldset/TAMPCR_F7_H7_L0: + extedns: TAMPCR_3 + description: tamper configuration register + fields: + - name: TAMP1IE + description: Tamper 1 interrupt enable + bit_offset: 16 + bit_size: 1 + - name: TAMP1NOERASE + description: Tamper 1 no erase + bit_offset: 17 + bit_size: 1 + - name: TAMP1MF + description: Tamper 1 mask flag + bit_offset: 18 + bit_size: 1 + - name: TAMP2IE + description: Tamper 2 interrupt enable + bit_offset: 19 + bit_size: 1 + - name: TAMP2NOERASE + description: Tamper 2 no erase + bit_offset: 20 + bit_size: 1 + - name: TAMP2MF + description: Tamper 2 mask flag + bit_offset: 21 + bit_size: 1 + - name: TAMP3IE + description: Tamper 3 interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TAMP3NOERASE + description: Tamper 3 no erase + bit_offset: 23 + bit_size: 1 + - name: TAMP3MF + description: Tamper 3 mask flag + bit_offset: 24 + bit_size: 1 +fieldset/TR: + description: time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: TR_PM +fieldset/TSDR: + description: timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ADDHW: + bit_size: 1 + variants: + - name: Add1 + description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode + value: 1 +enum/ADDSW: + bit_size: 1 + variants: + - name: Add1 + description: Add one second to the clock/calendar + value: 1 +enum/ALRAE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A disabled + value: 0 + - name: Enabled + description: Alarm A enabled + value: 1 +enum/ALRAFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRAFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRAIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm A interrupt disabled + value: 0 + - name: Enabled + description: Alarm A interrupt enabled + value: 1 +enum/ALRAWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRBE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B disabled + value: 0 + - name: Enabled + description: Alarm B enabled + value: 1 +enum/ALRBFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + value: 1 +enum/ALRBFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRBIE: + bit_size: 1 + variants: + - name: Disabled + description: Alarm B Interrupt disabled + value: 0 + - name: Enabled + description: Alarm B Interrupt enabled + value: 1 +enum/ALRMAR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMAR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMAR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMBR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMBR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMBR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: DST_Not_Changed + description: Daylight Saving Time change has not been performed + value: 0 + - name: DST_Changed + description: Daylight Saving Time change has been performed + value: 1 +enum/BYPSHAD: + bit_size: 1 + variants: + - name: ShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" + value: 0 + - name: BypassShadowReg + description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COE: + bit_size: 1 + variants: + - name: Disabled + description: Calibration output disabled + value: 0 + - name: Enabled + description: Calibration output enabled + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/PCMODE: + bit_size: 1 + variants: + - name: Floating + description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + value: 0 + - name: PushPull + description: PCx is forced to push-pull output if LSE is disabled + value: 1 +enum/PCVALUE: + bit_size: 1 + variants: + - name: Low + description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low" + value: 0 + - name: High + description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high" + value: 1 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SUBHW: + bit_size: 1 + variants: + - name: Sub1 + description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + value: 1 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSE: + bit_size: 1 + variants: + - name: Disabled + description: Timestamp disabled + value: 0 + - name: Enabled + description: Timestamp enabled + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSIE: + bit_size: 1 + variants: + - name: Disabled + description: Time-stamp Interrupt disabled + value: 0 + - name: Enabled + description: Time-stamp Interrupt enabled + value: 1 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer disabled + value: 0 + - name: Enabled + description: Wakeup timer enabled + value: 1 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTIE: + bit_size: 1 + variants: + - name: Disabled + description: Wakeup timer interrupt disabled + value: 0 + - name: Enabled + description: Wakeup timer interrupt enabled + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 From 85162f723f1019ca27974e638cb50e5adca50e97 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Fri, 3 Jun 2022 02:29:26 +0300 Subject: [PATCH 05/11] Manually cleanup all RTC registers --- data/registers/rtc_v2-f0.yaml | 616 ++++++++++-- data/registers/rtc_v2-f2.yaml | 506 +++++++--- data/registers/rtc_v2-f3.yaml | 588 +++-------- data/registers/rtc_v2-f4.yaml | 599 ++++------- data/registers/rtc_v2-f7.yaml | 589 ++++------- data/registers/rtc_v2-h7.yaml | 713 +++++-------- data/registers/rtc_v2-l0.yaml | 609 +++-------- data/registers/rtc_v2-l1.yaml | 683 +++++++++---- data/registers/rtc_v2-l4.yaml | 667 ++++++++---- data/registers/rtc_v2-u5.yaml | 813 --------------- data/registers/rtc_v2-wb.yaml | 851 +++++++++------- data/registers/rtc_v2.yaml | 1786 --------------------------------- data/registers/rtc_v3-u5.yaml | 1153 +++++++++++++++++++++ data/registers/rtc_v3.yaml | 757 ++++++++++---- stm32data/__main__.py | 2 +- 15 files changed, 4991 insertions(+), 5941 deletions(-) delete mode 100644 data/registers/rtc_v2-u5.yaml delete mode 100644 data/registers/rtc_v2.yaml create mode 100644 data/registers/rtc_v3-u5.yaml diff --git a/data/registers/rtc_v2-f0.yaml b/data/registers/rtc_v2-f0.yaml index c97b18a..3ba9016 100644 --- a/data/registers/rtc_v2-f0.yaml +++ b/data/registers/rtc_v2-f0.yaml @@ -3,203 +3,225 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: "initialization and status register" + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 1 + stride: 4 byte_offset: 28 - fieldset: ALRMAR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: timestamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: timestamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: time-stamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: calibration register + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAFCR - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register byte_offset: 64 fieldset: TAFCR - - name: ALRMASSR - description: alarm A sub second register + - name: ALRMSSR + description: Alarm sub second register + array: + len: 1 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR + fieldset: ALRMSSR - name: BKPR - description: backup register + description: Backup register array: len: 5 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: alarm A register +fieldset/ALRMR: + description: Alarm register fields: - name: SU - description: "Second units in BCD format." + description: Second units in BCD format bit_offset: 0 bit_size: 4 - name: ST - description: Second tens in BCD format. + description: Second tens in BCD format bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm A seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 + enum: ALRMR_MSK - name: MNU - description: "Minute units in BCD format." + description: Minute units in BCD format bit_offset: 8 bit_size: 4 - name: MNT - description: Minute tens in BCD format. + description: Minute tens in BCD format bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm A minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 + enum: ALRMR_MSK - name: HU - description: Hour units in BCD format. + description: Hour units in BCD format bit_offset: 16 bit_size: 4 - name: HT - description: Hour tens in BCD format. + description: Hour tens in BCD format bit_offset: 20 bit_size: 2 - name: PM description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: ALRMR_PM - name: MSK3 - description: Alarm A hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 + enum: ALRMR_MSK - name: DU - description: "Date units or day in BCD format." + description: Date units or day in BCD format bit_offset: 24 bit_size: 4 - name: DT - description: Date tens in BCD format. + description: Date tens in BCD format bit_offset: 28 bit_size: 2 - name: WDSEL description: Week day selection bit_offset: 30 bit_size: 1 + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm A date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value bit_offset: 0 bit_size: 15 - name: MASKSS - description: "Mask the most-significant bits starting at this bit" + description: Mask the most-significant bits starting at this bit bit_offset: 24 bit_size: 4 fieldset/BKPR: - description: backup register + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus bit_offset: 0 bit_size: 9 - name: CALW16 - description: "Use a 16-second calibration cycle period" + description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 + enum: CALW16 - name: CALW8 - description: "Use a 8-second calibration cycle period" + description: Use an 8-second calibration cycle period bit_offset: 14 bit_size: 1 + enum: CALW8 - name: CALP - description: "Increase frequency of RTC by 488.5 ppm" + description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 + enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection bit_offset: 0 bit_size: 3 + enum: WUCKSEL - name: TSEDGE - description: "Time-stamp event active edge" + description: Timestamp event active edge bit_offset: 3 bit_size: 1 + enum: TSEDGE - name: REFCKON - description: "RTC_REFIN reference clock detection enable (50 or 60 Hz)" + description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 + enum: REFCKON - name: BYPSHAD - description: "Bypass the shadow registers" + description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - name: FMT description: Hour format bit_offset: 6 bit_size: 1 - - name: ALRAE - description: Alarm A enable + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 1 + stride: 1 bit_offset: 8 bit_size: 1 - name: WUTE @@ -207,27 +229,30 @@ fieldset/CR: bit_offset: 10 bit_size: 1 - name: TSE - description: timestamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 1 + stride: 1 bit_offset: 12 bit_size: 1 - name: WUTIE - description: "Wakeup timer interrupt enable" + description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - name: TSIE - description: "Time-stamp interrupt enable" + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - name: ADD1H - description: "Add 1 hour (summer time change)" + description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - name: SUB1H - description: "Subtract 1 hour (winter time change)" + description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - name: BKP @@ -235,23 +260,26 @@ fieldset/CR: bit_offset: 18 bit_size: 1 - name: COSEL - description: "Calibration output selection" + description: Calibration output selection bit_offset: 19 bit_size: 1 + enum: COSEL - name: POL description: Output polarity bit_offset: 20 bit_size: 1 + enum: POL - name: OSEL description: Output selection bit_offset: 21 bit_size: 2 + enum: OSEL - name: COE description: Calibration output enable bit_offset: 23 bit_size: 1 fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -282,16 +310,21 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: "initialization and status register" + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 1 + stride: 1 bit_offset: 0 bit_size: 1 + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 + enum_read: WUTWFR - name: SHPF description: Shift operation pending bit_offset: 3 @@ -300,66 +333,80 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 + enum_read: INITSR - name: RSF - description: "Registers synchronization flag" + description: Registers synchronization flag bit_offset: 5 bit_size: 1 + enum_read: RSFR + enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 + enum_read: INITFR - name: INIT description: Initialization mode bit_offset: 7 bit_size: 1 - - name: ALRAF - description: Alarm A flag + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 1 + stride: 1 bit_offset: 8 bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW - name: TSF - description: Time-stamp flag + description: Timestamp flag bit_offset: 11 bit_size: 1 + enum_read: TSFR + enum_write: TSFW - name: TSOVF - description: Time-stamp overflow flag + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - - name: TAMP1F - description: RTC_TAMP1 detection flag + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - - name: TAMP2F - description: RTC_TAMP2 detection flag - bit_offset: 14 - bit_size: 1 - - name: TAMP3F - description: RTC_TAMP3 detection flag - bit_offset: 15 - bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF - description: Recalibration pending Flag + description: Recalibration pending flag bit_offset: 16 bit_size: 1 + enum_read: RECALPFR fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S - description: "Synchronous prescaler factor" + description: Synchronous prescaler factor bit_offset: 0 bit_size: 15 - name: PREDIV_A - description: "Asynchronous prescaler factor" + description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS - description: "Subtract a fraction of a second" + description: Subtract a fraction of a second bit_offset: 0 bit_size: 15 - name: ADD1S @@ -367,89 +414,102 @@ fieldset/SHIFTR: bit_offset: 31 bit_size: 1 fieldset/SSR: - description: sub second register + description: Sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAFCR: - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register fields: - name: TAMP1E - description: "RTC_TAMP1 input detection enable" + description: Tamper 1 detection enable bit_offset: 0 bit_size: 1 - name: TAMP1TRG - description: "Active level for RTC_TAMP1 input" + description: Active level for tamper 1 bit_offset: 1 bit_size: 1 + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - name: TAMP2E - description: "RTC_TAMP2 input detection enable" + description: Tamper 2 detection enable bit_offset: 3 bit_size: 1 - name: TAMP2TRG - description: "Active level for RTC_TAMP2 input" + description: Active level for tamper 2 bit_offset: 4 bit_size: 1 + enum: TAMPTRG - name: TAMP3E - description: "RTC_TAMP3 input detection enable" + description: Tamper 3 detection enable bit_offset: 5 bit_size: 1 - name: TAMP3TRG - description: "Active level for RTC_TAMP3 input" + description: Active level for tamper 3 bit_offset: 6 bit_size: 1 + enum: TAMPTRG - name: TAMPTS - description: "Activate timestamp on tamper detection event" + description: Activate timestamp on tamper detection event bit_offset: 7 bit_size: 1 - name: TAMPFREQ description: Tamper sampling frequency bit_offset: 8 bit_size: 3 + enum: TAMPFREQ - name: TAMPFLT - description: RTC_TAMPx filter count + description: Tamper filter count bit_offset: 11 bit_size: 2 - - name: TAMP_PRCH - description: "RTC_TAMPx precharge duration" + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration bit_offset: 13 bit_size: 2 - - name: TAMP_PUDIS - description: RTC_TAMPx pull-up disable + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 + enum: TAMPPUDIS - name: PC13VALUE - description: "RTC_ALARM output type/PC13 value" + description: RTC_ALARM output type/PC13 value bit_offset: 18 bit_size: 1 + enum: PCVALUE - name: PC13MODE description: PC13 mode bit_offset: 19 bit_size: 1 + enum: PCMODE - name: PC14VALUE description: PC14 value bit_offset: 20 bit_size: 1 + enum: PCVALUE - name: PC14MODE description: PC14 mode bit_offset: 21 bit_size: 1 + enum: PCMODE - name: PC15VALUE description: PC15 value bit_offset: 22 bit_size: 1 + enum: PCVALUE - name: PC15MODE description: PC15 mode bit_offset: 23 bit_size: 1 + enum: PCMODE fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -479,8 +539,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/TSDR: - description: timestamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -503,54 +564,391 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: time-stamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: timestamp time register + description: Timestamp time register fields: - name: SU - description: "Second units in BCD format." + description: Second units in BCD format bit_offset: 0 bit_size: 4 - name: ST - description: Second tens in BCD format. + description: Second tens in BCD format bit_offset: 4 bit_size: 3 - name: MNU - description: "Minute units in BCD format." + description: Minute units in BCD format bit_offset: 8 bit_size: 4 - name: MNT - description: Minute tens in BCD format. + description: Minute tens in BCD format bit_offset: 12 bit_size: 3 - name: HU - description: Hour units in BCD format. + description: Hour units in BCD format bit_offset: 16 bit_size: 4 - name: HT - description: Hour tens in BCD format. + description: Hour tens in BCD format bit_offset: 20 bit_size: 2 - name: PM description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2-f2.yaml b/data/registers/rtc_v2-f2.yaml index bf12574..c3587d7 100644 --- a/data/registers/rtc_v2-f2.yaml +++ b/data/registers/rtc_v2-f2.yaml @@ -3,69 +3,68 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: "initialization and status register" + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - name: CALIBR - description: calibration register + description: Calibration register byte_offset: 24 fieldset: CALIBR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: TSTR - description: time stamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TAFCR - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register byte_offset: 64 fieldset: TAFCR - name: BKPR - description: backup register + description: Backup register array: len: 20 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: alarm A register +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -76,9 +75,10 @@ fieldset/ALRMAR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm A seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -88,9 +88,10 @@ fieldset/ALRMAR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm A minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -103,12 +104,14 @@ fieldset/ALRMAR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: ALRMR_PM - name: MSK3 - description: Alarm A hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 + enum: ALRMR_MSK - name: DU - description: "Date units or day in BCD format" + description: Date units or day in BCD format bit_offset: 24 bit_size: 4 - name: DT @@ -119,78 +122,21 @@ fieldset/ALRMAR: description: Week day selection bit_offset: 30 bit_size: 1 + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: "Date units or day in BCD format" - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm B date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 + enum: ALRMR_MSK fieldset/BKPR: - description: backup register + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALIBR: - description: calibration register + description: Calibration register fields: - name: DC description: Digital calibration @@ -201,66 +147,67 @@ fieldset/CALIBR: bit_offset: 7 bit_size: 1 fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection bit_offset: 0 bit_size: 3 + enum: WUCKSEL - name: TSEDGE - description: "Time-stamp event active edge" + description: Timestamp event active edge bit_offset: 3 bit_size: 1 + enum: TSEDGE - name: REFCKON - description: "Reference clock detection enable (50 or 60 Hz)" + description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 + enum: REFCKON - name: FMT description: Hour format bit_offset: 6 bit_size: 1 - name: DCE - description: "Coarse digital calibration enable" + description: Coarse digital calibration enable bit_offset: 7 bit_size: 1 - - name: ALRAE - description: Alarm A enable + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - name: WUTIE - description: "Wakeup timer interrupt enable" + description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - name: TSIE - description: "Time-stamp interrupt enable" + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - name: ADD1H - description: "Add 1 hour (summer time change)" + description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - name: SUB1H - description: "Subtract 1 hour (winter time change)" + description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - name: BKP @@ -271,16 +218,18 @@ fieldset/CR: description: Output polarity bit_offset: 20 bit_size: 1 + enum: POL - name: OSEL description: Output selection bit_offset: 21 bit_size: 2 + enum: OSEL - name: COE description: Calibration output enable bit_offset: 23 bit_size: 1 fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -311,73 +260,91 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: "initialization and status register" + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 + enum_read: WUTWFR - name: INITS description: Initialization status flag bit_offset: 4 bit_size: 1 + enum_read: INITSR - name: RSF - description: "Registers synchronization flag" + description: Registers synchronization flag bit_offset: 5 bit_size: 1 + enum_read: RSFR + enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 + enum_read: INITFR - name: INIT description: Initialization mode bit_offset: 7 bit_size: 1 - - name: ALRAF - description: Alarm A flag + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW - name: TSF - description: Time-stamp flag + description: Timestamp flag bit_offset: 11 bit_size: 1 + enum_read: TSFR + enum_write: TSFW - name: TSOVF - description: Time-stamp overflow flag + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - - name: TAMP1F + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF description: Tamper detection flag + array: + len: 1 + stride: 1 bit_offset: 13 bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S - description: "Synchronous prescaler factor" + description: Synchronous prescaler factor bit_offset: 0 - bit_size: 13 + bit_size: 15 - name: PREDIV_A - description: "Asynchronous prescaler factor" + description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 fieldset/TAFCR: - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register fields: - name: TAMP1E description: Tamper 1 detection enable @@ -387,16 +354,17 @@ fieldset/TAFCR: description: Active level for tamper 1 bit_offset: 1 bit_size: 1 + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - name: TAMP1INSEL - description: TAMPER1 mapping + description: Tamper 1 mapping bit_offset: 16 bit_size: 1 - name: TSINSEL - description: TIMESTAMP mapping + description: Timestamp mapping bit_offset: 17 bit_size: 1 - name: ALARMOUTTYPE @@ -404,7 +372,7 @@ fieldset/TAFCR: bit_offset: 18 bit_size: 1 fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -434,8 +402,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -458,7 +427,7 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSTR: - description: time stamp time register + description: Timestamp time register fields: - name: SU description: Second units in BCD format @@ -488,17 +457,276 @@ fieldset/TSTR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT - description: "Wakeup auto-reload value bits" + description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2-f3.yaml b/data/registers/rtc_v2-f3.yaml index c0a718f..18b73e0 100644 --- a/data/registers/rtc_v2-f3.yaml +++ b/data/registers/rtc_v2-f3.yaml @@ -3,92 +3,90 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: "initialization and status register" + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: time stamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: timestamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: calibration register + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAFCR - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register byte_offset: 64 fieldset: TAFCR - - name: ALRMASSR - description: alarm A sub second register + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: BKPR - description: backup register + description: Backup register array: len: 32 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: alarm A register +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -99,10 +97,10 @@ fieldset/ALRMAR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm A seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -112,10 +110,10 @@ fieldset/ALRMAR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm A minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -128,14 +126,14 @@ fieldset/ALRMAR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: ALRMAR_PM + enum: ALRMR_PM - name: MSK3 - description: Alarm A hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: DU - description: "Date units or day in BCD format" + description: Date units or day in BCD format bit_offset: 24 bit_size: 4 - name: DT @@ -146,130 +144,54 @@ fieldset/ALRMAR: description: Week day selection bit_offset: 30 bit_size: 1 - enum: ALRMAR_WDSEL + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm A date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 - enum: ALRMAR_MSK1 -fieldset/ALRMASSR: - description: alarm A sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value bit_offset: 0 bit_size: 15 - name: MASKSS - description: "Mask the most-significant bits starting at this bit" - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMBR_PM - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: DU - description: "Date units or day in BCD format" - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMBR_WDSEL - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMBR_MSK1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting at this bit" + description: Mask the most-significant bits starting at this bit bit_offset: 24 bit_size: 4 fieldset/BKPR: - description: backup register + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus bit_offset: 0 bit_size: 9 - name: CALW16 - description: "Use a 16-second calibration cycle period" + description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 enum: CALW16 - name: CALW8 - description: "Use an 8-second calibration cycle period" + description: Use an 8-second calibration cycle period bit_offset: 14 bit_size: 1 enum: CALW8 - name: CALP - description: "Increase frequency of RTC by 488.5 ppm" + description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection @@ -277,82 +199,68 @@ fieldset/CR: bit_size: 3 enum: WUCKSEL - name: TSEDGE - description: "Time-stamp event active edge" + description: Timestamp event active edge bit_offset: 3 bit_size: 1 enum: TSEDGE - name: REFCKON - description: "Reference clock detection enable (50 or 60 Hz)" + description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 enum: REFCKON - name: BYPSHAD - description: "Bypass the shadow registers" + description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - enum: BYPSHAD - name: FMT description: Hour format bit_offset: 6 bit_size: 1 enum: FMT - - name: ALRAE - description: Alarm A enable + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum: ALRAE - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - enum: ALRBE - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - enum: WUTE - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - enum: TSE - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - enum: ALRAIE - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - enum: ALRBIE - name: WUTIE - description: "Wakeup timer interrupt enable" + description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - enum: WUTIE - name: TSIE - description: "Time-stamp interrupt enable" + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - enum: TSIE - name: ADD1H - description: "Add 1 hour (summer time change)" + description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - enum_write: ADD1HW - name: SUB1H - description: "Subtract 1 hour (winter time change)" + description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - enum_write: SUB1HW - name: BKP description: Backup bit_offset: 18 bit_size: 1 - enum: BKP - name: COSEL - description: "Calibration output selection" + description: Calibration output selection bit_offset: 19 bit_size: 1 enum: COSEL @@ -370,9 +278,8 @@ fieldset/CR: description: Calibration output enable bit_offset: 23 bit_size: 1 - enum: COE fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -403,18 +310,16 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: "initialization and status register" + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - enum_read: ALRAWFR - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 - enum_read: ALRAWFR + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 @@ -424,14 +329,13 @@ fieldset/ISR: description: Shift operation pending bit_offset: 3 bit_size: 1 - enum_read: SHPFR - name: INITS description: Initialization status flag bit_offset: 4 bit_size: 1 enum_read: INITSR - name: RSF - description: "Registers synchronization flag" + description: Registers synchronization flag bit_offset: 5 bit_size: 1 enum_read: RSFR @@ -446,18 +350,15 @@ fieldset/ISR: bit_offset: 7 bit_size: 1 enum: INIT - - name: ALRAF - description: Alarm A flag + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum_read: ALRAFR - enum_write: ALRAFW - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 - enum_read: ALRBFR - enum_write: ALRBFW + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 @@ -465,103 +366,89 @@ fieldset/ISR: enum_read: WUTFR enum_write: WUTFW - name: TSF - description: Time-stamp flag + description: Timestamp flag bit_offset: 11 bit_size: 1 enum_read: TSFR enum_write: TSFW - name: TSOVF - description: Time-stamp overflow flag + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 enum_read: TSOVFR enum_write: TSOVFW - - name: TAMP1F + - name: TAMPF description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP2F - description: RTC_TAMP2 detection flag - bit_offset: 14 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP3F - description: RTC_TAMP3 detection flag - bit_offset: 15 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF - description: Recalibration pending Flag + description: Recalibration pending flag bit_offset: 16 bit_size: 1 enum_read: RECALPFR fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S - description: "Synchronous prescaler factor" + description: Synchronous prescaler factor bit_offset: 0 bit_size: 15 - name: PREDIV_A - description: "Asynchronous prescaler factor" + description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS - description: "Subtract a fraction of a second" + description: Subtract a fraction of a second bit_offset: 0 bit_size: 15 - name: ADD1S description: Add one second bit_offset: 31 bit_size: 1 - enum_write: ADD1SW fieldset/SSR: - description: sub second register + description: Sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAFCR: - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register fields: - name: TAMP1E description: Tamper 1 detection enable bit_offset: 0 bit_size: 1 - enum: TAMP1E - name: TAMP1TRG description: Active level for tamper 1 bit_offset: 1 bit_size: 1 - enum: TAMP1TRG + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - enum: TAMPIE - name: TAMP2E description: Tamper 2 detection enable bit_offset: 3 bit_size: 1 - enum: TAMP1E - name: TAMP2TRG description: Active level for tamper 2 bit_offset: 4 bit_size: 1 - enum: TAMP1TRG + enum: TAMPTRG - name: TAMPTS - description: "Activate timestamp on tamper detection event" + description: Activate timestamp on tamper detection event bit_offset: 7 bit_size: 1 - enum: TAMPTS - name: TAMPFREQ description: Tamper sampling frequency bit_offset: 8 @@ -578,7 +465,7 @@ fieldset/TAFCR: bit_size: 2 enum: TAMPPRCH - name: TAMPPUDIS - description: TAMPER pull-up disable + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 enum: TAMPPUDIS @@ -586,34 +473,34 @@ fieldset/TAFCR: description: PC13 value bit_offset: 18 bit_size: 1 - enum: PC13VALUE + enum: PCVALUE - name: PC13MODE description: PC13 mode bit_offset: 19 bit_size: 1 - enum: PC13MODE + enum: PCMODE - name: PC14VALUE description: PC14 value bit_offset: 20 bit_size: 1 - enum: PC13VALUE + enum: PCVALUE - name: PC14MODE description: PC 14 mode bit_offset: 21 bit_size: 1 - enum: PC13MODE + enum: PCMODE - name: PC15VALUE description: PC15 value bit_offset: 22 bit_size: 1 - enum: PC13VALUE + enum: PCVALUE - name: PC15MODE description: PC15 mode bit_offset: 23 bit_size: 1 - enum: PC13MODE + enum: PCMODE fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -643,9 +530,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: TR_PM + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -668,14 +555,14 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: timestamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: time stamp time register + description: Timestamp time register fields: - name: SU description: Second units in BCD format @@ -705,63 +592,34 @@ fieldset/TSTR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT - description: "Wakeup auto-reload value bits" + description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ADD1HW: - bit_size: 1 - variants: - - name: Add1 - description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - value: 1 -enum/ADD1SW: - bit_size: 1 - variants: - - name: Add1 - description: Add one second to the clock/calendar - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A disabled - value: 0 - - name: Enabled - description: Alarm A enabled - value: 1 -enum/ALRAFR: +enum/ALRFR: bit_size: 1 variants: - name: Match description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) value: 1 -enum/ALRAFW: +enum/ALRFW: bit_size: 1 variants: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/ALRAIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A interrupt disabled - value: 0 - - name: Enabled - description: Alarm A interrupt enabled - value: 1 -enum/ALRAWFR: +enum/ALRWFR: bit_size: 1 variants: - name: UpdateNotAllowed @@ -770,37 +628,7 @@ enum/ALRAWFR: - name: UpdateAllowed description: Alarm update allowed value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B disabled - value: 0 - - name: Enabled - description: Alarm B enabled - value: 1 -enum/ALRBFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - value: 1 -enum/ALRBFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRBIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B Interrupt disabled - value: 0 - - name: Enabled - description: Alarm B Interrupt enabled - value: 1 -enum/ALRMAR_MSK1: +enum/ALRMR_MSK: bit_size: 1 variants: - name: Mask @@ -809,7 +637,7 @@ enum/ALRMAR_MSK1: - name: NotMask description: Date/day don’t care in Alarm comparison value: 1 -enum/ALRMAR_PM: +enum/ALRMR_PM: bit_size: 1 variants: - name: AM @@ -818,59 +646,14 @@ enum/ALRMAR_PM: - name: PM description: PM value: 1 -enum/ALRMAR_WDSEL: +enum/ALRMR_WDSEL: bit_size: 1 variants: - name: DateUnits - description: "DU[3:0] represents the date units" + description: DU[3:0] represents the date units value: 0 - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/ALRMBR_MSK1: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMBR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: DST_Not_Changed - description: Daylight Saving Time change has not been performed - value: 0 - - name: DST_Changed - description: Daylight Saving Time change has been performed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - name: ShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" - value: 0 - - name: BypassShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + description: DU[3:0] represents the week day. DT[1:0] is don’t care value: 1 enum/CALP: bit_size: 1 @@ -885,22 +668,13 @@ enum/CALW16: bit_size: 1 variants: - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 value: 1 enum/CALW8: bit_size: 1 variants: - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 -enum/COE: - bit_size: 1 - variants: - - name: Disabled - description: Calibration output disabled - value: 0 - - name: Enabled - description: Calibration output enabled + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected value: 1 enum/COSEL: bit_size: 1 @@ -927,7 +701,7 @@ enum/INIT: description: Free running mode value: 0 - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. value: 1 enum/INITFR: bit_size: 1 @@ -962,7 +736,7 @@ enum/OSEL: - name: Wakeup description: Wakeup output enabled value: 3 -enum/PC13MODE: +enum/PCMODE: bit_size: 1 variants: - name: Floating @@ -971,29 +745,29 @@ enum/PC13MODE: - name: PushPull description: PCx is forced to push-pull output if LSE is disabled value: 1 -enum/PC13VALUE: +enum/PCVALUE: bit_size: 1 variants: - name: Low - description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low" + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low value: 0 - name: High - description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high" + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high value: 1 enum/POL: bit_size: 1 variants: - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 0 - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 1 enum/RECALPFR: bit_size: 1 variants: - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 value: 1 enum/REFCKON: bit_size: 1 @@ -1019,43 +793,19 @@ enum/RSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 -enum/SUB1HW: - bit_size: 1 - variants: - - name: Sub1 - description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode - value: 1 -enum/TAMP1E: - bit_size: 1 - variants: - - name: Disabled - description: RTC_TAMPx input detection disabled - value: 0 - - name: Enabled - description: RTC_TAMPx input detection enabled - value: 1 -enum/TAMP1FR: +enum/TAMPFR: bit_size: 1 variants: - name: Tampered description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input value: 1 -enum/TAMP1FW: +enum/TAMPFW: bit_size: 1 variants: - name: Clear description: Flag cleared by software writing 0 value: 0 -enum/TAMP1TRG: +enum/TAMPTRG: bit_size: 1 variants: - name: RisingEdge @@ -1106,15 +856,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPIE: - bit_size: 1 - variants: - - name: Disabled - description: Tamper interrupt disabled - value: 0 - - name: Enabled - description: Tamper interrupt enabled - value: 1 enum/TAMPPRCH: bit_size: 2 variants: @@ -1139,16 +880,7 @@ enum/TAMPPUDIS: - name: Disabled description: Disable precharge of RTC_TAMPx pins value: 1 -enum/TAMPTS: - bit_size: 1 - variants: - - name: NoSave - description: Tamper detection event does not cause a timestamp to be saved - value: 0 - - name: Save - description: Save timestamp on tamper detection event - value: 1 -enum/TR_PM: +enum/AMPM: bit_size: 1 variants: - name: AM @@ -1157,15 +889,6 @@ enum/TR_PM: - name: PM description: PM value: 1 -enum/TSE: - bit_size: 1 - variants: - - name: Disabled - description: Timestamp disabled - value: 0 - - name: Enabled - description: Timestamp enabled - value: 1 enum/TSEDGE: bit_size: 1 variants: @@ -1187,20 +910,11 @@ enum/TSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/TSIE: - bit_size: 1 - variants: - - name: Disabled - description: Time-stamp Interrupt disabled - value: 0 - - name: Enabled - description: Time-stamp Interrupt enabled - value: 1 enum/TSOVFR: bit_size: 1 variants: - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + description: This flag is set by hardware when a timestamp event occurs while TSF is already set value: 1 enum/TSOVFW: bit_size: 1 @@ -1229,15 +943,6 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer disabled - value: 0 - - name: Enabled - description: Wakeup timer enabled - value: 1 enum/WUTFR: bit_size: 1 variants: @@ -1250,15 +955,6 @@ enum/WUTFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/WUTIE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer interrupt disabled - value: 0 - - name: Enabled - description: Wakeup timer interrupt enabled - value: 1 enum/WUTWFR: bit_size: 1 variants: diff --git a/data/registers/rtc_v2-f4.yaml b/data/registers/rtc_v2-f4.yaml index ecde10c..ab623ad 100644 --- a/data/registers/rtc_v2-f4.yaml +++ b/data/registers/rtc_v2-f4.yaml @@ -3,96 +3,94 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: "initialization and status register" + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - name: CALIBR - description: calibration register + description: Calibration register byte_offset: 24 fieldset: CALIBR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: time stamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: timestamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: calibration register + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAFCR - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register byte_offset: 64 fieldset: TAFCR - - name: ALRMASSR - description: alarm A sub second register + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: BKPR - description: backup register + description: Backup register array: len: 20 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: alarm A register +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -103,10 +101,10 @@ fieldset/ALRMAR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm A seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -116,10 +114,10 @@ fieldset/ALRMAR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm A minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -132,14 +130,14 @@ fieldset/ALRMAR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: ALRMAR_PM + enum: ALRMR_PM - name: MSK3 - description: Alarm A hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: DU - description: "Date units or day in BCD format" + description: Date units or day in BCD format bit_offset: 24 bit_size: 4 - name: DT @@ -150,108 +148,32 @@ fieldset/ALRMAR: description: Week day selection bit_offset: 30 bit_size: 1 - enum: ALRMAR_WDSEL + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm A date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 - enum: ALRMAR_MSK1 -fieldset/ALRMASSR: - description: alarm A sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value bit_offset: 0 bit_size: 15 - name: MASKSS - description: "Mask the most-significant bits starting at this bit" - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMBR_PM - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: DU - description: "Date units or day in BCD format" - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMBR_WDSEL - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMBR_MSK1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting at this bit" + description: Mask the most-significant bits starting at this bit bit_offset: 24 bit_size: 4 fieldset/BKPR: - description: backup register + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALIBR: - description: calibration register + description: Calibration register fields: - name: DC description: Digital calibration @@ -262,29 +184,29 @@ fieldset/CALIBR: bit_offset: 7 bit_size: 1 fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus bit_offset: 0 bit_size: 9 - name: CALW16 - description: "Use a 16-second calibration cycle period" + description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 enum: CALW16 - name: CALW8 - description: "Use an 8-second calibration cycle period" + description: Use an 8-second calibration cycle period bit_offset: 14 bit_size: 1 enum: CALW8 - name: CALP - description: "Increase frequency of RTC by 488.5 ppm" + description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection @@ -292,86 +214,72 @@ fieldset/CR: bit_size: 3 enum: WUCKSEL - name: TSEDGE - description: "Time-stamp event active edge" + description: Timestamp event active edge bit_offset: 3 bit_size: 1 enum: TSEDGE - name: REFCKON - description: "Reference clock detection enable (50 or 60 Hz)" + description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 enum: REFCKON - name: BYPSHAD - description: "Bypass the shadow registers" + description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - enum: BYPSHAD - name: FMT description: Hour format bit_offset: 6 bit_size: 1 enum: FMT - name: DCE - description: "Coarse digital calibration enable" + description: Coarse digital calibration enable bit_offset: 7 bit_size: 1 - - name: ALRAE - description: Alarm A enable + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum: ALRAE - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - enum: ALRBE - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - enum: WUTE - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - enum: TSE - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - enum: ALRAIE - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - enum: ALRBIE - name: WUTIE - description: "Wakeup timer interrupt enable" + description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - enum: WUTIE - name: TSIE - description: "Time-stamp interrupt enable" + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - enum: TSIE - name: ADD1H - description: "Add 1 hour (summer time change)" + description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - enum_write: ADD1HW - name: SUB1H - description: "Subtract 1 hour (winter time change)" + description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - enum_write: SUB1HW - name: BKP description: Backup bit_offset: 18 bit_size: 1 - enum: BKP - name: COSEL - description: "Calibration Output selection" + description: Calibration output selection bit_offset: 19 bit_size: 1 enum: COSEL @@ -389,9 +297,8 @@ fieldset/CR: description: Calibration output enable bit_offset: 23 bit_size: 1 - enum: COE fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -422,18 +329,16 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: "initialization and status register" + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - enum_read: ALRAWFR - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 - enum_read: ALRAWFR + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 @@ -443,14 +348,13 @@ fieldset/ISR: description: Shift operation pending bit_offset: 3 bit_size: 1 - enum_read: SHPFR - name: INITS description: Initialization status flag bit_offset: 4 bit_size: 1 enum_read: INITSR - name: RSF - description: "Registers synchronization flag" + description: Registers synchronization flag bit_offset: 5 bit_size: 1 enum_read: RSFR @@ -465,18 +369,15 @@ fieldset/ISR: bit_offset: 7 bit_size: 1 enum: INIT - - name: ALRAF - description: Alarm A flag + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum_read: ALRAFR - enum_write: ALRAFW - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 - enum_read: ALRBFR - enum_write: ALRBFW + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 @@ -484,66 +385,62 @@ fieldset/ISR: enum_read: WUTFR enum_write: WUTFW - name: TSF - description: Time-stamp flag + description: Timestamp flag bit_offset: 11 bit_size: 1 enum_read: TSFR enum_write: TSFW - name: TSOVF - description: Time-stamp overflow flag + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 enum_read: TSOVFR enum_write: TSOVFW - - name: TAMP1F + - name: TAMPF description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP2F - description: TAMPER2 detection flag - bit_offset: 14 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF - description: Recalibration pending Flag + description: Recalibration pending flag bit_offset: 16 bit_size: 1 enum_read: RECALPFR fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S - description: "Synchronous prescaler factor" + description: Synchronous prescaler factor bit_offset: 0 bit_size: 15 - name: PREDIV_A - description: "Asynchronous prescaler factor" + description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS - description: "Subtract a fraction of a second" + description: Subtract a fraction of a second bit_offset: 0 bit_size: 15 - name: ADD1S description: Add one second bit_offset: 31 bit_size: 1 - enum_write: ADD1SW fieldset/SSR: - description: sub second register + description: Sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAFCR: - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register fields: - name: TAMP1E description: Tamper 1 detection enable @@ -553,6 +450,7 @@ fieldset/TAFCR: description: Active level for tamper 1 bit_offset: 1 bit_size: 1 + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 @@ -565,32 +463,37 @@ fieldset/TAFCR: description: Active level for tamper 2 bit_offset: 4 bit_size: 1 + enum: TAMPTRG - name: TAMPTS - description: "Activate timestamp on tamper detection event" + description: Activate timestamp on tamper detection event bit_offset: 7 bit_size: 1 - name: TAMPFREQ description: Tamper sampling frequency bit_offset: 8 bit_size: 3 + enum: TAMPFREQ - name: TAMPFLT description: Tamper filter count bit_offset: 11 bit_size: 2 + enum: TAMPFLT - name: TAMPPRCH description: Tamper precharge duration bit_offset: 13 bit_size: 2 + enum: TAMPPRCH - name: TAMPPUDIS - description: TAMPER pull-up disable + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 + enum: TAMPPUDIS - name: TAMP1INSEL - description: TAMPER1 mapping + description: Tamper 1 mapping bit_offset: 16 bit_size: 1 - name: TSINSEL - description: TIMESTAMP mapping + description: Timestamp mapping bit_offset: 17 bit_size: 1 - name: ALARMOUTTYPE @@ -598,7 +501,7 @@ fieldset/TAFCR: bit_offset: 18 bit_size: 1 fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -628,9 +531,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: TR_PM + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -653,14 +556,14 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: timestamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: time stamp time register + description: Timestamp time register fields: - name: SU description: Second units in BCD format @@ -690,63 +593,34 @@ fieldset/TSTR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT - description: "Wakeup auto-reload value bits" + description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ADD1HW: - bit_size: 1 - variants: - - name: Add1 - description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - value: 1 -enum/ADD1SW: - bit_size: 1 - variants: - - name: Add1 - description: Add one second to the clock/calendar - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A disabled - value: 0 - - name: Enabled - description: Alarm A enabled - value: 1 -enum/ALRAFR: +enum/ALRFR: bit_size: 1 variants: - name: Match description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) value: 1 -enum/ALRAFW: +enum/ALRFW: bit_size: 1 variants: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/ALRAIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A interrupt disabled - value: 0 - - name: Enabled - description: Alarm A interrupt enabled - value: 1 -enum/ALRAWFR: +enum/ALRWFR: bit_size: 1 variants: - name: UpdateNotAllowed @@ -755,37 +629,7 @@ enum/ALRAWFR: - name: UpdateAllowed description: Alarm update allowed value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B disabled - value: 0 - - name: Enabled - description: Alarm B enabled - value: 1 -enum/ALRBFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - value: 1 -enum/ALRBFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRBIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B Interrupt disabled - value: 0 - - name: Enabled - description: Alarm B Interrupt enabled - value: 1 -enum/ALRMAR_MSK1: +enum/ALRMR_MSK: bit_size: 1 variants: - name: Mask @@ -794,7 +638,7 @@ enum/ALRMAR_MSK1: - name: NotMask description: Date/day don’t care in Alarm comparison value: 1 -enum/ALRMAR_PM: +enum/ALRMR_PM: bit_size: 1 variants: - name: AM @@ -803,59 +647,14 @@ enum/ALRMAR_PM: - name: PM description: PM value: 1 -enum/ALRMAR_WDSEL: +enum/ALRMR_WDSEL: bit_size: 1 variants: - name: DateUnits - description: "DU[3:0] represents the date units" + description: DU[3:0] represents the date units value: 0 - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/ALRMBR_MSK1: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMBR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: DST_Not_Changed - description: Daylight Saving Time change has not been performed - value: 0 - - name: DST_Changed - description: Daylight Saving Time change has been performed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - name: ShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" - value: 0 - - name: BypassShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + description: DU[3:0] represents the week day. DT[1:0] is don’t care value: 1 enum/CALP: bit_size: 1 @@ -870,22 +669,13 @@ enum/CALW16: bit_size: 1 variants: - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 value: 1 enum/CALW8: bit_size: 1 variants: - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 -enum/COE: - bit_size: 1 - variants: - - name: Disabled - description: Calibration output disabled - value: 0 - - name: Enabled - description: Calibration output enabled + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected value: 1 enum/COSEL: bit_size: 1 @@ -912,7 +702,7 @@ enum/INIT: description: Free running mode value: 0 - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. value: 1 enum/INITFR: bit_size: 1 @@ -951,16 +741,16 @@ enum/POL: bit_size: 1 variants: - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 0 - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 1 enum/RECALPFR: bit_size: 1 variants: - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 value: 1 enum/REFCKON: bit_size: 1 @@ -1007,13 +797,88 @@ enum/TAMP1FR: - name: Tampered description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input value: 1 -enum/TAMP1FW: +enum/TAMPFW: bit_size: 1 variants: - name: Clear description: Flag cleared by software writing 0 value: 0 -enum/TR_PM: +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: bit_size: 1 variants: - name: AM @@ -1022,15 +887,6 @@ enum/TR_PM: - name: PM description: PM value: 1 -enum/TSE: - bit_size: 1 - variants: - - name: Disabled - description: Timestamp disabled - value: 0 - - name: Enabled - description: Timestamp enabled - value: 1 enum/TSEDGE: bit_size: 1 variants: @@ -1052,20 +908,11 @@ enum/TSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/TSIE: - bit_size: 1 - variants: - - name: Disabled - description: Time-stamp Interrupt disabled - value: 0 - - name: Enabled - description: Time-stamp Interrupt enabled - value: 1 enum/TSOVFR: bit_size: 1 variants: - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + description: This flag is set by hardware when a timestamp event occurs while TSF is already set value: 1 enum/TSOVFW: bit_size: 1 @@ -1094,15 +941,6 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer disabled - value: 0 - - name: Enabled - description: Wakeup timer enabled - value: 1 enum/WUTFR: bit_size: 1 variants: @@ -1115,15 +953,6 @@ enum/WUTFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/WUTIE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer interrupt disabled - value: 0 - - name: Enabled - description: Wakeup timer interrupt enabled - value: 1 enum/WUTWFR: bit_size: 1 variants: diff --git a/data/registers/rtc_v2-f7.yaml b/data/registers/rtc_v2-f7.yaml index 1f76e62..ceafc1f 100644 --- a/data/registers/rtc_v2-f7.yaml +++ b/data/registers/rtc_v2-f7.yaml @@ -3,96 +3,94 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: initialization and status register + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: time stamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: timestamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: calibration register + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAMPCR - description: tamper configuration register + description: Tamper configuration register byte_offset: 64 fieldset: TAMPCR - - name: ALRMASSR - description: alarm A sub second register + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: OR - description: option register + description: Option register byte_offset: 76 fieldset: OR - name: BKPR - description: backup register + description: Backup register array: len: 32 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: alarm A register +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -103,10 +101,10 @@ fieldset/ALRMAR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm A seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -116,10 +114,10 @@ fieldset/ALRMAR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm A minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -132,12 +130,12 @@ fieldset/ALRMAR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: ALRMAR_PM + enum: ALRMR_PM - name: MSK3 - description: Alarm A hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 - enum: ALRMAR_MSK1 + enum: ALRMR_MSK - name: DU description: Date units or day in BCD format bit_offset: 24 @@ -150,90 +148,14 @@ fieldset/ALRMAR: description: Week day selection bit_offset: 30 bit_size: 1 - enum: ALRMAR_WDSEL + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm A date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 - enum: ALRMAR_MSK1 -fieldset/ALRMASSR: - description: alarm A sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMBR_PM - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMBR_MSK1 - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMBR_WDSEL - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMBR_MSK1 -fieldset/ALRMBSSR: - description: alarm B sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value @@ -244,14 +166,14 @@ fieldset/ALRMBSSR: bit_offset: 24 bit_size: 4 fieldset/BKPR: - description: backup register + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus @@ -273,7 +195,7 @@ fieldset/CALR: bit_size: 1 enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection @@ -281,7 +203,7 @@ fieldset/CR: bit_size: 3 enum: WUCKSEL - name: TSEDGE - description: Time-stamp event active edge + description: Timestamp event active edge bit_offset: 3 bit_size: 1 enum: TSEDGE @@ -294,67 +216,53 @@ fieldset/CR: description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - enum: BYPSHAD - name: FMT description: Hour format bit_offset: 6 bit_size: 1 enum: FMT - - name: ALRAE - description: Alarm A enable + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum: ALRAE - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - enum: ALRBE - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - enum: WUTE - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - enum: TSE - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - enum: ALRAIE - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - enum: ALRBIE - name: WUTIE description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - enum: WUTIE - name: TSIE - description: Time-stamp interrupt enable + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - enum: TSIE - name: ADD1H description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - enum_write: ADD1HW - name: SUB1H description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - enum_write: SUB1HW - name: BKP description: Backup bit_offset: 18 bit_size: 1 - enum: BKP - name: COSEL description: Calibration output selection bit_offset: 19 @@ -374,13 +282,12 @@ fieldset/CR: description: Calibration output enable bit_offset: 23 bit_size: 1 - enum: COE - name: ITSE - description: timestamp on internal event enable + description: Timestamp on internal event enable bit_offset: 24 bit_size: 1 fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -411,18 +318,16 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: initialization and status register + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - enum_read: ALRAWFR - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 - enum_read: ALRAWFR + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 @@ -432,7 +337,6 @@ fieldset/ISR: description: Shift operation pending bit_offset: 3 bit_size: 1 - enum_read: SHPFR - name: INITS description: Initialization status flag bit_offset: 4 @@ -454,18 +358,15 @@ fieldset/ISR: bit_offset: 7 bit_size: 1 enum: INIT - - name: ALRAF - description: Alarm A flag + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum_read: ALRAFR - enum_write: ALRAFW - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 - enum_read: ALRBFR - enum_write: ALRBFW + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 @@ -473,37 +374,28 @@ fieldset/ISR: enum_read: WUTFR enum_write: WUTFW - name: TSF - description: Time-stamp flag + description: Timestamp flag bit_offset: 11 bit_size: 1 enum_read: TSFR enum_write: TSFW - name: TSOVF - description: Time-stamp overflow flag + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 enum_read: TSOVFR enum_write: TSOVFW - - name: TAMP1F + - name: TAMPF description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP2F - description: RTC_TAMP2 detection flag - bit_offset: 14 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP3F - description: RTC_TAMP3 detection flag - bit_offset: 15 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF - description: Recalibration pending Flag + description: Recalibration pending flag bit_offset: 16 bit_size: 1 enum_read: RECALPFR @@ -512,18 +404,18 @@ fieldset/ISR: bit_offset: 17 bit_size: 1 fieldset/OR: - description: option register + description: Option register fields: - name: TSINSEL - description: TIMESTAMP mapping + description: Timestamp mapping bit_offset: 1 - bit_size: 1 + bit_size: 2 - name: RTC_ALARM_TYPE description: RTC_ALARM on PC13 output type bit_offset: 3 bit_size: 1 fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S description: Synchronous prescaler factor @@ -534,7 +426,7 @@ fieldset/PRER: bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS description: Subtract a fraction of a second @@ -544,16 +436,15 @@ fieldset/SHIFTR: description: Add one second bit_offset: 31 bit_size: 1 - enum_write: ADD1SW fieldset/SSR: - description: sub second register + description: Sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAMPCR: - description: tamper configuration register + description: Tamper configuration register fields: - name: TAMP1E description: Tamper 1 detection enable @@ -563,6 +454,7 @@ fieldset/TAMPCR: description: Active level for tamper 1 bit_offset: 1 bit_size: 1 + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 @@ -575,6 +467,7 @@ fieldset/TAMPCR: description: Active level for tamper 2 bit_offset: 4 bit_size: 1 + enum: TAMPTRG - name: TAMP3E description: Tamper 3 detection enable bit_offset: 5 @@ -583,6 +476,7 @@ fieldset/TAMPCR: description: Active level for tamper 3 bit_offset: 6 bit_size: 1 + enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 @@ -591,18 +485,22 @@ fieldset/TAMPCR: description: Tamper sampling frequency bit_offset: 8 bit_size: 3 + enum: TAMPFREQ - name: TAMPFLT description: Tamper filter count bit_offset: 11 bit_size: 2 + enum: TAMPFLT - name: TAMPPRCH description: Tamper precharge duration bit_offset: 13 bit_size: 2 + enum: TAMPPRCH - name: TAMPPUDIS - description: TAMPER pull-up disable + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 + enum: TAMPPUDIS - name: TAMP1IE description: Tamper 1 interrupt enable bit_offset: 16 @@ -640,7 +538,7 @@ fieldset/TAMPCR: bit_offset: 24 bit_size: 1 fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -670,9 +568,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: TR_PM + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -695,14 +593,14 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: timestamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: time stamp time register + description: Timestamp time register fields: - name: SU description: Second units in BCD format @@ -732,63 +630,34 @@ fieldset/TSTR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ADD1HW: - bit_size: 1 - variants: - - name: Add1 - description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - value: 1 -enum/ADD1SW: - bit_size: 1 - variants: - - name: Add1 - description: Add one second to the clock/calendar - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A disabled - value: 0 - - name: Enabled - description: Alarm A enabled - value: 1 -enum/ALRAFR: +enum/ALRFR: bit_size: 1 variants: - name: Match description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) value: 1 -enum/ALRAFW: +enum/ALRFW: bit_size: 1 variants: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/ALRAIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A interrupt disabled - value: 0 - - name: Enabled - description: Alarm A interrupt enabled - value: 1 -enum/ALRAWFR: +enum/ALRWFR: bit_size: 1 variants: - name: UpdateNotAllowed @@ -797,37 +666,7 @@ enum/ALRAWFR: - name: UpdateAllowed description: Alarm update allowed value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B disabled - value: 0 - - name: Enabled - description: Alarm B enabled - value: 1 -enum/ALRBFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - value: 1 -enum/ALRBFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRBIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B Interrupt disabled - value: 0 - - name: Enabled - description: Alarm B Interrupt enabled - value: 1 -enum/ALRMAR_MSK1: +enum/ALRMR_MSK: bit_size: 1 variants: - name: Mask @@ -836,7 +675,7 @@ enum/ALRMAR_MSK1: - name: NotMask description: Date/day don’t care in Alarm comparison value: 1 -enum/ALRMAR_PM: +enum/ALRMR_PM: bit_size: 1 variants: - name: AM @@ -845,59 +684,14 @@ enum/ALRMAR_PM: - name: PM description: PM value: 1 -enum/ALRMAR_WDSEL: +enum/ALRMR_WDSEL: bit_size: 1 variants: - name: DateUnits - description: "DU[3:0] represents the date units" + description: DU[3:0] represents the date units value: 0 - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/ALRMBR_MSK1: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMBR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: DST_Not_Changed - description: Daylight Saving Time change has not been performed - value: 0 - - name: DST_Changed - description: Daylight Saving Time change has been performed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - name: ShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" - value: 0 - - name: BypassShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + description: DU[3:0] represents the week day. DT[1:0] is don’t care value: 1 enum/CALP: bit_size: 1 @@ -912,22 +706,13 @@ enum/CALW16: bit_size: 1 variants: - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 value: 1 enum/CALW8: bit_size: 1 variants: - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 -enum/COE: - bit_size: 1 - variants: - - name: Disabled - description: Calibration output disabled - value: 0 - - name: Enabled - description: Calibration output enabled + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected value: 1 enum/COSEL: bit_size: 1 @@ -954,7 +739,7 @@ enum/INIT: description: Free running mode value: 0 - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. value: 1 enum/INITFR: bit_size: 1 @@ -993,16 +778,16 @@ enum/POL: bit_size: 1 variants: - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 0 - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 1 enum/RECALPFR: bit_size: 1 variants: - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 value: 1 enum/REFCKON: bit_size: 1 @@ -1028,34 +813,94 @@ enum/RSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 -enum/SUB1HW: - bit_size: 1 - variants: - - name: Sub1 - description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode - value: 1 -enum/TAMP1FR: +enum/TAMPFR: bit_size: 1 variants: - name: Tampered description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input value: 1 -enum/TAMP1FW: +enum/TAMPFW: bit_size: 1 variants: - name: Clear description: Flag cleared by software writing 0 value: 0 -enum/TR_PM: +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: bit_size: 1 variants: - name: AM @@ -1064,15 +909,6 @@ enum/TR_PM: - name: PM description: PM value: 1 -enum/TSE: - bit_size: 1 - variants: - - name: Disabled - description: Timestamp disabled - value: 0 - - name: Enabled - description: Timestamp enabled - value: 1 enum/TSEDGE: bit_size: 1 variants: @@ -1094,20 +930,11 @@ enum/TSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/TSIE: - bit_size: 1 - variants: - - name: Disabled - description: Time-stamp Interrupt disabled - value: 0 - - name: Enabled - description: Time-stamp Interrupt enabled - value: 1 enum/TSOVFR: bit_size: 1 variants: - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + description: This flag is set by hardware when a timestamp event occurs while TSF is already set value: 1 enum/TSOVFW: bit_size: 1 @@ -1136,15 +963,6 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer disabled - value: 0 - - name: Enabled - description: Wakeup timer enabled - value: 1 enum/WUTFR: bit_size: 1 variants: @@ -1157,15 +975,6 @@ enum/WUTFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/WUTIE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer interrupt disabled - value: 0 - - name: Enabled - description: Wakeup timer interrupt enabled - value: 1 enum/WUTWFR: bit_size: 1 variants: diff --git a/data/registers/rtc_v2-h7.yaml b/data/registers/rtc_v2-h7.yaml index 89b2e34..ef3273d 100644 --- a/data/registers/rtc_v2-h7.yaml +++ b/data/registers/rtc_v2-h7.yaml @@ -1,174 +1,96 @@ --- block/RTC: - description: RTC + description: Real-time clock items: - name: TR - description: "The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: "The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: RTC control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: "This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9." + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: "This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: "This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - - name: ALRMAR - description: "This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: "This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: RTC write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: RTC sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: "This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: "The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset." + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: "This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAMPCR - description: "RTC tamper and alternate function configuration register" + description: Tamper configuration register byte_offset: 64 fieldset: TAMPCR - - name: ALRMASSR - description: "This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9" + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: "This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection." - byte_offset: 72 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: OR - description: RTC option register + description: Option register byte_offset: 76 fieldset: OR - name: BKPR - description: RTC backup registers + description: Backup register array: len: 32 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: "This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." - fields: - - name: SU - description: "Second units in BCD format." - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format. - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: MNU - description: "Minute units in BCD format." - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format. - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: HU - description: Hour units in BCD format. - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format. - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMAR_PM - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: DU - description: "Date units or day in BCD format." - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format. - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMAR_WDSEL - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMAR_MSK1 -fieldset/ALRMASSR: - description: "This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9" - fields: - - name: SS - description: "Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared." - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation." - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: "This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -179,10 +101,10 @@ fieldset/ALRMBR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm B seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 - enum: ALRMBR_MSK1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -192,10 +114,10 @@ fieldset/ALRMBR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm B minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 - enum: ALRMBR_MSK1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -208,14 +130,14 @@ fieldset/ALRMBR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: ALRMBR_PM + enum: ALRMR_PM - name: MSK3 - description: Alarm B hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 - enum: ALRMBR_MSK1 + enum: ALRMR_MSK - name: DU - description: "Date units or day in BCD format" + description: Date units or day in BCD format bit_offset: 24 bit_size: 4 - name: DT @@ -226,54 +148,54 @@ fieldset/ALRMBR: description: Week day selection bit_offset: 30 bit_size: 1 - enum: ALRMBR_WDSEL + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm B date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 - enum: ALRMBR_MSK1 -fieldset/ALRMBSSR: - description: "This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection." + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS - description: "Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared." + description: Sub seconds value bit_offset: 0 bit_size: 15 - name: MASKSS - description: "Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation." + description: Mask the most-significant bits starting at this bit bit_offset: 24 bit_size: 4 fieldset/BKPR: - description: RTC backup registers + description: Backup register fields: - name: BKP - description: "The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." + description: BKP bit_offset: 0 bit_size: 32 fieldset/CALR: - description: "This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Calibration register fields: - name: CALM - description: "Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section24.3.12: RTC smooth digital calibration on page13." + description: Calibration minus bit_offset: 0 bit_size: 9 - name: CALW16 - description: "Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM[0] is stuck at 0 when CALW16= 1. Refer to Section24.3.12: RTC smooth digital calibration." + description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 enum: CALW16 - name: CALW8 - description: "Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00; when CALW8= 1. Refer to Section24.3.12: RTC smooth digital calibration." + description: Use an 8-second calibration cycle period bit_offset: 14 bit_size: 1 enum: CALW8 - name: CALP - description: "Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section24.3.12: RTC smooth digital calibration." + description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 enum: CALP fieldset/CR: - description: RTC control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection @@ -281,107 +203,91 @@ fieldset/CR: bit_size: 3 enum: WUCKSEL - name: TSEDGE - description: "Time-stamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting." + description: Timestamp event active edge bit_offset: 3 bit_size: 1 enum: TSEDGE - name: REFCKON - description: "RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF." + description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 enum: REFCKON - name: BYPSHAD - description: "Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1." + description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - enum: BYPSHAD - name: FMT description: Hour format bit_offset: 6 bit_size: 1 enum: FMT - - name: ALRAE - description: Alarm A enable + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum: ALRAE - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - enum: ALRBE - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - enum: WUTE - name: TSE - description: timestamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - enum: TSE - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - enum: ALRAIE - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - enum: ALRBIE - name: WUTIE - description: "Wakeup timer interrupt enable" + description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - enum: WUTIE - name: TSIE - description: "Time-stamp interrupt enable" + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - enum: TSIE - name: ADD1H - description: "Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0." + description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - enum_write: ADD1HW - name: SUB1H - description: "Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0." + description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - enum_write: SUB1HW - name: BKP - description: "Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not." + description: Backup bit_offset: 18 bit_size: 1 - enum: BKP - name: COSEL - description: "Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section24.3.15: Calibration clock output" + description: Calibration output selection bit_offset: 19 bit_size: 1 enum: COSEL - name: POL - description: "Output polarity This bit is used to configure the polarity of RTC_ALARM output" + description: Output polarity bit_offset: 20 bit_size: 1 enum: POL - name: OSEL - description: "Output selection These bits are used to select the flag to be routed to RTC_ALARM output" + description: Output selection bit_offset: 21 bit_size: 2 enum: OSEL - name: COE - description: "Calibration output enable This bit enables the RTC_CALIB output" + description: Calibration output enable bit_offset: 23 bit_size: 1 - enum: COE - name: ITSE - description: "timestamp on internal event enable" + description: Timestamp on internal event enable bit_offset: 24 bit_size: 1 - enum: ITSE fieldset/DR: - description: "The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Date register fields: - name: DU description: Date units in BCD format @@ -412,41 +318,38 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: "This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9." + description: Initialization and status register fields: - - name: ALRAWF - description: "Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode." + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - enum_read: ALRAWFR - - name: ALRBWF - description: "Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode." - bit_offset: 1 - bit_size: 1 - enum_read: ALRAWFR + enum_read: ALRWFR - name: WUTWF - description: "Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set." + description: Wakeup timer write flag bit_offset: 2 bit_size: 1 enum_read: WUTWFR - name: SHPF - description: "Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect." + description: Shift operation pending bit_offset: 3 bit_size: 1 - enum_read: SHPFR - name: INITS - description: "Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state)." + description: Initialization status flag bit_offset: 4 bit_size: 1 enum_read: INITSR - name: RSF - description: "Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode." + description: Registers synchronization flag bit_offset: 5 bit_size: 1 enum_read: RSFR enum_write: RSFW - name: INITF - description: "Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated." + description: Initialization flag bit_offset: 6 bit_size: 1 enum_read: INITFR @@ -455,70 +358,56 @@ fieldset/ISR: bit_offset: 7 bit_size: 1 enum: INIT - - name: ALRAF - description: "Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0." + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum_read: ALRAFR - enum_write: ALRAFW - - name: ALRBF - description: "Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0." - bit_offset: 9 - bit_size: 1 - enum_read: ALRBFR - enum_write: ALRBFW + enum_read: ALRFR + enum_write: ALRFW - name: WUTF - description: "Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again." + description: Wakeup timer flag bit_offset: 10 bit_size: 1 enum_read: WUTFR enum_write: WUTFW - name: TSF - description: "Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0." + description: Timestamp flag bit_offset: 11 bit_size: 1 enum_read: TSFR enum_write: TSFW - name: TSOVF - description: "Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-stamp event occurs immediately before the TSF bit is cleared." + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 enum_read: TSOVFR enum_write: TSOVFW - - name: TAMP1F - description: "RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0" + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP2F - description: "RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0" - bit_offset: 14 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP3F - description: "RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0" - bit_offset: 15 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF - description: "Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly." + description: Recalibration pending flag bit_offset: 16 bit_size: 1 enum_read: RECALPFR - name: ITSF - description: Internal tTime-stamp flag + description: Internal time-stamp flag bit_offset: 17 bit_size: 1 - enum_read: ITSFR - enum_write: ITSFW fieldset/OR: - description: RTC option register + description: Option register fields: - name: RTC_ALARM_TYPE - description: "RTC_ALARM output type on PC13" + description: RTC_ALARM output type on PC13 bit_offset: 0 bit_size: 1 - name: RTC_OUT_RMP @@ -526,86 +415,92 @@ fieldset/OR: bit_offset: 1 bit_size: 1 fieldset/PRER: - description: "This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Prescaler register fields: - name: PREDIV_S - description: "Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)" + description: Synchronous prescaler factor bit_offset: 0 bit_size: 15 - name: PREDIV_A - description: "Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)" + description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: "This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Shift control register fields: - name: SUBFS - description: "Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time." + description: Subtract a fraction of a second bit_offset: 0 bit_size: 15 - name: ADD1S - description: "Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation." + description: Add one second bit_offset: 31 bit_size: 1 - enum_write: ADD1SW fieldset/SSR: - description: RTC sub second register + description: Sub second register fields: - name: SS - description: "Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR." + description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAMPCR: - description: "RTC tamper and alternate function configuration register" + description: Tamper configuration register fields: - name: TAMP1E - description: "RTC_TAMP1 input detection enable" + description: Tamper 1 detection enable bit_offset: 0 bit_size: 1 - name: TAMP1TRG - description: "Active level for RTC_TAMP1 input If TAMPFLT != 00 if TAMPFLT = 00:" + description: Active level for tamper 1 bit_offset: 1 bit_size: 1 + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - name: TAMP2E - description: "RTC_TAMP2 input detection enable" + description: Tamper 2 detection enable bit_offset: 3 bit_size: 1 - name: TAMP2TRG - description: "Active level for RTC_TAMP2 input if TAMPFLT != 00: if TAMPFLT = 00:" + description: Active level for tamper 2 bit_offset: 4 bit_size: 1 + enum: TAMPTRG - name: TAMP3E - description: RTC_TAMP3 detection enable + description: Tamper 3 detection enable bit_offset: 5 bit_size: 1 - name: TAMP3TRG - description: "Active level for RTC_TAMP3 input if TAMPFLT != 00: if TAMPFLT = 00:" + description: Active level for tamper 3 bit_offset: 6 bit_size: 1 + enum: TAMPTRG - name: TAMPTS - description: "Activate timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register." + description: Activate timestamp on tamper detection event bit_offset: 7 bit_size: 1 - name: TAMPFREQ - description: "Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled." + description: Tamper sampling frequency bit_offset: 8 bit_size: 3 + enum: TAMPFREQ - name: TAMPFLT - description: "RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs." + description: Tamper filter count bit_offset: 11 bit_size: 2 + enum: TAMPFLT - name: TAMPPRCH - description: "RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs." + description: Tamper precharge duration bit_offset: 13 bit_size: 2 + enum: TAMPPRCH - name: TAMPPUDIS - description: "RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample." + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 + enum: TAMPPUDIS - name: TAMP1IE description: Tamper 1 interrupt enable bit_offset: 16 @@ -643,7 +538,7 @@ fieldset/TAMPCR: bit_offset: 24 bit_size: 1 fieldset/TR: - description: "The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Time register fields: - name: SU description: Second units in BCD format @@ -673,9 +568,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: TR_PM + enum: AMPM fieldset/TSDR: - description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -698,100 +593,71 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: "The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset." + description: Timestamp sub second register fields: - name: SS - description: "Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred." + description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: "The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." + description: Timestamp time register fields: - name: SU - description: "Second units in BCD format." + description: Second units in BCD format bit_offset: 0 bit_size: 4 - name: ST - description: Second tens in BCD format. + description: Second tens in BCD format bit_offset: 4 bit_size: 3 - name: MNU - description: "Minute units in BCD format." + description: Minute units in BCD format bit_offset: 8 bit_size: 4 - name: MNT - description: Minute tens in BCD format. + description: Minute tens in BCD format bit_offset: 12 bit_size: 3 - name: HU - description: Hour units in BCD format. + description: Hour units in BCD format bit_offset: 16 bit_size: 4 - name: HT - description: Hour tens in BCD format. + description: Hour tens in BCD format bit_offset: 20 bit_size: 2 - name: PM description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: RTC write protection register + description: Write protection register fields: - name: KEY - description: "Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection." + description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: "This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9." + description: Wakeup timer register fields: - name: WUT - description: "Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden." + description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ADD1HW: - bit_size: 1 - variants: - - name: Add1 - description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - value: 1 -enum/ADD1SW: - bit_size: 1 - variants: - - name: Add1 - description: Add one second to the clock/calendar - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A disabled - value: 0 - - name: Enabled - description: Alarm A enabled - value: 1 -enum/ALRAFR: +enum/ALRFR: bit_size: 1 variants: - name: Match description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) value: 1 -enum/ALRAFW: +enum/ALRFW: bit_size: 1 variants: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/ALRAIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A interrupt disabled - value: 0 - - name: Enabled - description: Alarm A interrupt enabled - value: 1 -enum/ALRAWFR: +enum/ALRWFR: bit_size: 1 variants: - name: UpdateNotAllowed @@ -800,37 +666,7 @@ enum/ALRAWFR: - name: UpdateAllowed description: Alarm update allowed value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B disabled - value: 0 - - name: Enabled - description: Alarm B enabled - value: 1 -enum/ALRBFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - value: 1 -enum/ALRBFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRBIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B Interrupt disabled - value: 0 - - name: Enabled - description: Alarm B Interrupt enabled - value: 1 -enum/ALRMAR_MSK1: +enum/ALRMR_MSK: bit_size: 1 variants: - name: Mask @@ -839,7 +675,7 @@ enum/ALRMAR_MSK1: - name: NotMask description: Date/day don’t care in Alarm comparison value: 1 -enum/ALRMAR_PM: +enum/ALRMR_PM: bit_size: 1 variants: - name: AM @@ -848,59 +684,14 @@ enum/ALRMAR_PM: - name: PM description: PM value: 1 -enum/ALRMAR_WDSEL: +enum/ALRMR_WDSEL: bit_size: 1 variants: - name: DateUnits - description: "DU[3:0] represents the date units" + description: DU[3:0] represents the date units value: 0 - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/ALRMBR_MSK1: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMBR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: DST_Not_Changed - description: Daylight Saving Time change has not been performed - value: 0 - - name: DST_Changed - description: Daylight Saving Time change has been performed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - name: ShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" - value: 0 - - name: BypassShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + description: DU[3:0] represents the week day. DT[1:0] is don’t care value: 1 enum/CALP: bit_size: 1 @@ -915,22 +706,13 @@ enum/CALW16: bit_size: 1 variants: - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 value: 1 enum/CALW8: bit_size: 1 variants: - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 -enum/COE: - bit_size: 1 - variants: - - name: Disabled - description: Calibration output disabled - value: 0 - - name: Enabled - description: Calibration output enabled + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected value: 1 enum/COSEL: bit_size: 1 @@ -957,7 +739,7 @@ enum/INIT: description: Free running mode value: 0 - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. value: 1 enum/INITFR: bit_size: 1 @@ -977,27 +759,6 @@ enum/INITSR: - name: Initalized description: Calendar has been initialized value: 1 -enum/ITSE: - bit_size: 1 - variants: - - name: Disabled - description: Internal event timestamp is disabled - value: 0 - - name: Enabled - description: Internal event timestamp is enabled - value: 1 -enum/ITSFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when a time-stamp on the internal event occurs - value: 1 -enum/ITSFW: - bit_size: 1 - variants: - - name: Clear - description: "This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits" - value: 0 enum/OSEL: bit_size: 2 variants: @@ -1017,16 +778,16 @@ enum/POL: bit_size: 1 variants: - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 0 - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 1 enum/RECALPFR: bit_size: 1 variants: - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 value: 1 enum/REFCKON: bit_size: 1 @@ -1052,34 +813,94 @@ enum/RSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 -enum/SUB1HW: - bit_size: 1 - variants: - - name: Sub1 - description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode - value: 1 -enum/TAMP1FR: +enum/TAMPFR: bit_size: 1 variants: - name: Tampered description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input value: 1 -enum/TAMP1FW: +enum/TAMPFW: bit_size: 1 variants: - name: Clear description: Flag cleared by software writing 0 value: 0 -enum/TR_PM: +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: bit_size: 1 variants: - name: AM @@ -1088,15 +909,6 @@ enum/TR_PM: - name: PM description: PM value: 1 -enum/TSE: - bit_size: 1 - variants: - - name: Disabled - description: Timestamp disabled - value: 0 - - name: Enabled - description: Timestamp enabled - value: 1 enum/TSEDGE: bit_size: 1 variants: @@ -1118,20 +930,11 @@ enum/TSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/TSIE: - bit_size: 1 - variants: - - name: Disabled - description: Time-stamp Interrupt disabled - value: 0 - - name: Enabled - description: Time-stamp Interrupt enabled - value: 1 enum/TSOVFR: bit_size: 1 variants: - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + description: This flag is set by hardware when a timestamp event occurs while TSF is already set value: 1 enum/TSOVFW: bit_size: 1 @@ -1160,15 +963,6 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer disabled - value: 0 - - name: Enabled - description: Wakeup timer enabled - value: 1 enum/WUTFR: bit_size: 1 variants: @@ -1181,15 +975,6 @@ enum/WUTFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/WUTIE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer interrupt disabled - value: 0 - - name: Enabled - description: Wakeup timer interrupt enabled - value: 1 enum/WUTWFR: bit_size: 1 variants: diff --git a/data/registers/rtc_v2-l0.yaml b/data/registers/rtc_v2-l0.yaml index 7c340c7..2136f5f 100644 --- a/data/registers/rtc_v2-l0.yaml +++ b/data/registers/rtc_v2-l0.yaml @@ -3,172 +3,94 @@ block/RTC: description: Real-time clock items: - name: TR - description: RTC time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: RTC date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: RTC control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: RTC initialization and status register + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: RTC prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: RTC wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - - name: ALRMAR - description: RTC alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: RTC alarm B register - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: RTC sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: RTC shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: RTC timestamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: RTC timestamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: RTC time-stamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: RTC calibration register + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAMPCR - description: RTC tamper configuration register + description: Tamper configuration register byte_offset: 64 fieldset: TAMPCR - - name: ALRMASSR - description: RTC alarm A sub second register + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: RTC alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: OR - description: option register + description: Option register byte_offset: 76 fieldset: OR - name: BKPR - description: RTC backup registers + description: Backup register array: len: 5 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: RTC alarm A register - fields: - - name: SU - description: Second units in BCD format. - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format. - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: MNU - description: Minute units in BCD format. - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format. - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: HU - description: Hour units in BCD format. - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format. - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMAR_PM - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - enum: ALRMAR_MSK1 - - name: DU - description: Date units or day in BCD format. - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format. - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMAR_WDSEL - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 - enum: ALRMAR_MSK1 -fieldset/ALRMASSR: - description: RTC alarm A sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: RTC alarm B register +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -179,10 +101,10 @@ fieldset/ALRMBR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm B seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 - enum: ALRMBR_MSK1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -192,10 +114,10 @@ fieldset/ALRMBR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm B minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 - enum: ALRMBR_MSK1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -208,12 +130,12 @@ fieldset/ALRMBR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: ALRMBR_PM + enum: ALRMR_PM - name: MSK3 - description: Alarm B hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 - enum: ALRMBR_MSK1 + enum: ALRMR_MSK - name: DU description: Date units or day in BCD format bit_offset: 24 @@ -226,14 +148,14 @@ fieldset/ALRMBR: description: Week day selection bit_offset: 30 bit_size: 1 - enum: ALRMBR_WDSEL + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm B date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 - enum: ALRMBR_MSK1 -fieldset/ALRMBSSR: - description: RTC alarm B sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value @@ -244,14 +166,14 @@ fieldset/ALRMBSSR: bit_offset: 24 bit_size: 4 fieldset/BKPR: - description: RTC backup registers + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALR: - description: RTC calibration register + description: Calibration register fields: - name: CALM description: Calibration minus @@ -273,7 +195,7 @@ fieldset/CALR: bit_size: 1 enum: CALP fieldset/CR: - description: RTC control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection @@ -281,12 +203,12 @@ fieldset/CR: bit_size: 3 enum: WUCKSEL - name: TSEDGE - description: Time-stamp event active edge + description: Timestamp event active edge bit_offset: 3 bit_size: 1 enum: TSEDGE - name: REFCKON - description: RTC_REFIN reference clock detection enable (50 or 60 Hz) + description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 enum: REFCKON @@ -294,67 +216,53 @@ fieldset/CR: description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - enum: BYPSHAD - name: FMT description: Hour format bit_offset: 6 bit_size: 1 enum: FMT - - name: ALRAE - description: Alarm A enable + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum: ALRAE - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - enum: ALRBE - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - enum: WUTE - name: TSE - description: timestamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - enum: TSE - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - enum: ALRAIE - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - enum: ALRBIE - name: WUTIE description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - enum: WUTIE - name: TSIE - description: Time-stamp interrupt enable + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - enum: TSIE - name: ADD1H description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - enum_write: ADD1HW - name: SUB1H description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - enum_write: SUB1HW - name: BKP description: Backup bit_offset: 18 bit_size: 1 - enum: BKP - name: COSEL description: Calibration output selection bit_offset: 19 @@ -374,9 +282,8 @@ fieldset/CR: description: Calibration output enable bit_offset: 23 bit_size: 1 - enum: COE fieldset/DR: - description: RTC date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -407,18 +314,16 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: RTC initialization and status register + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - enum_read: ALRAWFR - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 - enum_read: ALRAWFR + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 @@ -428,7 +333,6 @@ fieldset/ISR: description: Shift operation pending bit_offset: 3 bit_size: 1 - enum_read: SHPFR - name: INITS description: Initialization status flag bit_offset: 4 @@ -450,18 +354,15 @@ fieldset/ISR: bit_offset: 7 bit_size: 1 enum: INIT - - name: ALRAF - description: Alarm A flag + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum_read: ALRAFR - enum_write: ALRAFW - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 - enum_read: ALRBFR - enum_write: ALRBFW + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 @@ -469,42 +370,33 @@ fieldset/ISR: enum_read: WUTFR enum_write: WUTFW - name: TSF - description: Time-stamp flag + description: Timestamp flag bit_offset: 11 bit_size: 1 enum_read: TSFR enum_write: TSFW - name: TSOVF - description: Time-stamp overflow flag + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 enum_read: TSOVFR enum_write: TSOVFW - - name: TAMP1F - description: RTC_TAMP1 detection flag + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP2F - description: RTC_TAMP2 detection flag - bit_offset: 14 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW - - name: TAMP3F - description: RTC_TAMP3 detection flag - bit_offset: 15 - bit_size: 1 - enum_read: TAMP1FR - enum_write: TAMP1FW + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF description: Recalibration pending flag bit_offset: 16 bit_size: 1 enum_read: RECALPFR fieldset/OR: - description: option register + description: Option register fields: - name: RTC_ALARM_TYPE description: RTC_ALARM on PC13 output type @@ -515,18 +407,18 @@ fieldset/OR: bit_offset: 1 bit_size: 1 fieldset/PRER: - description: RTC prescaler register + description: Prescaler register fields: - name: PREDIV_S description: Synchronous prescaler factor bit_offset: 0 - bit_size: 16 + bit_size: 15 - name: PREDIV_A description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: RTC shift control register + description: Shift control register fields: - name: SUBFS description: Subtract a fraction of a second @@ -536,74 +428,68 @@ fieldset/SHIFTR: description: Add one second bit_offset: 31 bit_size: 1 - enum_write: ADD1SW fieldset/SSR: - description: RTC sub second register + description: Sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAMPCR: - description: RTC tamper configuration register + description: Tamper configuration register fields: - name: TAMP1E - description: RTC_TAMP1 input detection enable + description: Tamper 1 detection enable bit_offset: 0 bit_size: 1 - enum: TAMP1E - name: TAMP1TRG - description: Active level for RTC_TAMP1 input + description: Active level for tamper 1 bit_offset: 1 bit_size: 1 - enum: TAMP1TRG + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - enum: TAMPIE - name: TAMP2E - description: RTC_TAMP2 input detection enable + description: Tamper 2 detection enable bit_offset: 3 bit_size: 1 - enum: TAMP1E - name: TAMP2TRG - description: Active level for RTC_TAMP2 input + description: Active level for tamper 2 bit_offset: 4 bit_size: 1 - enum: TAMP1TRG + enum: TAMPTRG - name: TAMP3E - description: RTC_TAMP3 detection enable + description: Tamper 3 detection enable bit_offset: 5 bit_size: 1 - enum: TAMP1E - name: TAMP3TRG - description: Active level for RTC_TAMP3 input + description: Active level for tamper 3 bit_offset: 6 bit_size: 1 - enum: TAMP1TRG + enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 bit_size: 1 - enum: TAMPTS - name: TAMPFREQ description: Tamper sampling frequency bit_offset: 8 bit_size: 3 enum: TAMPFREQ - name: TAMPFLT - description: RTC_TAMPx filter count + description: Tamper filter count bit_offset: 11 bit_size: 2 enum: TAMPFLT - name: TAMPPRCH - description: RTC_TAMPx precharge duration + description: Tamper precharge duration bit_offset: 13 bit_size: 2 enum: TAMPPRCH - name: TAMPPUDIS - description: RTC_TAMPx pull-up disable + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 enum: TAMPPUDIS @@ -611,49 +497,40 @@ fieldset/TAMPCR: description: Tamper 1 interrupt enable bit_offset: 16 bit_size: 1 - enum: TAMP1IE - name: TAMP1NOERASE description: Tamper 1 no erase bit_offset: 17 bit_size: 1 - enum: TAMP1NOERASE - name: TAMP1MF description: Tamper 1 mask flag bit_offset: 18 bit_size: 1 - enum: TAMP1MF - name: TAMP2IE description: Tamper 2 interrupt enable bit_offset: 19 bit_size: 1 - enum: TAMP1IE - name: TAMP2NOERASE description: Tamper 2 no erase bit_offset: 20 bit_size: 1 - enum: TAMP1NOERASE - name: TAMP2MF description: Tamper 2 mask flag bit_offset: 21 bit_size: 1 - enum: TAMP1MF - name: TAMP3IE description: Tamper 3 interrupt enable bit_offset: 22 bit_size: 1 - enum: TAMP1IE - name: TAMP3NOERASE description: Tamper 3 no erase bit_offset: 23 bit_size: 1 - enum: TAMP1NOERASE - name: TAMP3MF description: Tamper 3 mask flag bit_offset: 24 bit_size: 1 - enum: TAMP1MF fieldset/TR: - description: RTC time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -683,9 +560,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: TR_PM + enum: AMPM fieldset/TSDR: - description: RTC timestamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -708,100 +585,71 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: RTC time-stamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: RTC timestamp time register + description: Timestamp time register fields: - name: SU - description: Second units in BCD format. + description: Second units in BCD format bit_offset: 0 bit_size: 4 - name: ST - description: Second tens in BCD format. + description: Second tens in BCD format bit_offset: 4 bit_size: 3 - name: MNU - description: Minute units in BCD format. + description: Minute units in BCD format bit_offset: 8 bit_size: 4 - name: MNT - description: Minute tens in BCD format. + description: Minute tens in BCD format bit_offset: 12 bit_size: 3 - name: HU - description: Hour units in BCD format. + description: Hour units in BCD format bit_offset: 16 bit_size: 4 - name: HT - description: Hour tens in BCD format. + description: Hour tens in BCD format bit_offset: 20 bit_size: 2 - name: PM description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: RTC wakeup timer register + description: Wakeup timer register fields: - name: WUT description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ADD1HW: - bit_size: 1 - variants: - - name: Add1 - description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - value: 1 -enum/ADD1SW: - bit_size: 1 - variants: - - name: Add1 - description: Add one second to the clock/calendar - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A disabled - value: 0 - - name: Enabled - description: Alarm A enabled - value: 1 -enum/ALRAFR: +enum/ALRFR: bit_size: 1 variants: - name: Match description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) value: 1 -enum/ALRAFW: +enum/ALRFW: bit_size: 1 variants: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/ALRAIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A interrupt disabled - value: 0 - - name: Enabled - description: Alarm A interrupt enabled - value: 1 -enum/ALRAWFR: +enum/ALRWFR: bit_size: 1 variants: - name: UpdateNotAllowed @@ -810,37 +658,7 @@ enum/ALRAWFR: - name: UpdateAllowed description: Alarm update allowed value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B disabled - value: 0 - - name: Enabled - description: Alarm B enabled - value: 1 -enum/ALRBFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - value: 1 -enum/ALRBFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRBIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B Interrupt disabled - value: 0 - - name: Enabled - description: Alarm B Interrupt enabled - value: 1 -enum/ALRMAR_MSK1: +enum/ALRMR_MSK: bit_size: 1 variants: - name: Mask @@ -849,7 +667,7 @@ enum/ALRMAR_MSK1: - name: NotMask description: Date/day don’t care in Alarm comparison value: 1 -enum/ALRMAR_PM: +enum/ALRMR_PM: bit_size: 1 variants: - name: AM @@ -858,59 +676,14 @@ enum/ALRMAR_PM: - name: PM description: PM value: 1 -enum/ALRMAR_WDSEL: +enum/ALRMR_WDSEL: bit_size: 1 variants: - name: DateUnits - description: "DU[3:0] represents the date units" + description: DU[3:0] represents the date units value: 0 - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/ALRMBR_MSK1: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMBR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: DST_Not_Changed - description: Daylight Saving Time change has not been performed - value: 0 - - name: DST_Changed - description: Daylight Saving Time change has been performed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - name: ShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" - value: 0 - - name: BypassShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + description: DU[3:0] represents the week day. DT[1:0] is don’t care value: 1 enum/CALP: bit_size: 1 @@ -925,22 +698,13 @@ enum/CALW16: bit_size: 1 variants: - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 value: 1 enum/CALW8: bit_size: 1 variants: - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 -enum/COE: - bit_size: 1 - variants: - - name: Disabled - description: Calibration output disabled - value: 0 - - name: Enabled - description: Calibration output enabled + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected value: 1 enum/COSEL: bit_size: 1 @@ -967,7 +731,7 @@ enum/INIT: description: Free running mode value: 0 - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. value: 1 enum/INITFR: bit_size: 1 @@ -1006,16 +770,16 @@ enum/POL: bit_size: 1 variants: - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 0 - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) value: 1 enum/RECALPFR: bit_size: 1 variants: - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 value: 1 enum/REFCKON: bit_size: 1 @@ -1041,70 +805,19 @@ enum/RSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 -enum/SUB1HW: - bit_size: 1 - variants: - - name: Sub1 - description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode - value: 1 -enum/TAMP1E: - bit_size: 1 - variants: - - name: Disabled - description: RTC_TAMPx input detection disabled - value: 0 - - name: Enabled - description: RTC_TAMPx input detection enabled - value: 1 -enum/TAMP1FR: +enum/TAMPFR: bit_size: 1 variants: - name: Tampered description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input value: 1 -enum/TAMP1FW: +enum/TAMPFW: bit_size: 1 variants: - name: Clear description: Flag cleared by software writing 0 value: 0 -enum/TAMP1IE: - bit_size: 1 - variants: - - name: Disabled - description: Tamper x interrupt is disabled if TAMPIE = 0 - value: 0 - - name: Enabled - description: Tamper x interrupt enabled - value: 1 -enum/TAMP1MF: - bit_size: 1 - variants: - - name: NotMasked - description: Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection - value: 0 - - name: Masked - description: Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. - value: 1 -enum/TAMP1NOERASE: - bit_size: 1 - variants: - - name: Erase - description: Tamper x event erases the backup registers - value: 0 - - name: NoErase - description: Tamper x event does not erase the backup registers - value: 1 -enum/TAMP1TRG: +enum/TAMPTRG: bit_size: 1 variants: - name: RisingEdge @@ -1155,15 +868,6 @@ enum/TAMPFREQ: - name: Div256 description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) value: 7 -enum/TAMPIE: - bit_size: 1 - variants: - - name: Disabled - description: Tamper interrupt disabled - value: 0 - - name: Enabled - description: Tamper interrupt enabled - value: 1 enum/TAMPPRCH: bit_size: 2 variants: @@ -1188,16 +892,7 @@ enum/TAMPPUDIS: - name: Disabled description: Disable precharge of RTC_TAMPx pins value: 1 -enum/TAMPTS: - bit_size: 1 - variants: - - name: NoSave - description: Tamper detection event does not cause a timestamp to be saved - value: 0 - - name: Save - description: Save timestamp on tamper detection event - value: 1 -enum/TR_PM: +enum/AMPM: bit_size: 1 variants: - name: AM @@ -1206,15 +901,6 @@ enum/TR_PM: - name: PM description: PM value: 1 -enum/TSE: - bit_size: 1 - variants: - - name: Disabled - description: Timestamp disabled - value: 0 - - name: Enabled - description: Timestamp enabled - value: 1 enum/TSEDGE: bit_size: 1 variants: @@ -1236,20 +922,11 @@ enum/TSFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/TSIE: - bit_size: 1 - variants: - - name: Disabled - description: Time-stamp Interrupt disabled - value: 0 - - name: Enabled - description: Time-stamp Interrupt enabled - value: 1 enum/TSOVFR: bit_size: 1 variants: - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + description: This flag is set by hardware when a timestamp event occurs while TSF is already set value: 1 enum/TSOVFW: bit_size: 1 @@ -1278,15 +955,6 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer disabled - value: 0 - - name: Enabled - description: Wakeup timer enabled - value: 1 enum/WUTFR: bit_size: 1 variants: @@ -1299,15 +967,6 @@ enum/WUTFW: - name: Clear description: This flag is cleared by software by writing 0 value: 0 -enum/WUTIE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer interrupt disabled - value: 0 - - name: Enabled - description: Wakeup timer interrupt enabled - value: 1 enum/WUTWFR: bit_size: 1 variants: diff --git a/data/registers/rtc_v2-l1.yaml b/data/registers/rtc_v2-l1.yaml index 0fbf5f4..72ed04a 100644 --- a/data/registers/rtc_v2-l1.yaml +++ b/data/registers/rtc_v2-l1.yaml @@ -3,166 +3,94 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: "initialization and status register" + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - name: CALIBR - description: calibration register + description: Calibration register byte_offset: 24 fieldset: CALIBR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: TSTR + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: timestamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: calibration register + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAFCR - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register byte_offset: 64 fieldset: TAFCR - - name: ALRMASSR - description: alarm A sub second register + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: BKPR - description: backup register + description: Backup register array: len: 32 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: alarm A register - fields: - - name: SU - description: "Second units in BCD format." - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format. - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: "Minute units in BCD format." - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format. - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format. - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format. - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: "Date units or day in BCD format." - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format. - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting at this bit" - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -173,9 +101,10 @@ fieldset/ALRMBR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm B seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -185,9 +114,10 @@ fieldset/ALRMBR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm B minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -200,12 +130,14 @@ fieldset/ALRMBR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: ALRMR_PM - name: MSK3 - description: Alarm B hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 + enum: ALRMR_MSK - name: DU - description: "Date units or day in BCD format" + description: Date units or day in BCD format bit_offset: 24 bit_size: 4 - name: DT @@ -216,30 +148,32 @@ fieldset/ALRMBR: description: Week day selection bit_offset: 30 bit_size: 1 + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm B date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 -fieldset/ALRMBSSR: - description: alarm B sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value bit_offset: 0 bit_size: 15 - name: MASKSS - description: "Mask the most-significant bits starting at this bit" + description: Mask the most-significant bits starting at this bit bit_offset: 24 bit_size: 4 fieldset/BKPR: - description: backup register + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALIBR: - description: calibration register + description: Calibration register fields: - name: DC description: Digital calibration @@ -250,89 +184,94 @@ fieldset/CALIBR: bit_offset: 7 bit_size: 1 fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus bit_offset: 0 bit_size: 9 - name: CALW16 - description: CALW16 + description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 + enum: CALW16 - name: CALW8 - description: "Use a 16-second calibration cycle period" + description: Use an 8-second calibration cycle period bit_offset: 14 bit_size: 1 + enum: CALW8 - name: CALP - description: "Use an 8-second calibration cycle period" + description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 + enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection bit_offset: 0 bit_size: 3 + enum: WUCKSEL - name: TSEDGE - description: "Time-stamp event active edge" + description: Timestamp event active edge bit_offset: 3 bit_size: 1 + enum: TSEDGE - name: REFCKON - description: "Reference clock detection enable" + description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 + enum: REFCKON - name: BYPSHAD - description: "Bypass the shadow registers" + description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - name: FMT description: Hour format bit_offset: 6 bit_size: 1 + enum: FMT - name: DCE - description: "Coarse digital calibration enable" + description: Coarse digital calibration enable bit_offset: 7 bit_size: 1 - - name: ALRAE - description: Alarm A enable + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - name: WUTIE - description: "Wakeup timer interrupt enable" + description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - name: TSIE - description: "Time-stamp interrupt enable" + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - name: ADD1H - description: Add 1 hour + description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - name: SUB1H - description: Subtract 1 hour + description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - name: BKP @@ -340,23 +279,26 @@ fieldset/CR: bit_offset: 18 bit_size: 1 - name: COSEL - description: "Calibration output selection" + description: Calibration output selection bit_offset: 19 bit_size: 1 + enum: COSEL - name: POL description: Output polarity bit_offset: 20 bit_size: 1 + enum: POL - name: OSEL description: Output selection bit_offset: 21 bit_size: 2 + enum: OSEL - name: COE description: Calibration output enable bit_offset: 23 bit_size: 1 fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -387,20 +329,21 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: "initialization and status register" + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 + enum_read: WUTWFR - name: SHPF description: Shift operation pending bit_offset: 3 @@ -409,94 +352,105 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 + enum_read: INITSR - name: RSF - description: "Registers synchronization flag" + description: Registers synchronization flag bit_offset: 5 bit_size: 1 + enum_read: RSFR + enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 + enum_read: INITFR - name: INIT description: Initialization mode bit_offset: 7 bit_size: 1 - - name: ALRAF - description: Alarm A flag + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW - name: TSF description: Timestamp flag bit_offset: 11 bit_size: 1 + enum_read: TSFR + enum_write: TSFW - name: TSOVF description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - - name: TAMP1F + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - - name: TAMP2F - description: TAMPER2 detection flag - bit_offset: 14 - bit_size: 1 - - name: TAMP3F - description: TAMPER3 detection flag - bit_offset: 15 - bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF - description: Recalibration pending Flag + description: Recalibration pending flag bit_offset: 16 bit_size: 1 + enum_read: RECALPFR fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S - description: "Synchronous prescaler factor" + description: Synchronous prescaler factor bit_offset: 0 bit_size: 15 - name: PREDIV_A - description: "Asynchronous prescaler factor" + description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS - description: "Subtract a fraction of a second" + description: Subtract a fraction of a second bit_offset: 0 bit_size: 15 - name: ADD1S - description: ADD1S + description: Add one second bit_offset: 31 bit_size: 1 fieldset/SSR: - description: sub second register + description: Sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAFCR: - description: "tamper and alternate function configuration register" + description: Tamper and alternate function configuration register fields: - name: TAMP1E description: Tamper 1 detection enable bit_offset: 0 bit_size: 1 - - name: TAMP1ETRG + - name: TAMP1TRG description: Active level for tamper 1 bit_offset: 1 bit_size: 1 + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 @@ -509,40 +463,46 @@ fieldset/TAFCR: description: Active level for tamper 2 bit_offset: 4 bit_size: 1 + enum: TAMPTRG - name: TAMP3E - description: TIMESTAMP mapping + description: Tamper 3 detection enable bit_offset: 5 bit_size: 1 - name: TAMP3TRG - description: TAMPER1 mapping + description: Active level for tamper 3 bit_offset: 6 bit_size: 1 + enum: TAMPTRG - name: TAMPTS - description: "Activate timestamp on tamper detection event" + description: Activate timestamp on tamper detection event bit_offset: 7 bit_size: 1 - name: TAMPFREQ description: Tamper sampling frequency bit_offset: 8 bit_size: 3 + enum: TAMPFREQ - name: TAMPFLT description: Tamper filter count bit_offset: 11 bit_size: 2 + enum: TAMPFLT - name: TAMPPRCH description: Tamper precharge duration bit_offset: 13 bit_size: 2 + enum: TAMPPRCH - name: TAMPPUDIS - description: TAMPER pull-up disable + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 + enum: TAMPPUDIS - name: ALARMOUTTYPE description: AFO_ALARM output type bit_offset: 18 bit_size: 1 fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -572,8 +532,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -596,54 +557,394 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: timestamp sub second register + description: Timestamp sub second register fields: - name: SS - description: "RTC timestamp subsecond field" + description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: TSTR + description: Timestamp time register fields: - name: SU - description: "Second units in BCD format." + description: Second units in BCD format bit_offset: 0 bit_size: 4 - name: ST - description: Second tens in BCD format. + description: Second tens in BCD format bit_offset: 4 bit_size: 3 - name: MNU - description: "Minute units in BCD format." + description: Minute units in BCD format bit_offset: 8 bit_size: 4 - name: MNT - description: Minute tens in BCD format. + description: Minute tens in BCD format bit_offset: 12 bit_size: 3 - name: HU - description: Hour units in BCD format. + description: Hour units in BCD format bit_offset: 16 bit_size: 4 - name: HT - description: Hour tens in BCD format. + description: Hour tens in BCD format bit_offset: 20 bit_size: 2 - name: PM description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT - description: "Wakeup auto-reload value bits" + description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2-l4.yaml b/data/registers/rtc_v2-l4.yaml index 80a64a7..b710a2e 100644 --- a/data/registers/rtc_v2-l4.yaml +++ b/data/registers/rtc_v2-l4.yaml @@ -3,96 +3,94 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: "initialization and status register" + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: time stamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: timestamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: calibration register + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAMPCR - description: tamper configuration register + description: Tamper configuration register byte_offset: 64 fieldset: TAMPCR - - name: ALRMASSR - description: alarm A sub second register + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: OR - description: option register + description: Option register byte_offset: 76 fieldset: OR - name: BKPR - description: backup register + description: Backup register array: len: 32 stride: 4 byte_offset: 80 fieldset: BKPR -fieldset/ALRMAR: - description: alarm A register +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -103,9 +101,10 @@ fieldset/ALRMAR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm A seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -115,9 +114,10 @@ fieldset/ALRMAR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm A minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -130,12 +130,14 @@ fieldset/ALRMAR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: ALRMR_PM - name: MSK3 - description: Alarm A hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 + enum: ALRMR_MSK - name: DU - description: "Date units or day in BCD format" + description: Date units or day in BCD format bit_offset: 24 bit_size: 4 - name: DT @@ -146,178 +148,115 @@ fieldset/ALRMAR: description: Week day selection bit_offset: 30 bit_size: 1 + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm A date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value bit_offset: 0 bit_size: 15 - name: MASKSS - description: "Mask the most-significant bits starting at this bit" - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: "Date units or day in BCD format" - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting at this bit" + description: Mask the most-significant bits starting at this bit bit_offset: 24 bit_size: 4 fieldset/BKPR: - description: backup register + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus bit_offset: 0 bit_size: 9 - name: CALW16 - description: "Use a 16-second calibration cycle period" + description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 + enum: CALW16 - name: CALW8 - description: "Use an 8-second calibration cycle period" + description: Use an 8-second calibration cycle period bit_offset: 14 bit_size: 1 + enum: CALW8 - name: CALP - description: "Increase frequency of RTC by 488.5 ppm" + description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 + enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection bit_offset: 0 bit_size: 3 + enum: WUCKSEL - name: TSEDGE - description: "Time-stamp event active edge" + description: Timestamp event active edge bit_offset: 3 bit_size: 1 + enum: TSEDGE - name: REFCKON - description: "Reference clock detection enable (50 or 60 Hz)" + description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 + enum: REFCKON - name: BYPSHAD - description: "Bypass the shadow registers" + description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - name: FMT description: Hour format bit_offset: 6 bit_size: 1 - - name: ALRAE - description: Alarm A enable + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - name: WUTIE - description: "Wakeup timer interrupt enable" + description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - name: TSIE - description: "Time-stamp interrupt enable" + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - name: ADD1H - description: "Add 1 hour (summer time change)" + description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - name: SUB1H - description: "Subtract 1 hour (winter time change)" + description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - name: BKP @@ -325,27 +264,30 @@ fieldset/CR: bit_offset: 18 bit_size: 1 - name: COSEL - description: "Calibration output selection" + description: Calibration output selection bit_offset: 19 bit_size: 1 + enum: COSEL - name: POL description: Output polarity bit_offset: 20 bit_size: 1 + enum: POL - name: OSEL description: Output selection bit_offset: 21 bit_size: 2 + enum: OSEL - name: COE description: Calibration output enable bit_offset: 23 bit_size: 1 - name: ITSE - description: "timestamp on internal event enable" + description: Timestamp on internal event enable bit_offset: 24 bit_size: 1 fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -376,20 +318,21 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: "initialization and status register" + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 + enum_read: WUTWFR - name: SHPF description: Shift operation pending bit_offset: 3 @@ -398,59 +341,69 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 + enum_read: INITSR - name: RSF - description: "Registers synchronization flag" + description: Registers synchronization flag bit_offset: 5 bit_size: 1 + enum_read: RSFR + enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 + enum_read: INITFR - name: INIT description: Initialization mode bit_offset: 7 bit_size: 1 - - name: ALRAF - description: Alarm A flag + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW - name: TSF - description: Time-stamp flag + description: Timestamp flag bit_offset: 11 bit_size: 1 + enum_read: TSFR + enum_write: TSFW - name: TSOVF - description: Time-stamp overflow flag + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - - name: TAMP1F + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - - name: TAMP2F - description: RTC_TAMP2 detection flag - bit_offset: 14 - bit_size: 1 - - name: TAMP3F - description: RTC_TAMP3 detection flag - bit_offset: 15 - bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF - description: Recalibration pending Flag + description: Recalibration pending flag bit_offset: 16 bit_size: 1 + enum_read: RECALPFR fieldset/OR: - description: option register + description: Option register fields: - name: RTC_ALARM_TYPE - description: "RTC_ALARM on PC13 output type" + description: RTC_ALARM on PC13 output type bit_offset: 0 bit_size: 1 - name: RTC_OUT_RMP @@ -458,21 +411,21 @@ fieldset/OR: bit_offset: 1 bit_size: 1 fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S - description: "Synchronous prescaler factor" + description: Synchronous prescaler factor bit_offset: 0 bit_size: 15 - name: PREDIV_A - description: "Asynchronous prescaler factor" + description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS - description: "Subtract a fraction of a second" + description: Subtract a fraction of a second bit_offset: 0 bit_size: 15 - name: ADD1S @@ -480,14 +433,14 @@ fieldset/SHIFTR: bit_offset: 31 bit_size: 1 fieldset/SSR: - description: sub second register + description: Sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAMPCR: - description: tamper configuration register + description: Tamper configuration register fields: - name: TAMP1E description: Tamper 1 detection enable @@ -497,6 +450,7 @@ fieldset/TAMPCR: description: Active level for tamper 1 bit_offset: 1 bit_size: 1 + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 @@ -509,6 +463,7 @@ fieldset/TAMPCR: description: Active level for tamper 2 bit_offset: 4 bit_size: 1 + enum: TAMPTRG - name: TAMP3E description: Tamper 3 detection enable bit_offset: 5 @@ -517,26 +472,31 @@ fieldset/TAMPCR: description: Active level for tamper 3 bit_offset: 6 bit_size: 1 + enum: TAMPTRG - name: TAMPTS - description: "Activate timestamp on tamper detection event" + description: Activate timestamp on tamper detection event bit_offset: 7 bit_size: 1 - name: TAMPFREQ description: Tamper sampling frequency bit_offset: 8 bit_size: 3 + enum: TAMPFREQ - name: TAMPFLT description: Tamper filter count bit_offset: 11 bit_size: 2 + enum: TAMPFLT - name: TAMPPRCH description: Tamper precharge duration bit_offset: 13 bit_size: 2 + enum: TAMPPRCH - name: TAMPPUDIS - description: TAMPER pull-up disable + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 + enum: TAMPPUDIS - name: TAMP1IE description: Tamper 1 interrupt enable bit_offset: 16 @@ -574,7 +534,7 @@ fieldset/TAMPCR: bit_offset: 24 bit_size: 1 fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -604,8 +564,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -628,14 +589,14 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: timestamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: time stamp time register + description: Timestamp time register fields: - name: SU description: Second units in BCD format @@ -665,17 +626,357 @@ fieldset/TSTR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT - description: "Wakeup auto-reload value bits" + description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2-u5.yaml b/data/registers/rtc_v2-u5.yaml deleted file mode 100644 index b81ee9f..0000000 --- a/data/registers/rtc_v2-u5.yaml +++ /dev/null @@ -1,813 +0,0 @@ ---- -block/RTC: - description: Real-time clock - items: - - name: TR - description: time register - byte_offset: 0 - fieldset: TR - - name: DR - description: date register - byte_offset: 4 - fieldset: DR - - name: SSR - description: RTC sub second register - byte_offset: 8 - access: Read - fieldset: SSR - - name: ICSR - description: "RTC initialization control and status register" - byte_offset: 12 - fieldset: ICSR - - name: PRER - description: prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: CR - description: RTC control register - byte_offset: 24 - fieldset: CR - - name: PRIVCR - description: "RTC privilege mode control register" - byte_offset: 28 - fieldset: PRIVCR - - name: SECCFGR - description: "RTC secure mode control register" - byte_offset: 32 - fieldset: SECCFGR - - name: WPR - description: write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: CALR - description: calibration register - byte_offset: 40 - fieldset: CALR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: time stamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: time stamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: ALRMAR - description: alarm A register - byte_offset: 64 - fieldset: ALRMAR - - name: ALRMASSR - description: alarm A sub second register - byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBR - description: alarm B register - byte_offset: 72 - fieldset: ALRMBR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 76 - fieldset: ALRMBSSR - - name: SR - description: RTC status register - byte_offset: 80 - access: Read - fieldset: SR - - name: MISR - description: "RTC non-secure masked interrupt status register" - byte_offset: 84 - access: Read - fieldset: MISR - - name: SMISR - description: "RTC secure masked interrupt status register" - byte_offset: 88 - access: Read - fieldset: SMISR - - name: SCR - description: RTC status clear register - byte_offset: 92 - access: Write - fieldset: SCR - - name: ALRABINR - description: RTC alarm A binary mode register - byte_offset: 112 - fieldset: ALRABINR - - name: ALRBBINR - description: RTC alarm B binary mode register - byte_offset: 116 - fieldset: ALRBBINR -fieldset/ALRABINR: - description: RTC alarm A binary mode register - fields: - - name: SS - description: Synchronous counter alarm value in Binary mode - bit_offset: 0 - bit_size: 32 -fieldset/ALRBBINR: - description: RTC alarm B binary mode register - fields: - - name: SS - description: Synchronous counter alarm value in Binary mode - bit_offset: 0 - bit_size: 32 -fieldset/ALRMAR: - description: alarm A register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: "Date units or day in BCD format" - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting at this bit" - bit_offset: 24 - bit_size: 6 - - name: SSCLR - description: SSCLR - bit_offset: 31 - bit_size: 1 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: "Date units or day in BCD format" - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: "Mask the most-significant bits starting at this bit" - bit_offset: 24 - bit_size: 6 - - name: SSCLR - description: SSCLR - bit_offset: 31 - bit_size: 1 -fieldset/CALR: - description: calibration register - fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: LPCAL - description: LPCAL - bit_offset: 12 - bit_size: 1 - - name: CALW16 - description: "Use a 16-second calibration cycle period" - bit_offset: 13 - bit_size: 1 - - name: CALW8 - description: "Use an 8-second calibration cycle period" - bit_offset: 14 - bit_size: 1 - - name: CALP - description: "Increase frequency of RTC by 488.5 ppm" - bit_offset: 15 - bit_size: 1 -fieldset/CR: - description: RTC control register - fields: - - name: WUCKSEL - description: WUCKSEL - bit_offset: 0 - bit_size: 3 - - name: TSEDGE - description: TSEDGE - bit_offset: 3 - bit_size: 1 - - name: REFCKON - description: REFCKON - bit_offset: 4 - bit_size: 1 - - name: BYPSHAD - description: BYPSHAD - bit_offset: 5 - bit_size: 1 - - name: FMT - description: FMT - bit_offset: 6 - bit_size: 1 - - name: SSRUIE - description: SSRUIE - bit_offset: 7 - bit_size: 1 - - name: ALRAE - description: ALRAE - bit_offset: 8 - bit_size: 1 - - name: ALRBE - description: ALRBE - bit_offset: 9 - bit_size: 1 - - name: WUTE - description: WUTE - bit_offset: 10 - bit_size: 1 - - name: TSE - description: TSE - bit_offset: 11 - bit_size: 1 - - name: ALRAIE - description: ALRAIE - bit_offset: 12 - bit_size: 1 - - name: ALRBIE - description: ALRBIE - bit_offset: 13 - bit_size: 1 - - name: WUTIE - description: WUTIE - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: TSIE - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: ADD1H - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: SUB1H - bit_offset: 17 - bit_size: 1 - - name: BKP - description: BKP - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: COSEL - bit_offset: 19 - bit_size: 1 - - name: POL - description: POL - bit_offset: 20 - bit_size: 1 - - name: OSEL - description: OSEL - bit_offset: 21 - bit_size: 2 - - name: COE - description: COE - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: ITSE - bit_offset: 24 - bit_size: 1 - - name: TAMPTS - description: TAMPTS - bit_offset: 25 - bit_size: 1 - - name: TAMPOE - description: TAMPOE - bit_offset: 26 - bit_size: 1 - - name: ALRAFCLR - description: ALRAFCLR - bit_offset: 27 - bit_size: 1 - - name: ALRBFCLR - description: ALRBFCLR - bit_offset: 28 - bit_size: 1 - - name: TAMPALRM_PU - description: TAMPALRM_PU - bit_offset: 29 - bit_size: 1 - - name: TAMPALRM_TYPE - description: TAMPALRM_TYPE - bit_offset: 30 - bit_size: 1 - - name: OUT2EN - description: OUT2EN - bit_offset: 31 - bit_size: 1 -fieldset/DR: - description: date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 -fieldset/ICSR: - description: "RTC initialization control and status register" - fields: - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: "Registers synchronization flag" - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - - name: BIN - description: BIN - bit_offset: 8 - bit_size: 2 - - name: BCDU - description: BCDU - bit_offset: 10 - bit_size: 3 - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 -fieldset/MISR: - description: "RTC non-secure masked interrupt status register" - fields: - - name: ALRAMF - description: ALRAMF - bit_offset: 0 - bit_size: 1 - - name: ALRBMF - description: ALRBMF - bit_offset: 1 - bit_size: 1 - - name: WUTMF - description: WUTMF - bit_offset: 2 - bit_size: 1 - - name: TSMF - description: TSMF - bit_offset: 3 - bit_size: 1 - - name: TSOVMF - description: TSOVMF - bit_offset: 4 - bit_size: 1 - - name: ITSMF - description: ITSMF - bit_offset: 5 - bit_size: 1 - - name: SSRUMF - description: SSRUMF - bit_offset: 6 - bit_size: 1 -fieldset/PRER: - description: prescaler register - fields: - - name: PREDIV_S - description: "Synchronous prescaler factor" - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: "Asynchronous prescaler factor" - bit_offset: 16 - bit_size: 7 -fieldset/PRIVCR: - description: "RTC privilege mode control register" - fields: - - name: ALRAPRIV - description: ALRAPRIV - bit_offset: 0 - bit_size: 1 - - name: ALRBPRIV - description: ALRBPRIV - bit_offset: 1 - bit_size: 1 - - name: WUTPRIV - description: WUTPRIV - bit_offset: 2 - bit_size: 1 - - name: TSPRIV - description: TSPRIV - bit_offset: 3 - bit_size: 1 - - name: CALPRIV - description: CALPRIV - bit_offset: 13 - bit_size: 1 - - name: INITPRIV - description: INITPRIV - bit_offset: 14 - bit_size: 1 - - name: PRIV - description: PRIV - bit_offset: 15 - bit_size: 1 -fieldset/SCR: - description: RTC status clear register - fields: - - name: CALRAF - description: CALRAF - bit_offset: 0 - bit_size: 1 - - name: CALRBF - description: CALRBF - bit_offset: 1 - bit_size: 1 - - name: CWUTF - description: CWUTF - bit_offset: 2 - bit_size: 1 - - name: CTSF - description: CTSF - bit_offset: 3 - bit_size: 1 - - name: CTSOVF - description: CTSOVF - bit_offset: 4 - bit_size: 1 - - name: CITSF - description: CITSF - bit_offset: 5 - bit_size: 1 - - name: CSSRUF - description: CSSRUF - bit_offset: 6 - bit_size: 1 -fieldset/SECCFGR: - description: "RTC secure mode control register" - fields: - - name: ALRASEC - description: ALRASEC - bit_offset: 0 - bit_size: 1 - - name: ALRBSEC - description: ALRBSEC - bit_offset: 1 - bit_size: 1 - - name: WUTSEC - description: WUTSEC - bit_offset: 2 - bit_size: 1 - - name: TSSEC - description: TSSEC - bit_offset: 3 - bit_size: 1 - - name: CALSEC - description: CALSEC - bit_offset: 13 - bit_size: 1 - - name: INITSEC - description: INITSEC - bit_offset: 14 - bit_size: 1 - - name: SEC - description: SEC - bit_offset: 15 - bit_size: 1 -fieldset/SHIFTR: - description: shift control register - fields: - - name: SUBFS - description: "Subtract a fraction of a second" - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 -fieldset/SMISR: - description: "RTC secure masked interrupt status register" - fields: - - name: ALRAMF - description: ALRAMF - bit_offset: 0 - bit_size: 1 - - name: ALRBMF - description: ALRBMF - bit_offset: 1 - bit_size: 1 - - name: WUTMF - description: WUTMF - bit_offset: 2 - bit_size: 1 - - name: TSMF - description: TSMF - bit_offset: 3 - bit_size: 1 - - name: TSOVMF - description: TSOVMF - bit_offset: 4 - bit_size: 1 - - name: ITSMF - description: ITSMF - bit_offset: 5 - bit_size: 1 - - name: SSRUMF - description: SSRUMF - bit_offset: 6 - bit_size: 1 -fieldset/SR: - description: RTC status register - fields: - - name: ALRAF - description: ALRAF - bit_offset: 0 - bit_size: 1 - - name: ALRBF - description: ALRBF - bit_offset: 1 - bit_size: 1 - - name: WUTF - description: WUTF - bit_offset: 2 - bit_size: 1 - - name: TSF - description: TSF - bit_offset: 3 - bit_size: 1 - - name: TSOVF - description: TSOVF - bit_offset: 4 - bit_size: 1 - - name: ITSF - description: ITSF - bit_offset: 5 - bit_size: 1 - - name: SSRUF - description: SSRUF - bit_offset: 6 - bit_size: 1 -fieldset/SSR: - description: RTC sub second register - fields: - - name: SS - description: SS - bit_offset: 0 - bit_size: 32 -fieldset/TR: - description: time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/TSDR: - description: time stamp date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 -fieldset/TSSSR: - description: timestamp sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 32 -fieldset/TSTR: - description: time stamp time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/WPR: - description: write protection register - fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 -fieldset/WUTR: - description: wakeup timer register - fields: - - name: WUT - description: "Wakeup auto-reload value bits" - bit_offset: 0 - bit_size: 16 - - name: WUTOCLR - description: WUTOCLR - bit_offset: 16 - bit_size: 16 diff --git a/data/registers/rtc_v2-wb.yaml b/data/registers/rtc_v2-wb.yaml index 2afb3ed..2ba866b 100644 --- a/data/registers/rtc_v2-wb.yaml +++ b/data/registers/rtc_v2-wb.yaml @@ -3,169 +3,94 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: CR - description: control register + description: Control register byte_offset: 8 fieldset: CR - name: ISR - description: initialization and status register + description: Initialization and status register byte_offset: 12 fieldset: ISR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register - byte_offset: 32 - fieldset: ALRMBR + fieldset: ALRMR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: SSR - description: sub second register + description: Sub second register byte_offset: 40 access: Read fieldset: SSR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: time stamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: timestamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - name: CALR - description: calibration register + description: Calibration register byte_offset: 60 fieldset: CALR - name: TAMPCR - description: tamper configuration register + description: Tamper configuration register byte_offset: 64 fieldset: TAMPCR - - name: ALRMASSR - description: alarm A sub second register + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: OR - description: option register + description: Option register byte_offset: 76 fieldset: OR - - name: BKP0R - description: backup register + - name: BKPR + description: Backup register + array: + len: 20 + stride: 4 byte_offset: 80 - fieldset: BKP0R - - name: BKP1R - description: backup register - byte_offset: 84 - fieldset: BKP1R - - name: BKP2R - description: backup register - byte_offset: 88 - fieldset: BKP2R - - name: BKP3R - description: backup register - byte_offset: 92 - fieldset: BKP3R - - name: BKP4R - description: backup register - byte_offset: 96 - fieldset: BKP4R - - name: BKP5R - description: backup register - byte_offset: 100 - fieldset: BKP5R - - name: BKP6R - description: backup register - byte_offset: 104 - fieldset: BKP6R - - name: BKP7R - description: backup register - byte_offset: 108 - fieldset: BKP7R - - name: BKP8R - description: backup register - byte_offset: 112 - fieldset: BKP8R - - name: BKP9R - description: backup register - byte_offset: 116 - fieldset: BKP9R - - name: BKP10R - description: backup register - byte_offset: 120 - fieldset: BKP10R - - name: BKP11R - description: backup register - byte_offset: 124 - fieldset: BKP11R - - name: BKP12R - description: backup register - byte_offset: 128 - fieldset: BKP12R - - name: BKP13R - description: backup register - byte_offset: 132 - fieldset: BKP13R - - name: BKP14R - description: backup register - byte_offset: 136 - fieldset: BKP14R - - name: BKP15R - description: backup register - byte_offset: 140 - fieldset: BKP15R - - name: BKP16R - description: backup register - byte_offset: 144 - fieldset: BKP16R - - name: BKP17R - description: backup register - byte_offset: 148 - fieldset: BKP17R - - name: BKP18R - description: backup register - byte_offset: 152 - fieldset: BKP18R - - name: BKP19R - description: backup register - byte_offset: 156 - fieldset: BKP19R -fieldset/ALRMAR: - description: alarm A register + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -176,9 +101,10 @@ fieldset/ALRMAR: bit_offset: 4 bit_size: 3 - name: MSK1 - description: Alarm A seconds mask + description: Alarm seconds mask bit_offset: 7 bit_size: 1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -188,9 +114,10 @@ fieldset/ALRMAR: bit_offset: 12 bit_size: 3 - name: MSK2 - description: Alarm A minutes mask + description: Alarm minutes mask bit_offset: 15 bit_size: 1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -203,10 +130,12 @@ fieldset/ALRMAR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: ALRMR_PM - name: MSK3 - description: Alarm A hours mask + description: Alarm hours mask bit_offset: 23 bit_size: 1 + enum: ALRMR_MSK - name: DU description: Date units or day in BCD format bit_offset: 24 @@ -219,12 +148,14 @@ fieldset/ALRMAR: description: Week day selection bit_offset: 30 bit_size: 1 + enum: ALRMR_WDSEL - name: MSK4 - description: Alarm A date mask + description: Alarm date mask bit_offset: 31 bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value @@ -234,218 +165,15 @@ fieldset/ALRMASSR: description: Mask the most-significant bits starting at this bit bit_offset: 24 bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 -fieldset/BKP0R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP10R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP11R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP12R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP13R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP14R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP15R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP16R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP17R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP18R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP19R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP1R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP2R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP3R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP4R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP5R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP6R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP7R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP8R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP9R: - description: backup register +fieldset/BKPR: + description: Backup register fields: - name: BKP description: BKP bit_offset: 0 bit_size: 32 fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus @@ -455,29 +183,35 @@ fieldset/CALR: description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 + enum: CALW16 - name: CALW8 description: Use an 8-second calibration cycle period bit_offset: 14 bit_size: 1 + enum: CALW8 - name: CALP description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 + enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection bit_offset: 0 bit_size: 3 + enum: WUCKSEL - name: TSEDGE - description: Time-stamp event active edge + description: Timestamp event active edge bit_offset: 3 bit_size: 1 + enum: TSEDGE - name: REFCKON description: Reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 + enum: REFCKON - name: BYPSHAD description: Bypass the shadow registers bit_offset: 5 @@ -486,36 +220,35 @@ fieldset/CR: description: Hour format bit_offset: 6 bit_size: 1 - - name: ALRAE - description: Alarm A enable + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - - name: ALRAIE - description: Alarm A interrupt enable + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - name: WUTIE description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - name: TSIE - description: Time-stamp interrupt enable + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - name: ADD1H @@ -534,24 +267,27 @@ fieldset/CR: description: Calibration output selection bit_offset: 19 bit_size: 1 + enum: COSEL - name: POL description: Output polarity bit_offset: 20 bit_size: 1 + enum: POL - name: OSEL description: Output selection bit_offset: 21 bit_size: 2 + enum: OSEL - name: COE description: Calibration output enable bit_offset: 23 bit_size: 1 - name: ITSE - description: timestamp on internal event enable + description: Timestamp on internal event enable bit_offset: 24 bit_size: 1 fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -582,20 +318,21 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ISR: - description: initialization and status register + description: Initialization and status register fields: - - name: ALRAWF - description: Alarm A write flag + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 + enum_read: ALRWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 + enum_read: WUTWFR - name: SHPF description: Shift operation pending bit_offset: 3 @@ -604,60 +341,70 @@ fieldset/ISR: description: Initialization status flag bit_offset: 4 bit_size: 1 + enum_read: INITSR - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 + enum_read: RSFR + enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 + enum_read: INITFR - name: INIT description: Initialization mode bit_offset: 7 bit_size: 1 - - name: ALRAF - description: Alarm A flag + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW - name: WUTF description: Wakeup timer flag bit_offset: 10 bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW - name: TSF - description: Time-stamp flag + description: Timestamp flag bit_offset: 11 bit_size: 1 + enum_read: TSFR + enum_write: TSFW - name: TSOVF - description: Time-stamp overflow flag + description: Timestamp overflow flag bit_offset: 12 bit_size: 1 - - name: TAMP1F + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF description: Tamper detection flag + array: + len: 3 + stride: 1 bit_offset: 13 bit_size: 1 - - name: TAMP2F - description: RTC_TAMP2 detection flag - bit_offset: 14 - bit_size: 1 - - name: TAMP3F - description: RTC_TAMP3 detection flag - bit_offset: 15 - bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW - name: RECALPF - description: Recalibration pending Flag + description: Recalibration pending flag bit_offset: 16 bit_size: 1 + enum_read: RECALPFR - name: ITSF - description: INTERNAL TIME-STAMP FLAG + description: Internal time-stamp flag bit_offset: 17 bit_size: 1 fieldset/OR: - description: option register + description: Option register fields: - name: RTC_ALARM_TYPE description: RTC_ALARM on PC13 output type @@ -668,7 +415,7 @@ fieldset/OR: bit_offset: 1 bit_size: 1 fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S description: Synchronous prescaler factor @@ -679,7 +426,7 @@ fieldset/PRER: bit_offset: 16 bit_size: 7 fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS description: Subtract a fraction of a second @@ -690,14 +437,14 @@ fieldset/SHIFTR: bit_offset: 31 bit_size: 1 fieldset/SSR: - description: sub second register + description: Sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TAMPCR: - description: tamper configuration register + description: Tamper configuration register fields: - name: TAMP1E description: Tamper 1 detection enable @@ -707,6 +454,7 @@ fieldset/TAMPCR: description: Active level for tamper 1 bit_offset: 1 bit_size: 1 + enum: TAMPTRG - name: TAMPIE description: Tamper interrupt enable bit_offset: 2 @@ -719,6 +467,7 @@ fieldset/TAMPCR: description: Active level for tamper 2 bit_offset: 4 bit_size: 1 + enum: TAMPTRG - name: TAMP3E description: Tamper 3 detection enable bit_offset: 5 @@ -727,6 +476,7 @@ fieldset/TAMPCR: description: Active level for tamper 3 bit_offset: 6 bit_size: 1 + enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 @@ -735,18 +485,22 @@ fieldset/TAMPCR: description: Tamper sampling frequency bit_offset: 8 bit_size: 3 + enum: TAMPFREQ - name: TAMPFLT description: Tamper filter count bit_offset: 11 bit_size: 2 + enum: TAMPFLT - name: TAMPPRCH description: Tamper precharge duration bit_offset: 13 bit_size: 2 + enum: TAMPPRCH - name: TAMPPUDIS - description: TAMPER pull-up disable + description: Tamper pull-up disable bit_offset: 15 bit_size: 1 + enum: TAMPPUDIS - name: TAMP1IE description: Tamper 1 interrupt enable bit_offset: 16 @@ -784,7 +538,7 @@ fieldset/TAMPCR: bit_offset: 24 bit_size: 1 fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -814,8 +568,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -838,14 +593,14 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: timestamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 bit_size: 16 fieldset/TSTR: - description: time stamp time register + description: Timestamp time register fields: - name: SU description: Second units in BCD format @@ -875,17 +630,357 @@ fieldset/TSTR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2.yaml b/data/registers/rtc_v2.yaml deleted file mode 100644 index 33f84b6..0000000 --- a/data/registers/rtc_v2.yaml +++ /dev/null @@ -1,1786 +0,0 @@ ---- -block/RTC: - description: Real-time clock - items: - - name: TR - description: time register - byte_offset: 0 - fieldset: TR - - name: DR - description: date register - byte_offset: 4 - fieldset: DR - - name: CR - description: control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMR - description: alarm register - array: - len: 1 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: WPR - description: write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: TSTR - description: timestamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: timestamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: calibration register - byte_offset: 60 - fieldset: CALR - - name: TAMPCR - description: tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAMPCR - - name: ALRMSSR - description: alarm sub second register - array: - len: 1 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR -block/RTC_F0: - description: Real-time clock - extends: RTC_BASE - items: - - name: SSR - description: sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TAMPCR - description: tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR_F0 - - name: BKPR - description: backup register - array: - len: 5 - stride: 4 - byte_offset: 80 - fieldset: BKPR -block/RTC_F2: - description: Real-time clock - extends: RTC_BASE - items: - - name: CALIBR - description: calibration register - byte_offset: 24 - fieldset: CALIBR - - name: ALRMR - description: alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: TAMPCR - description: tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR_F2 - - name: ALRMSSR - description: alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: BKPR - description: backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR -block/RTC_F3: - description: Real-time clock - extends: RTC_BASE - items: - - name: ALRMR - description: alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: SSR - description: sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TAMPCR - description: tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR_F0_F3 - - name: ALRMSSR - description: alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: BKPR - description: backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR -block/RTC_F4: - description: Real-time clock - extends: RTC_BASE - items: - - name: CALIBR - description: calibration register - byte_offset: 24 - fieldset: CALIBR - - name: ALRMR - description: alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: SSR - description: sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TAMPCR - description: tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAFCR_F4 - - name: ALRMSSR - description: alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: BKPR - description: backup register - array: - len: 20 - stride: 4 - byte_offset: 80 - fieldset: BKPR -block/RTC_F7_H7: - description: Real-time clock - extends: RTC_BASE - items: - - name: ALRMR - description: alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: SSR - description: sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TAMPCR - description: tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAMPCR_F7 - - name: ALRMSSR - description: alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: OR - description: option register - byte_offset: 76 - fieldset: OR - - name: BKPR - description: backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR -block/RTC_L0: - description: Real-time clock - extends: RTC_BASE - items: - - name: ALRMR - description: alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: SSR - description: sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TAMPCR - description: tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAMPCR_L0 - - name: ALRMSSR - description: alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: OR - description: option register - byte_offset: 76 - fieldset: OR_L0 - - name: BKPR - description: backup register - array: - len: 5 - stride: 4 - byte_offset: 80 - fieldset: BKPR -block/RTC_L1: - description: Real-time clock - extends: RTC_BASE - items: - - name: CALIBR - description: calibration register - byte_offset: 24 - fieldset: CALIBR - - name: ALRMR - description: alarm register - array: - len: 2 - stride: 4 - byte_offset: 28 - fieldset: ALRMR - - name: SSR - description: sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TAMPCR - description: tamper and alternate function configuration register - byte_offset: 64 - fieldset: TAMPCR_L0 - - name: ALRMSSR - description: alarm sub second register - array: - len: 2 - stride: 4 - byte_offset: 68 - fieldset: ALRMSSR - - name: BKPR - description: backup register - array: - len: 32 - stride: 4 - byte_offset: 80 - fieldset: BKPR -fieldset/ALRMR: - description: alarm register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm seconds mask - bit_offset: 7 - bit_size: 1 - enum: ALRMR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMR_PM - - name: MSK3 - description: Alarm hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMR_WDSEL - - name: MSK4 - description: Alarm date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMSSR: - description: alarm sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 -fieldset/BKPR: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/CALIBR: - description: calibration register - fields: - - name: DC - description: Digital calibration - bit_offset: 0 - bit_size: 5 - - name: DCS - description: Digital calibration sign - bit_offset: 7 - bit_size: 1 -fieldset/CALR: - description: calibration register - fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - - name: CALW8 - description: Use a 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 - enum: CALP -fieldset/CR: - description: control register - fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - enum: WUCKSEL - - name: TSEDGE - description: Time-stamp event active edge - bit_offset: 3 - bit_size: 1 - enum: TSEDGE - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - enum: REFCKON - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - enum: FMT - - name: ALRE - description: Alarm enable - array: - len: 1 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum: ALRE - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - enum: WUTE - - name: TSE - description: Timestamp enable - bit_offset: 11 - bit_size: 1 - enum: TSE - - name: ALRIE - description: Alarm interrupt enable - array: - len: 1 - stride: 1 - bit_offset: 12 - bit_size: 1 - enum: ALRIE - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - enum: WUTIE - - name: TSIE - description: Time-stamp interrupt enable - bit_offset: 15 - bit_size: 1 - enum: TSIE - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - enum_write: ADDHW - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - enum_write: SUBHW - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - enum: BKP - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - enum: POL - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - enum: OSEL - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - enum: COE -fieldset/CR_F0: - extemds: CR - description: control register - fields: - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - enum: BYPSHAD - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL -fieldset/CR_F2: - extemds: CR - description: control register - fields: - - name: DCE - description: Coarse digital calibration enable - bit_offset: 7 - bit_size: 1 - - name: ALRE - description: Alarm enable - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum: ALRE - - name: ALRIE - description: Alarm interrupt enable - array: - len: 2 - stride: 1 - bit_offset: 12 - bit_size: 1 - enum: ALRIE -fieldset/CR_F3: - extemds: CR - description: control register - fields: - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - enum: BYPSHAD - - name: ALRE - description: Alarm enable - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum: ALRE - - name: ALRIE - description: Alarm interrupt enable - array: - len: 2 - stride: 1 - bit_offset: 12 - bit_size: 1 - enum: ALRIE - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL -fieldset/CR_F4: - extemds: CR - description: control register - fields: - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - enum: BYPSHAD - - name: DCE - description: Coarse digital calibration enable - bit_offset: 7 - bit_size: 1 - - name: ALRE - description: Alarm enable - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum: ALRE - - name: ALRIE - description: Alarm interrupt enable - array: - len: 2 - stride: 1 - bit_offset: 12 - bit_size: 1 - enum: ALRIE - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL -fieldset/CR_F7_H7: - extemds: CR - description: control register - fields: - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - enum: BYPSHAD - - name: ALRE - description: Alarm enable - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum: ALRE - - name: ALRIE - description: Alarm interrupt enable - array: - len: 2 - stride: 1 - bit_offset: 12 - bit_size: 1 - enum: ALRIE - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL - - name: ITSE - description: timestamp on internal event enable - bit_offset: 24 - bit_size: 1 -fieldset/CR_L0: - extemds: CR - description: control register - fields: - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - enum: BYPSHAD - - name: ALRE - description: Alarm enable - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum: ALRE - - name: ALRIE - description: Alarm interrupt enable - array: - len: 2 - stride: 1 - bit_offset: 12 - bit_size: 1 - enum: ALRIE - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - enum: COSEL -fieldset/CR_L1: - extemds: CR - description: control register - fields: - - name: DCE - description: Coarse digital calibration enable - bit_offset: 7 - bit_size: 1 -fieldset/DR: - description: date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 -fieldset/ISR: - description: initialization and status register - fields: - - name: ALRWF - description: Alarm write flag - array: - len: 1 - stride: 1 - bit_offset: 0 - bit_size: 1 - enum_read: ALRWFR - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - enum_read: WUTWFR - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - enum_read: INITSR - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - enum_read: RSFR - enum_write: RSFW - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - enum_read: INITFR - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - enum: INIT - - name: ALRF - description: Alarm flag - array: - len: 1 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum_read: ALRFR - enum_write: ALRFW - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - - name: TSF - description: Time-stamp flag - bit_offset: 11 - bit_size: 1 - enum_read: TSFR - enum_write: TSFW - - name: TSOVF - description: Time-stamp overflow flag - bit_offset: 12 - bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - - name: TAMPF - description: Tamper detection flag - array: - len: 1 - stride: 1 - bit_offset: 13 - bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW -fieldset/ISR_F0: - extedns: ISR - description: initialization and status register - fields: - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - enum_read: SHPFR - - name: TAMPF - description: Tamper detection flag - array: - len: 3 - stride: 1 - bit_offset: 13 - bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - enum_read: RECALPFR -fieldset/ISR_F2: - extedns: ISR - description: initialization and status register - fields: - - name: ALRWF - description: Alarm write flag - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - enum_read: ALRWFR - - name: ALRF - description: Alarm flag - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum_read: ALRFR - enum_write: ALRFW -fieldset/ISR_F3: - extedns: ISR - description: initialization and status register - fields: - - name: ALRWF - description: Alarm write flag - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - enum_read: ALRWFR - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - enum_read: SHPFR - - name: ALRF - description: Alarm flag - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum_read: ALRFR - enum_write: ALRFW - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - enum_read: RECALPFR -fieldset/ISR_F4: - extedns: ISR - description: initialization and status register - fields: - - name: ALRWF - description: Alarm write flag - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - enum_read: ALRWFR - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - enum_read: SHPFR - - name: ALRF - description: Alarm flag - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum_read: ALRFR - enum_write: ALRFW - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - enum_read: RECALPFR -fieldset/ISR_F7_H7: - extedns: ISR - description: initialization and status register - fields: - - name: ALRWF - description: Alarm write flag - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - enum_read: ALRWFR - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - enum_read: SHPFR - - name: ALRF - description: Alarm flag - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum_read: ALRFR - enum_write: ALRFW - - name: TAMPF - description: Tamper detection flag - array: - len: 3 - stride: 1 - bit_offset: 13 - bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - enum_read: RECALPFR - - name: ITSF - description: Internal timestamp flag - bit_offset: 17 - bit_size: 1 -fieldset/ISR_L0: - extedns: ISR - description: initialization and status register - fields: - - name: ALRWF - description: Alarm write flag - array: - len: 2 - stride: 1 - bit_offset: 0 - bit_size: 1 - enum_read: ALRWFR - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - enum_read: SHPFR - - name: ALRF - description: Alarm flag - array: - len: 2 - stride: 1 - bit_offset: 8 - bit_size: 1 - enum_read: ALRFR - enum_write: ALRFW - - name: TAMPF - description: Tamper detection flag - array: - len: 3 - stride: 1 - bit_offset: 13 - bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - enum_read: RECALPFR -fieldset/OR_F7: - description: option register - fields: - - name: TSINSEL - description: TIMESTAMP mapping - bit_offset: 1 - bit_size: 2 - - name: RTC_ALARM_TYPE - description: RTC_ALARM on PC13 output type - bit_offset: 3 - bit_size: 1 -fieldset/OR_H7_L0: - description: option register - fields: - - name: RTC_ALARM_TYPE - description: RTC_ALARM on PC13 output type - bit_offset: 0 - bit_size: 1 - - name: RTC_OUT_RMP - description: RTC_OUT remap - bit_offset: 1 - bit_size: 1 -fieldset/PRER: - description: prescaler register - fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 -fieldset/PRER_F2: - extends: PRER - description: prescaler register - fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 13 -fieldset/SHIFTR: - description: shift control register - fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 - enum_write: ADDSW -fieldset/SSR: - description: sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 -fieldset/TAMPCR: - description: tamper configuration register - fields: - - name: TAMP1E - description: Tamper 1 detection enable - bit_offset: 0 - bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 - bit_offset: 1 - bit_size: 1 - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 -fieldset/TAMPCR_2: - extends: TAMPCR - description: tamper configuration register - fields: - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - - name: TAMPPUDIS - description: Tamper pull-up disable - bit_offset: 15 - bit_size: 1 -fieldset/TAMPCR_3: - extends: TAMPCR_2 - description: tamper configuration register - fields: - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 -fieldset/TAFCR_F0_F3: - extedns: TAMPCR_3 - description: tamper and alternate function configuration register - fields: - - name: PC13VALUE - description: "RTC_ALARM output type/PC13 value" - bit_offset: 18 - bit_size: 1 - enum: PCVALUE - - name: PC13MODE - description: PC13 mode - bit_offset: 19 - bit_size: 1 - enum: PCMODE - - name: PC14VALUE - description: PC14 value - bit_offset: 20 - bit_size: 1 - enum: PCVALUE - - name: PC14MODE - description: PC14 mode - bit_offset: 21 - bit_size: 1 - enum: PCMODE - - name: PC15VALUE - description: PC15 value - bit_offset: 22 - bit_size: 1 - enum: PCVALUE - - name: PC15MODE - description: PC15 mode - bit_offset: 23 - bit_size: 1 - enum: PCMODE -fieldset/TAFCR_F2: - extedns: TAMPCR - description: tamper and alternate function configuration register - fields: - - name: TAMP1INSEL - description: TAMPER1 mapping - bit_offset: 16 - bit_size: 1 - - name: TSINSEL - description: TIMESTAMP mapping - bit_offset: 17 - bit_size: 1 - - name: ALARMOUTTYPE - description: AFO_ALARM output type - bit_offset: 18 - bit_size: 1 -fieldset/TAFCR_F4: - extedns: TAMPCR - description: tamper and alternate function configuration register - fields: - - name: TAMP1INSEL - description: TAMPER1 mapping - bit_offset: 16 - bit_size: 1 - - name: TSINSEL - description: TIMESTAMP mapping - bit_offset: 17 - bit_size: 1 - - name: ALARMOUTTYPE - description: AFO_ALARM output type - bit_offset: 18 - bit_size: 1 -fieldset/TAMPCR_F7_H7_L0: - extedns: TAMPCR_3 - description: tamper configuration register - fields: - - name: TAMP1IE - description: Tamper 1 interrupt enable - bit_offset: 16 - bit_size: 1 - - name: TAMP1NOERASE - description: Tamper 1 no erase - bit_offset: 17 - bit_size: 1 - - name: TAMP1MF - description: Tamper 1 mask flag - bit_offset: 18 - bit_size: 1 - - name: TAMP2IE - description: Tamper 2 interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TAMP2NOERASE - description: Tamper 2 no erase - bit_offset: 20 - bit_size: 1 - - name: TAMP2MF - description: Tamper 2 mask flag - bit_offset: 21 - bit_size: 1 - - name: TAMP3IE - description: Tamper 3 interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TAMP3NOERASE - description: Tamper 3 no erase - bit_offset: 23 - bit_size: 1 - - name: TAMP3MF - description: Tamper 3 mask flag - bit_offset: 24 - bit_size: 1 -fieldset/TR: - description: time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: TR_PM -fieldset/TSDR: - description: timestamp date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 -fieldset/TSSSR: - description: timestamp sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 -fieldset/TSTR: - description: timestamp time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/WPR: - description: write protection register - fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 -fieldset/WUTR: - description: wakeup timer register - fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 -enum/ADDHW: - bit_size: 1 - variants: - - name: Add1 - description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - value: 1 -enum/ADDSW: - bit_size: 1 - variants: - - name: Add1 - description: Add one second to the clock/calendar - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A disabled - value: 0 - - name: Enabled - description: Alarm A enabled - value: 1 -enum/ALRAFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) - value: 1 -enum/ALRAFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRAIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A interrupt disabled - value: 0 - - name: Enabled - description: Alarm A interrupt enabled - value: 1 -enum/ALRAWFR: - bit_size: 1 - variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B disabled - value: 0 - - name: Enabled - description: Alarm B enabled - value: 1 -enum/ALRBFR: - bit_size: 1 - variants: - - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) - value: 1 -enum/ALRBFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRBIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B Interrupt disabled - value: 0 - - name: Enabled - description: Alarm B Interrupt enabled - value: 1 -enum/ALRMAR_MSK: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMAR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMAR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/ALRMBR_MSK: - bit_size: 1 - variants: - - name: Mask - description: Alarm set if the date/day match - value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison - value: 1 -enum/ALRMBR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 - variants: - - name: DateUnits - description: "DU[3:0] represents the date units" - value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: DST_Not_Changed - description: Daylight Saving Time change has not been performed - value: 0 - - name: DST_Changed - description: Daylight Saving Time change has been performed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - name: ShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" - value: 0 - - name: BypassShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" - value: 1 -enum/CALP: - bit_size: 1 - variants: - - name: NoChange - description: No RTCCLK pulses are added - value: 0 - - name: IncreaseFreq - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) - value: 1 -enum/CALW16: - bit_size: 1 - variants: - - name: Sixteen_Second - description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" - value: 1 -enum/CALW8: - bit_size: 1 - variants: - - name: Eight_Second - description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" - value: 1 -enum/COE: - bit_size: 1 - variants: - - name: Disabled - description: Calibration output disabled - value: 0 - - name: Enabled - description: Calibration output enabled - value: 1 -enum/COSEL: - bit_size: 1 - variants: - - name: CalFreq_512Hz - description: Calibration output is 512 Hz (with default prescaler setting) - value: 0 - - name: CalFreq_1Hz - description: Calibration output is 1 Hz (with default prescaler setting) - value: 1 -enum/FMT: - bit_size: 1 - variants: - - name: Twenty_Four_Hour - description: 24 hour/day format - value: 0 - - name: AM_PM - description: AM/PM hour format - value: 1 -enum/INIT: - bit_size: 1 - variants: - - name: FreeRunningMode - description: Free running mode - value: 0 - - name: InitMode - description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." - value: 1 -enum/INITFR: - bit_size: 1 - variants: - - name: NotAllowed - description: Calendar registers update is not allowed - value: 0 - - name: Allowed - description: Calendar registers update is allowed - value: 1 -enum/INITSR: - bit_size: 1 - variants: - - name: NotInitalized - description: Calendar has not been initialized - value: 0 - - name: Initalized - description: Calendar has been initialized - value: 1 -enum/OSEL: - bit_size: 2 - variants: - - name: Disabled - description: Output disabled - value: 0 - - name: AlarmA - description: Alarm A output enabled - value: 1 - - name: AlarmB - description: Alarm B output enabled - value: 2 - - name: Wakeup - description: Wakeup output enabled - value: 3 -enum/PCMODE: - bit_size: 1 - variants: - - name: Floating - description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode - value: 0 - - name: PushPull - description: PCx is forced to push-pull output if LSE is disabled - value: 1 -enum/PCVALUE: - bit_size: 1 - variants: - - name: Low - description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low" - value: 0 - - name: High - description: "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high" - value: 1 -enum/POL: - bit_size: 1 - variants: - - name: High - description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 0 - - name: Low - description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" - value: 1 -enum/RECALPFR: - bit_size: 1 - variants: - - name: Pending - description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" - value: 1 -enum/REFCKON: - bit_size: 1 - variants: - - name: Disabled - description: RTC_REFIN detection disabled - value: 0 - - name: Enabled - description: RTC_REFIN detection enabled - value: 1 -enum/RSFR: - bit_size: 1 - variants: - - name: NotSynced - description: Calendar shadow registers not yet synchronized - value: 0 - - name: Synced - description: Calendar shadow registers synchronized - value: 1 -enum/RSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/SHPFR: - bit_size: 1 - variants: - - name: NoShiftPending - description: No shift operation is pending - value: 0 - - name: ShiftPending - description: A shift operation is pending - value: 1 -enum/SUBHW: - bit_size: 1 - variants: - - name: Sub1 - description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode - value: 1 -enum/TAMPFR: - bit_size: 1 - variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 - value: 0 -enum/TR_PM: - bit_size: 1 - variants: - - name: AM - description: AM or 24-hour format - value: 0 - - name: PM - description: PM - value: 1 -enum/TSE: - bit_size: 1 - variants: - - name: Disabled - description: Timestamp disabled - value: 0 - - name: Enabled - description: Timestamp enabled - value: 1 -enum/TSEDGE: - bit_size: 1 - variants: - - name: RisingEdge - description: RTC_TS input rising edge generates a time-stamp event - value: 0 - - name: FallingEdge - description: RTC_TS input falling edge generates a time-stamp event - value: 1 -enum/TSFR: - bit_size: 1 - variants: - - name: TimestampEvent - description: This flag is set by hardware when a time-stamp event occurs - value: 1 -enum/TSFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSIE: - bit_size: 1 - variants: - - name: Disabled - description: Time-stamp Interrupt disabled - value: 0 - - name: Enabled - description: Time-stamp Interrupt enabled - value: 1 -enum/TSOVFR: - bit_size: 1 - variants: - - name: Overflow - description: This flag is set by hardware when a time-stamp event occurs while TSF is already set - value: 1 -enum/TSOVFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUCKSEL: - bit_size: 3 - variants: - - name: Div16 - description: RTC/16 clock is selected - value: 0 - - name: Div8 - description: RTC/8 clock is selected - value: 1 - - name: Div4 - description: RTC/4 clock is selected - value: 2 - - name: Div2 - description: RTC/2 clock is selected - value: 3 - - name: ClockSpare - description: ck_spre (usually 1 Hz) clock is selected - value: 4 - - name: ClockSpareWithOffset - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value - value: 6 -enum/WUTE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer disabled - value: 0 - - name: Enabled - description: Wakeup timer enabled - value: 1 -enum/WUTFR: - bit_size: 1 - variants: - - name: Zero - description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 - value: 1 -enum/WUTFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTIE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer interrupt disabled - value: 0 - - name: Enabled - description: Wakeup timer interrupt enabled - value: 1 -enum/WUTWFR: - bit_size: 1 - variants: - - name: UpdateNotAllowed - description: Wakeup timer configuration update not allowed - value: 0 - - name: UpdateAllowed - description: Wakeup timer configuration update allowed - value: 1 diff --git a/data/registers/rtc_v3-u5.yaml b/data/registers/rtc_v3-u5.yaml new file mode 100644 index 0000000..35f40c4 --- /dev/null +++ b/data/registers/rtc_v3-u5.yaml @@ -0,0 +1,1153 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: Sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: Initialization control and status register + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: Control register + byte_offset: 24 + fieldset: CR + - name: PRIVCR + description: Privilege mode control register + byte_offset: 28 + fieldset: PRIVCR + - name: SECCFGR + description: Secure mode control register + byte_offset: 32 + fieldset: SECCFGR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: Calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 8 + byte_offset: 64 + fieldset: ALRMR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 8 + byte_offset: 68 + fieldset: ALRMSSR + - name: SR + description: Status register + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: Masked interrupt status register + byte_offset: 84 + access: Read + fieldset: MISR + - name: SMISR + description: Secure masked interrupt status register + byte_offset: 88 + access: Read + fieldset: SMISR + - name: SCR + description: Status clear register + byte_offset: 92 + access: Write + fieldset: SCR + - name: ALRBINR + description: Alarm binary mode register + array: + len: 2 + stride: 4 + byte_offset: 112 + fieldset: ALRBINR +fieldset/ALRBINR: + description: RTC alarm A binary mode register + fields: + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 6 + - name: SSCLR + description: Clear synchronous counter on alarm (Binary mode only) + bit_offset: 31 + bit_size: 1 + enum: ALRMSSR_SSCLR +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: LPCAL + description: Calibration low-power mode + bit_offset: 12 + bit_size: 1 + enum: LPCAL + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: RTC_REFIN reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: SSRUIE + description: SSR underflow interrupt enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: Tamper detection output enable on TAMPALRM + bit_offset: 26 + bit_size: 1 + - name: ALRFCLR + description: ALRFCLR + array: + len: 2 + stride: 1 + bit_offset: 27 + bit_size: 1 + - name: TAMPALRM_PU + description: TAMPALRM pull-up enable + bit_offset: 29 + bit_size: 1 + enum: TAMPALRM_PU + - name: TAMPALRM_TYPE + description: TAMPALRM output type + bit_offset: 30 + bit_size: 1 + enum: TAMPALRM_TYPE + - name: OUT2EN + description: RTC_OUT2 output enable + bit_offset: 31 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ICSR: + description: Initialization control and status register + fields: + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: BIN + description: Binary mode + bit_offset: 8 + bit_size: 2 + enum: BIN + - name: BCDU + description: BCD update + bit_offset: 10 + bit_size: 3 + enum: BCDU + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/MISR: + description: Masked interrupt status register + fields: + - name: ALRMF + description: Alarm masked flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum: ALRMF + - name: WUTMF + description: Wakeup timer masked flag + bit_offset: 2 + bit_size: 1 + enum: WUTMF + - name: TSMF + description: Timestamp masked flag + bit_offset: 3 + bit_size: 1 + enum: TSMF + - name: TSOVMF + description: Timestamp overflow masked flag + bit_offset: 4 + bit_size: 1 + enum: TSOVMF + - name: ITSMF + description: Internal timestamp masked flag + bit_offset: 5 + bit_size: 1 + enum: ITSMF + - name: SSRUMF + description: SSR underflow masked flag + bit_offset: 6 + bit_size: 1 + enum: SSRUMF +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/PRIVCR: + description: Privilege mode control register + fields: + - name: ALRAPRIV + description: ALRAPRIV + bit_offset: 0 + bit_size: 1 + - name: ALRBPRIV + description: ALRBPRIV + bit_offset: 1 + bit_size: 1 + - name: WUTPRIV + description: WUTPRIV + bit_offset: 2 + bit_size: 1 + - name: TSPRIV + description: TSPRIV + bit_offset: 3 + bit_size: 1 + - name: CALPRIV + description: CALPRIV + bit_offset: 13 + bit_size: 1 + - name: INITPRIV + description: INITPRIV + bit_offset: 14 + bit_size: 1 + - name: PRIV + description: PRIV + bit_offset: 15 + bit_size: 1 +fieldset/SCR: + description: Status clear register + fields: + - name: CALRF + description: Clear alarm A flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum: CALRF + - name: CWUTF + description: Clear wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: CALRF + - name: CTSF + description: Clear timestamp flag + bit_offset: 3 + bit_size: 1 + enum: CALRF + - name: CTSOVF + description: Clear timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: CALRF + - name: CITSF + description: Clear internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: CALRF + - name: CSSRUF + description: Clear SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: CALRF +fieldset/SECCFGR: + description: Secure mode control register + fields: + - name: ALRASEC + description: ALRASEC + bit_offset: 0 + bit_size: 1 + - name: ALRBSEC + description: ALRBSEC + bit_offset: 1 + bit_size: 1 + - name: WUTSEC + description: WUTSEC + bit_offset: 2 + bit_size: 1 + - name: TSSEC + description: TSSEC + bit_offset: 3 + bit_size: 1 + - name: CALSEC + description: CALSEC + bit_offset: 13 + bit_size: 1 + - name: INITSEC + description: INITSEC + bit_offset: 14 + bit_size: 1 + - name: SEC + description: SEC + bit_offset: 15 + bit_size: 1 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SMISR: + description: Secure masked interrupt status register + fields: + - name: ALRAMF + description: ALRAMF + bit_offset: 0 + bit_size: 1 + - name: ALRBMF + description: ALRBMF + bit_offset: 1 + bit_size: 1 + - name: WUTMF + description: WUTMF + bit_offset: 2 + bit_size: 1 + - name: TSMF + description: TSMF + bit_offset: 3 + bit_size: 1 + - name: TSOVMF + description: TSOVMF + bit_offset: 4 + bit_size: 1 + - name: ITSMF + description: ITSMF + bit_offset: 5 + bit_size: 1 + - name: SSRUMF + description: SSRUMF + bit_offset: 6 + bit_size: 1 +fieldset/SR: + description: Status register + fields: + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum: ALRF + - name: WUTF + description: Wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: WUTF + - name: TSF + description: Timestamp flag + bit_offset: 3 + bit_size: 1 + enum: TSF + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: TSOVF + - name: ITSF + description: Internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: ITSF + - name: SSRUF + description: SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: SSRUF +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Synchronous binary counter + bit_offset: 0 + bit_size: 32 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 32 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 + enum: KEY +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 + - name: WUTOCLR + description: Wakeup auto-reload output clear value + bit_offset: 16 + bit_size: 16 +enum/ALRF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRMF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMSSR_SSCLR: + bit_size: 1 + variants: + - name: FreeRunning + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" + value: 0 + - name: ALRMBINR + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" + value: 1 +enum/BCDU: + bit_size: 3 + variants: + - name: Bit7 + description: "1s increment each time SS[7:0]=0" + value: 0 + - name: Bit8 + description: "1s increment each time SS[8:0]=0" + value: 1 + - name: Bit9 + description: "1s increment each time SS[9:0]=0" + value: 2 + - name: Bit10 + description: "1s increment each time SS[10:0]=0" + value: 3 + - name: Bit11 + description: "1s increment each time SS[11:0]=0" + value: 4 + - name: Bit12 + description: "1s increment each time SS[12:0]=0" + value: 5 + - name: Bit13 + description: "1s increment each time SS[13:0]=0" + value: 6 + - name: Bit14 + description: "1s increment each time SS[14:0]=0" + value: 7 +enum/BIN: + bit_size: 2 + variants: + - name: BCD + description: Free running BCD calendar mode (Binary mode disabled) + value: 0 + - name: Binary + description: Free running Binary mode (BCD mode disabled) + value: 1 + - name: BinBCD + description: Free running BCD calendar and Binary modes + value: 2 + - name: BinBCD2 + description: Free running BCD calendar and Binary modes + value: 3 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALRF: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag by writing 1 + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: SixteenSeconds + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: EightSeconds + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: TwentyFourHour + description: 24 hour/day format + value: 0 + - name: AmPm + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/ITSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/ITSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/KEY: + bit_size: 8 + variants: + - name: Activate + description: Activate write protection (any value that is not the keys) + value: 0 + - name: Deactivate2 + description: Key 2 + value: 83 + - name: Deactivate1 + description: Key 1 + value: 202 +enum/LPCAL: + bit_size: 1 + variants: + - name: RTCCLK + description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" + value: 0 + - name: CkApre + description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SSRUF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/SSRUIE: + bit_size: 1 + variants: + - name: Disabled + description: SSR underflow interrupt disabled + value: 0 + - name: Enabled + description: SSR underflow interrupt enabled + value: 1 +enum/SSRUMF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/TAMPALRM_PU: + bit_size: 1 + variants: + - name: NoPullUp + description: No pull-up is applied on TAMPALRM output + value: 0 + - name: PullUp + description: A pull-up is applied on TAMPALRM output + value: 1 +enum/TAMPALRM_TYPE: + bit_size: 1 + variants: + - name: PushPull + description: TAMPALRM is push-pull output + value: 0 + - name: OpenDrain + description: TAMPALRM is open-drain output + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSOVF: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVMF: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTF: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTMF: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v3.yaml b/data/registers/rtc_v3.yaml index fec8a49..16e5158 100644 --- a/data/registers/rtc_v3.yaml +++ b/data/registers/rtc_v3.yaml @@ -3,96 +3,108 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - name: SSR - description: sub second register + description: Sub second register byte_offset: 8 access: Read fieldset: SSR - name: ICSR - description: initialization and status register + description: Initialization control and status register byte_offset: 12 fieldset: ICSR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - name: CR - description: control register + description: Control register byte_offset: 24 fieldset: CR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - name: CALR - description: calibration register + description: Calibration register byte_offset: 40 fieldset: CALR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: time stamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: timestamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - - name: ALRMAR - description: alarm A register + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 8 byte_offset: 64 - fieldset: ALRMAR - - name: ALRMASSR - description: alarm A sub second register + fieldset: ALRMR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 8 byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBR - description: alarm B register - byte_offset: 72 - fieldset: ALRMBR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 76 - fieldset: ALRMBSSR + fieldset: ALRMSSR - name: SR - description: status register + description: Status register byte_offset: 80 access: Read fieldset: SR - name: MISR - description: status register + description: Masked interrupt status register byte_offset: 84 access: Read fieldset: MISR - name: SCR - description: status register + description: Status clear register byte_offset: 92 access: Write fieldset: SCR -fieldset/ALRMAR: - description: alarm A register + - name: ALRBINR + description: Alarm binary mode register + array: + len: 2 + stride: 4 + byte_offset: 112 + fieldset: ALRBINR +fieldset/ALRBINR: + description: RTC alarm A binary mode register + fields: + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -106,6 +118,7 @@ fieldset/ALRMAR: description: Alarm A seconds mask bit_offset: 7 bit_size: 1 + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -118,6 +131,7 @@ fieldset/ALRMAR: description: Alarm A minutes mask bit_offset: 15 bit_size: 1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -130,10 +144,12 @@ fieldset/ALRMAR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: ALRMR_PM - name: MSK3 description: Alarm A hours mask bit_offset: 23 bit_size: 1 + enum: ALRMR_MSK - name: DU description: Date units or day in BCD format bit_offset: 24 @@ -146,12 +162,14 @@ fieldset/ALRMAR: description: Week day selection bit_offset: 30 bit_size: 1 + enum: ALRMR_WDSEL - name: MSK4 description: Alarm A date mask bit_offset: 31 bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value @@ -160,111 +178,57 @@ fieldset/ALRMASSR: - name: MASKSS description: Mask the most-significant bits starting at this bit bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm B date mask + bit_size: 6 + - name: SSCLR + description: Clear synchronous counter on alarm (Binary mode only) bit_offset: 31 bit_size: 1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 + enum: ALRMSSR_SSCLR fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus bit_offset: 0 bit_size: 9 + - name: LPCAL + description: Calibration low-power mode + bit_offset: 12 + bit_size: 1 + enum: LPCAL - name: CALW16 description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 + enum: CALW16 - name: CALW8 description: Use an 8-second calibration cycle period bit_offset: 14 bit_size: 1 + enum: CALW8 - name: CALP description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 + enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection bit_offset: 0 bit_size: 3 + enum: WUCKSEL - name: TSEDGE - description: Time-stamp event active edge + description: Timestamp event active edge bit_offset: 3 bit_size: 1 + enum: TSEDGE - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) + description: RTC_REFIN reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 + enum: REFCKON - name: BYPSHAD description: Bypass the shadow registers bit_offset: 5 @@ -273,36 +237,39 @@ fieldset/CR: description: Hour format bit_offset: 6 bit_size: 1 - - name: ALRAE - description: Alarm A enable - bit_offset: 8 + enum: FMT + - name: SSRUIE + description: SSR underflow interrupt enable + bit_offset: 7 bit_size: 1 - - name: ALRBE - description: Alarm B enable - bit_offset: 9 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 bit_size: 1 - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - name: ALRAIE - description: Alarm A interrupt enable + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - name: WUTIE description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - name: TSIE - description: Time-stamp interrupt enable + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - name: ADD1H @@ -321,44 +288,49 @@ fieldset/CR: description: Calibration output selection bit_offset: 19 bit_size: 1 + enum: COSEL - name: POL description: Output polarity bit_offset: 20 bit_size: 1 + enum: POL - name: OSEL description: Output selection bit_offset: 21 bit_size: 2 + enum: OSEL - name: COE description: Calibration output enable bit_offset: 23 bit_size: 1 - name: ITSE - description: timestamp on internal event enable + description: Timestamp on internal event enable bit_offset: 24 bit_size: 1 - name: TAMPTS - description: TAMPTS + description: Activate timestamp on tamper detection event bit_offset: 25 bit_size: 1 - name: TAMPOE - description: TAMPOE + description: Tamper detection output enable on TAMPALRM bit_offset: 26 bit_size: 1 - name: TAMPALRM_PU - description: TAMPALRM_PU + description: TAMPALRM pull-up enable bit_offset: 29 bit_size: 1 + enum: TAMPALRM_PU - name: TAMPALRM_TYPE - description: TAMPALRM_TYPE + description: TAMPALRM output type bit_offset: 30 bit_size: 1 + enum: TAMPALRM_TYPE - name: OUT2EN - description: OUT2EN + description: RTC_OUT2 output enable bit_offset: 31 bit_size: 1 fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -389,20 +361,13 @@ fieldset/DR: bit_offset: 20 bit_size: 4 fieldset/ICSR: - description: initialization and status register + description: Initialization control and status register fields: - - name: ALRAWF - description: Alarm A write flag - bit_offset: 0 - bit_size: 1 - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 - name: WUTWF description: Wakeup timer write flag bit_offset: 2 bit_size: 1 + enum_read: WUTWFR - name: SHPF description: Shift operation pending bit_offset: 3 @@ -411,51 +376,76 @@ fieldset/ICSR: description: Initialization status flag bit_offset: 4 bit_size: 1 + enum_read: INITSR - name: RSF description: Registers synchronization flag bit_offset: 5 bit_size: 1 + enum_read: RSFR + enum_write: RSFW - name: INITF description: Initialization flag bit_offset: 6 bit_size: 1 + enum_read: INITFR - name: INIT description: Initialization mode bit_offset: 7 bit_size: 1 + enum: INIT + - name: BIN + description: Binary mode + bit_offset: 8 + bit_size: 2 + enum: BIN + - name: BCDU + description: BCD update + bit_offset: 10 + bit_size: 3 + enum: BCDU - name: RECALPF description: Recalibration pending Flag bit_offset: 16 bit_size: 1 + enum_read: RECALPFR fieldset/MISR: - description: status register + description: Masked interrupt status register fields: - - name: ALRAMF - description: ALRAMF + - name: ALRMF + description: Alarm masked flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - - name: ALRBMF - description: ALRBMF - bit_offset: 1 - bit_size: 1 + enum: ALRMF - name: WUTMF - description: WUTMF + description: Wakeup timer masked flag bit_offset: 2 bit_size: 1 + enum: WUTMF - name: TSMF - description: TSMF + description: Timestamp masked flag bit_offset: 3 bit_size: 1 + enum: TSMF - name: TSOVMF - description: TSOVMF + description: Timestamp overflow masked flag bit_offset: 4 bit_size: 1 + enum: TSOVMF - name: ITSMF - description: ITSMF + description: Internal timestamp masked flag bit_offset: 5 bit_size: 1 + enum: ITSMF + - name: SSRUMF + description: SSR underflow masked flag + bit_offset: 6 + bit_size: 1 + enum: SSRUMF fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S description: Synchronous prescaler factor @@ -466,34 +456,43 @@ fieldset/PRER: bit_offset: 16 bit_size: 7 fieldset/SCR: - description: status register + description: Status clear register fields: - - name: CALRAF - description: CALRAF + - name: CALRF + description: Clear alarm A flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - - name: CALRBF - description: CALRBF - bit_offset: 1 - bit_size: 1 + enum: CALRF - name: CWUTF - description: CWUTF + description: Clear wakeup timer flag bit_offset: 2 bit_size: 1 + enum: CALRF - name: CTSF - description: CTSF + description: Clear timestamp flag bit_offset: 3 bit_size: 1 + enum: CALRF - name: CTSOVF - description: CTSOVF + description: Clear timestamp overflow flag bit_offset: 4 bit_size: 1 + enum: CALRF - name: CITSF - description: CITSF + description: Clear internal timestamp flag bit_offset: 5 bit_size: 1 + enum: CALRF + - name: CSSRUF + description: Clear SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: CALRF fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS description: Subtract a fraction of a second @@ -504,41 +503,50 @@ fieldset/SHIFTR: bit_offset: 31 bit_size: 1 fieldset/SR: - description: status register + description: Status register fields: - - name: ALRAF - description: ALRAF + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 bit_offset: 0 bit_size: 1 - - name: ALRBF - description: ALRBF - bit_offset: 1 - bit_size: 1 + enum: ALRF - name: WUTF - description: WUTF + description: Wakeup timer flag bit_offset: 2 bit_size: 1 + enum: WUTF - name: TSF - description: TSF + description: Timestamp flag bit_offset: 3 bit_size: 1 + enum: TSF - name: TSOVF - description: TSOVF + description: Timestamp overflow flag bit_offset: 4 bit_size: 1 + enum: TSOVF - name: ITSF - description: ITSF + description: Internal timestamp flag bit_offset: 5 bit_size: 1 + enum: ITSF + - name: SSRUF + description: SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: SSRUF fieldset/SSR: - description: sub second register + description: Sub second register fields: - name: SS - description: Sub second value + description: Synchronous binary counter bit_offset: 0 - bit_size: 16 + bit_size: 32 fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -568,8 +576,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -592,14 +601,14 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: timestamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 - bit_size: 16 + bit_size: 32 fieldset/TSTR: - description: time stamp time register + description: Timestamp time register fields: - name: SU description: Second units in BCD format @@ -630,16 +639,402 @@ fieldset/TSTR: bit_offset: 22 bit_size: 1 fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 + enum: KEY fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 + - name: WUTOCLR + description: Wakeup auto-reload output clear value + bit_offset: 16 + bit_size: 16 +enum/ALRF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRMF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMSSR_SSCLR: + bit_size: 1 + variants: + - name: FreeRunning + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" + value: 0 + - name: ALRMBINR + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" + value: 1 +enum/BCDU: + bit_size: 3 + variants: + - name: Bit7 + description: "1s increment each time SS[7:0]=0" + value: 0 + - name: Bit8 + description: "1s increment each time SS[8:0]=0" + value: 1 + - name: Bit9 + description: "1s increment each time SS[9:0]=0" + value: 2 + - name: Bit10 + description: "1s increment each time SS[10:0]=0" + value: 3 + - name: Bit11 + description: "1s increment each time SS[11:0]=0" + value: 4 + - name: Bit12 + description: "1s increment each time SS[12:0]=0" + value: 5 + - name: Bit13 + description: "1s increment each time SS[13:0]=0" + value: 6 + - name: Bit14 + description: "1s increment each time SS[14:0]=0" + value: 7 +enum/BIN: + bit_size: 2 + variants: + - name: BCD + description: Free running BCD calendar mode (Binary mode disabled) + value: 0 + - name: Binary + description: Free running Binary mode (BCD mode disabled) + value: 1 + - name: BinBCD + description: Free running BCD calendar and Binary modes + value: 2 + - name: BinBCD2 + description: Free running BCD calendar and Binary modes + value: 3 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALRF: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag by writing 1 + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: SixteenSeconds + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: EightSeconds + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: TwentyFourHour + description: 24 hour/day format + value: 0 + - name: AmPm + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/ITSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/ITSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/KEY: + bit_size: 8 + variants: + - name: Activate + description: Activate write protection (any value that is not the keys) + value: 0 + - name: Deactivate2 + description: Key 2 + value: 83 + - name: Deactivate1 + description: Key 1 + value: 202 +enum/LPCAL: + bit_size: 1 + variants: + - name: RTCCLK + description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" + value: 0 + - name: CkApre + description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SSRUF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/SSRUIE: + bit_size: 1 + variants: + - name: Disabled + description: SSR underflow interrupt disabled + value: 0 + - name: Enabled + description: SSR underflow interrupt enabled + value: 1 +enum/SSRUMF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/TAMPALRM_PU: + bit_size: 1 + variants: + - name: NoPullUp + description: No pull-up is applied on TAMPALRM output + value: 0 + - name: PullUp + description: A pull-up is applied on TAMPALRM output + value: 1 +enum/TAMPALRM_TYPE: + bit_size: 1 + variants: + - name: PushPull + description: TAMPALRM is push-pull output + value: 0 + - name: OpenDrain + description: TAMPALRM is open-drain output + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSOVF: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVMF: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTF: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTMF: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index c174420..0e23d7c 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -173,8 +173,8 @@ perimap = [ ('STM32L0.*:RTC:rtc2_.*', ('rtc', 'v2-l0', 'RTC')), ('STM32L1.*:RTC:rtc2_.*', ('rtc', 'v2-l1', 'RTC')), ('STM32L4.*:RTC:rtc2_.*', ('rtc', 'v2-l4', 'RTC')), - ('STM32U5.*:RTC:rtc2_.*', ('rtc', 'v2-u5', 'RTC')), ('STM32WB.*:RTC:rtc2_.*', ('rtc', 'v2-wb', 'RTC')), + ('STM32U5.*:RTC:rtc2_.*', ('rtc', 'v3-u5', 'RTC')), # Cube says v2, but it's v3 with security stuff ('.*:RTC:rtc3_v1_0_Cube', ('rtc', 'v3', 'RTC')), ('.*:RTC:rtc3_v1_1_Cube', ('rtc', 'v3', 'RTC')), ('.*:RTC:rtc3_v2_0_Cube', ('rtc', 'v3', 'RTC')), From 6811a0967900689e8821517bffe64373744b472c Mon Sep 17 00:00:00 2001 From: chemicstry Date: Fri, 3 Jun 2022 02:37:49 +0300 Subject: [PATCH 06/11] Fix names --- .../{rtc_v2-f0.yaml => rtc_v2f0.yaml} | 0 .../{rtc_v2-f2.yaml => rtc_v2f2.yaml} | 0 .../{rtc_v2-f3.yaml => rtc_v2f3.yaml} | 0 .../{rtc_v2-f4.yaml => rtc_v2f4.yaml} | 0 .../{rtc_v2-f7.yaml => rtc_v2f7.yaml} | 0 .../{rtc_v2-h7.yaml => rtc_v2h7.yaml} | 0 .../{rtc_v2-l0.yaml => rtc_v2l0.yaml} | 0 .../{rtc_v2-l1.yaml => rtc_v2l1.yaml} | 0 .../{rtc_v2-l4.yaml => rtc_v2l4.yaml} | 0 .../{rtc_v2-wb.yaml => rtc_v2wb.yaml} | 0 .../{rtc_v3-u5.yaml => rtc_v3u5.yaml} | 0 stm32data/__main__.py | 22 +++++++++---------- 12 files changed, 11 insertions(+), 11 deletions(-) rename data/registers/{rtc_v2-f0.yaml => rtc_v2f0.yaml} (100%) rename data/registers/{rtc_v2-f2.yaml => rtc_v2f2.yaml} (100%) rename data/registers/{rtc_v2-f3.yaml => rtc_v2f3.yaml} (100%) rename data/registers/{rtc_v2-f4.yaml => rtc_v2f4.yaml} (100%) rename data/registers/{rtc_v2-f7.yaml => rtc_v2f7.yaml} (100%) rename data/registers/{rtc_v2-h7.yaml => rtc_v2h7.yaml} (100%) rename data/registers/{rtc_v2-l0.yaml => rtc_v2l0.yaml} (100%) rename data/registers/{rtc_v2-l1.yaml => rtc_v2l1.yaml} (100%) rename data/registers/{rtc_v2-l4.yaml => rtc_v2l4.yaml} (100%) rename data/registers/{rtc_v2-wb.yaml => rtc_v2wb.yaml} (100%) rename data/registers/{rtc_v3-u5.yaml => rtc_v3u5.yaml} (100%) diff --git a/data/registers/rtc_v2-f0.yaml b/data/registers/rtc_v2f0.yaml similarity index 100% rename from data/registers/rtc_v2-f0.yaml rename to data/registers/rtc_v2f0.yaml diff --git a/data/registers/rtc_v2-f2.yaml b/data/registers/rtc_v2f2.yaml similarity index 100% rename from data/registers/rtc_v2-f2.yaml rename to data/registers/rtc_v2f2.yaml diff --git a/data/registers/rtc_v2-f3.yaml b/data/registers/rtc_v2f3.yaml similarity index 100% rename from data/registers/rtc_v2-f3.yaml rename to data/registers/rtc_v2f3.yaml diff --git a/data/registers/rtc_v2-f4.yaml b/data/registers/rtc_v2f4.yaml similarity index 100% rename from data/registers/rtc_v2-f4.yaml rename to data/registers/rtc_v2f4.yaml diff --git a/data/registers/rtc_v2-f7.yaml b/data/registers/rtc_v2f7.yaml similarity index 100% rename from data/registers/rtc_v2-f7.yaml rename to data/registers/rtc_v2f7.yaml diff --git a/data/registers/rtc_v2-h7.yaml b/data/registers/rtc_v2h7.yaml similarity index 100% rename from data/registers/rtc_v2-h7.yaml rename to data/registers/rtc_v2h7.yaml diff --git a/data/registers/rtc_v2-l0.yaml b/data/registers/rtc_v2l0.yaml similarity index 100% rename from data/registers/rtc_v2-l0.yaml rename to data/registers/rtc_v2l0.yaml diff --git a/data/registers/rtc_v2-l1.yaml b/data/registers/rtc_v2l1.yaml similarity index 100% rename from data/registers/rtc_v2-l1.yaml rename to data/registers/rtc_v2l1.yaml diff --git a/data/registers/rtc_v2-l4.yaml b/data/registers/rtc_v2l4.yaml similarity index 100% rename from data/registers/rtc_v2-l4.yaml rename to data/registers/rtc_v2l4.yaml diff --git a/data/registers/rtc_v2-wb.yaml b/data/registers/rtc_v2wb.yaml similarity index 100% rename from data/registers/rtc_v2-wb.yaml rename to data/registers/rtc_v2wb.yaml diff --git a/data/registers/rtc_v3-u5.yaml b/data/registers/rtc_v3u5.yaml similarity index 100% rename from data/registers/rtc_v3-u5.yaml rename to data/registers/rtc_v3u5.yaml diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 0e23d7c..4179313 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -164,17 +164,17 @@ perimap = [ ('.*:QUADSPI:quadspi1_v1_0', ('quadspi', 'v1', 'QUADSPI')), ('STM32F1.*:BKP.*', ('bkp', 'v1', 'BKP')), ('.*:RTC:rtc1_v1_1_Cube', ('rtc', 'v1', 'RTC')), - ('STM32F0.*:RTC:rtc2_.*', ('rtc', 'v2-f0', 'RTC')), - ('STM32F2.*:RTC:rtc2_.*', ('rtc', 'v2-f2', 'RTC')), - ('STM32F3.*:RTC:rtc2_.*', ('rtc', 'v2-f3', 'RTC')), - ('STM32F4.*:RTC:rtc2_.*', ('rtc', 'v2-f4', 'RTC')), - ('STM32F7.*:RTC:rtc2_.*', ('rtc', 'v2-f7', 'RTC')), - ('STM32H7.*:RTC:rtc2_.*', ('rtc', 'v2-h7', 'RTC')), - ('STM32L0.*:RTC:rtc2_.*', ('rtc', 'v2-l0', 'RTC')), - ('STM32L1.*:RTC:rtc2_.*', ('rtc', 'v2-l1', 'RTC')), - ('STM32L4.*:RTC:rtc2_.*', ('rtc', 'v2-l4', 'RTC')), - ('STM32WB.*:RTC:rtc2_.*', ('rtc', 'v2-wb', 'RTC')), - ('STM32U5.*:RTC:rtc2_.*', ('rtc', 'v3-u5', 'RTC')), # Cube says v2, but it's v3 with security stuff + ('STM32F0.*:RTC:rtc2_.*', ('rtc', 'v2f0', 'RTC')), + ('STM32F2.*:RTC:rtc2_.*', ('rtc', 'v2f2', 'RTC')), + ('STM32F3.*:RTC:rtc2_.*', ('rtc', 'v2f3', 'RTC')), + ('STM32F4.*:RTC:rtc2_.*', ('rtc', 'v2f4', 'RTC')), + ('STM32F7.*:RTC:rtc2_.*', ('rtc', 'v2f7', 'RTC')), + ('STM32H7.*:RTC:rtc2_.*', ('rtc', 'v2h7', 'RTC')), + ('STM32L0.*:RTC:rtc2_.*', ('rtc', 'v2l0', 'RTC')), + ('STM32L1.*:RTC:rtc2_.*', ('rtc', 'v2l1', 'RTC')), + ('STM32L4.*:RTC:rtc2_.*', ('rtc', 'v2l4', 'RTC')), + ('STM32WB.*:RTC:rtc2_.*', ('rtc', 'v2wb', 'RTC')), + ('STM32U5.*:RTC:rtc2_.*', ('rtc', 'v3u5', 'RTC')), # Cube says v2, but it's v3 with security stuff ('.*:RTC:rtc3_v1_0_Cube', ('rtc', 'v3', 'RTC')), ('.*:RTC:rtc3_v1_1_Cube', ('rtc', 'v3', 'RTC')), ('.*:RTC:rtc3_v2_0_Cube', ('rtc', 'v3', 'RTC')), From 660faf14dd82c98c0c5b1a437c841f04d05036e6 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Fri, 3 Jun 2022 02:50:40 +0300 Subject: [PATCH 07/11] Add missing enums --- data/registers/rtc_v2f0.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/data/registers/rtc_v2f0.yaml b/data/registers/rtc_v2f0.yaml index 3ba9016..a2a81e8 100644 --- a/data/registers/rtc_v2f0.yaml +++ b/data/registers/rtc_v2f0.yaml @@ -742,6 +742,24 @@ enum/OSEL: - name: Wakeup description: Wakeup output enabled value: 3 +enum/PCMODE: + bit_size: 1 + variants: + - name: Floating + description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + value: 0 + - name: PushPull + description: PCx is forced to push-pull output if LSE is disabled + value: 1 +enum/PCVALUE: + bit_size: 1 + variants: + - name: Low + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low + value: 0 + - name: High + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high + value: 1 enum/POL: bit_size: 1 variants: From 419e4aa9fe1409d36da80ef91b51580134ea3b31 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Fri, 3 Jun 2022 03:05:47 +0300 Subject: [PATCH 08/11] Fixup names --- data/registers/rtc_v2f0.yaml | 2 +- data/registers/rtc_v2f3.yaml | 2 +- data/registers/rtc_v2f4.yaml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/data/registers/rtc_v2f0.yaml b/data/registers/rtc_v2f0.yaml index a2a81e8..2c1c780 100644 --- a/data/registers/rtc_v2f0.yaml +++ b/data/registers/rtc_v2f0.yaml @@ -479,7 +479,7 @@ fieldset/TAFCR: bit_size: 1 enum: TAMPPUDIS - name: PC13VALUE - description: RTC_ALARM output type/PC13 value + description: PC13 value bit_offset: 18 bit_size: 1 enum: PCVALUE diff --git a/data/registers/rtc_v2f3.yaml b/data/registers/rtc_v2f3.yaml index 18b73e0..4b773f5 100644 --- a/data/registers/rtc_v2f3.yaml +++ b/data/registers/rtc_v2f3.yaml @@ -485,7 +485,7 @@ fieldset/TAFCR: bit_size: 1 enum: PCVALUE - name: PC14MODE - description: PC 14 mode + description: PC14 mode bit_offset: 21 bit_size: 1 enum: PCMODE diff --git a/data/registers/rtc_v2f4.yaml b/data/registers/rtc_v2f4.yaml index ab623ad..51028be 100644 --- a/data/registers/rtc_v2f4.yaml +++ b/data/registers/rtc_v2f4.yaml @@ -791,7 +791,7 @@ enum/SUB1HW: - name: Sub1 description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode value: 1 -enum/TAMP1FR: +enum/TAMPFR: bit_size: 1 variants: - name: Tampered From 706d803b174c4fc509b778208aec67dc9bee35b6 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Fri, 3 Jun 2022 10:57:09 +0300 Subject: [PATCH 09/11] Cleanup RTCv1 register names --- data/registers/rtc_v1.yaml | 94 +++++++++++++++++++++++--------------- 1 file changed, 57 insertions(+), 37 deletions(-) diff --git a/data/registers/rtc_v1.yaml b/data/registers/rtc_v1.yaml index cdc4f28..50d3fff 100644 --- a/data/registers/rtc_v1.yaml +++ b/data/registers/rtc_v1.yaml @@ -1,148 +1,168 @@ --- block/RTC: - description: Real time clock + description: Real-time clock items: - name: CRH - description: RTC Control Register High + description: Control Register High byte_offset: 0 fieldset: CRH - name: CRL - description: RTC Control Register Low + description: Control Register Low byte_offset: 4 fieldset: CRL - name: PRLH - description: "RTC Prescaler Load Register High" + description: Prescaler Load Register High byte_offset: 8 access: Write fieldset: PRLH - name: PRLL - description: "RTC Prescaler Load Register Low" + description: Prescaler Load Register Low byte_offset: 12 access: Write fieldset: PRLL - name: DIVH - description: "RTC Prescaler Divider Register High" + description: Prescaler Divider Register High byte_offset: 16 access: Read fieldset: DIVH - name: DIVL - description: "RTC Prescaler Divider Register Low" + description: Prescaler Divider Register Low byte_offset: 20 access: Read fieldset: DIVL - name: CNTH - description: RTC Counter Register High + description: Counter Register High byte_offset: 24 fieldset: CNTH - name: CNTL - description: RTC Counter Register Low + description: Counter Register Low byte_offset: 28 fieldset: CNTL - name: ALRH - description: RTC Alarm Register High + description: Alarm Register High byte_offset: 32 access: Write fieldset: ALRH - name: ALRL - description: RTC Alarm Register Low + description: Alarm Register Low byte_offset: 36 access: Write fieldset: ALRL fieldset/ALRH: - description: RTC Alarm Register High + description: Alarm Register High fields: - name: ALRH - description: RTC alarm register high + description: Alarm register high bit_offset: 0 bit_size: 16 fieldset/ALRL: - description: RTC Alarm Register Low + description: Alarm Register Low fields: - name: ALRL - description: RTC alarm register low + description: Alarm register low bit_offset: 0 bit_size: 16 fieldset/CNTH: - description: RTC Counter Register High + description: Counter Register High fields: - name: CNTH - description: RTC counter register high + description: Counter register high bit_offset: 0 bit_size: 16 fieldset/CNTL: - description: RTC Counter Register Low + description: Counter Register Low fields: - name: CNTL - description: RTC counter register Low + description: Counter register low bit_offset: 0 bit_size: 16 fieldset/CRH: - description: RTC Control Register High + description: Control Register High fields: - name: SECIE - description: Second interrupt Enable + description: Second interrupt enable bit_offset: 0 bit_size: 1 - name: ALRIE - description: Alarm interrupt Enable + description: Alarm interrupt enable bit_offset: 1 bit_size: 1 - name: OWIE - description: Overflow interrupt Enable + description: Overflow interrupt enable bit_offset: 2 bit_size: 1 fieldset/CRL: - description: RTC Control Register Low + description: Control Register Low fields: - name: SECF - description: Second Flag + description: Second flag bit_offset: 0 bit_size: 1 - name: ALRF - description: Alarm Flag + description: Alarm flag bit_offset: 1 bit_size: 1 - name: OWF - description: Overflow Flag + description: Overflow flag bit_offset: 2 bit_size: 1 - name: RSF - description: "Registers Synchronized Flag" + description: Registers synchronized flag bit_offset: 3 bit_size: 1 - name: CNF - description: Configuration Flag + description: Configuration flag bit_offset: 4 bit_size: 1 + enum: CNF - name: RTOFF description: RTC operation OFF bit_offset: 5 bit_size: 1 + enum: RTOFF fieldset/DIVH: - description: "RTC Prescaler Divider Register High" + description: Prescaler Divider Register High fields: - name: DIVH - description: "RTC prescaler divider register high" + description: Prescaler divider register high bit_offset: 0 bit_size: 4 fieldset/DIVL: - description: "RTC Prescaler Divider Register Low" + description: Prescaler Divider Register Low fields: - name: DIVL - description: "RTC prescaler divider register Low" + description: Prescaler divider register low bit_offset: 0 bit_size: 16 fieldset/PRLH: - description: "RTC Prescaler Load Register High" + description: Prescaler Load Register High fields: - name: PRLH - description: "RTC Prescaler Load Register High" + description: Prescaler load register high bit_offset: 0 bit_size: 4 fieldset/PRLL: - description: "RTC Prescaler Load Register Low" + description: Prescaler Load Register Low fields: - name: PRLL - description: "RTC Prescaler Divider Register Low" + description: Prescaler divider register low bit_offset: 0 bit_size: 16 +enum/CNF: + bit_size: 1 + variants: + - name: Exit + description: Exit configuration mode (start update of RTC registers) + value: 0 + - name: Enter + description: Enter configuration mode + value: 1 +enum/RTOFF: + bit_size: 1 + variants: + - name: Enabled + description: Last write operation on RTC registers is still ongoing + value: 0 + - name: Disabled + description: Last write operation on RTC registers terminated + value: 1 From 02763581abc65942ba6cff1a59a0edc8bf33fa8b Mon Sep 17 00:00:00 2001 From: chemicstry Date: Fri, 3 Jun 2022 11:04:22 +0300 Subject: [PATCH 10/11] Fix RTC peripheral version names --- stm32data/__main__.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 4179313..896ed9b 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -163,7 +163,7 @@ perimap = [ ('.*:MDIOS:mdios1_v1_0', ('mdios', 'v1', 'MDIOS')), ('.*:QUADSPI:quadspi1_v1_0', ('quadspi', 'v1', 'QUADSPI')), ('STM32F1.*:BKP.*', ('bkp', 'v1', 'BKP')), - ('.*:RTC:rtc1_v1_1_Cube', ('rtc', 'v1', 'RTC')), + ('.*:RTC:rtc1_v1_1', ('rtc', 'v1', 'RTC')), ('STM32F0.*:RTC:rtc2_.*', ('rtc', 'v2f0', 'RTC')), ('STM32F2.*:RTC:rtc2_.*', ('rtc', 'v2f2', 'RTC')), ('STM32F3.*:RTC:rtc2_.*', ('rtc', 'v2f3', 'RTC')), @@ -174,11 +174,11 @@ perimap = [ ('STM32L1.*:RTC:rtc2_.*', ('rtc', 'v2l1', 'RTC')), ('STM32L4.*:RTC:rtc2_.*', ('rtc', 'v2l4', 'RTC')), ('STM32WB.*:RTC:rtc2_.*', ('rtc', 'v2wb', 'RTC')), - ('STM32U5.*:RTC:rtc2_.*', ('rtc', 'v3u5', 'RTC')), # Cube says v2, but it's v3 with security stuff - ('.*:RTC:rtc3_v1_0_Cube', ('rtc', 'v3', 'RTC')), - ('.*:RTC:rtc3_v1_1_Cube', ('rtc', 'v3', 'RTC')), - ('.*:RTC:rtc3_v2_0_Cube', ('rtc', 'v3', 'RTC')), - ('.*:RTC:rtc3_v3_0_Cube', ('rtc', 'v3', 'RTC')), + ('STM32U5.*:RTC:rtc2_.*', ('rtc', 'v3u5', 'RTC')), # Cube says v2, but it's v3 with security stuff + ('.*:RTC:rtc3_v1_0', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v1_1', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v2_0', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v3_0', ('rtc', 'v3', 'RTC')), ('.*:SAI:sai1_v1_1', ('sai', 'v1', 'SAI')), ('.*:SDIO:sdmmc_v1_2', ('sdmmc', 'v1', 'SDMMC')), ('.*:SDMMC:sdmmc_v1_3', ('sdmmc', 'v1', 'SDMMC')), From 95f79fcfd7e60df1272c2744b63004a1a379e3d0 Mon Sep 17 00:00:00 2001 From: chemicstry Date: Sat, 4 Jun 2022 21:00:14 +0300 Subject: [PATCH 11/11] Arrayify more fields --- data/registers/rtc_v2f0.yaml | 36 +++++++--------- data/registers/rtc_v2f2.yaml | 14 +++++-- data/registers/rtc_v2f3.yaml | 25 ++++++----- data/registers/rtc_v2f4.yaml | 25 ++++++----- data/registers/rtc_v2f7.yaml | 81 +++++++++++++----------------------- data/registers/rtc_v2h7.yaml | 81 +++++++++++++----------------------- data/registers/rtc_v2l0.yaml | 81 +++++++++++++----------------------- data/registers/rtc_v2l1.yaml | 36 +++++++--------- data/registers/rtc_v2l4.yaml | 81 +++++++++++++----------------------- data/registers/rtc_v2wb.yaml | 81 +++++++++++++----------------------- 10 files changed, 207 insertions(+), 334 deletions(-) diff --git a/data/registers/rtc_v2f0.yaml b/data/registers/rtc_v2f0.yaml index 2c1c780..6e14f81 100644 --- a/data/registers/rtc_v2f0.yaml +++ b/data/registers/rtc_v2f0.yaml @@ -423,12 +423,22 @@ fieldset/SSR: fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -436,24 +446,6 @@ fieldset/TAFCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 diff --git a/data/registers/rtc_v2f2.yaml b/data/registers/rtc_v2f2.yaml index c3587d7..b959d23 100644 --- a/data/registers/rtc_v2f2.yaml +++ b/data/registers/rtc_v2f2.yaml @@ -346,12 +346,18 @@ fieldset/PRER: fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 bit_offset: 1 bit_size: 1 enum: TAMPTRG diff --git a/data/registers/rtc_v2f3.yaml b/data/registers/rtc_v2f3.yaml index 4b773f5..88f7776 100644 --- a/data/registers/rtc_v2f3.yaml +++ b/data/registers/rtc_v2f3.yaml @@ -423,12 +423,20 @@ fieldset/SSR: fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -436,15 +444,6 @@ fieldset/TAFCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 diff --git a/data/registers/rtc_v2f4.yaml b/data/registers/rtc_v2f4.yaml index 51028be..1663d70 100644 --- a/data/registers/rtc_v2f4.yaml +++ b/data/registers/rtc_v2f4.yaml @@ -442,12 +442,20 @@ fieldset/SSR: fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -455,15 +463,6 @@ fieldset/TAFCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 diff --git a/data/registers/rtc_v2f7.yaml b/data/registers/rtc_v2f7.yaml index ceafc1f..6748450 100644 --- a/data/registers/rtc_v2f7.yaml +++ b/data/registers/rtc_v2f7.yaml @@ -446,12 +446,22 @@ fieldset/SSR: fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -459,24 +469,6 @@ fieldset/TAMPCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 @@ -501,42 +493,27 @@ fieldset/TAMPCR: bit_offset: 15 bit_size: 1 enum: TAMPPUDIS - - name: TAMP1IE - description: Tamper 1 interrupt enable + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 bit_offset: 16 bit_size: 1 - - name: TAMP1NOERASE - description: Tamper 1 no erase + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 bit_offset: 17 bit_size: 1 - - name: TAMP1MF - description: Tamper 1 mask flag + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 bit_offset: 18 bit_size: 1 - - name: TAMP2IE - description: Tamper 2 interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TAMP2NOERASE - description: Tamper 2 no erase - bit_offset: 20 - bit_size: 1 - - name: TAMP2MF - description: Tamper 2 mask flag - bit_offset: 21 - bit_size: 1 - - name: TAMP3IE - description: Tamper 3 interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TAMP3NOERASE - description: Tamper 3 no erase - bit_offset: 23 - bit_size: 1 - - name: TAMP3MF - description: Tamper 3 mask flag - bit_offset: 24 - bit_size: 1 fieldset/TR: description: Time register fields: diff --git a/data/registers/rtc_v2h7.yaml b/data/registers/rtc_v2h7.yaml index ef3273d..7289c39 100644 --- a/data/registers/rtc_v2h7.yaml +++ b/data/registers/rtc_v2h7.yaml @@ -446,12 +446,22 @@ fieldset/SSR: fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -459,24 +469,6 @@ fieldset/TAMPCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 @@ -501,42 +493,27 @@ fieldset/TAMPCR: bit_offset: 15 bit_size: 1 enum: TAMPPUDIS - - name: TAMP1IE - description: Tamper 1 interrupt enable + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 bit_offset: 16 bit_size: 1 - - name: TAMP1NOERASE - description: Tamper 1 no erase + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 bit_offset: 17 bit_size: 1 - - name: TAMP1MF - description: Tamper 1 mask flag + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 bit_offset: 18 bit_size: 1 - - name: TAMP2IE - description: Tamper 2 interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TAMP2NOERASE - description: Tamper 2 no erase - bit_offset: 20 - bit_size: 1 - - name: TAMP2MF - description: Tamper 2 mask flag - bit_offset: 21 - bit_size: 1 - - name: TAMP3IE - description: Tamper 3 interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TAMP3NOERASE - description: Tamper 3 no erase - bit_offset: 23 - bit_size: 1 - - name: TAMP3MF - description: Tamper 3 mask flag - bit_offset: 24 - bit_size: 1 fieldset/TR: description: Time register fields: diff --git a/data/registers/rtc_v2l0.yaml b/data/registers/rtc_v2l0.yaml index 2136f5f..abe81c1 100644 --- a/data/registers/rtc_v2l0.yaml +++ b/data/registers/rtc_v2l0.yaml @@ -438,12 +438,22 @@ fieldset/SSR: fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -451,24 +461,6 @@ fieldset/TAMPCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 @@ -493,42 +485,27 @@ fieldset/TAMPCR: bit_offset: 15 bit_size: 1 enum: TAMPPUDIS - - name: TAMP1IE - description: Tamper 1 interrupt enable + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 bit_offset: 16 bit_size: 1 - - name: TAMP1NOERASE - description: Tamper 1 no erase + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 bit_offset: 17 bit_size: 1 - - name: TAMP1MF - description: Tamper 1 mask flag + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 bit_offset: 18 bit_size: 1 - - name: TAMP2IE - description: Tamper 2 interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TAMP2NOERASE - description: Tamper 2 no erase - bit_offset: 20 - bit_size: 1 - - name: TAMP2MF - description: Tamper 2 mask flag - bit_offset: 21 - bit_size: 1 - - name: TAMP3IE - description: Tamper 3 interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TAMP3NOERASE - description: Tamper 3 no erase - bit_offset: 23 - bit_size: 1 - - name: TAMP3MF - description: Tamper 3 mask flag - bit_offset: 24 - bit_size: 1 fieldset/TR: description: Time register fields: diff --git a/data/registers/rtc_v2l1.yaml b/data/registers/rtc_v2l1.yaml index 72ed04a..6cd766a 100644 --- a/data/registers/rtc_v2l1.yaml +++ b/data/registers/rtc_v2l1.yaml @@ -442,12 +442,22 @@ fieldset/SSR: fieldset/TAFCR: description: Tamper and alternate function configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -455,24 +465,6 @@ fieldset/TAFCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 diff --git a/data/registers/rtc_v2l4.yaml b/data/registers/rtc_v2l4.yaml index b710a2e..cfdd7bc 100644 --- a/data/registers/rtc_v2l4.yaml +++ b/data/registers/rtc_v2l4.yaml @@ -442,12 +442,22 @@ fieldset/SSR: fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -455,24 +465,6 @@ fieldset/TAMPCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 @@ -497,42 +489,27 @@ fieldset/TAMPCR: bit_offset: 15 bit_size: 1 enum: TAMPPUDIS - - name: TAMP1IE - description: Tamper 1 interrupt enable + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 bit_offset: 16 bit_size: 1 - - name: TAMP1NOERASE - description: Tamper 1 no erase + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 bit_offset: 17 bit_size: 1 - - name: TAMP1MF - description: Tamper 1 mask flag + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 bit_offset: 18 bit_size: 1 - - name: TAMP2IE - description: Tamper 2 interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TAMP2NOERASE - description: Tamper 2 no erase - bit_offset: 20 - bit_size: 1 - - name: TAMP2MF - description: Tamper 2 mask flag - bit_offset: 21 - bit_size: 1 - - name: TAMP3IE - description: Tamper 3 interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TAMP3NOERASE - description: Tamper 3 no erase - bit_offset: 23 - bit_size: 1 - - name: TAMP3MF - description: Tamper 3 mask flag - bit_offset: 24 - bit_size: 1 fieldset/TR: description: Time register fields: diff --git a/data/registers/rtc_v2wb.yaml b/data/registers/rtc_v2wb.yaml index 2ba866b..2bd85f8 100644 --- a/data/registers/rtc_v2wb.yaml +++ b/data/registers/rtc_v2wb.yaml @@ -446,12 +446,22 @@ fieldset/SSR: fieldset/TAMPCR: description: Tamper configuration register fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 bit_offset: 1 bit_size: 1 enum: TAMPTRG @@ -459,24 +469,6 @@ fieldset/TAMPCR: description: Tamper interrupt enable bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - enum: TAMPTRG - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 - enum: TAMPTRG - name: TAMPTS description: Activate timestamp on tamper detection event bit_offset: 7 @@ -501,42 +493,27 @@ fieldset/TAMPCR: bit_offset: 15 bit_size: 1 enum: TAMPPUDIS - - name: TAMP1IE - description: Tamper 1 interrupt enable + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 bit_offset: 16 bit_size: 1 - - name: TAMP1NOERASE - description: Tamper 1 no erase + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 bit_offset: 17 bit_size: 1 - - name: TAMP1MF - description: Tamper 1 mask flag + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 bit_offset: 18 bit_size: 1 - - name: TAMP2IE - description: Tamper 2 interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TAMP2NOERASE - description: Tamper 2 no erase - bit_offset: 20 - bit_size: 1 - - name: TAMP2MF - description: Tamper 2 mask flag - bit_offset: 21 - bit_size: 1 - - name: TAMP3IE - description: Tamper 3 interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TAMP3NOERASE - description: Tamper 3 no erase - bit_offset: 23 - bit_size: 1 - - name: TAMP3MF - description: Tamper 3 mask flag - bit_offset: 24 - bit_size: 1 fieldset/TR: description: Time register fields: