diff --git a/data/registers/rtc_v1.yaml b/data/registers/rtc_v1.yaml new file mode 100644 index 0000000..50d3fff --- /dev/null +++ b/data/registers/rtc_v1.yaml @@ -0,0 +1,168 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: CRH + description: Control Register High + byte_offset: 0 + fieldset: CRH + - name: CRL + description: Control Register Low + byte_offset: 4 + fieldset: CRL + - name: PRLH + description: Prescaler Load Register High + byte_offset: 8 + access: Write + fieldset: PRLH + - name: PRLL + description: Prescaler Load Register Low + byte_offset: 12 + access: Write + fieldset: PRLL + - name: DIVH + description: Prescaler Divider Register High + byte_offset: 16 + access: Read + fieldset: DIVH + - name: DIVL + description: Prescaler Divider Register Low + byte_offset: 20 + access: Read + fieldset: DIVL + - name: CNTH + description: Counter Register High + byte_offset: 24 + fieldset: CNTH + - name: CNTL + description: Counter Register Low + byte_offset: 28 + fieldset: CNTL + - name: ALRH + description: Alarm Register High + byte_offset: 32 + access: Write + fieldset: ALRH + - name: ALRL + description: Alarm Register Low + byte_offset: 36 + access: Write + fieldset: ALRL +fieldset/ALRH: + description: Alarm Register High + fields: + - name: ALRH + description: Alarm register high + bit_offset: 0 + bit_size: 16 +fieldset/ALRL: + description: Alarm Register Low + fields: + - name: ALRL + description: Alarm register low + bit_offset: 0 + bit_size: 16 +fieldset/CNTH: + description: Counter Register High + fields: + - name: CNTH + description: Counter register high + bit_offset: 0 + bit_size: 16 +fieldset/CNTL: + description: Counter Register Low + fields: + - name: CNTL + description: Counter register low + bit_offset: 0 + bit_size: 16 +fieldset/CRH: + description: Control Register High + fields: + - name: SECIE + description: Second interrupt enable + bit_offset: 0 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + bit_offset: 1 + bit_size: 1 + - name: OWIE + description: Overflow interrupt enable + bit_offset: 2 + bit_size: 1 +fieldset/CRL: + description: Control Register Low + fields: + - name: SECF + description: Second flag + bit_offset: 0 + bit_size: 1 + - name: ALRF + description: Alarm flag + bit_offset: 1 + bit_size: 1 + - name: OWF + description: Overflow flag + bit_offset: 2 + bit_size: 1 + - name: RSF + description: Registers synchronized flag + bit_offset: 3 + bit_size: 1 + - name: CNF + description: Configuration flag + bit_offset: 4 + bit_size: 1 + enum: CNF + - name: RTOFF + description: RTC operation OFF + bit_offset: 5 + bit_size: 1 + enum: RTOFF +fieldset/DIVH: + description: Prescaler Divider Register High + fields: + - name: DIVH + description: Prescaler divider register high + bit_offset: 0 + bit_size: 4 +fieldset/DIVL: + description: Prescaler Divider Register Low + fields: + - name: DIVL + description: Prescaler divider register low + bit_offset: 0 + bit_size: 16 +fieldset/PRLH: + description: Prescaler Load Register High + fields: + - name: PRLH + description: Prescaler load register high + bit_offset: 0 + bit_size: 4 +fieldset/PRLL: + description: Prescaler Load Register Low + fields: + - name: PRLL + description: Prescaler divider register low + bit_offset: 0 + bit_size: 16 +enum/CNF: + bit_size: 1 + variants: + - name: Exit + description: Exit configuration mode (start update of RTC registers) + value: 0 + - name: Enter + description: Enter configuration mode + value: 1 +enum/RTOFF: + bit_size: 1 + variants: + - name: Enabled + description: Last write operation on RTC registers is still ongoing + value: 0 + - name: Disabled + description: Last write operation on RTC registers terminated + value: 1 diff --git a/data/registers/rtc_v2f0.yaml b/data/registers/rtc_v2f0.yaml new file mode 100644 index 0000000..6e14f81 --- /dev/null +++ b/data/registers/rtc_v2f0.yaml @@ -0,0 +1,964 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 1 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 1 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: Backup register + array: + len: 5 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 1 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 1 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 1 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 1 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAFCR: + description: Tamper and alternate function configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: PC13VALUE + description: PC13 value + bit_offset: 18 + bit_size: 1 + enum: PCVALUE + - name: PC13MODE + description: PC13 mode + bit_offset: 19 + bit_size: 1 + enum: PCMODE + - name: PC14VALUE + description: PC14 value + bit_offset: 20 + bit_size: 1 + enum: PCVALUE + - name: PC14MODE + description: PC14 mode + bit_offset: 21 + bit_size: 1 + enum: PCMODE + - name: PC15VALUE + description: PC15 value + bit_offset: 22 + bit_size: 1 + enum: PCVALUE + - name: PC15MODE + description: PC15 mode + bit_offset: 23 + bit_size: 1 + enum: PCMODE +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/PCMODE: + bit_size: 1 + variants: + - name: Floating + description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + value: 0 + - name: PushPull + description: PCx is forced to push-pull output if LSE is disabled + value: 1 +enum/PCVALUE: + bit_size: 1 + variants: + - name: Low + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low + value: 0 + - name: High + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high + value: 1 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2f2.yaml b/data/registers/rtc_v2f2.yaml new file mode 100644 index 0000000..b959d23 --- /dev/null +++ b/data/registers/rtc_v2f2.yaml @@ -0,0 +1,738 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: Calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: BKPR + description: Backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALIBR: + description: Calibration register + fields: + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 1 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/TAFCR: + description: Tamper and alternate function configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMP1INSEL + description: Tamper 1 mapping + bit_offset: 16 + bit_size: 1 + - name: TSINSEL + description: Timestamp mapping + bit_offset: 17 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2f3.yaml b/data/registers/rtc_v2f3.yaml new file mode 100644 index 0000000..88f7776 --- /dev/null +++ b/data/registers/rtc_v2f3.yaml @@ -0,0 +1,965 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAFCR: + description: Tamper and alternate function configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: PC13VALUE + description: PC13 value + bit_offset: 18 + bit_size: 1 + enum: PCVALUE + - name: PC13MODE + description: PC13 mode + bit_offset: 19 + bit_size: 1 + enum: PCMODE + - name: PC14VALUE + description: PC14 value + bit_offset: 20 + bit_size: 1 + enum: PCVALUE + - name: PC14MODE + description: PC14 mode + bit_offset: 21 + bit_size: 1 + enum: PCMODE + - name: PC15VALUE + description: PC15 value + bit_offset: 22 + bit_size: 1 + enum: PCVALUE + - name: PC15MODE + description: PC15 mode + bit_offset: 23 + bit_size: 1 + enum: PCMODE +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/PCMODE: + bit_size: 1 + variants: + - name: Floating + description: PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode + value: 0 + - name: PushPull + description: PCx is forced to push-pull output if LSE is disabled + value: 1 +enum/PCVALUE: + bit_size: 1 + variants: + - name: Low + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low + value: 0 + - name: High + description: If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high + value: 1 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2f4.yaml b/data/registers/rtc_v2f4.yaml new file mode 100644 index 0000000..1663d70 --- /dev/null +++ b/data/registers/rtc_v2f4.yaml @@ -0,0 +1,963 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: Calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: Backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALIBR: + description: Calibration register + fields: + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAFCR: + description: Tamper and alternate function configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMP1INSEL + description: Tamper 1 mapping + bit_offset: 16 + bit_size: 1 + - name: TSINSEL + description: Timestamp mapping + bit_offset: 17 + bit_size: 1 + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SUB1HW: + bit_size: 1 + variants: + - name: Sub1 + description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + value: 1 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2f7.yaml b/data/registers/rtc_v2f7.yaml new file mode 100644 index 0000000..6748450 --- /dev/null +++ b/data/registers/rtc_v2f7.yaml @@ -0,0 +1,963 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR + - name: ITSF + description: Internal time-stamp flag + bit_offset: 17 + bit_size: 1 +fieldset/OR: + description: Option register + fields: + - name: TSINSEL + description: Timestamp mapping + bit_offset: 1 + bit_size: 2 + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 3 + bit_size: 1 +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: Tamper configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 + bit_offset: 16 + bit_size: 1 + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 + bit_offset: 17 + bit_size: 1 + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2h7.yaml b/data/registers/rtc_v2h7.yaml new file mode 100644 index 0000000..7289c39 --- /dev/null +++ b/data/registers/rtc_v2h7.yaml @@ -0,0 +1,963 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR + - name: ITSF + description: Internal time-stamp flag + bit_offset: 17 + bit_size: 1 +fieldset/OR: + description: Option register + fields: + - name: RTC_ALARM_TYPE + description: RTC_ALARM output type on PC13 + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: Tamper configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 + bit_offset: 16 + bit_size: 1 + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 + bit_offset: 17 + bit_size: 1 + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2l0.yaml b/data/registers/rtc_v2l0.yaml new file mode 100644 index 0000000..abe81c1 --- /dev/null +++ b/data/registers/rtc_v2l0.yaml @@ -0,0 +1,955 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 5 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/OR: + description: Option register + fields: + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_ALARM on PC13 output type + bit_offset: 1 + bit_size: 1 +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: Tamper configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 + bit_offset: 16 + bit_size: 1 + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 + bit_offset: 17 + bit_size: 1 + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2l1.yaml b/data/registers/rtc_v2l1.yaml new file mode 100644 index 0000000..6cd766a --- /dev/null +++ b/data/registers/rtc_v2l1.yaml @@ -0,0 +1,942 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CALIBR + description: Calibration register + byte_offset: 24 + fieldset: CALIBR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAFCR + description: Tamper and alternate function configuration register + byte_offset: 64 + fieldset: TAFCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALIBR: + description: Calibration register + fields: + - name: DC + description: Digital calibration + bit_offset: 0 + bit_size: 5 + - name: DCS + description: Digital calibration sign + bit_offset: 7 + bit_size: 1 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: DCE + description: Coarse digital calibration enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAFCR: + description: Tamper and alternate function configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: ALARMOUTTYPE + description: AFO_ALARM output type + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2l4.yaml b/data/registers/rtc_v2l4.yaml new file mode 100644 index 0000000..cfdd7bc --- /dev/null +++ b/data/registers/rtc_v2l4.yaml @@ -0,0 +1,959 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 32 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/OR: + description: Option register + fields: + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: Tamper configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 + bit_offset: 16 + bit_size: 1 + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 + bit_offset: 17 + bit_size: 1 + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2wb.yaml b/data/registers/rtc_v2wb.yaml new file mode 100644 index 0000000..2bd85f8 --- /dev/null +++ b/data/registers/rtc_v2wb.yaml @@ -0,0 +1,963 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: ISR + description: Initialization and status register + byte_offset: 12 + fieldset: ISR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 4 + byte_offset: 28 + fieldset: ALRMR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: SSR + description: Sub second register + byte_offset: 40 + access: Read + fieldset: SSR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: CALR + description: Calibration register + byte_offset: 60 + fieldset: CALR + - name: TAMPCR + description: Tamper configuration register + byte_offset: 64 + fieldset: TAMPCR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 4 + byte_offset: 68 + fieldset: ALRMSSR + - name: OR + description: Option register + byte_offset: 76 + fieldset: OR + - name: BKPR + description: Backup register + array: + len: 20 + stride: 4 + byte_offset: 80 + fieldset: BKPR +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 4 +fieldset/BKPR: + description: Backup register + fields: + - name: BKP + description: BKP + bit_offset: 0 + bit_size: 32 +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: Reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ISR: + description: Initialization and status register + fields: + - name: ALRWF + description: Alarm write flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum_read: ALRWFR + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + enum_read: ALRFR + enum_write: ALRFW + - name: WUTF + description: Wakeup timer flag + bit_offset: 10 + bit_size: 1 + enum_read: WUTFR + enum_write: WUTFW + - name: TSF + description: Timestamp flag + bit_offset: 11 + bit_size: 1 + enum_read: TSFR + enum_write: TSFW + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 12 + bit_size: 1 + enum_read: TSOVFR + enum_write: TSOVFW + - name: TAMPF + description: Tamper detection flag + array: + len: 3 + stride: 1 + bit_offset: 13 + bit_size: 1 + enum_read: TAMPFR + enum_write: TAMPFW + - name: RECALPF + description: Recalibration pending flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR + - name: ITSF + description: Internal time-stamp flag + bit_offset: 17 + bit_size: 1 +fieldset/OR: + description: Option register + fields: + - name: RTC_ALARM_TYPE + description: RTC_ALARM on PC13 output type + bit_offset: 0 + bit_size: 1 + - name: RTC_OUT_RMP + description: RTC_OUT remap + bit_offset: 1 + bit_size: 1 +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TAMPCR: + description: Tamper configuration register + fields: + - name: TAMPE + description: Tamper detection enable + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 0 + bit_size: 1 + - name: TAMPTRG + description: Active level for tamper + array: + offsets: + - 0 + - 3 + - 5 + bit_offset: 1 + bit_size: 1 + enum: TAMPTRG + - name: TAMPIE + description: Tamper interrupt enable + bit_offset: 2 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 7 + bit_size: 1 + - name: TAMPFREQ + description: Tamper sampling frequency + bit_offset: 8 + bit_size: 3 + enum: TAMPFREQ + - name: TAMPFLT + description: Tamper filter count + bit_offset: 11 + bit_size: 2 + enum: TAMPFLT + - name: TAMPPRCH + description: Tamper precharge duration + bit_offset: 13 + bit_size: 2 + enum: TAMPPRCH + - name: TAMPPUDIS + description: Tamper pull-up disable + bit_offset: 15 + bit_size: 1 + enum: TAMPPUDIS + - name: TAMPXIE + description: Tamper interrupt enable + array: + len: 3 + stride: 3 + bit_offset: 16 + bit_size: 1 + - name: TAMPXNOERASE + description: Tamper no erase + array: + len: 3 + stride: 3 + bit_offset: 17 + bit_size: 1 + - name: TAMPXMF + description: Tamper mask flag + array: + len: 3 + stride: 3 + bit_offset: 18 + bit_size: 1 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 16 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 +enum/ALRFR: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/ALRWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Alarm update not allowed + value: 0 + - name: UpdateAllowed + description: Alarm update allowed + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: DU[3:0] represents the date units + value: 0 + - name: WeekDay + description: DU[3:0] represents the week day. DT[1:0] is don’t care + value: 1 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: Sixteen_Second + description: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1 + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: Eight_Second + description: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: Twenty_Four_Hour + description: 24 hour/day format + value: 0 + - name: AM_PM + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset. + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 0 + - name: Low + description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0 + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TAMPFR: + bit_size: 1 + variants: + - name: Tampered + description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - name: Clear + description: Flag cleared by software writing 0 + value: 0 +enum/TAMPTRG: + bit_size: 1 + variants: + - name: RisingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event." + value: 0 + - name: FallingEdge + description: "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event" + value: 1 +enum/TAMPFLT: + bit_size: 2 + variants: + - name: Immediate + description: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input) + value: 0 + - name: Samples2 + description: Tamper event is activated after 2 consecutive samples at the active level + value: 1 + - name: Samples4 + description: Tamper event is activated after 4 consecutive samples at the active level + value: 2 + - name: Samples8 + description: Tamper event is activated after 8 consecutive samples at the active level + value: 3 +enum/TAMPFREQ: + bit_size: 3 + variants: + - name: Div32768 + description: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz) + value: 0 + - name: Div16384 + description: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz) + value: 1 + - name: Div8192 + description: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz) + value: 2 + - name: Div4096 + description: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz) + value: 3 + - name: Div2048 + description: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz) + value: 4 + - name: Div1024 + description: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz) + value: 5 + - name: Div512 + description: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz) + value: 6 + - name: Div256 + description: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz) + value: 7 +enum/TAMPPRCH: + bit_size: 2 + variants: + - name: Cycles1 + description: 1 RTCCLK cycle + value: 0 + - name: Cycles2 + description: 2 RTCCLK cycles + value: 1 + - name: Cycles4 + description: 4 RTCCLK cycles + value: 2 + - name: Cycles8 + description: 8 RTCCLK cycles + value: 3 +enum/TAMPPUDIS: + bit_size: 1 + variants: + - name: Enabled + description: Precharge RTC_TAMPx pins before sampling (enable internal pull-up) + value: 0 + - name: Disabled + description: Disable precharge of RTC_TAMPx pins + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/TSOVFR: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a timestamp event occurs while TSF is already set + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTFR: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v3.yaml b/data/registers/rtc_v3.yaml new file mode 100644 index 0000000..16e5158 --- /dev/null +++ b/data/registers/rtc_v3.yaml @@ -0,0 +1,1040 @@ +--- +block/RTC: + description: Real-time clock + items: + - name: TR + description: Time register + byte_offset: 0 + fieldset: TR + - name: DR + description: Date register + byte_offset: 4 + fieldset: DR + - name: SSR + description: Sub second register + byte_offset: 8 + access: Read + fieldset: SSR + - name: ICSR + description: Initialization control and status register + byte_offset: 12 + fieldset: ICSR + - name: PRER + description: Prescaler register + byte_offset: 16 + fieldset: PRER + - name: WUTR + description: Wakeup timer register + byte_offset: 20 + fieldset: WUTR + - name: CR + description: Control register + byte_offset: 24 + fieldset: CR + - name: WPR + description: Write protection register + byte_offset: 36 + access: Write + fieldset: WPR + - name: CALR + description: Calibration register + byte_offset: 40 + fieldset: CALR + - name: SHIFTR + description: Shift control register + byte_offset: 44 + access: Write + fieldset: SHIFTR + - name: TSTR + description: Timestamp time register + byte_offset: 48 + access: Read + fieldset: TSTR + - name: TSDR + description: Timestamp date register + byte_offset: 52 + access: Read + fieldset: TSDR + - name: TSSSR + description: Timestamp sub second register + byte_offset: 56 + access: Read + fieldset: TSSSR + - name: ALRMR + description: Alarm register + array: + len: 2 + stride: 8 + byte_offset: 64 + fieldset: ALRMR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 8 + byte_offset: 68 + fieldset: ALRMSSR + - name: SR + description: Status register + byte_offset: 80 + access: Read + fieldset: SR + - name: MISR + description: Masked interrupt status register + byte_offset: 84 + access: Read + fieldset: MISR + - name: SCR + description: Status clear register + byte_offset: 92 + access: Write + fieldset: SCR + - name: ALRBINR + description: Alarm binary mode register + array: + len: 2 + stride: 4 + byte_offset: 112 + fieldset: ALRBINR +fieldset/ALRBINR: + description: RTC alarm A binary mode register + fields: + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 +fieldset/ALRMR: + description: Alarm register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MSK1 + description: Alarm A seconds mask + bit_offset: 7 + bit_size: 1 + enum: ALRMR_MSK + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: ALRMR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK + - name: DU + description: Date units or day in BCD format + bit_offset: 24 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 28 + bit_size: 2 + - name: WDSEL + description: Week day selection + bit_offset: 30 + bit_size: 1 + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register + fields: + - name: SS + description: Sub seconds value + bit_offset: 0 + bit_size: 15 + - name: MASKSS + description: Mask the most-significant bits starting at this bit + bit_offset: 24 + bit_size: 6 + - name: SSCLR + description: Clear synchronous counter on alarm (Binary mode only) + bit_offset: 31 + bit_size: 1 + enum: ALRMSSR_SSCLR +fieldset/CALR: + description: Calibration register + fields: + - name: CALM + description: Calibration minus + bit_offset: 0 + bit_size: 9 + - name: LPCAL + description: Calibration low-power mode + bit_offset: 12 + bit_size: 1 + enum: LPCAL + - name: CALW16 + description: Use a 16-second calibration cycle period + bit_offset: 13 + bit_size: 1 + enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 + - name: CALP + description: Increase frequency of RTC by 488.5 ppm + bit_offset: 15 + bit_size: 1 + enum: CALP +fieldset/CR: + description: Control register + fields: + - name: WUCKSEL + description: Wakeup clock selection + bit_offset: 0 + bit_size: 3 + enum: WUCKSEL + - name: TSEDGE + description: Timestamp event active edge + bit_offset: 3 + bit_size: 1 + enum: TSEDGE + - name: REFCKON + description: RTC_REFIN reference clock detection enable (50 or 60 Hz) + bit_offset: 4 + bit_size: 1 + enum: REFCKON + - name: BYPSHAD + description: Bypass the shadow registers + bit_offset: 5 + bit_size: 1 + - name: FMT + description: Hour format + bit_offset: 6 + bit_size: 1 + enum: FMT + - name: SSRUIE + description: SSR underflow interrupt enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 + bit_offset: 8 + bit_size: 1 + - name: WUTE + description: Wakeup timer enable + bit_offset: 10 + bit_size: 1 + - name: TSE + description: Timestamp enable + bit_offset: 11 + bit_size: 1 + - name: ALRAIE + description: Alarm interrupt enable + array: + len: 2 + stride: 1 + bit_offset: 12 + bit_size: 1 + - name: WUTIE + description: Wakeup timer interrupt enable + bit_offset: 14 + bit_size: 1 + - name: TSIE + description: Timestamp interrupt enable + bit_offset: 15 + bit_size: 1 + - name: ADD1H + description: Add 1 hour (summer time change) + bit_offset: 16 + bit_size: 1 + - name: SUB1H + description: Subtract 1 hour (winter time change) + bit_offset: 17 + bit_size: 1 + - name: BKP + description: Backup + bit_offset: 18 + bit_size: 1 + - name: COSEL + description: Calibration output selection + bit_offset: 19 + bit_size: 1 + enum: COSEL + - name: POL + description: Output polarity + bit_offset: 20 + bit_size: 1 + enum: POL + - name: OSEL + description: Output selection + bit_offset: 21 + bit_size: 2 + enum: OSEL + - name: COE + description: Calibration output enable + bit_offset: 23 + bit_size: 1 + - name: ITSE + description: Timestamp on internal event enable + bit_offset: 24 + bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: Tamper detection output enable on TAMPALRM + bit_offset: 26 + bit_size: 1 + - name: TAMPALRM_PU + description: TAMPALRM pull-up enable + bit_offset: 29 + bit_size: 1 + enum: TAMPALRM_PU + - name: TAMPALRM_TYPE + description: TAMPALRM output type + bit_offset: 30 + bit_size: 1 + enum: TAMPALRM_TYPE + - name: OUT2EN + description: RTC_OUT2 output enable + bit_offset: 31 + bit_size: 1 +fieldset/DR: + description: Date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 + - name: YU + description: Year units in BCD format + bit_offset: 16 + bit_size: 4 + - name: YT + description: Year tens in BCD format + bit_offset: 20 + bit_size: 4 +fieldset/ICSR: + description: Initialization control and status register + fields: + - name: WUTWF + description: Wakeup timer write flag + bit_offset: 2 + bit_size: 1 + enum_read: WUTWFR + - name: SHPF + description: Shift operation pending + bit_offset: 3 + bit_size: 1 + - name: INITS + description: Initialization status flag + bit_offset: 4 + bit_size: 1 + enum_read: INITSR + - name: RSF + description: Registers synchronization flag + bit_offset: 5 + bit_size: 1 + enum_read: RSFR + enum_write: RSFW + - name: INITF + description: Initialization flag + bit_offset: 6 + bit_size: 1 + enum_read: INITFR + - name: INIT + description: Initialization mode + bit_offset: 7 + bit_size: 1 + enum: INIT + - name: BIN + description: Binary mode + bit_offset: 8 + bit_size: 2 + enum: BIN + - name: BCDU + description: BCD update + bit_offset: 10 + bit_size: 3 + enum: BCDU + - name: RECALPF + description: Recalibration pending Flag + bit_offset: 16 + bit_size: 1 + enum_read: RECALPFR +fieldset/MISR: + description: Masked interrupt status register + fields: + - name: ALRMF + description: Alarm masked flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum: ALRMF + - name: WUTMF + description: Wakeup timer masked flag + bit_offset: 2 + bit_size: 1 + enum: WUTMF + - name: TSMF + description: Timestamp masked flag + bit_offset: 3 + bit_size: 1 + enum: TSMF + - name: TSOVMF + description: Timestamp overflow masked flag + bit_offset: 4 + bit_size: 1 + enum: TSOVMF + - name: ITSMF + description: Internal timestamp masked flag + bit_offset: 5 + bit_size: 1 + enum: ITSMF + - name: SSRUMF + description: SSR underflow masked flag + bit_offset: 6 + bit_size: 1 + enum: SSRUMF +fieldset/PRER: + description: Prescaler register + fields: + - name: PREDIV_S + description: Synchronous prescaler factor + bit_offset: 0 + bit_size: 15 + - name: PREDIV_A + description: Asynchronous prescaler factor + bit_offset: 16 + bit_size: 7 +fieldset/SCR: + description: Status clear register + fields: + - name: CALRF + description: Clear alarm A flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum: CALRF + - name: CWUTF + description: Clear wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: CALRF + - name: CTSF + description: Clear timestamp flag + bit_offset: 3 + bit_size: 1 + enum: CALRF + - name: CTSOVF + description: Clear timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: CALRF + - name: CITSF + description: Clear internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: CALRF + - name: CSSRUF + description: Clear SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: CALRF +fieldset/SHIFTR: + description: Shift control register + fields: + - name: SUBFS + description: Subtract a fraction of a second + bit_offset: 0 + bit_size: 15 + - name: ADD1S + description: Add one second + bit_offset: 31 + bit_size: 1 +fieldset/SR: + description: Status register + fields: + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum: ALRF + - name: WUTF + description: Wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: WUTF + - name: TSF + description: Timestamp flag + bit_offset: 3 + bit_size: 1 + enum: TSF + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: TSOVF + - name: ITSF + description: Internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: ITSF + - name: SSRUF + description: SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: SSRUF +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Synchronous binary counter + bit_offset: 0 + bit_size: 32 +fieldset/TR: + description: Time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 + enum: AMPM +fieldset/TSDR: + description: Timestamp date register + fields: + - name: DU + description: Date units in BCD format + bit_offset: 0 + bit_size: 4 + - name: DT + description: Date tens in BCD format + bit_offset: 4 + bit_size: 2 + - name: MU + description: Month units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MT + description: Month tens in BCD format + bit_offset: 12 + bit_size: 1 + - name: WDU + description: Week day units + bit_offset: 13 + bit_size: 3 +fieldset/TSSSR: + description: Timestamp sub second register + fields: + - name: SS + description: Sub second value + bit_offset: 0 + bit_size: 32 +fieldset/TSTR: + description: Timestamp time register + fields: + - name: SU + description: Second units in BCD format + bit_offset: 0 + bit_size: 4 + - name: ST + description: Second tens in BCD format + bit_offset: 4 + bit_size: 3 + - name: MNU + description: Minute units in BCD format + bit_offset: 8 + bit_size: 4 + - name: MNT + description: Minute tens in BCD format + bit_offset: 12 + bit_size: 3 + - name: HU + description: Hour units in BCD format + bit_offset: 16 + bit_size: 4 + - name: HT + description: Hour tens in BCD format + bit_offset: 20 + bit_size: 2 + - name: PM + description: AM/PM notation + bit_offset: 22 + bit_size: 1 +fieldset/WPR: + description: Write protection register + fields: + - name: KEY + description: Write protection key + bit_offset: 0 + bit_size: 8 + enum: KEY +fieldset/WUTR: + description: Wakeup timer register + fields: + - name: WUT + description: Wakeup auto-reload value bits + bit_offset: 0 + bit_size: 16 + - name: WUTOCLR + description: Wakeup auto-reload output clear value + bit_offset: 16 + bit_size: 16 +enum/ALRF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRMF: + bit_size: 1 + variants: + - name: Match + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) + value: 1 +enum/ALRMR_MSK: + bit_size: 1 + variants: + - name: Mask + description: Alarm set if the date/day match + value: 0 + - name: NotMask + description: Date/day don’t care in Alarm comparison + value: 1 +enum/ALRMR_PM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/ALRMR_WDSEL: + bit_size: 1 + variants: + - name: DateUnits + description: "DU[3:0] represents the date units" + value: 0 + - name: WeekDay + description: "DU[3:0] represents the week day. DT[1:0] is don’t care." + value: 1 +enum/ALRMSSR_SSCLR: + bit_size: 1 + variants: + - name: FreeRunning + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" + value: 0 + - name: ALRMBINR + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" + value: 1 +enum/BCDU: + bit_size: 3 + variants: + - name: Bit7 + description: "1s increment each time SS[7:0]=0" + value: 0 + - name: Bit8 + description: "1s increment each time SS[8:0]=0" + value: 1 + - name: Bit9 + description: "1s increment each time SS[9:0]=0" + value: 2 + - name: Bit10 + description: "1s increment each time SS[10:0]=0" + value: 3 + - name: Bit11 + description: "1s increment each time SS[11:0]=0" + value: 4 + - name: Bit12 + description: "1s increment each time SS[12:0]=0" + value: 5 + - name: Bit13 + description: "1s increment each time SS[13:0]=0" + value: 6 + - name: Bit14 + description: "1s increment each time SS[14:0]=0" + value: 7 +enum/BIN: + bit_size: 2 + variants: + - name: BCD + description: Free running BCD calendar mode (Binary mode disabled) + value: 0 + - name: Binary + description: Free running Binary mode (BCD mode disabled) + value: 1 + - name: BinBCD + description: Free running BCD calendar and Binary modes + value: 2 + - name: BinBCD2 + description: Free running BCD calendar and Binary modes + value: 3 +enum/CALP: + bit_size: 1 + variants: + - name: NoChange + description: No RTCCLK pulses are added + value: 0 + - name: IncreaseFreq + description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) + value: 1 +enum/CALRF: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag by writing 1 + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - name: SixteenSeconds + description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - name: EightSeconds + description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - name: CalFreq_512Hz + description: Calibration output is 512 Hz (with default prescaler setting) + value: 0 + - name: CalFreq_1Hz + description: Calibration output is 1 Hz (with default prescaler setting) + value: 1 +enum/FMT: + bit_size: 1 + variants: + - name: TwentyFourHour + description: 24 hour/day format + value: 0 + - name: AmPm + description: AM/PM hour format + value: 1 +enum/INIT: + bit_size: 1 + variants: + - name: FreeRunningMode + description: Free running mode + value: 0 + - name: InitMode + description: "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset." + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - name: NotAllowed + description: Calendar registers update is not allowed + value: 0 + - name: Allowed + description: Calendar registers update is allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - name: NotInitalized + description: Calendar has not been initialized + value: 0 + - name: Initalized + description: Calendar has been initialized + value: 1 +enum/ITSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/ITSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/KEY: + bit_size: 8 + variants: + - name: Activate + description: Activate write protection (any value that is not the keys) + value: 0 + - name: Deactivate2 + description: Key 2 + value: 83 + - name: Deactivate1 + description: Key 1 + value: 202 +enum/LPCAL: + bit_size: 1 + variants: + - name: RTCCLK + description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" + value: 0 + - name: CkApre + description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - name: Disabled + description: Output disabled + value: 0 + - name: AlarmA + description: Alarm A output enabled + value: 1 + - name: AlarmB + description: Alarm B output enabled + value: 2 + - name: Wakeup + description: Wakeup output enabled + value: 3 +enum/POL: + bit_size: 1 + variants: + - name: High + description: "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 0 + - name: Low + description: "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])" + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - name: Pending + description: "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0" + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - name: Disabled + description: RTC_REFIN detection disabled + value: 0 + - name: Enabled + description: RTC_REFIN detection enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - name: NotSynced + description: Calendar shadow registers not yet synchronized + value: 0 + - name: Synced + description: Calendar shadow registers synchronized + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - name: Clear + description: This flag is cleared by software by writing 0 + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - name: NoShiftPending + description: No shift operation is pending + value: 0 + - name: ShiftPending + description: A shift operation is pending + value: 1 +enum/SSRUF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/SSRUIE: + bit_size: 1 + variants: + - name: Disabled + description: SSR underflow interrupt disabled + value: 0 + - name: Enabled + description: SSR underflow interrupt enabled + value: 1 +enum/SSRUMF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/TAMPALRM_PU: + bit_size: 1 + variants: + - name: NoPullUp + description: No pull-up is applied on TAMPALRM output + value: 0 + - name: PullUp + description: A pull-up is applied on TAMPALRM output + value: 1 +enum/TAMPALRM_TYPE: + bit_size: 1 + variants: + - name: PushPull + description: TAMPALRM is push-pull output + value: 0 + - name: OpenDrain + description: TAMPALRM is open-drain output + value: 1 +enum/AMPM: + bit_size: 1 + variants: + - name: AM + description: AM or 24-hour format + value: 0 + - name: PM + description: PM + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - name: RisingEdge + description: RTC_TS input rising edge generates a time-stamp event + value: 0 + - name: FallingEdge + description: RTC_TS input falling edge generates a time-stamp event + value: 1 +enum/TSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs + value: 1 +enum/TSOVF: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/TSOVMF: + bit_size: 1 + variants: + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 +enum/WUCKSEL: + bit_size: 3 + variants: + - name: Div16 + description: RTC/16 clock is selected + value: 0 + - name: Div8 + description: RTC/8 clock is selected + value: 1 + - name: Div4 + description: RTC/4 clock is selected + value: 2 + - name: Div2 + description: RTC/2 clock is selected + value: 3 + - name: ClockSpare + description: ck_spre (usually 1 Hz) clock is selected + value: 4 + - name: ClockSpareWithOffset + description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value + value: 6 +enum/WUTF: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTMF: + bit_size: 1 + variants: + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - name: UpdateNotAllowed + description: Wakeup timer configuration update not allowed + value: 0 + - name: UpdateAllowed + description: Wakeup timer configuration update allowed + value: 1 diff --git a/data/registers/rtc_v2.yaml b/data/registers/rtc_v3u5.yaml similarity index 60% rename from data/registers/rtc_v2.yaml rename to data/registers/rtc_v3u5.yaml index 20ada52..35f40c4 100644 --- a/data/registers/rtc_v2.yaml +++ b/data/registers/rtc_v3u5.yaml @@ -3,96 +3,121 @@ block/RTC: description: Real-time clock items: - name: TR - description: time register + description: Time register byte_offset: 0 fieldset: TR - name: DR - description: date register + description: Date register byte_offset: 4 fieldset: DR - - name: CR - description: control register + - name: SSR + description: Sub second register byte_offset: 8 - fieldset: CR - - name: ISR - description: initialization and status register + access: Read + fieldset: SSR + - name: ICSR + description: Initialization control and status register byte_offset: 12 - fieldset: ISR + fieldset: ICSR - name: PRER - description: prescaler register + description: Prescaler register byte_offset: 16 fieldset: PRER - name: WUTR - description: wakeup timer register + description: Wakeup timer register byte_offset: 20 fieldset: WUTR - - name: ALRMAR - description: alarm A register + - name: CR + description: Control register + byte_offset: 24 + fieldset: CR + - name: PRIVCR + description: Privilege mode control register byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register + fieldset: PRIVCR + - name: SECCFGR + description: Secure mode control register byte_offset: 32 - fieldset: ALRMBR + fieldset: SECCFGR - name: WPR - description: write protection register + description: Write protection register byte_offset: 36 access: Write fieldset: WPR - - name: SSR - description: sub second register + - name: CALR + description: Calibration register byte_offset: 40 - access: Read - fieldset: SSR + fieldset: CALR - name: SHIFTR - description: shift control register + description: Shift control register byte_offset: 44 access: Write fieldset: SHIFTR - name: TSTR - description: time stamp time register + description: Timestamp time register byte_offset: 48 access: Read fieldset: TSTR - name: TSDR - description: time stamp date register + description: Timestamp date register byte_offset: 52 access: Read fieldset: TSDR - name: TSSSR - description: timestamp sub second register + description: Timestamp sub second register byte_offset: 56 access: Read fieldset: TSSSR - - name: CALR - description: calibration register - byte_offset: 60 - fieldset: CALR - - name: TAMPCR - description: tamper configuration register - byte_offset: 64 - fieldset: TAMPCR - - name: ALRMASSR - description: alarm A sub second register - byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR - - name: OR - description: option register - byte_offset: 76 - fieldset: OR - - name: BKPR - description: backup register + - name: ALRMR + description: Alarm register array: - len: 32 - stride: 4 + len: 2 + stride: 8 + byte_offset: 64 + fieldset: ALRMR + - name: ALRMSSR + description: Alarm sub second register + array: + len: 2 + stride: 8 + byte_offset: 68 + fieldset: ALRMSSR + - name: SR + description: Status register byte_offset: 80 - fieldset: BKPR -fieldset/ALRMAR: - description: alarm A register + access: Read + fieldset: SR + - name: MISR + description: Masked interrupt status register + byte_offset: 84 + access: Read + fieldset: MISR + - name: SMISR + description: Secure masked interrupt status register + byte_offset: 88 + access: Read + fieldset: SMISR + - name: SCR + description: Status clear register + byte_offset: 92 + access: Write + fieldset: SCR + - name: ALRBINR + description: Alarm binary mode register + array: + len: 2 + stride: 4 + byte_offset: 112 + fieldset: ALRBINR +fieldset/ALRBINR: + description: RTC alarm A binary mode register + fields: + - name: SS + description: Synchronous counter alarm value in Binary mode + bit_offset: 0 + bit_size: 32 +fieldset/ALRMR: + description: Alarm register fields: - name: SU description: Second units in BCD format @@ -102,14 +127,11 @@ fieldset/ALRMAR: description: Second tens in BCD format bit_offset: 4 bit_size: 3 - - name: MSK + - name: MSK1 description: Alarm A seconds mask bit_offset: 7 bit_size: 1 - array: - len: 4 - stride: 8 - enum: ALRMAR_MSK + enum: ALRMR_MSK - name: MNU description: Minute units in BCD format bit_offset: 8 @@ -118,6 +140,11 @@ fieldset/ALRMAR: description: Minute tens in BCD format bit_offset: 12 bit_size: 3 + - name: MSK2 + description: Alarm A minutes mask + bit_offset: 15 + bit_size: 1 + enum: ALRMR_MSK - name: HU description: Hour units in BCD format bit_offset: 16 @@ -130,7 +157,12 @@ fieldset/ALRMAR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: ALRMAR_PM + enum: ALRMR_PM + - name: MSK3 + description: Alarm A hours mask + bit_offset: 23 + bit_size: 1 + enum: ALRMR_MSK - name: DU description: Date units or day in BCD format bit_offset: 24 @@ -143,9 +175,14 @@ fieldset/ALRMAR: description: Week day selection bit_offset: 30 bit_size: 1 - enum: ALRMAR_WDSEL -fieldset/ALRMASSR: - description: alarm A sub second register + enum: ALRMR_WDSEL + - name: MSK4 + description: Alarm A date mask + bit_offset: 31 + bit_size: 1 + enum: ALRMR_MSK +fieldset/ALRMSSR: + description: Alarm sub second register fields: - name: SS description: Sub seconds value @@ -154,100 +191,41 @@ fieldset/ALRMASSR: - name: MASKSS description: Mask the most-significant bits starting at this bit bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK - description: Alarm B seconds mask - bit_offset: 7 + bit_size: 6 + - name: SSCLR + description: Clear synchronous counter on alarm (Binary mode only) + bit_offset: 31 bit_size: 1 - array: - len: 4 - stride: 8 - enum: ALRMBR_MSK - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - enum: ALRMBR_PM - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - enum: ALRMBR_WDSEL -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 -fieldset/BKPR: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 + enum: ALRMSSR_SSCLR fieldset/CALR: - description: calibration register + description: Calibration register fields: - name: CALM description: Calibration minus bit_offset: 0 bit_size: 9 - - name: CALW + - name: LPCAL + description: Calibration low-power mode + bit_offset: 12 + bit_size: 1 + enum: LPCAL + - name: CALW16 description: Use a 16-second calibration cycle period bit_offset: 13 bit_size: 1 - array: - len: 2 - stride: 1 enum: CALW16 + - name: CALW8 + description: Use an 8-second calibration cycle period + bit_offset: 14 + bit_size: 1 + enum: CALW8 - name: CALP description: Increase frequency of RTC by 488.5 ppm bit_offset: 15 bit_size: 1 enum: CALP fieldset/CR: - description: control register + description: Control register fields: - name: WUCKSEL description: Wakeup clock selection @@ -255,12 +233,12 @@ fieldset/CR: bit_size: 3 enum: WUCKSEL - name: TSEDGE - description: Time-stamp event active edge + description: Timestamp event active edge bit_offset: 3 bit_size: 1 enum: TSEDGE - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) + description: RTC_REFIN reference clock detection enable (50 or 60 Hz) bit_offset: 4 bit_size: 1 enum: REFCKON @@ -268,67 +246,57 @@ fieldset/CR: description: Bypass the shadow registers bit_offset: 5 bit_size: 1 - enum: BYPSHAD - name: FMT description: Hour format bit_offset: 6 bit_size: 1 enum: FMT - - name: ALRAE - description: Alarm A enable + - name: SSRUIE + description: SSR underflow interrupt enable + bit_offset: 7 + bit_size: 1 + - name: ALRE + description: Alarm enable + array: + len: 2 + stride: 1 bit_offset: 8 bit_size: 1 - enum: ALRAE - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - enum: ALRBE - name: WUTE description: Wakeup timer enable bit_offset: 10 bit_size: 1 - enum: WUTE - name: TSE - description: Time stamp enable + description: Timestamp enable bit_offset: 11 bit_size: 1 - enum: TSE - name: ALRAIE - description: Alarm A interrupt enable + description: Alarm interrupt enable + array: + len: 2 + stride: 1 bit_offset: 12 bit_size: 1 - enum: ALRAIE - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - enum: ALRBIE - name: WUTIE description: Wakeup timer interrupt enable bit_offset: 14 bit_size: 1 - enum: WUTIE - name: TSIE - description: Time-stamp interrupt enable + description: Timestamp interrupt enable bit_offset: 15 bit_size: 1 - enum: TSIE - name: ADD1H description: Add 1 hour (summer time change) bit_offset: 16 bit_size: 1 - enum_write: ADDHW - name: SUB1H description: Subtract 1 hour (winter time change) bit_offset: 17 bit_size: 1 - enum_write: SUBHW - name: BKP description: Backup bit_offset: 18 bit_size: 1 - enum: BKP - name: COSEL description: Calibration output selection bit_offset: 19 @@ -348,13 +316,41 @@ fieldset/CR: description: Calibration output enable bit_offset: 23 bit_size: 1 - enum: COE - name: ITSE - description: timestamp on internal event enable + description: Timestamp on internal event enable bit_offset: 24 bit_size: 1 + - name: TAMPTS + description: Activate timestamp on tamper detection event + bit_offset: 25 + bit_size: 1 + - name: TAMPOE + description: Tamper detection output enable on TAMPALRM + bit_offset: 26 + bit_size: 1 + - name: ALRFCLR + description: ALRFCLR + array: + len: 2 + stride: 1 + bit_offset: 27 + bit_size: 1 + - name: TAMPALRM_PU + description: TAMPALRM pull-up enable + bit_offset: 29 + bit_size: 1 + enum: TAMPALRM_PU + - name: TAMPALRM_TYPE + description: TAMPALRM output type + bit_offset: 30 + bit_size: 1 + enum: TAMPALRM_TYPE + - name: OUT2EN + description: RTC_OUT2 output enable + bit_offset: 31 + bit_size: 1 fieldset/DR: - description: date register + description: Date register fields: - name: DU description: Date units in BCD format @@ -384,19 +380,9 @@ fieldset/DR: description: Year tens in BCD format bit_offset: 20 bit_size: 4 -fieldset/ISR: - description: initialization and status register +fieldset/ICSR: + description: Initialization control and status register fields: - - name: ALRAWF - description: Alarm A write flag - bit_offset: 0 - bit_size: 1 - enum_read: ALRAWFR - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 - enum_read: ALRAWFR - name: WUTWF description: Wakeup timer write flag bit_offset: 2 @@ -406,7 +392,6 @@ fieldset/ISR: description: Shift operation pending bit_offset: 3 bit_size: 1 - enum_read: SHPFR - name: INITS description: Initialization status flag bit_offset: 4 @@ -428,80 +413,59 @@ fieldset/ISR: bit_offset: 7 bit_size: 1 enum: INIT - - name: ALRAF - description: Alarm A flag + - name: BIN + description: Binary mode bit_offset: 8 - bit_size: 1 - enum_read: ALRAFR - enum_write: ALRAFW - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 - enum_read: ALRBFR - enum_write: ALRBFW - - name: WUTF - description: Wakeup timer flag + bit_size: 2 + enum: BIN + - name: BCDU + description: BCD update bit_offset: 10 - bit_size: 1 - enum_read: WUTFR - enum_write: WUTFW - - name: TSF - description: Time-stamp flag - bit_offset: 11 - bit_size: 1 - enum_read: TSFR - enum_write: TSFW - - name: TSOVF - description: Time-stamp overflow flag - bit_offset: 12 - bit_size: 1 - enum_read: TSOVFR - enum_write: TSOVFW - - name: TAMP1F - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW - - name: TAMP2F - description: RTC_TAMP2 detection flag - bit_offset: 14 - bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW - - name: TAMP3F - description: RTC_TAMP3 detection flag - bit_offset: 15 - bit_size: 1 - enum_read: TAMPFR - enum_write: TAMPFW + bit_size: 3 + enum: BCDU - name: RECALPF description: Recalibration pending Flag bit_offset: 16 bit_size: 1 enum_read: RECALPFR - - name: ITSF - description: Internal tTime-stamp flag - bit_offset: 17 - bit_size: 1 -fieldset/OR: - description: option register +fieldset/MISR: + description: Masked interrupt status register fields: - - name: RTC_OUT_RMP - description: RTC_OUT remap - bit_offset: 1 + - name: ALRMF + description: Alarm masked flag + array: + len: 2 + stride: 1 + bit_offset: 0 bit_size: 1 - - name: TSINSEL - description: TIMESTAMP mapping - bit_offset: 1 + enum: ALRMF + - name: WUTMF + description: Wakeup timer masked flag + bit_offset: 2 bit_size: 1 - - name: RTC_ALARM_TYPE - description: RTC_ALARM on PC13 output type + enum: WUTMF + - name: TSMF + description: Timestamp masked flag bit_offset: 3 bit_size: 1 + enum: TSMF + - name: TSOVMF + description: Timestamp overflow masked flag + bit_offset: 4 + bit_size: 1 + enum: TSOVMF + - name: ITSMF + description: Internal timestamp masked flag + bit_offset: 5 + bit_size: 1 + enum: ITSMF + - name: SSRUMF + description: SSR underflow masked flag + bit_offset: 6 + bit_size: 1 + enum: SSRUMF fieldset/PRER: - description: prescaler register + description: Prescaler register fields: - name: PREDIV_S description: Synchronous prescaler factor @@ -511,8 +475,106 @@ fieldset/PRER: description: Asynchronous prescaler factor bit_offset: 16 bit_size: 7 +fieldset/PRIVCR: + description: Privilege mode control register + fields: + - name: ALRAPRIV + description: ALRAPRIV + bit_offset: 0 + bit_size: 1 + - name: ALRBPRIV + description: ALRBPRIV + bit_offset: 1 + bit_size: 1 + - name: WUTPRIV + description: WUTPRIV + bit_offset: 2 + bit_size: 1 + - name: TSPRIV + description: TSPRIV + bit_offset: 3 + bit_size: 1 + - name: CALPRIV + description: CALPRIV + bit_offset: 13 + bit_size: 1 + - name: INITPRIV + description: INITPRIV + bit_offset: 14 + bit_size: 1 + - name: PRIV + description: PRIV + bit_offset: 15 + bit_size: 1 +fieldset/SCR: + description: Status clear register + fields: + - name: CALRF + description: Clear alarm A flag + array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + enum: CALRF + - name: CWUTF + description: Clear wakeup timer flag + bit_offset: 2 + bit_size: 1 + enum: CALRF + - name: CTSF + description: Clear timestamp flag + bit_offset: 3 + bit_size: 1 + enum: CALRF + - name: CTSOVF + description: Clear timestamp overflow flag + bit_offset: 4 + bit_size: 1 + enum: CALRF + - name: CITSF + description: Clear internal timestamp flag + bit_offset: 5 + bit_size: 1 + enum: CALRF + - name: CSSRUF + description: Clear SSR underflow flag + bit_offset: 6 + bit_size: 1 + enum: CALRF +fieldset/SECCFGR: + description: Secure mode control register + fields: + - name: ALRASEC + description: ALRASEC + bit_offset: 0 + bit_size: 1 + - name: ALRBSEC + description: ALRBSEC + bit_offset: 1 + bit_size: 1 + - name: WUTSEC + description: WUTSEC + bit_offset: 2 + bit_size: 1 + - name: TSSEC + description: TSSEC + bit_offset: 3 + bit_size: 1 + - name: CALSEC + description: CALSEC + bit_offset: 13 + bit_size: 1 + - name: INITSEC + description: INITSEC + bit_offset: 14 + bit_size: 1 + - name: SEC + description: SEC + bit_offset: 15 + bit_size: 1 fieldset/SHIFTR: - description: shift control register + description: Shift control register fields: - name: SUBFS description: Subtract a fraction of a second @@ -522,103 +584,82 @@ fieldset/SHIFTR: description: Add one second bit_offset: 31 bit_size: 1 - enum_write: ADDSW -fieldset/SSR: - description: sub second register +fieldset/SMISR: + description: Secure masked interrupt status register fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 -fieldset/TAMPCR: - description: tamper configuration register - fields: - - name: TAMP1E - description: Tamper 1 detection enable + - name: ALRAMF + description: ALRAMF bit_offset: 0 bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 + - name: ALRBMF + description: ALRBMF bit_offset: 1 bit_size: 1 - - name: TAMPIE - description: Tamper interrupt enable + - name: WUTMF + description: WUTMF bit_offset: 2 bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable + - name: TSMF + description: TSMF bit_offset: 3 bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 + - name: TSOVMF + description: TSOVMF bit_offset: 4 bit_size: 1 - - name: TAMP3E - description: Tamper 3 detection enable + - name: ITSMF + description: ITSMF bit_offset: 5 bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 + - name: SSRUMF + description: SSRUMF bit_offset: 6 bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 +fieldset/SR: + description: Status register + fields: + - name: ALRF + description: Alarm flag + array: + len: 2 + stride: 1 + bit_offset: 0 bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - - name: TAMPPUDIS - description: TAMPER pull-up disable - bit_offset: 15 + enum: ALRF + - name: WUTF + description: Wakeup timer flag + bit_offset: 2 bit_size: 1 - - name: TAMP1IE - description: Tamper 1 interrupt enable - bit_offset: 16 + enum: WUTF + - name: TSF + description: Timestamp flag + bit_offset: 3 bit_size: 1 - - name: TAMP1NOERASE - description: Tamper 1 no erase - bit_offset: 17 + enum: TSF + - name: TSOVF + description: Timestamp overflow flag + bit_offset: 4 bit_size: 1 - - name: TAMP1MF - description: Tamper 1 mask flag - bit_offset: 18 + enum: TSOVF + - name: ITSF + description: Internal timestamp flag + bit_offset: 5 bit_size: 1 - - name: TAMP2IE - description: Tamper 2 interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TAMP2NOERASE - description: Tamper 2 no erase - bit_offset: 20 - bit_size: 1 - - name: TAMP2MF - description: Tamper 2 mask flag - bit_offset: 21 - bit_size: 1 - - name: TAMP3IE - description: Tamper 3 interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TAMP3NOERASE - description: Tamper 3 no erase - bit_offset: 23 - bit_size: 1 - - name: TAMP3MF - description: Tamper 3 mask flag - bit_offset: 24 + enum: ITSF + - name: SSRUF + description: SSR underflow flag + bit_offset: 6 bit_size: 1 + enum: SSRUF +fieldset/SSR: + description: Sub second register + fields: + - name: SS + description: Synchronous binary counter + bit_offset: 0 + bit_size: 32 fieldset/TR: - description: time register + description: Time register fields: - name: SU description: Second units in BCD format @@ -648,9 +689,9 @@ fieldset/TR: description: AM/PM notation bit_offset: 22 bit_size: 1 - enum: TR_PM + enum: AMPM fieldset/TSDR: - description: time stamp date register + description: Timestamp date register fields: - name: DU description: Date units in BCD format @@ -673,14 +714,14 @@ fieldset/TSDR: bit_offset: 13 bit_size: 3 fieldset/TSSSR: - description: timestamp sub second register + description: Timestamp sub second register fields: - name: SS description: Sub second value bit_offset: 0 - bit_size: 16 + bit_size: 32 fieldset/TSTR: - description: time stamp time register + description: Timestamp time register fields: - name: SU description: Second units in BCD format @@ -711,101 +752,37 @@ fieldset/TSTR: bit_offset: 22 bit_size: 1 fieldset/WPR: - description: write protection register + description: Write protection register fields: - name: KEY description: Write protection key bit_offset: 0 bit_size: 8 + enum: KEY fieldset/WUTR: - description: wakeup timer register + description: Wakeup timer register fields: - name: WUT description: Wakeup auto-reload value bits bit_offset: 0 bit_size: 16 -enum/ADDHW: - bit_size: 1 - variants: - - name: Add1 - description: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode - value: 1 -enum/ADDSW: - bit_size: 1 - variants: - - name: Add1 - description: Add one second to the clock/calendar - value: 1 -enum/ALRAE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A disabled - value: 0 - - name: Enabled - description: Alarm A enabled - value: 1 -enum/ALRAFR: + - name: WUTOCLR + description: Wakeup auto-reload output clear value + bit_offset: 16 + bit_size: 16 +enum/ALRF: bit_size: 1 variants: - name: Match description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) value: 1 -enum/ALRAFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRAIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm A interrupt disabled - value: 0 - - name: Enabled - description: Alarm A interrupt enabled - value: 1 -enum/ALRAWFR: - bit_size: 1 - variants: - - name: UpdateNotAllowed - description: Alarm update not allowed - value: 0 - - name: UpdateAllowed - description: Alarm update allowed - value: 1 -enum/ALRBE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B disabled - value: 0 - - name: Enabled - description: Alarm B enabled - value: 1 -enum/ALRBFR: +enum/ALRMF: bit_size: 1 variants: - name: Match - description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR) + description: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR) value: 1 -enum/ALRBFW: - bit_size: 1 - variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/ALRBIE: - bit_size: 1 - variants: - - name: Disabled - description: Alarm B Interrupt disabled - value: 0 - - name: Enabled - description: Alarm B Interrupt enabled - value: 1 -enum/ALRMAR_MSK: +enum/ALRMR_MSK: bit_size: 1 variants: - name: Mask @@ -814,7 +791,7 @@ enum/ALRMAR_MSK: - name: NotMask description: Date/day don’t care in Alarm comparison value: 1 -enum/ALRMAR_PM: +enum/ALRMR_PM: bit_size: 1 variants: - name: AM @@ -823,7 +800,7 @@ enum/ALRMAR_PM: - name: PM description: PM value: 1 -enum/ALRMAR_WDSEL: +enum/ALRMR_WDSEL: bit_size: 1 variants: - name: DateUnits @@ -832,51 +809,57 @@ enum/ALRMAR_WDSEL: - name: WeekDay description: "DU[3:0] represents the week day. DT[1:0] is don’t care." value: 1 -enum/ALRMBR_MSK: +enum/ALRMSSR_SSCLR: bit_size: 1 variants: - - name: Mask - description: Alarm set if the date/day match + - name: FreeRunning + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running" value: 0 - - name: NotMask - description: Date/day don’t care in Alarm comparison + - name: ALRMBINR + description: "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]" value: 1 -enum/ALRMBR_PM: - bit_size: 1 +enum/BCDU: + bit_size: 3 variants: - - name: AM - description: AM or 24-hour format + - name: Bit7 + description: "1s increment each time SS[7:0]=0" value: 0 - - name: PM - description: PM + - name: Bit8 + description: "1s increment each time SS[8:0]=0" value: 1 -enum/ALRMBR_WDSEL: - bit_size: 1 + - name: Bit9 + description: "1s increment each time SS[9:0]=0" + value: 2 + - name: Bit10 + description: "1s increment each time SS[10:0]=0" + value: 3 + - name: Bit11 + description: "1s increment each time SS[11:0]=0" + value: 4 + - name: Bit12 + description: "1s increment each time SS[12:0]=0" + value: 5 + - name: Bit13 + description: "1s increment each time SS[13:0]=0" + value: 6 + - name: Bit14 + description: "1s increment each time SS[14:0]=0" + value: 7 +enum/BIN: + bit_size: 2 variants: - - name: DateUnits - description: "DU[3:0] represents the date units" + - name: BCD + description: Free running BCD calendar mode (Binary mode disabled) value: 0 - - name: WeekDay - description: "DU[3:0] represents the week day. DT[1:0] is don’t care." - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: DST_Not_Changed - description: Daylight Saving Time change has not been performed - value: 0 - - name: DST_Changed - description: Daylight Saving Time change has been performed - value: 1 -enum/BYPSHAD: - bit_size: 1 - variants: - - name: ShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles" - value: 0 - - name: BypassShadowReg - description: "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters" + - name: Binary + description: Free running Binary mode (BCD mode disabled) value: 1 + - name: BinBCD + description: Free running BCD calendar and Binary modes + value: 2 + - name: BinBCD2 + description: Free running BCD calendar and Binary modes + value: 3 enum/CALP: bit_size: 1 variants: @@ -886,27 +869,24 @@ enum/CALP: - name: IncreaseFreq description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm) value: 1 +enum/CALRF: + bit_size: 1 + variants: + - name: Clear + description: Clear interrupt flag by writing 1 + value: 1 enum/CALW16: bit_size: 1 variants: - - name: Sixteen_Second + - name: SixteenSeconds description: "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1" value: 1 enum/CALW8: bit_size: 1 variants: - - name: Eight_Second + - name: EightSeconds description: "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected" value: 1 -enum/COE: - bit_size: 1 - variants: - - name: Disabled - description: Calibration output disabled - value: 0 - - name: Enabled - description: Calibration output enabled - value: 1 enum/COSEL: bit_size: 1 variants: @@ -919,10 +899,10 @@ enum/COSEL: enum/FMT: bit_size: 1 variants: - - name: Twenty_Four_Hour + - name: TwentyFourHour description: 24 hour/day format value: 0 - - name: AM_PM + - name: AmPm description: AM/PM hour format value: 1 enum/INIT: @@ -952,6 +932,39 @@ enum/INITSR: - name: Initalized description: Calendar has been initialized value: 1 +enum/ITSF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/ITSMF: + bit_size: 1 + variants: + - name: TimestampEvent + description: This flag is set by hardware when a timestamp on the internal event occurs + value: 1 +enum/KEY: + bit_size: 8 + variants: + - name: Activate + description: Activate write protection (any value that is not the keys) + value: 0 + - name: Deactivate2 + description: Key 2 + value: 83 + - name: Deactivate1 + description: Key 1 + value: 202 +enum/LPCAL: + bit_size: 1 + variants: + - name: RTCCLK + description: "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required" + value: 0 + - name: CkApre + description: "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode" + value: 1 enum/OSEL: bit_size: 2 variants: @@ -1015,25 +1028,46 @@ enum/SHPFR: - name: ShiftPending description: A shift operation is pending value: 1 -enum/SUBHW: +enum/SSRUF: bit_size: 1 variants: - - name: Sub1 - description: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 value: 1 -enum/TAMPFR: +enum/SSRUIE: bit_size: 1 variants: - - name: Tampered - description: This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input - value: 1 -enum/TAMPFW: - bit_size: 1 - variants: - - name: Clear - description: Flag cleared by software writing 0 + - name: Disabled + description: SSR underflow interrupt disabled value: 0 -enum/TR_PM: + - name: Enabled + description: SSR underflow interrupt enabled + value: 1 +enum/SSRUMF: + bit_size: 1 + variants: + - name: Underflow + description: This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1 + value: 1 +enum/TAMPALRM_PU: + bit_size: 1 + variants: + - name: NoPullUp + description: No pull-up is applied on TAMPALRM output + value: 0 + - name: PullUp + description: A pull-up is applied on TAMPALRM output + value: 1 +enum/TAMPALRM_TYPE: + bit_size: 1 + variants: + - name: PushPull + description: TAMPALRM is push-pull output + value: 0 + - name: OpenDrain + description: TAMPALRM is open-drain output + value: 1 +enum/AMPM: bit_size: 1 variants: - name: AM @@ -1042,15 +1076,6 @@ enum/TR_PM: - name: PM description: PM value: 1 -enum/TSE: - bit_size: 1 - variants: - - name: Disabled - description: Timestamp disabled - value: 0 - - name: Enabled - description: Timestamp enabled - value: 1 enum/TSEDGE: bit_size: 1 variants: @@ -1060,39 +1085,30 @@ enum/TSEDGE: - name: FallingEdge description: RTC_TS input falling edge generates a time-stamp event value: 1 -enum/TSFR: +enum/TSF: bit_size: 1 variants: - name: TimestampEvent description: This flag is set by hardware when a time-stamp event occurs value: 1 -enum/TSFW: +enum/TSMF: bit_size: 1 variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/TSIE: - bit_size: 1 - variants: - - name: Disabled - description: Time-stamp Interrupt disabled - value: 0 - - name: Enabled - description: Time-stamp Interrupt enabled + - name: TimestampEvent + description: This flag is set by hardware when a time-stamp event occurs value: 1 -enum/TSOVFR: +enum/TSOVF: bit_size: 1 variants: - name: Overflow description: This flag is set by hardware when a time-stamp event occurs while TSF is already set value: 1 -enum/TSOVFW: +enum/TSOVMF: bit_size: 1 variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 + - name: Overflow + description: This flag is set by hardware when a time-stamp event occurs while TSF is already set + value: 1 enum/WUCKSEL: bit_size: 3 variants: @@ -1114,35 +1130,17 @@ enum/WUCKSEL: - name: ClockSpareWithOffset description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value value: 6 -enum/WUTE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer disabled - value: 0 - - name: Enabled - description: Wakeup timer enabled - value: 1 -enum/WUTFR: +enum/WUTF: bit_size: 1 variants: - name: Zero description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 value: 1 -enum/WUTFW: +enum/WUTMF: bit_size: 1 variants: - - name: Clear - description: This flag is cleared by software by writing 0 - value: 0 -enum/WUTIE: - bit_size: 1 - variants: - - name: Disabled - description: Wakeup timer interrupt disabled - value: 0 - - name: Enabled - description: Wakeup timer interrupt enabled + - name: Zero + description: This flag is set by hardware when the wakeup auto-reload counter reaches 0 value: 1 enum/WUTWFR: bit_size: 1 diff --git a/data/registers/rtc_wb.yaml b/data/registers/rtc_wb.yaml deleted file mode 100644 index 2afb3ed..0000000 --- a/data/registers/rtc_wb.yaml +++ /dev/null @@ -1,891 +0,0 @@ ---- -block/RTC: - description: Real-time clock - items: - - name: TR - description: time register - byte_offset: 0 - fieldset: TR - - name: DR - description: date register - byte_offset: 4 - fieldset: DR - - name: CR - description: control register - byte_offset: 8 - fieldset: CR - - name: ISR - description: initialization and status register - byte_offset: 12 - fieldset: ISR - - name: PRER - description: prescaler register - byte_offset: 16 - fieldset: PRER - - name: WUTR - description: wakeup timer register - byte_offset: 20 - fieldset: WUTR - - name: ALRMAR - description: alarm A register - byte_offset: 28 - fieldset: ALRMAR - - name: ALRMBR - description: alarm B register - byte_offset: 32 - fieldset: ALRMBR - - name: WPR - description: write protection register - byte_offset: 36 - access: Write - fieldset: WPR - - name: SSR - description: sub second register - byte_offset: 40 - access: Read - fieldset: SSR - - name: SHIFTR - description: shift control register - byte_offset: 44 - access: Write - fieldset: SHIFTR - - name: TSTR - description: time stamp time register - byte_offset: 48 - access: Read - fieldset: TSTR - - name: TSDR - description: time stamp date register - byte_offset: 52 - access: Read - fieldset: TSDR - - name: TSSSR - description: timestamp sub second register - byte_offset: 56 - access: Read - fieldset: TSSSR - - name: CALR - description: calibration register - byte_offset: 60 - fieldset: CALR - - name: TAMPCR - description: tamper configuration register - byte_offset: 64 - fieldset: TAMPCR - - name: ALRMASSR - description: alarm A sub second register - byte_offset: 68 - fieldset: ALRMASSR - - name: ALRMBSSR - description: alarm B sub second register - byte_offset: 72 - fieldset: ALRMBSSR - - name: OR - description: option register - byte_offset: 76 - fieldset: OR - - name: BKP0R - description: backup register - byte_offset: 80 - fieldset: BKP0R - - name: BKP1R - description: backup register - byte_offset: 84 - fieldset: BKP1R - - name: BKP2R - description: backup register - byte_offset: 88 - fieldset: BKP2R - - name: BKP3R - description: backup register - byte_offset: 92 - fieldset: BKP3R - - name: BKP4R - description: backup register - byte_offset: 96 - fieldset: BKP4R - - name: BKP5R - description: backup register - byte_offset: 100 - fieldset: BKP5R - - name: BKP6R - description: backup register - byte_offset: 104 - fieldset: BKP6R - - name: BKP7R - description: backup register - byte_offset: 108 - fieldset: BKP7R - - name: BKP8R - description: backup register - byte_offset: 112 - fieldset: BKP8R - - name: BKP9R - description: backup register - byte_offset: 116 - fieldset: BKP9R - - name: BKP10R - description: backup register - byte_offset: 120 - fieldset: BKP10R - - name: BKP11R - description: backup register - byte_offset: 124 - fieldset: BKP11R - - name: BKP12R - description: backup register - byte_offset: 128 - fieldset: BKP12R - - name: BKP13R - description: backup register - byte_offset: 132 - fieldset: BKP13R - - name: BKP14R - description: backup register - byte_offset: 136 - fieldset: BKP14R - - name: BKP15R - description: backup register - byte_offset: 140 - fieldset: BKP15R - - name: BKP16R - description: backup register - byte_offset: 144 - fieldset: BKP16R - - name: BKP17R - description: backup register - byte_offset: 148 - fieldset: BKP17R - - name: BKP18R - description: backup register - byte_offset: 152 - fieldset: BKP18R - - name: BKP19R - description: backup register - byte_offset: 156 - fieldset: BKP19R -fieldset/ALRMAR: - description: alarm A register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm A seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm A minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm A hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm A date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMASSR: - description: alarm A sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 -fieldset/ALRMBR: - description: alarm B register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MSK1 - description: Alarm B seconds mask - bit_offset: 7 - bit_size: 1 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: MSK2 - description: Alarm B minutes mask - bit_offset: 15 - bit_size: 1 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 - - name: MSK3 - description: Alarm B hours mask - bit_offset: 23 - bit_size: 1 - - name: DU - description: Date units or day in BCD format - bit_offset: 24 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 28 - bit_size: 2 - - name: WDSEL - description: Week day selection - bit_offset: 30 - bit_size: 1 - - name: MSK4 - description: Alarm B date mask - bit_offset: 31 - bit_size: 1 -fieldset/ALRMBSSR: - description: alarm B sub second register - fields: - - name: SS - description: Sub seconds value - bit_offset: 0 - bit_size: 15 - - name: MASKSS - description: Mask the most-significant bits starting at this bit - bit_offset: 24 - bit_size: 4 -fieldset/BKP0R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP10R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP11R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP12R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP13R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP14R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP15R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP16R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP17R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP18R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP19R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP1R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP2R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP3R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP4R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP5R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP6R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP7R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP8R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/BKP9R: - description: backup register - fields: - - name: BKP - description: BKP - bit_offset: 0 - bit_size: 32 -fieldset/CALR: - description: calibration register - fields: - - name: CALM - description: Calibration minus - bit_offset: 0 - bit_size: 9 - - name: CALW16 - description: Use a 16-second calibration cycle period - bit_offset: 13 - bit_size: 1 - - name: CALW8 - description: Use an 8-second calibration cycle period - bit_offset: 14 - bit_size: 1 - - name: CALP - description: Increase frequency of RTC by 488.5 ppm - bit_offset: 15 - bit_size: 1 -fieldset/CR: - description: control register - fields: - - name: WUCKSEL - description: Wakeup clock selection - bit_offset: 0 - bit_size: 3 - - name: TSEDGE - description: Time-stamp event active edge - bit_offset: 3 - bit_size: 1 - - name: REFCKON - description: Reference clock detection enable (50 or 60 Hz) - bit_offset: 4 - bit_size: 1 - - name: BYPSHAD - description: Bypass the shadow registers - bit_offset: 5 - bit_size: 1 - - name: FMT - description: Hour format - bit_offset: 6 - bit_size: 1 - - name: ALRAE - description: Alarm A enable - bit_offset: 8 - bit_size: 1 - - name: ALRBE - description: Alarm B enable - bit_offset: 9 - bit_size: 1 - - name: WUTE - description: Wakeup timer enable - bit_offset: 10 - bit_size: 1 - - name: TSE - description: Time stamp enable - bit_offset: 11 - bit_size: 1 - - name: ALRAIE - description: Alarm A interrupt enable - bit_offset: 12 - bit_size: 1 - - name: ALRBIE - description: Alarm B interrupt enable - bit_offset: 13 - bit_size: 1 - - name: WUTIE - description: Wakeup timer interrupt enable - bit_offset: 14 - bit_size: 1 - - name: TSIE - description: Time-stamp interrupt enable - bit_offset: 15 - bit_size: 1 - - name: ADD1H - description: Add 1 hour (summer time change) - bit_offset: 16 - bit_size: 1 - - name: SUB1H - description: Subtract 1 hour (winter time change) - bit_offset: 17 - bit_size: 1 - - name: BKP - description: Backup - bit_offset: 18 - bit_size: 1 - - name: COSEL - description: Calibration output selection - bit_offset: 19 - bit_size: 1 - - name: POL - description: Output polarity - bit_offset: 20 - bit_size: 1 - - name: OSEL - description: Output selection - bit_offset: 21 - bit_size: 2 - - name: COE - description: Calibration output enable - bit_offset: 23 - bit_size: 1 - - name: ITSE - description: timestamp on internal event enable - bit_offset: 24 - bit_size: 1 -fieldset/DR: - description: date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 - - name: YU - description: Year units in BCD format - bit_offset: 16 - bit_size: 4 - - name: YT - description: Year tens in BCD format - bit_offset: 20 - bit_size: 4 -fieldset/ISR: - description: initialization and status register - fields: - - name: ALRAWF - description: Alarm A write flag - bit_offset: 0 - bit_size: 1 - - name: ALRBWF - description: Alarm B write flag - bit_offset: 1 - bit_size: 1 - - name: WUTWF - description: Wakeup timer write flag - bit_offset: 2 - bit_size: 1 - - name: SHPF - description: Shift operation pending - bit_offset: 3 - bit_size: 1 - - name: INITS - description: Initialization status flag - bit_offset: 4 - bit_size: 1 - - name: RSF - description: Registers synchronization flag - bit_offset: 5 - bit_size: 1 - - name: INITF - description: Initialization flag - bit_offset: 6 - bit_size: 1 - - name: INIT - description: Initialization mode - bit_offset: 7 - bit_size: 1 - - name: ALRAF - description: Alarm A flag - bit_offset: 8 - bit_size: 1 - - name: ALRBF - description: Alarm B flag - bit_offset: 9 - bit_size: 1 - - name: WUTF - description: Wakeup timer flag - bit_offset: 10 - bit_size: 1 - - name: TSF - description: Time-stamp flag - bit_offset: 11 - bit_size: 1 - - name: TSOVF - description: Time-stamp overflow flag - bit_offset: 12 - bit_size: 1 - - name: TAMP1F - description: Tamper detection flag - bit_offset: 13 - bit_size: 1 - - name: TAMP2F - description: RTC_TAMP2 detection flag - bit_offset: 14 - bit_size: 1 - - name: TAMP3F - description: RTC_TAMP3 detection flag - bit_offset: 15 - bit_size: 1 - - name: RECALPF - description: Recalibration pending Flag - bit_offset: 16 - bit_size: 1 - - name: ITSF - description: INTERNAL TIME-STAMP FLAG - bit_offset: 17 - bit_size: 1 -fieldset/OR: - description: option register - fields: - - name: RTC_ALARM_TYPE - description: RTC_ALARM on PC13 output type - bit_offset: 0 - bit_size: 1 - - name: RTC_OUT_RMP - description: RTC_OUT remap - bit_offset: 1 - bit_size: 1 -fieldset/PRER: - description: prescaler register - fields: - - name: PREDIV_S - description: Synchronous prescaler factor - bit_offset: 0 - bit_size: 15 - - name: PREDIV_A - description: Asynchronous prescaler factor - bit_offset: 16 - bit_size: 7 -fieldset/SHIFTR: - description: shift control register - fields: - - name: SUBFS - description: Subtract a fraction of a second - bit_offset: 0 - bit_size: 15 - - name: ADD1S - description: Add one second - bit_offset: 31 - bit_size: 1 -fieldset/SSR: - description: sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 -fieldset/TAMPCR: - description: tamper configuration register - fields: - - name: TAMP1E - description: Tamper 1 detection enable - bit_offset: 0 - bit_size: 1 - - name: TAMP1TRG - description: Active level for tamper 1 - bit_offset: 1 - bit_size: 1 - - name: TAMPIE - description: Tamper interrupt enable - bit_offset: 2 - bit_size: 1 - - name: TAMP2E - description: Tamper 2 detection enable - bit_offset: 3 - bit_size: 1 - - name: TAMP2TRG - description: Active level for tamper 2 - bit_offset: 4 - bit_size: 1 - - name: TAMP3E - description: Tamper 3 detection enable - bit_offset: 5 - bit_size: 1 - - name: TAMP3TRG - description: Active level for tamper 3 - bit_offset: 6 - bit_size: 1 - - name: TAMPTS - description: Activate timestamp on tamper detection event - bit_offset: 7 - bit_size: 1 - - name: TAMPFREQ - description: Tamper sampling frequency - bit_offset: 8 - bit_size: 3 - - name: TAMPFLT - description: Tamper filter count - bit_offset: 11 - bit_size: 2 - - name: TAMPPRCH - description: Tamper precharge duration - bit_offset: 13 - bit_size: 2 - - name: TAMPPUDIS - description: TAMPER pull-up disable - bit_offset: 15 - bit_size: 1 - - name: TAMP1IE - description: Tamper 1 interrupt enable - bit_offset: 16 - bit_size: 1 - - name: TAMP1NOERASE - description: Tamper 1 no erase - bit_offset: 17 - bit_size: 1 - - name: TAMP1MF - description: Tamper 1 mask flag - bit_offset: 18 - bit_size: 1 - - name: TAMP2IE - description: Tamper 2 interrupt enable - bit_offset: 19 - bit_size: 1 - - name: TAMP2NOERASE - description: Tamper 2 no erase - bit_offset: 20 - bit_size: 1 - - name: TAMP2MF - description: Tamper 2 mask flag - bit_offset: 21 - bit_size: 1 - - name: TAMP3IE - description: Tamper 3 interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TAMP3NOERASE - description: Tamper 3 no erase - bit_offset: 23 - bit_size: 1 - - name: TAMP3MF - description: Tamper 3 mask flag - bit_offset: 24 - bit_size: 1 -fieldset/TR: - description: time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/TSDR: - description: time stamp date register - fields: - - name: DU - description: Date units in BCD format - bit_offset: 0 - bit_size: 4 - - name: DT - description: Date tens in BCD format - bit_offset: 4 - bit_size: 2 - - name: MU - description: Month units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MT - description: Month tens in BCD format - bit_offset: 12 - bit_size: 1 - - name: WDU - description: Week day units - bit_offset: 13 - bit_size: 3 -fieldset/TSSSR: - description: timestamp sub second register - fields: - - name: SS - description: Sub second value - bit_offset: 0 - bit_size: 16 -fieldset/TSTR: - description: time stamp time register - fields: - - name: SU - description: Second units in BCD format - bit_offset: 0 - bit_size: 4 - - name: ST - description: Second tens in BCD format - bit_offset: 4 - bit_size: 3 - - name: MNU - description: Minute units in BCD format - bit_offset: 8 - bit_size: 4 - - name: MNT - description: Minute tens in BCD format - bit_offset: 12 - bit_size: 3 - - name: HU - description: Hour units in BCD format - bit_offset: 16 - bit_size: 4 - - name: HT - description: Hour tens in BCD format - bit_offset: 20 - bit_size: 2 - - name: PM - description: AM/PM notation - bit_offset: 22 - bit_size: 1 -fieldset/WPR: - description: write protection register - fields: - - name: KEY - description: Write protection key - bit_offset: 0 - bit_size: 8 -fieldset/WUTR: - description: wakeup timer register - fields: - - name: WUT - description: Wakeup auto-reload value bits - bit_offset: 0 - bit_size: 16 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index d8856ca..896ed9b 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -163,8 +163,22 @@ perimap = [ ('.*:MDIOS:mdios1_v1_0', ('mdios', 'v1', 'MDIOS')), ('.*:QUADSPI:quadspi1_v1_0', ('quadspi', 'v1', 'QUADSPI')), ('STM32F1.*:BKP.*', ('bkp', 'v1', 'BKP')), - ('.*:RTC:rtc2_v2_6', ('rtc', 'v2', 'RTC')), - ('.*:RTC:rtc2_v2_WB', ('rtc', 'wb', 'RTC')), + ('.*:RTC:rtc1_v1_1', ('rtc', 'v1', 'RTC')), + ('STM32F0.*:RTC:rtc2_.*', ('rtc', 'v2f0', 'RTC')), + ('STM32F2.*:RTC:rtc2_.*', ('rtc', 'v2f2', 'RTC')), + ('STM32F3.*:RTC:rtc2_.*', ('rtc', 'v2f3', 'RTC')), + ('STM32F4.*:RTC:rtc2_.*', ('rtc', 'v2f4', 'RTC')), + ('STM32F7.*:RTC:rtc2_.*', ('rtc', 'v2f7', 'RTC')), + ('STM32H7.*:RTC:rtc2_.*', ('rtc', 'v2h7', 'RTC')), + ('STM32L0.*:RTC:rtc2_.*', ('rtc', 'v2l0', 'RTC')), + ('STM32L1.*:RTC:rtc2_.*', ('rtc', 'v2l1', 'RTC')), + ('STM32L4.*:RTC:rtc2_.*', ('rtc', 'v2l4', 'RTC')), + ('STM32WB.*:RTC:rtc2_.*', ('rtc', 'v2wb', 'RTC')), + ('STM32U5.*:RTC:rtc2_.*', ('rtc', 'v3u5', 'RTC')), # Cube says v2, but it's v3 with security stuff + ('.*:RTC:rtc3_v1_0', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v1_1', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v2_0', ('rtc', 'v3', 'RTC')), + ('.*:RTC:rtc3_v3_0', ('rtc', 'v3', 'RTC')), ('.*:SAI:sai1_v1_1', ('sai', 'v1', 'SAI')), ('.*:SDIO:sdmmc_v1_2', ('sdmmc', 'v1', 'SDMMC')), ('.*:SDMMC:sdmmc_v1_3', ('sdmmc', 'v1', 'SDMMC')),