diff --git a/data/registers/rng_v1.yaml b/data/registers/rng_v1.yaml index 896d227..bb95691 100644 --- a/data/registers/rng_v1.yaml +++ b/data/registers/rng_v1.yaml @@ -25,6 +25,10 @@ fieldset/CR: description: Interrupt enable bit_offset: 3 bit_size: 1 + - name: CED + description: Clock error detection + bit_offset: 5 + bit_size: 1 fieldset/SR: description: status register fields: diff --git a/data/registers/rng_v2.yaml b/data/registers/rng_v2.yaml index f445f77..a90b9a8 100644 --- a/data/registers/rng_v2.yaml +++ b/data/registers/rng_v2.yaml @@ -17,15 +17,16 @@ block/RNG: - name: HTCR description: health test control register byte_offset: 16 + fieldset: HTCR fieldset/CR: description: control register fields: - name: RNGEN - description: True random number generator enable + description: Random number generator enable bit_offset: 2 bit_size: 1 - name: IE - description: Interrupt Enable + description: Interrupt enable bit_offset: 3 bit_size: 1 - name: CED @@ -36,6 +37,7 @@ fieldset/CR: description: RNG configuration 3 bit_offset: 8 bit_size: 4 + enum: RNG_CONFIG3 - name: NISTC description: Non NIST compliant bit_offset: 12 @@ -45,14 +47,17 @@ fieldset/CR: description: RNG configuration 2 bit_offset: 13 bit_size: 3 + enum: RNG_CONFIG2 - name: CLKDIV description: Clock divider factor bit_offset: 16 bit_size: 4 + enum: CLKDIV - name: RNG_CONFIG1 description: RNG configuration 1 bit_offset: 20 bit_size: 6 + enum: RNG_CONFIG1 - name: CONDRST description: Conditioning soft reset bit_offset: 30 @@ -61,18 +66,11 @@ fieldset/CR: description: Config Lock bit_offset: 31 bit_size: 1 -fieldset/HTCR: - description: health test control register - fields: - - name: HTCFG - description: health test configuration - bit_offset: 0 - bit_size: 32 fieldset/SR: description: status register fields: - name: DRDY - description: Data Ready + description: Data ready bit_offset: 0 bit_size: 1 - name: CECS @@ -91,6 +89,74 @@ fieldset/SR: description: Seed error interrupt status bit_offset: 6 bit_size: 1 +fieldset/HTCR: + description: Health test control register + fields: + - name: HTCFG + description: Health test configuration + bit_offset: 0 + bit_size: 32 + enum: HTCFG +enum/CLKDIV: + bit_size: 4 + variants: + - name: NoDiv + description: Internal RNG clock after divider is similar to incoming RNG clock + value: 0 + - name: Div_2_1 + description: Divide RNG clock by 2^1 + value: 1 + - name: Div_2_2 + description: Divide RNG clock by 2^2 + value: 2 + - name: Div_2_3 + description: Divide RNG clock by 2^3 + value: 3 + - name: Div_2_4 + description: Divide RNG clock by 2^4 + value: 4 + - name: Div_2_5 + description: Divide RNG clock by 2^5 + value: 5 + - name: Div_2_6 + description: Divide RNG clock by 2^6 + value: 6 + - name: Div_2_7 + description: Divide RNG clock by 2^7 + value: 7 + - name: Div_2_8 + description: Divide RNG clock by 2^8 + value: 8 + - name: Div_2_9 + description: Divide RNG clock by 2^9 + value: 9 + - name: Div_2_10 + description: Divide RNG clock by 2^10 + value: 10 + - name: Div_2_11 + description: Divide RNG clock by 2^11 + value: 11 + - name: Div_2_12 + description: Divide RNG clock by 2^12 + value: 12 + - name: Div_2_13 + description: Divide RNG clock by 2^13 + value: 13 + - name: Div_2_14 + description: Divide RNG clock by 2^14 + value: 14 + - name: Div_2_15 + description: Divide RNG clock by 2^15 + value: 15 +enum/HTCFG: + bit_size: 32 + variants: + - name: Recommended + description: Recommended value for RNG certification (0x0000_AA74) + value: 43636 + - name: Magic + description: Magic number to be written before any write (0x1759_0ABC) + value: 391711420 enum/NISTC: bit_size: 1 variants: @@ -100,3 +166,27 @@ enum/NISTC: - name: Custom description: Custom values for NIST compliant RNG value: 1 +enum/RNG_CONFIG1: + bit_size: 6 + variants: + - name: ConfigA + description: Recommended value for config A (NIST certifiable) + value: 15 + - name: ConfigB + description: Recommended value for config B (not NIST certifiable) + value: 24 +enum/RNG_CONFIG2: + bit_size: 3 + variants: + - name: ConfigA_B + description: Recommended value for config A and B + value: 0 +enum/RNG_CONFIG3: + bit_size: 4 + variants: + - name: ConfigB + description: Recommended value for config B (not NIST certifiable) + value: 0 + - name: ConfigA + description: Recommended value for config A (NIST certifiable) + value: 13 diff --git a/data/registers/rng_v3.yaml b/data/registers/rng_v3.yaml new file mode 100644 index 0000000..5530968 --- /dev/null +++ b/data/registers/rng_v3.yaml @@ -0,0 +1,196 @@ +--- +block/RNG: + description: Random number generator + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SR + description: status register + byte_offset: 4 + fieldset: SR + - name: DR + description: data register + byte_offset: 8 + access: Read + - name: HTCR + description: health test control register + byte_offset: 16 + fieldset: HTCR +fieldset/CR: + description: control register + fields: + - name: RNGEN + description: Random number generator enable + bit_offset: 2 + bit_size: 1 + - name: IE + description: Interrupt enable + bit_offset: 3 + bit_size: 1 + - name: CED + description: Clock error detection + bit_offset: 5 + bit_size: 1 + - name: ARDIS + description: Auto reset disable + bit_offset: 7 + bit_size: 1 + - name: RNG_CONFIG3 + description: RNG configuration 3 + bit_offset: 8 + bit_size: 4 + enum: RNG_CONFIG3 + - name: NISTC + description: Non NIST compliant + bit_offset: 12 + bit_size: 1 + enum: NISTC + - name: RNG_CONFIG2 + description: RNG configuration 2 + bit_offset: 13 + bit_size: 3 + enum: RNG_CONFIG2 + - name: CLKDIV + description: Clock divider factor + bit_offset: 16 + bit_size: 4 + enum: CLKDIV + - name: RNG_CONFIG1 + description: RNG configuration 1 + bit_offset: 20 + bit_size: 6 + enum: RNG_CONFIG1 + - name: CONDRST + description: Conditioning soft reset + bit_offset: 30 + bit_size: 1 + - name: CONFIGLOCK + description: Config Lock + bit_offset: 31 + bit_size: 1 +fieldset/SR: + description: status register + fields: + - name: DRDY + description: Data ready + bit_offset: 0 + bit_size: 1 + - name: CECS + description: Clock error current status + bit_offset: 1 + bit_size: 1 + - name: SECS + description: Seed error current status + bit_offset: 2 + bit_size: 1 + - name: CEIS + description: Clock error interrupt status + bit_offset: 5 + bit_size: 1 + - name: SEIS + description: Seed error interrupt status + bit_offset: 6 + bit_size: 1 +fieldset/HTCR: + description: Health test control register + fields: + - name: HTCFG + description: Health test configuration + bit_offset: 0 + bit_size: 32 + enum: HTCFG +enum/CLKDIV: + bit_size: 4 + variants: + - name: NoDiv + description: Internal RNG clock after divider is similar to incoming RNG clock + value: 0 + - name: Div_2_1 + description: Divide RNG clock by 2^1 + value: 1 + - name: Div_2_2 + description: Divide RNG clock by 2^2 + value: 2 + - name: Div_2_3 + description: Divide RNG clock by 2^3 + value: 3 + - name: Div_2_4 + description: Divide RNG clock by 2^4 + value: 4 + - name: Div_2_5 + description: Divide RNG clock by 2^5 + value: 5 + - name: Div_2_6 + description: Divide RNG clock by 2^6 + value: 6 + - name: Div_2_7 + description: Divide RNG clock by 2^7 + value: 7 + - name: Div_2_8 + description: Divide RNG clock by 2^8 + value: 8 + - name: Div_2_9 + description: Divide RNG clock by 2^9 + value: 9 + - name: Div_2_10 + description: Divide RNG clock by 2^10 + value: 10 + - name: Div_2_11 + description: Divide RNG clock by 2^11 + value: 11 + - name: Div_2_12 + description: Divide RNG clock by 2^12 + value: 12 + - name: Div_2_13 + description: Divide RNG clock by 2^13 + value: 13 + - name: Div_2_14 + description: Divide RNG clock by 2^14 + value: 14 + - name: Div_2_15 + description: Divide RNG clock by 2^15 + value: 15 +enum/HTCFG: + bit_size: 32 + variants: + - name: Recommended + description: Recommended value for RNG certification (0x0000_AA74) + value: 43636 + - name: Magic + description: Magic number to be written before any write (0x1759_0ABC) + value: 391711420 +enum/NISTC: + bit_size: 1 + variants: + - name: Default + description: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used + value: 0 + - name: Custom + description: Custom values for NIST compliant RNG + value: 1 +enum/RNG_CONFIG1: + bit_size: 6 + variants: + - name: ConfigA + description: Recommended value for config A (NIST certifiable) + value: 15 + - name: ConfigB + description: Recommended value for config B (not NIST certifiable) + value: 24 +enum/RNG_CONFIG2: + bit_size: 3 + variants: + - name: ConfigA_B + description: Recommended value for config A and B + value: 0 +enum/RNG_CONFIG3: + bit_size: 4 + variants: + - name: ConfigB + description: Recommended value for config B (not NIST certifiable) + value: 0 + - name: ConfigA + description: Recommended value for config A (NIST certifiable) + value: 13 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index b0e0f14..9320984 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -130,12 +130,18 @@ impl PeriMatcher { (".*:LPUART:sci3_v1_2", ("usart", "v4", "LPUART")), (".*:LPUART:sci3_v1_3", ("usart", "v4", "LPUART")), (".*:LPUART:sci3_v1_4", ("usart", "v4", "LPUART")), + ("STM32[HU]5.*:RNG:.*", ("rng", "v3", "RNG")), ("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")), - (".*:RNG:rng1_v1_1", ("rng", "v1", "RNG")), - (".*:RNG:rng1_v2_0", ("rng", "v1", "RNG")), - (".*:RNG:rng1_v2_1", ("rng", "v1", "RNG")), - (".*:RNG:rng1_v3_1", ("rng", "v2", "RNG")), - (".*:RNG:rng1_v4_1", ("rng", "v2", "RNG")), + ("STM32L4[PQ]5.*:RNG:.*", ("rng", "v2", "RNG")), + ("STM32WL.*:RNG:.*", ("rng", "v2", "RNG")), + ("STM32F2.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32F4.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32F7.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32L0.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32L4.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32H7.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32G0.*:RNG:.*", ("rng", "v1", "RNG")), + ("STM32G4.*:RNG:.*", ("rng", "v1", "RNG")), (".*:SPI:spi2_v1_4", ("spi", "f1", "SPI")), (".*:SPI:spi2s1_v2_1", ("spi", "v1", "SPI")), (".*:SPI:spi2s1_v2_2", ("spi", "v1", "SPI")),