rcc: more accurate f0 mapping.
This commit is contained in:
Dario Nieuwenhuis
parent
156cb15b80
commit
7734584b20
995
data/registers/rcc_f0v1.yaml
Normal file
995
data/registers/rcc_f0v1.yaml
Normal file
@ -0,0 +1,995 @@
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block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: CFGR
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description: Clock configuration register (RCC_CFGR)
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byte_offset: 4
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fieldset: CFGR
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- name: CIR
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description: Clock interrupt register (RCC_CIR)
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byte_offset: 8
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fieldset: CIR
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- name: APB2RSTR
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description: APB2 peripheral reset register (RCC_APB2RSTR)
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byte_offset: 12
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fieldset: APB2RSTR
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- name: APB1RSTR
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description: APB1 peripheral reset register (RCC_APB1RSTR)
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byte_offset: 16
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fieldset: APB1RSTR
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- name: AHBENR
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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byte_offset: 20
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fieldset: AHBENR
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- name: APB2ENR
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description: APB2 peripheral clock enable register (RCC_APB2ENR)
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byte_offset: 24
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fieldset: APB2ENR
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- name: APB1ENR
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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byte_offset: 28
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fieldset: APB1ENR
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- name: BDCR
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description: Backup domain control register (RCC_BDCR)
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byte_offset: 32
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fieldset: BDCR
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- name: CSR
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description: Control/status register (RCC_CSR)
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byte_offset: 36
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fieldset: CSR
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- name: AHBRSTR
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description: AHB peripheral reset register
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byte_offset: 40
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fieldset: AHBRSTR
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- name: CFGR2
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description: Clock configuration register 2
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byte_offset: 44
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fieldset: CFGR2
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- name: CFGR3
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description: Clock configuration register 3
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byte_offset: 48
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fieldset: CFGR3
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- name: CR2
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description: Clock control register 2
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byte_offset: 52
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fieldset: CR2
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fieldset/AHBENR:
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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fields:
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- name: DMAEN
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description: DMA clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 1
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bit_size: 1
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- name: SRAMEN
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description: SRAM interface clock enable
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bit_offset: 2
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bit_size: 1
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- name: FLASHEN
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description: FLASH clock enable
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bit_offset: 4
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 6
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bit_size: 1
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- name: GPIOAEN
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description: I/O port A clock enable
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bit_offset: 17
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bit_size: 1
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- name: GPIOBEN
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description: I/O port B clock enable
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bit_offset: 18
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bit_size: 1
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- name: GPIOCEN
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description: I/O port C clock enable
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bit_offset: 19
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bit_size: 1
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- name: GPIODEN
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description: I/O port D clock enable
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bit_offset: 20
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bit_size: 1
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- name: GPIOEEN
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description: I/O port E clock enable
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bit_offset: 21
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bit_size: 1
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- name: GPIOFEN
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description: I/O port F clock enable
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bit_offset: 22
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bit_size: 1
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- name: TSCEN
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description: Touch sensing controller clock enable
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bit_offset: 24
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bit_size: 1
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fieldset/AHBRSTR:
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description: AHB peripheral reset register
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fields:
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- name: GPIOARST
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description: I/O port A reset
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bit_offset: 17
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bit_size: 1
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- name: GPIOBRST
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description: I/O port B reset
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bit_offset: 18
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bit_size: 1
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- name: GPIOCRST
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description: I/O port C reset
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bit_offset: 19
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bit_size: 1
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- name: GPIODRST
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description: I/O port D reset
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bit_offset: 20
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bit_size: 1
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- name: GPIOERST
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description: I/O port E reset
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bit_offset: 21
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bit_size: 1
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- name: GPIOFRST
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description: I/O port F reset
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bit_offset: 22
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bit_size: 1
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- name: TSCRST
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description: Touch sensing controller reset
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bit_offset: 24
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bit_size: 1
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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fields:
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- name: TIM2EN
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description: Timer 2 clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM3EN
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description: Timer 3 clock enable
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bit_offset: 1
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bit_size: 1
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- name: TIM6EN
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description: Timer 6 clock enable
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bit_offset: 4
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bit_size: 1
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- name: TIM7EN
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description: TIM7 timer clock enable
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bit_offset: 5
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bit_size: 1
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- name: TIM14EN
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description: Timer 14 clock enable
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bit_offset: 8
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bit_size: 1
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- name: WWDGEN
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description: Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: SPI 2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: USART2EN
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description: USART 2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: USART3EN
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description: USART3 clock enable
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bit_offset: 18
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bit_size: 1
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- name: USART4EN
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description: USART4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: USART5EN
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description: USART5 clock enable
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bit_offset: 20
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bit_size: 1
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- name: I2C1EN
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description: I2C 1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C 2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: USBEN
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description: USB interface clock enable
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bit_offset: 23
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bit_size: 1
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- name: CANEN
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description: CAN interface clock enable
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bit_offset: 25
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bit_size: 1
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- name: CRSEN
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description: Clock Recovery System interface clock enable
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bit_offset: 27
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: DACEN
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description: DAC interface clock enable
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bit_offset: 29
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bit_size: 1
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- name: CECEN
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description: HDMI CEC interface clock enable
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bit_offset: 30
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bit_size: 1
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fieldset/APB1RSTR:
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description: APB1 peripheral reset register (RCC_APB1RSTR)
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fields:
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- name: TIM2RST
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description: Timer 2 reset
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bit_offset: 0
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bit_size: 1
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- name: TIM3RST
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description: Timer 3 reset
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bit_offset: 1
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bit_size: 1
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- name: TIM6RST
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description: Timer 6 reset
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bit_offset: 4
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bit_size: 1
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- name: TIM7RST
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description: TIM7 timer reset
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bit_offset: 5
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bit_size: 1
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- name: TIM14RST
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description: Timer 14 reset
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bit_offset: 8
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bit_size: 1
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- name: WWDGRST
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description: Window watchdog reset
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bit_offset: 11
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bit_size: 1
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- name: SPI2RST
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description: SPI2 reset
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bit_offset: 14
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bit_size: 1
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- name: USART2RST
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description: USART 2 reset
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bit_offset: 17
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bit_size: 1
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- name: USART3RST
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description: USART3 reset
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bit_offset: 18
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bit_size: 1
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- name: USART4RST
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description: USART4 reset
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bit_offset: 19
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bit_size: 1
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- name: USART5RST
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description: USART5 reset
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bit_offset: 20
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bit_size: 1
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- name: I2C1RST
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description: I2C1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C2 reset
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bit_offset: 22
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bit_size: 1
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- name: USBRST
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description: USB interface reset
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bit_offset: 23
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bit_size: 1
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- name: CANRST
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description: CAN interface reset
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bit_offset: 25
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bit_size: 1
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- name: CRSRST
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description: Clock Recovery System interface reset
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bit_offset: 27
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bit_size: 1
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- name: PWRRST
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description: Power interface reset
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bit_offset: 28
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bit_size: 1
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- name: DACRST
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description: DAC interface reset
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bit_offset: 29
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bit_size: 1
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- name: CECRST
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description: HDMI CEC reset
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bit_offset: 30
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bit_size: 1
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fieldset/APB2ENR:
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description: APB2 peripheral clock enable register (RCC_APB2ENR)
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fields:
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- name: SYSCFGEN
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description: SYSCFG clock enable
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bit_offset: 0
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bit_size: 1
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- name: USART6EN
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description: USART6 clock enable
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bit_offset: 5
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bit_size: 1
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- name: USART7EN
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description: USART7 clock enable
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bit_offset: 6
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bit_size: 1
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- name: USART8EN
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description: USART8 clock enable
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bit_offset: 7
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bit_size: 1
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- name: ADCEN
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description: ADC 1 interface clock enable
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bit_offset: 9
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bit_size: 1
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- name: TIM1EN
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description: TIM1 Timer clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI1EN
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description: SPI 1 clock enable
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bit_offset: 12
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bit_size: 1
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- name: USART1EN
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description: USART1 clock enable
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bit_offset: 14
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bit_size: 1
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- name: TIM15EN
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description: TIM15 timer clock enable
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bit_offset: 16
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bit_size: 1
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- name: TIM16EN
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description: TIM16 timer clock enable
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bit_offset: 17
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bit_size: 1
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- name: TIM17EN
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description: TIM17 timer clock enable
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bit_offset: 18
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bit_size: 1
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- name: DBGMCUEN
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description: MCU debug module clock enable
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bit_offset: 22
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bit_size: 1
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fieldset/APB2RSTR:
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description: APB2 peripheral reset register (RCC_APB2RSTR)
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fields:
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- name: SYSCFGRST
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description: SYSCFG and COMP reset
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bit_offset: 0
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bit_size: 1
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- name: USART6RST
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description: USART6 reset
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bit_offset: 5
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bit_size: 1
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- name: USART7RST
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description: USART7 reset
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bit_offset: 6
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bit_size: 1
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- name: USART8RST
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description: USART8 reset
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bit_offset: 7
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bit_size: 1
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- name: ADCRST
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description: ADC interface reset
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bit_offset: 9
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bit_size: 1
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- name: TIM1RST
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description: TIM1 timer reset
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bit_offset: 11
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bit_size: 1
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- name: SPI1RST
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description: SPI 1 reset
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bit_offset: 12
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bit_size: 1
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- name: USART1RST
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description: USART1 reset
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bit_offset: 14
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bit_size: 1
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- name: TIM15RST
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description: TIM15 timer reset
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bit_offset: 16
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bit_size: 1
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- name: TIM16RST
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description: TIM16 timer reset
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bit_offset: 17
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bit_size: 1
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- name: TIM17RST
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description: TIM17 timer reset
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bit_offset: 18
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bit_size: 1
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- name: DBGMCURST
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description: Debug MCU reset
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bit_offset: 22
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bit_size: 1
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fieldset/BDCR:
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description: Backup domain control register (RCC_BDCR)
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fields:
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- name: LSEON
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description: External Low Speed oscillator enable
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bit_offset: 0
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bit_size: 1
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- name: LSERDY
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description: External Low Speed oscillator ready
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bit_offset: 1
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bit_size: 1
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- name: LSEBYP
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description: External Low Speed oscillator bypass
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bit_offset: 2
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bit_size: 1
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- name: LSEDRV
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description: LSE oscillator drive capability
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bit_offset: 3
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bit_size: 2
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enum: LSEDRV
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- name: RTCSEL
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description: RTC clock source selection
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bit_offset: 8
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bit_size: 2
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enum: RTCSEL
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- name: RTCEN
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description: RTC clock enable
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bit_offset: 15
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bit_size: 1
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- name: BDRST
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description: Backup domain software reset
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bit_offset: 16
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bit_size: 1
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fieldset/CFGR:
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description: Clock configuration register (RCC_CFGR)
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fields:
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- name: SW
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description: System clock Switch
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bit_offset: 0
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bit_size: 2
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enum: SW
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- name: SWS
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description: System Clock Switch Status
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bit_offset: 2
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bit_size: 2
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enum: SW
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- name: HPRE
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description: AHB prescaler
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bit_offset: 4
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bit_size: 4
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enum: HPRE
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- name: PPRE
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description: APB Low speed prescaler (APB1)
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bit_offset: 8
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bit_size: 3
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enum: PPRE
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- name: ADCPRE
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description: APCPRE is deprecated. See ADC field in CFGR2 register.
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bit_offset: 14
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bit_size: 1
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- name: PLLSRC
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description: PLL input clock source
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bit_offset: 16
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bit_size: 1
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enum: PLLSRC
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- name: PLLXTPRE
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description: HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning
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bit_offset: 17
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bit_size: 1
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enum: PLLXTPRE
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- name: PLLMUL
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description: PLL Multiplication Factor
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bit_offset: 18
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bit_size: 4
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enum: PLLMUL
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- name: MCOSEL
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description: Microcontroller clock output
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bit_offset: 24
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bit_size: 4
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enum: MCOSEL
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fieldset/CFGR2:
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description: Clock configuration register 2
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fields:
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- name: PREDIV
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description: PREDIV division factor
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bit_offset: 0
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bit_size: 4
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enum: PREDIV
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fieldset/CFGR3:
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description: Clock configuration register 3
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fields:
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- name: USART1SW
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description: USART1 clock source selection
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bit_offset: 0
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bit_size: 2
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enum: USARTSW
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- name: I2C1SW
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description: I2C1 clock source selection
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bit_offset: 4
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bit_size: 1
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enum: ICSW
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- name: CECSW
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description: HDMI CEC clock source selection
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bit_offset: 6
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bit_size: 1
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enum: CECSW
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- name: USBSW
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description: USB clock source selection
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bit_offset: 7
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bit_size: 1
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enum: USBSW
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- name: ADCSW
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description: ADCSW is deprecated. See ADC field in CFGR2 register.
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bit_offset: 8
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bit_size: 1
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- name: USART2SW
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description: USART2 clock source selection
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bit_offset: 16
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bit_size: 2
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enum: USARTSW
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- name: USART3SW
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description: USART3 clock source
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bit_offset: 18
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bit_size: 2
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enum: USARTSW
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fieldset/CIR:
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||||
description: Clock interrupt register (RCC_CIR)
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||||
fields:
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||||
- name: LSIRDYF
|
||||
description: LSI Ready Interrupt flag
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||||
bit_offset: 0
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||||
bit_size: 1
|
||||
- name: LSERDYF
|
||||
description: LSE Ready Interrupt flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HSIRDYF
|
||||
description: HSI Ready Interrupt flag
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HSERDYF
|
||||
description: HSE Ready Interrupt flag
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: PLLRDYF
|
||||
description: PLL Ready Interrupt flag
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: HSI14RDYF
|
||||
description: HSI14 ready interrupt flag
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: CSSF
|
||||
description: Clock Security System Interrupt flag
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: LSIRDYIE
|
||||
description: LSI Ready Interrupt Enable
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LSERDYIE
|
||||
description: LSE Ready Interrupt Enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: HSIRDYIE
|
||||
description: HSI Ready Interrupt Enable
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: HSERDYIE
|
||||
description: HSE Ready Interrupt Enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: PLLRDYIE
|
||||
description: PLL Ready Interrupt Enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: HSI14RDYIE
|
||||
description: HSI14 ready interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: LSIRDYC
|
||||
description: LSI Ready Interrupt Clear
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: LSERDYC
|
||||
description: LSE Ready Interrupt Clear
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: HSIRDYC
|
||||
description: HSI Ready Interrupt Clear
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: HSERDYC
|
||||
description: HSE Ready Interrupt Clear
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: PLLRDYC
|
||||
description: PLL Ready Interrupt Clear
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: HSI14RDYC
|
||||
description: HSI 14 MHz Ready Interrupt Clear
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: CSSC
|
||||
description: Clock security system interrupt clear
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Clock control register
|
||||
fields:
|
||||
- name: HSION
|
||||
description: Internal High Speed clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: HSIRDY
|
||||
description: Internal High Speed clock ready flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HSITRIM
|
||||
description: Internal High Speed clock trimming
|
||||
bit_offset: 3
|
||||
bit_size: 5
|
||||
- name: HSICAL
|
||||
description: Internal High Speed clock Calibration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
- name: HSEON
|
||||
description: External High Speed clock enable
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: HSERDY
|
||||
description: External High Speed clock ready flag
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: HSEBYP
|
||||
description: External High Speed clock Bypass
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: CSSON
|
||||
description: Clock Security System enable
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: PLLON
|
||||
description: PLL enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: PLLRDY
|
||||
description: PLL clock ready flag
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/CR2:
|
||||
description: Clock control register 2
|
||||
fields:
|
||||
- name: HSI14ON
|
||||
description: HSI14 clock enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: HSI14RDY
|
||||
description: HR14 clock ready flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: HSI14DIS
|
||||
description: HSI14 clock request from ADC disable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: HSI14TRIM
|
||||
description: HSI14 clock trimming
|
||||
bit_offset: 3
|
||||
bit_size: 5
|
||||
- name: HSI14CAL
|
||||
description: HSI14 clock calibration
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
fieldset/CSR:
|
||||
description: Control/status register (RCC_CSR)
|
||||
fields:
|
||||
- name: LSION
|
||||
description: Internal low speed oscillator enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: LSIRDY
|
||||
description: Internal low speed oscillator ready
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: V18PWRRSTF
|
||||
description: 1.8 V domain reset flag
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: RMVF
|
||||
description: Remove reset flag
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: OBLRSTF
|
||||
description: Option byte loader reset flag
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: PINRSTF
|
||||
description: PIN reset flag
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: PORRSTF
|
||||
description: POR/PDR reset flag
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: SFTRSTF
|
||||
description: Software reset flag
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: IWDGRSTF
|
||||
description: Independent watchdog reset flag
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: WWDGRSTF
|
||||
description: Window watchdog reset flag
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPWRRSTF
|
||||
description: Low-power reset flag
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum/CECSW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HSI_DIV_244
|
||||
description: HSI clock divided by 244 selected as CEC clock source
|
||||
value: 0
|
||||
- name: LSE
|
||||
description: LSE clock selected as CEC clock source
|
||||
value: 1
|
||||
enum/HPRE:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: SYSCLK not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: SYSCLK divided by 2
|
||||
value: 8
|
||||
- name: Div4
|
||||
description: SYSCLK divided by 4
|
||||
value: 9
|
||||
- name: Div8
|
||||
description: SYSCLK divided by 8
|
||||
value: 10
|
||||
- name: Div16
|
||||
description: SYSCLK divided by 16
|
||||
value: 11
|
||||
- name: Div64
|
||||
description: SYSCLK divided by 64
|
||||
value: 12
|
||||
- name: Div128
|
||||
description: SYSCLK divided by 128
|
||||
value: 13
|
||||
- name: Div256
|
||||
description: SYSCLK divided by 256
|
||||
value: 14
|
||||
- name: Div512
|
||||
description: SYSCLK divided by 512
|
||||
value: 15
|
||||
enum/ICSW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HSI
|
||||
description: HSI clock selected as I2C clock source
|
||||
value: 0
|
||||
- name: SYS
|
||||
description: SYSCLK clock selected as I2C clock source
|
||||
value: 1
|
||||
enum/LSEDRV:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Low
|
||||
description: Low driving capability
|
||||
value: 0
|
||||
- name: MediumHigh
|
||||
description: Medium high driving capability
|
||||
value: 1
|
||||
- name: MediumLow
|
||||
description: Medium low driving capability
|
||||
value: 2
|
||||
- name: High
|
||||
description: High driving capability
|
||||
value: 3
|
||||
enum/MCOSEL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: DISABLE
|
||||
description: MCO output disabled, no clock on MCO
|
||||
value: 0
|
||||
- name: HSI14
|
||||
description: Internal RC 14 MHz (HSI14) oscillator clock selected
|
||||
value: 1
|
||||
- name: LSI
|
||||
description: Internal low speed (LSI) oscillator clock selected
|
||||
value: 2
|
||||
- name: LSE
|
||||
description: External low speed (LSE) oscillator clock selected
|
||||
value: 3
|
||||
- name: SYS
|
||||
description: System clock selected
|
||||
value: 4
|
||||
- name: HSI
|
||||
description: Internal RC 8 MHz (HSI) oscillator clock selected
|
||||
value: 5
|
||||
- name: HSE
|
||||
description: External 4-32 MHz (HSE) oscillator clock selected
|
||||
value: 6
|
||||
- name: PLL
|
||||
description: PLL clock selected divided by 2
|
||||
value: 7
|
||||
enum/PLLMUL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Mul2
|
||||
description: PLL input clock x2
|
||||
value: 0
|
||||
- name: Mul3
|
||||
description: PLL input clock x3
|
||||
value: 1
|
||||
- name: Mul4
|
||||
description: PLL input clock x4
|
||||
value: 2
|
||||
- name: Mul5
|
||||
description: PLL input clock x5
|
||||
value: 3
|
||||
- name: Mul6
|
||||
description: PLL input clock x6
|
||||
value: 4
|
||||
- name: Mul7
|
||||
description: PLL input clock x7
|
||||
value: 5
|
||||
- name: Mul8
|
||||
description: PLL input clock x8
|
||||
value: 6
|
||||
- name: Mul9
|
||||
description: PLL input clock x9
|
||||
value: 7
|
||||
- name: Mul10
|
||||
description: PLL input clock x10
|
||||
value: 8
|
||||
- name: Mul11
|
||||
description: PLL input clock x11
|
||||
value: 9
|
||||
- name: Mul12
|
||||
description: PLL input clock x12
|
||||
value: 10
|
||||
- name: Mul13
|
||||
description: PLL input clock x13
|
||||
value: 11
|
||||
- name: Mul14
|
||||
description: PLL input clock x14
|
||||
value: 12
|
||||
- name: Mul15
|
||||
description: PLL input clock x15
|
||||
value: 13
|
||||
- name: Mul16
|
||||
description: PLL input clock x16
|
||||
value: 14
|
||||
enum/PLLSRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HSI_Div2
|
||||
description: HSI divided by 2 selected as PLL input clock
|
||||
value: 0
|
||||
- name: HSE_Div_PREDIV
|
||||
description: HSE divided by PREDIV selected as PLL input clock
|
||||
value: 1
|
||||
enum/PLLXTPRE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Div1
|
||||
description: HSE clock not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: HSE clock divided by 2
|
||||
value: 1
|
||||
enum/PPRE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Div1
|
||||
description: HCLK not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: HCLK divided by 2
|
||||
value: 4
|
||||
- name: Div4
|
||||
description: HCLK divided by 4
|
||||
value: 5
|
||||
- name: Div8
|
||||
description: HCLK divided by 8
|
||||
value: 6
|
||||
- name: Div16
|
||||
description: HCLK divided by 16
|
||||
value: 7
|
||||
enum/PREDIV:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: Div1
|
||||
description: PREDIV input clock not divided
|
||||
value: 0
|
||||
- name: Div2
|
||||
description: PREDIV input clock divided by 2
|
||||
value: 1
|
||||
- name: Div3
|
||||
description: PREDIV input clock divided by 3
|
||||
value: 2
|
||||
- name: Div4
|
||||
description: PREDIV input clock divided by 4
|
||||
value: 3
|
||||
- name: Div5
|
||||
description: PREDIV input clock divided by 5
|
||||
value: 4
|
||||
- name: Div6
|
||||
description: PREDIV input clock divided by 6
|
||||
value: 5
|
||||
- name: Div7
|
||||
description: PREDIV input clock divided by 7
|
||||
value: 6
|
||||
- name: Div8
|
||||
description: PREDIV input clock divided by 8
|
||||
value: 7
|
||||
- name: Div9
|
||||
description: PREDIV input clock divided by 9
|
||||
value: 8
|
||||
- name: Div10
|
||||
description: PREDIV input clock divided by 10
|
||||
value: 9
|
||||
- name: Div11
|
||||
description: PREDIV input clock divided by 11
|
||||
value: 10
|
||||
- name: Div12
|
||||
description: PREDIV input clock divided by 12
|
||||
value: 11
|
||||
- name: Div13
|
||||
description: PREDIV input clock divided by 13
|
||||
value: 12
|
||||
- name: Div14
|
||||
description: PREDIV input clock divided by 14
|
||||
value: 13
|
||||
- name: Div15
|
||||
description: PREDIV input clock divided by 15
|
||||
value: 14
|
||||
- name: Div16
|
||||
description: PREDIV input clock divided by 16
|
||||
value: 15
|
||||
enum/RTCSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: DISABLE
|
||||
description: No clock
|
||||
value: 0
|
||||
- name: LSE
|
||||
description: LSE oscillator clock used as RTC clock
|
||||
value: 1
|
||||
- name: LSI
|
||||
description: LSI oscillator clock used as RTC clock
|
||||
value: 2
|
||||
- name: HSE
|
||||
description: HSE oscillator clock divided by a prescaler used as RTC clock
|
||||
value: 3
|
||||
enum/SW:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: HSI
|
||||
description: HSI oscillator used as system clock
|
||||
value: 0
|
||||
- name: HSE
|
||||
description: HSE oscillator used as system clock
|
||||
value: 1
|
||||
- name: PLL1_P
|
||||
description: PLL used as system clock
|
||||
value: 2
|
||||
enum/USARTSW:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: PCLK1
|
||||
description: PCLK selected as USART clock source
|
||||
value: 0
|
||||
- name: SYS
|
||||
description: SYSCLK selected as USART clock source
|
||||
value: 1
|
||||
- name: LSE
|
||||
description: LSE selected as USART clock source
|
||||
value: 2
|
||||
- name: HSI
|
||||
description: HSI selected as USART clock source
|
||||
value: 3
|
||||
enum/USBSW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: PLL1_P
|
||||
description: PLL clock selected as USB clock source
|
||||
value: 1
|
||||
1041
data/registers/rcc_f0v2.yaml
Normal file
1041
data/registers/rcc_f0v2.yaml
Normal file
File diff suppressed because it is too large
Load Diff
1044
data/registers/rcc_f0v3.yaml
Normal file
1044
data/registers/rcc_f0v3.yaml
Normal file
File diff suppressed because it is too large
Load Diff
@ -465,7 +465,7 @@ fieldset/CFGR:
|
||||
bit_size: 2
|
||||
enum: PLLSRC
|
||||
- name: PLLXTPRE
|
||||
description: HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning
|
||||
description: HSE divider for PLL entry. Same bit as PREDIV[0] from CFGR2 register. Refer to it for its meaning
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
enum: PLLXTPRE
|
||||
@ -847,7 +847,7 @@ enum/MCOPRE:
|
||||
enum/MCOSEL:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: NoMCO
|
||||
- name: DISABLE
|
||||
description: MCO output disabled, no clock on MCO
|
||||
value: 0
|
||||
- name: HSI14
|
||||
@ -938,13 +938,13 @@ enum/PLLSRC:
|
||||
description: HSI divided by 2 selected as PLL input clock
|
||||
value: 0
|
||||
- name: HSI_Div_PREDIV
|
||||
description: NOT ALLOWED IN F0x0 - HSI divided by PREDIV selected as PLL input clock
|
||||
description: HSI divided by PREDIV selected as PLL input clock
|
||||
value: 1
|
||||
- name: HSE_Div_PREDIV
|
||||
description: HSE divided by PREDIV selected as PLL input clock
|
||||
value: 2
|
||||
- name: HSI48_Div_PREDIV
|
||||
description: NOT ALLOWED IN F0x0 - HSI48 divided by PREDIV selected as PLL input clock
|
||||
description: HSI48 divided by PREDIV selected as PLL input clock
|
||||
value: 3
|
||||
enum/PLLXTPRE:
|
||||
bit_size: 1
|
||||
@ -1052,7 +1052,7 @@ enum/SW:
|
||||
description: PLL used as system clock
|
||||
value: 2
|
||||
- name: HSI48
|
||||
description: HSI48 used as system clock (when avaiable)
|
||||
description: HSI48 used as system clock
|
||||
value: 3
|
||||
enum/USARTSW:
|
||||
bit_size: 2
|
||||
@ -1073,7 +1073,7 @@ enum/USBSW:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: HSI48
|
||||
description: NOT ALLOWED IN F0x0 - HSI48 selected as USB clock source
|
||||
description: HSI48 selected as USB clock source
|
||||
value: 0
|
||||
- name: PLL1_P
|
||||
description: PLL clock selected as USB clock source
|
||||
@ -296,7 +296,13 @@ impl PeriMatcher {
|
||||
(".*:USB_OTG_FS:otgfs1_.*", ("otg", "v1", "OTG")),
|
||||
(".*:USB_OTG_HS:otghs1_.*", ("otg", "v1", "OTG")),
|
||||
("STM32C0.*:RCC:.*", ("rcc", "c0", "RCC")),
|
||||
("STM32F0.*:RCC:.*", ("rcc", "f0", "RCC")),
|
||||
("STM32F030.[46].*:RCC:.*", ("rcc", "f0v1", "RCC")),
|
||||
("STM32F05[128].*:RCC:.*", ("rcc", "f0v1", "RCC")),
|
||||
("STM32F030.8.*:RCC:.*", ("rcc", "f0v2", "RCC")),
|
||||
("STM32F03[128].*:RCC:.*", ("rcc", "f0v2", "RCC")),
|
||||
("STM32F030.C.*:RCC:.*", ("rcc", "f0v3", "RCC")),
|
||||
("STM32F070.[6B].*:RCC:.*", ("rcc", "f0v3", "RCC")),
|
||||
("STM32F0[479][128].*:RCC:.*", ("rcc", "f0v4", "RCC")),
|
||||
("STM32F100.*:RCC:.*", ("rcc", "f100", "RCC")),
|
||||
("STM32F10[123].*:RCC:.*", ("rcc", "f1", "RCC")),
|
||||
("STM32F10[57].*:RCC:.*", ("rcc", "f1cl", "RCC")),
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user