usb_v4: fix inconsistencies with previous versions.

data/registers/usb_v4.yaml

@@ -2,50 +2,47 @@
 block/USB:
   description: Universal serial bus full-speed host/device interface
   items:
-    - name: CHEPR
+    - name: EPR
-      description: USB endpoint/channel
+      description: endpoint/channel
       array:
         len: 8
         stride: 4
       byte_offset: 0
-      fieldset: CHEPR
+      fieldset: EPR
     - name: CNTR
-      description: "USB control register "
+      description: control register
       byte_offset: 64
       fieldset: CNTR
     - name: ISTR
-      description: "USB interrupt status register "
+      description: interrupt status register
       byte_offset: 68
       fieldset: ISTR
     - name: FNR
-      description: "USB frame number register "
+      description: frame number register
       byte_offset: 72
+      access: Read
       fieldset: FNR
     - name: DADDR
-      description: "USB device address "
+      description: device address
       byte_offset: 76
       fieldset: DADDR
     - name: LPMCSR
-      description: "LPM control and status register "
+      description: LPM control and status register
       byte_offset: 84
       fieldset: LPMCSR
     - name: BCDR
-      description: "Battery charging detector "
+      description: Battery charging detector
       byte_offset: 88
       fieldset: BCDR
-      # USB SRAM is at 0x4000 9800
-      # USB registers are at 0x4000 5C00
-      # 9800 - 5C00 = 0x3C00 = 15360
-      # so this is a convenience method to access USB SRAM
     - name: EP_MEM
-      description: USB Endpoint memory
+      description: Endpoint memory
-      byte_offset: 15360
-      bit_size: 16
       array:
         len: 1024
         stride: 2
+      byte_offset: 15360
+      bit_size: 16
 fieldset/BCDR:
-  description: "Battery charging detector "
+  description: Battery charging detector
   fields:
     - name: BCDEN
       description: "Battery charging detector (BCD) enable Device mode This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to '0 in order to allow the normal USB operation."
@@ -75,16 +72,99 @@ fieldset/BCDR:
       description: Secondary detection (SD) status Device mode This bit gives the result of SD.
       bit_offset: 6
       bit_size: 1
+      enum: SDET
     - name: PS2DET
       description: "DM pull-up detection status Device mode This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification."
       bit_offset: 7
       bit_size: 1
-    - name: DPPU_DPD
+    - name: DPPU
       description: "DP pull-up / DPDM pull-down Device mode This bit is set by software to enable the embedded pull-up on DP line. Clearing it to '0 can be used to signal disconnect to the host when needed by the user software. Host mode This bit is set by software to enable the embedded pull-down on DP and DM lines."
       bit_offset: 15
       bit_size: 1
-fieldset/CHEPR:
+fieldset/CNTR:
-  description: USB endpoint/channel 0 register
+  description: control register
+  fields:
+    - name: FRES
+      description: "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB"
+      bit_offset: 0
+      bit_size: 1
+    - name: PDWN
+      description: "Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used."
+      bit_offset: 1
+      bit_size: 1
+    - name: LPMODE
+      description: "Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set."
+      bit_offset: 2
+      bit_size: 1
+    - name: FSUSP
+      description: "Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set."
+      bit_offset: 3
+      bit_size: 1
+    - name: RESUME
+      description: "L2 Remote Wakeup / Resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the Host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the Host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt."
+      bit_offset: 4
+      bit_size: 1
+    - name: L1RESUME
+      description: "L1 Remote Wakeup / Resume driver Device mode Software sets this bit to send a LPM L1 50us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. Host mode Software sets this bit to send L1 resume signaling to device. Resume duration and next SOF generation is automatically driven to set the restart of USB activity timely aligned with the programmed BESL value. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. This bit is cleared by hardware at the end of resume."
+      bit_offset: 5
+      bit_size: 1
+    - name: L1REQM
+      description: LPM L1 state request interrupt mask
+      bit_offset: 7
+      bit_size: 1
+    - name: ESOFM
+      description: Expected start of frame interrupt mask
+      bit_offset: 8
+      bit_size: 1
+    - name: SOFM
+      description: Start of frame interrupt mask
+      bit_offset: 9
+      bit_size: 1
+    - name: RESETM
+      description: reset interrupt mask
+      bit_offset: 10
+      bit_size: 1
+    - name: SUSPM
+      description: Suspend mode interrupt mask
+      bit_offset: 11
+      bit_size: 1
+    - name: WKUPM
+      description: Wakeup interrupt mask
+      bit_offset: 12
+      bit_size: 1
+    - name: ERRM
+      description: Error interrupt mask
+      bit_offset: 13
+      bit_size: 1
+    - name: PMAOVRM
+      description: Packet memory area over / underrun interrupt mask
+      bit_offset: 14
+      bit_size: 1
+    - name: CTRM
+      description: "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"
+      bit_offset: 15
+      bit_size: 1
+    - name: THR512M
+      description: 512 byte threshold interrupt mask
+      bit_offset: 16
+      bit_size: 1
+    - name: HOST
+      description: HOST mode HOST bit selects betweens Host or Device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit.
+      bit_offset: 31
+      bit_size: 1
+fieldset/DADDR:
+  description: device address
+  fields:
+    - name: ADD
+      description: Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction
+      bit_offset: 0
+      bit_size: 7
+    - name: EF
+      description: "Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers."
+      bit_offset: 7
+      bit_size: 1
+fieldset/EPR:
+  description: endpoint/channel 0 register
   fields:
     - name: EA
       description: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction.
@@ -99,15 +179,15 @@ fieldset/CHEPR:
       description: "Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1."
       bit_offset: 6
       bit_size: 1
-    - name: VTTX
+    - name: CTR_TX
       description: "Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions."
       bit_offset: 7
       bit_size: 1
-    - name: EPKIND
+    - name: EP_KIND
       description: "endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALL’ instead of 'ACK’. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required."
       bit_offset: 8
       bit_size: 1
-    - name: UTYPE
+    - name: EP_TYPE
       description: "USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers"
       bit_offset: 9
       bit_size: 2
@@ -125,7 +205,7 @@ fieldset/CHEPR:
       description: "Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1."
       bit_offset: 14
       bit_size: 1
-    - name: VTRX
+    - name: CTR_RX
       description: "USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect."
       bit_offset: 15
       bit_size: 1
@@ -149,90 +229,8 @@ fieldset/CHEPR:
       description: "Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated."
       bit_offset: 26
       bit_size: 1
-fieldset/CNTR:
-  description: "USB control register "
-  fields:
-    - name: RST
-      description: "USB Reset Device mode Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RESET bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RESET interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. Host mode Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software."
-      bit_offset: 0
-      bit_size: 1
-    - name: PDWN
-      description: "Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used."
-      bit_offset: 1
-      bit_size: 1
-    - name: SUSPRDY
-      description: "Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set."
-      bit_offset: 2
-      bit_size: 1
-    - name: SUSPEN
-      description: "Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3 ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set."
-      bit_offset: 3
-      bit_size: 1
-    - name: L2RESUME
-      description: "L2 Remote Wakeup / Resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the Host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the Host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt."
-      bit_offset: 4
-      bit_size: 1
-    - name: L1RESUME
-      description: "L1 Remote Wakeup / Resume driver Device mode Software sets this bit to send a LPM L1 50us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. Host mode Software sets this bit to send L1 resume signaling to device. Resume duration and next SOF generation is automatically driven to set the restart of USB activity timely aligned with the programmed BESL value. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. This bit is cleared by hardware at the end of resume."
-      bit_offset: 5
-      bit_size: 1
-    - name: L1REQM
-      description: LPM L1 state request interrupt mask
-      bit_offset: 7
-      bit_size: 1
-    - name: ESOFM
-      description: Expected start of frame interrupt mask
-      bit_offset: 8
-      bit_size: 1
-    - name: SOFM
-      description: Start of frame interrupt mask
-      bit_offset: 9
-      bit_size: 1
-    - name: RESETM
-      description: USB reset interrupt mask
-      bit_offset: 10
-      bit_size: 1
-    - name: SUSPM
-      description: Suspend mode interrupt mask
-      bit_offset: 11
-      bit_size: 1
-    - name: WKUPM
-      description: Wakeup interrupt mask
-      bit_offset: 12
-      bit_size: 1
-    - name: ERRM
-      description: Error interrupt mask
-      bit_offset: 13
-      bit_size: 1
-    - name: PMAOVRM
-      description: Packet memory area over / underrun interrupt mask
-      bit_offset: 14
-      bit_size: 1
-    - name: CTRM
-      description: Correct transfer interrupt mask
-      bit_offset: 15
-      bit_size: 1
-    - name: THR512M
-      description: 512 byte threshold interrupt mask
-      bit_offset: 16
-      bit_size: 1
-    - name: HOST
-      description: HOST mode HOST bit selects betweens Host or Device USB mode of operation. It must be set before enabling the USB peripheral by the function enable bit.
-      bit_offset: 31
-      bit_size: 1
-fieldset/DADDR:
-  description: "USB device address "
-  fields:
-    - name: ADD
-      description: Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction
-      bit_offset: 0
-      bit_size: 7
-    - name: EF
-      description: "Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits. If this bit is at '0 no transactions are handled, irrespective of the settings of USB_EPnR registers."
-      bit_offset: 7
-      bit_size: 1
 fieldset/FNR:
-  description: "USB frame number register "
+  description: frame number register
   fields:
     - name: FN
       description: Frame number This bit field contains the 11-bits frame number contained in the last received SOF packet. The frame number is incremented for every frame sent by the host and it is useful for Isochronous transfers. This bit field is updated on the generation of an SOF interrupt.
@@ -255,9 +253,9 @@ fieldset/FNR:
       bit_offset: 15
       bit_size: 1
 fieldset/ISTR:
-  description: "USB interrupt status register "
+  description: interrupt status register
   fields:
-    - name: IDN
+    - name: EP_ID
       description: "Device Endpoint / Host channel identification number These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: Two levels are defined, in order of priority: Isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only."
       bit_offset: 0
       bit_size: 4
@@ -265,6 +263,7 @@ fieldset/ISTR:
       description: "Direction of transaction This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. If DIR bit=0, VTTX bit is set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). If DIR bit=1, VTRX bit or both VTTX/VTRX are set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. This information can be used by the application software to access the USB_EPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only."
       bit_offset: 4
       bit_size: 1
+      enum: DIR
     - name: L1REQ
       description: "LPM L1 state request This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. This bit is read/write but only '0 can be written and writing '1 has no effect."
       bit_offset: 7
@@ -277,8 +276,8 @@ fieldset/ISTR:
       description: "Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1 ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only '0 can be written and writing '1 has no effect."
       bit_offset: 9
       bit_size: 1
-    - name: RST_DCON
+    - name: RESET
-      description: USB reset request Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is sampled for 22cycles consecutively from connected state.
+      description: reset request Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is sampled for 22cycles consecutively from connected state.
       bit_offset: 10
       bit_size: 1
     - name: SUSP
@@ -314,7 +313,7 @@ fieldset/ISTR:
       bit_offset: 30
       bit_size: 1
 fieldset/LPMCSR:
-  description: "LPM control and status register "
+  description: LPM control and status register
   fields:
     - name: LPMEN
       description: "LPM support enable Device mode This bit is set by the software to enable the LPM support within the USB device. If this bit is at '0 no LPM transactions are handled. Host mode Software sets this bit to transmit an LPM transaction to device. This bit is cleared by hardware, simultaneous with L1REQ flag set, when device answer is received"
@@ -333,30 +332,15 @@ fieldset/LPMCSR:
       description: BESL value Device mode These bits contain the BESL value received with last ACKed LPM Token Host mode These bits contain the BESL value transmitted with the LPM transaction
       bit_offset: 4
       bit_size: 4
-enum/LPMACK:
+enum/DIR:
   bit_size: 1
   variants:
-    - name: Nyet
+    - name: To
-      description: The valid LPM Token will be NYET / NYET answer
+      description: data transmitted by the USB peripheral to the host PC
       value: 0
-    - name: Ack
+    - name: From
-      description: The valid LPM Token will be ACK / ACK answer
+      description: data received by the USB peripheral from the host PC
       value: 1
-enum/STAT:
-  bit_size: 2
-  variants:
-    - name: Disabled
-      description: all requests addressed to this endpoint are ignored
-      value: 0
-    - name: Stall
-      description: the endpoint is stalled and all requests result in a STALL handshake
-      value: 1
-    - name: Nak
-      description: the endpoint is naked and all requests result in a NAK handshake
-      value: 2
-    - name: Valid
-      description: this endpoint is enabled, requests are ACKed
-      value: 3
 enum/EP_TYPE:
   bit_size: 2
   variants:
@@ -372,3 +356,36 @@ enum/EP_TYPE:
     - name: Interrupt
       description: Interrupt endpoint
       value: 3
+enum/LPMACK:
+  bit_size: 1
+  variants:
+    - name: Nyet
+      description: The valid LPM Token will be NYET / NYET answer
+      value: 0
+    - name: Ack
+      description: The valid LPM Token will be ACK / ACK answer
+      value: 1
+enum/SDET:
+  bit_size: 1
+  variants:
+    - name: CDP
+      description: CDP detected
+      value: 0
+    - name: DCP
+      description: DCP detected
+      value: 1
+enum/STAT:
+  bit_size: 2
+  variants:
+    - name: Disabled
+      description: all requests addressed to this endpoint are ignored
+      value: 0
+    - name: Stall
+      description: the endpoint is stalled and all requests result in a STALL handshake
+      value: 1
+    - name: Nak
+      description: the endpoint is naked and all requests result in a NAK handshake
+      value: 2
+    - name: Valid
+      description: "this endpoint is enabled, requests are ACKed"
+      value: 3