From 8059f940cf13ae25d26afc6715be6104e131d280 Mon Sep 17 00:00:00 2001 From: Alexandros Liarokapis Date: Wed, 15 May 2024 22:20:10 +0300 Subject: [PATCH] Added SPI45SEL to RCC for STM32H7 devices. RCC mux was missing the SPI45SEL selector. I had to add an extra rule to the rcc.rs and fix the wrong SPI45SEL entries in rcc_h7ab.yaml and rcc_h7rs.yaml. I confirmed that both default entries point to the PCLK2 instead of HCLK2. --- data/registers/rcc_h7ab.yaml | 2 +- data/registers/rcc_h7rs.yaml | 2 +- stm32-data-gen/src/rcc.rs | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index fbd1732..3d3fef6 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -4305,7 +4305,7 @@ enum/SPDIFRXSEL: enum/SPI45SEL: bit_size: 3 variants: - - name: HCLK2 + - name: PCLK2 description: APB2 clock selected as peripheral clock value: 0 - name: PLL2_Q diff --git a/data/registers/rcc_h7rs.yaml b/data/registers/rcc_h7rs.yaml index dbcf0b2..adbe7cf 100644 --- a/data/registers/rcc_h7rs.yaml +++ b/data/registers/rcc_h7rs.yaml @@ -4095,7 +4095,7 @@ enum/SPI123SEL: enum/SPI45SEL: bit_size: 3 variants: - - name: HCLK2 + - name: PCLK2 description: APB2 clock selected as peripheral clock value: 0 - name: PLL2_Q diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index e0c4ebf..62f76f2 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -284,8 +284,8 @@ impl ParsedRccs { ("SPI1", &["SPI12", "SPI123"]), ("SPI2", &["SPI12", "SPI123"]), ("SPI3", &["SPI123"]), - ("SPI4", &["SPI145"]), - ("SPI5", &["SPI145"]), + ("SPI4", &["SPI145", "SPI45"]), + ("SPI5", &["SPI145", "SPI45"]), ("SAI1", &["SAI12"]), ("SAI2", &["SAI12", "SAI23"]), ("SAI3", &["SAI23"]),