syscfg-cleanup
This commit is contained in:
parent
d35c07bece
commit
751158dace
@ -147,40 +147,33 @@ fieldset/CFGR1:
|
||||
bit_size: 1
|
||||
enum: I2C3_FMP
|
||||
- name: VBAT_MON
|
||||
description: VBAT monitoring enable
|
||||
description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
enum: VBAT_MON
|
||||
- name: FPU_IE0
|
||||
description: Invalid operation interrupt enable
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
enum: FPU_IE0
|
||||
- name: FPU_IE1
|
||||
description: Devide-by-zero interrupt enable
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
enum: FPU_IE1
|
||||
- name: FPU_IE2
|
||||
description: Underflow interrupt enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
enum: FPU_IE2
|
||||
- name: FPU_IE3
|
||||
description: Overflow interrupt enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
enum: FPU_IE3
|
||||
- name: FPU_IE4
|
||||
description: Input denormal interrupt enable
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
enum: FPU_IE4
|
||||
- name: FPU_IE5
|
||||
description: Inexact interrupt enable
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum: FPU_IE5
|
||||
fieldset/CFGR2:
|
||||
description: configuration register 2
|
||||
fields:
|
||||
@ -333,85 +326,69 @@ fieldset/RCR:
|
||||
description: CCM SRAM protection register
|
||||
fields:
|
||||
- name: PAGE0_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE1_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE2_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE3_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE4_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE5_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE6_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE7_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE8_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE9_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE10_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE11_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE12_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE13_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE14_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
- name: PAGE15_WP
|
||||
description: CCM SRAM page write protection bit
|
||||
description: CCM SRAM page write protection enabled
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: PAGE0_WP
|
||||
enum/ADC12_EXT13_RMP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -616,60 +593,6 @@ enum/ENCODER_MODE:
|
||||
- name: MapTim3Tim15
|
||||
description: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
|
||||
value: 2
|
||||
enum/FPU_IE0:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Invalid operation interrupt disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Invalid operation interrupt enable
|
||||
value: 1
|
||||
enum/FPU_IE1:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Devide-by-zero interrupt disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Devide-by-zero interrupt enable
|
||||
value: 1
|
||||
enum/FPU_IE2:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Underflow interrupt disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Underflow interrupt enable
|
||||
value: 1
|
||||
enum/FPU_IE3:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Overflow interrupt disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Overflow interrupt enable
|
||||
value: 1
|
||||
enum/FPU_IE4:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Input denormal interrupt disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Input denormal interrupt enable
|
||||
value: 1
|
||||
enum/FPU_IE5:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Inexact interrupt disable
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Inexact interrupt enable
|
||||
value: 1
|
||||
enum/I2C1_FMP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -781,15 +704,6 @@ enum/MEM_MODE:
|
||||
- name: SRAM
|
||||
description: Embedded SRAM mapped at 0x0000_0000
|
||||
value: 3
|
||||
enum/PAGE0_WP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Write protection of pagex is disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Write protection of pagex is enabled
|
||||
value: 1
|
||||
enum/PVD_LOCK:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -922,12 +836,3 @@ enum/USB_IT_RMP:
|
||||
- name: Remapped
|
||||
description: USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively
|
||||
value: 1
|
||||
enum/VBAT_MON:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disable
|
||||
description: Disable the power switch to not deliver VBAT voltage on ADC channel 18 input
|
||||
value: 0
|
||||
- name: Enable
|
||||
description: Enable the power switch to deliver VBAT voltage on ADC channel 18 input
|
||||
value: 1
|
||||
|
Loading…
x
Reference in New Issue
Block a user