From 75011dc243acbad372ef13f4a507d2992811579f Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 20:52:53 +0800 Subject: [PATCH] tailoring from tim2ch to tim1ch --- data/registers/tim1ch_v2.yaml | 422 ++++++++++++++++++++++++++++++++++ 1 file changed, 422 insertions(+) create mode 100644 data/registers/tim1ch_v2.yaml diff --git a/data/registers/tim1ch_v2.yaml b/data/registers/tim1ch_v2.yaml new file mode 100644 index 0000000..23acf72 --- /dev/null +++ b/data/registers/tim1ch_v2.yaml @@ -0,0 +1,422 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER + - name: CCR + description: capture/compare register x (x=1) (Dither mode disabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1) (Dither mode enabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL +fieldset/ARR: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 1 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 1 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 1 + stride: 8 + enum: OCM +fieldset/CCR: + description: capture/compare register x (x=1) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER: + description: capture/compare register x (x=1) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 16 +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1) generation + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1) input + bit_offset: 0 + bit_size: 4 + array: + len: 1 + stride: 8 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1