Implement h7 syscfg

data/registers/syscfg_h7.yaml

@@ -0,0 +1,410 @@
+---
+block/SYSCFG:
+  description: System configuration controller
+  items:
+    - name: PMCR
+      description: peripheral mode configuration register
+      byte_offset: 4
+      fieldset: PMCR
+    - name: EXTICR
+      description: external interrupt configuration register 1
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 8
+      fieldset: EXTICR
+    - name: CCCSR
+      description: compensation cell control/status register
+      byte_offset: 32
+      fieldset: CCCSR
+    - name: CCVR
+      description: SYSCFG compensation cell value register
+      byte_offset: 36
+      access: Read
+      fieldset: CCVR
+    - name: CCCR
+      description: SYSCFG compensation cell code register
+      byte_offset: 40
+      fieldset: CCCR
+    - name: PWRCR
+      description: SYSCFG power control register
+      byte_offset: 44
+      fieldset: PWRCR
+    - name: PKGR
+      description: SYSCFG package register
+      byte_offset: 292
+      access: Read
+      fieldset: PKGR
+    - name: UR0
+      description: SYSCFG user register 0
+      byte_offset: 768
+      access: Read
+      fieldset: UR0
+    - name: UR2
+      description: SYSCFG user register 2
+      byte_offset: 776
+      fieldset: UR2
+    - name: UR3
+      description: SYSCFG user register 3
+      byte_offset: 780
+      fieldset: UR3
+    - name: UR4
+      description: SYSCFG user register 4
+      byte_offset: 784
+      access: Read
+      fieldset: UR4
+    - name: UR5
+      description: SYSCFG user register 5
+      byte_offset: 788
+      access: Read
+      fieldset: UR5
+    - name: UR6
+      description: SYSCFG user register 6
+      byte_offset: 792
+      access: Read
+      fieldset: UR6
+    - name: UR7
+      description: SYSCFG user register 7
+      byte_offset: 796
+      access: Read
+      fieldset: UR7
+    - name: UR8
+      description: SYSCFG user register 8
+      byte_offset: 800
+      access: Read
+      fieldset: UR8
+    - name: UR9
+      description: SYSCFG user register 9
+      byte_offset: 804
+      access: Read
+      fieldset: UR9
+    - name: UR10
+      description: SYSCFG user register 10
+      byte_offset: 808
+      access: Read
+      fieldset: UR10
+    - name: UR11
+      description: SYSCFG user register 11
+      byte_offset: 812
+      access: Read
+      fieldset: UR11
+    - name: UR12
+      description: SYSCFG user register 12
+      byte_offset: 816
+      access: Read
+      fieldset: UR12
+    - name: UR13
+      description: SYSCFG user register 13
+      byte_offset: 820
+      access: Read
+      fieldset: UR13
+    - name: UR14
+      description: SYSCFG user register 14
+      byte_offset: 824
+      fieldset: UR14
+    - name: UR15
+      description: SYSCFG user register 15
+      byte_offset: 828
+      access: Read
+      fieldset: UR15
+    - name: UR16
+      description: SYSCFG user register 16
+      byte_offset: 832
+      access: Read
+      fieldset: UR16
+    - name: UR17
+      description: SYSCFG user register 17
+      byte_offset: 836
+      access: Read
+      fieldset: UR17
+fieldset/CCCR:
+  description: SYSCFG compensation cell code register
+  fields:
+    - name: NCC
+      description: NMOS compensation code
+      bit_offset: 0
+      bit_size: 4
+    - name: PCC
+      description: PMOS compensation code
+      bit_offset: 4
+      bit_size: 4
+fieldset/CCCSR:
+  description: compensation cell control/status register
+  fields:
+    - name: EN
+      description: enable
+      bit_offset: 0
+      bit_size: 1
+    - name: CS
+      description: Code selection
+      bit_offset: 1
+      bit_size: 1
+    - name: READY
+      description: Compensation cell ready flag
+      bit_offset: 8
+      bit_size: 1
+    - name: HSLV
+      description: High-speed at low-voltage
+      bit_offset: 16
+      bit_size: 1
+fieldset/CCVR:
+  description: SYSCFG compensation cell value register
+  fields:
+    - name: NCV
+      description: NMOS compensation value
+      bit_offset: 0
+      bit_size: 4
+    - name: PCV
+      description: PMOS compensation value
+      bit_offset: 4
+      bit_size: 4
+fieldset/EXTICR:
+  description: external interrupt configuration register 2
+  fields:
+    - name: EXTI
+      description: EXTI x configuration (x = 4 to 7)
+      bit_offset: 0
+      bit_size: 4
+      array:
+        len: 4
+        stride: 4
+fieldset/PKGR:
+  description: SYSCFG package register
+  fields:
+    - name: PKG
+      description: Package
+      bit_offset: 0
+      bit_size: 4
+fieldset/PMCR:
+  description: peripheral mode configuration register
+  fields:
+    - name: I2C1FMP
+      description: I2C1 Fm+
+      bit_offset: 0
+      bit_size: 1
+    - name: I2C2FMP
+      description: I2C2 Fm+
+      bit_offset: 1
+      bit_size: 1
+    - name: I2C3FMP
+      description: I2C3 Fm+
+      bit_offset: 2
+      bit_size: 1
+    - name: I2C4FMP
+      description: I2C4 Fm+
+      bit_offset: 3
+      bit_size: 1
+    - name: PB6FMP
+      description: PB(6) Fm+
+      bit_offset: 4
+      bit_size: 1
+    - name: PB7FMP
+      description: PB(7) Fast Mode Plus
+      bit_offset: 5
+      bit_size: 1
+    - name: PB8FMP
+      description: PB(8) Fast Mode Plus
+      bit_offset: 6
+      bit_size: 1
+    - name: PB9FMP
+      description: PB(9) Fm+
+      bit_offset: 7
+      bit_size: 1
+    - name: BOOSTE
+      description: Booster Enable
+      bit_offset: 8
+      bit_size: 1
+    - name: BOOSTVDDSEL
+      description: Analog switch supply voltage selection
+      bit_offset: 9
+      bit_size: 1
+    - name: EPIS
+      description: Ethernet PHY Interface Selection
+      bit_offset: 21
+      bit_size: 3
+    - name: PA0SO
+      description: PA0 Switch Open
+      bit_offset: 24
+      bit_size: 1
+    - name: PA1SO
+      description: PA1 Switch Open
+      bit_offset: 25
+      bit_size: 1
+    - name: PC2SO
+      description: PC2 Switch Open
+      bit_offset: 26
+      bit_size: 1
+    - name: PC3SO
+      description: PC3 Switch Open
+      bit_offset: 27
+      bit_size: 1
+fieldset/PWRCR:
+  description: SYSCFG power control register
+  fields:
+    - name: ODEN
+      description: " Overdrive enable"
+      bit_offset: 0
+      bit_size: 4
+fieldset/UR0:
+  description: SYSCFG user register 0
+  fields:
+    - name: BKS
+      description: Bank Swap
+      bit_offset: 0
+      bit_size: 1
+    - name: RDP
+      description: Readout protection
+      bit_offset: 16
+      bit_size: 8
+fieldset/UR10:
+  description: SYSCFG user register 10
+  fields:
+    - name: PA_END_2
+      description: Protected area end address for bank 2
+      bit_offset: 0
+      bit_size: 12
+    - name: SA_BEG_2
+      description: Secured area start address for bank 2
+      bit_offset: 16
+      bit_size: 12
+fieldset/UR11:
+  description: SYSCFG user register 11
+  fields:
+    - name: SA_END_2
+      description: Secured area end address for bank 2
+      bit_offset: 0
+      bit_size: 12
+    - name: IWDG1M
+      description: Independent Watchdog 1 mode
+      bit_offset: 16
+      bit_size: 1
+fieldset/UR12:
+  description: SYSCFG user register 12
+  fields:
+    - name: SECURE
+      description: Secure mode
+      bit_offset: 16
+      bit_size: 1
+fieldset/UR13:
+  description: SYSCFG user register 13
+  fields:
+    - name: SDRS
+      description: Secured DTCM RAM Size
+      bit_offset: 0
+      bit_size: 2
+    - name: D1SBRST
+      description: D1 Standby reset
+      bit_offset: 16
+      bit_size: 1
+fieldset/UR14:
+  description: SYSCFG user register 14
+  fields:
+    - name: D1STPRST
+      description: D1 Stop Reset
+      bit_offset: 0
+      bit_size: 1
+fieldset/UR15:
+  description: SYSCFG user register 15
+  fields:
+    - name: FZIWDGSTB
+      description: Freeze independent watchdog in Standby mode
+      bit_offset: 16
+      bit_size: 1
+fieldset/UR16:
+  description: SYSCFG user register 16
+  fields:
+    - name: FZIWDGSTP
+      description: Freeze independent watchdog in Stop mode
+      bit_offset: 0
+      bit_size: 1
+    - name: PKP
+      description: Private key programmed
+      bit_offset: 16
+      bit_size: 1
+fieldset/UR17:
+  description: SYSCFG user register 17
+  fields:
+    - name: IO_HSLV
+      description: I/O high speed / low voltage
+      bit_offset: 0
+      bit_size: 1
+fieldset/UR2:
+  description: SYSCFG user register 2
+  fields:
+    - name: BORH
+      description: BOR_LVL Brownout Reset Threshold Level
+      bit_offset: 0
+      bit_size: 2
+    - name: BOOT_ADD0
+      description: Boot Address 0
+      bit_offset: 16
+      bit_size: 16
+fieldset/UR3:
+  description: SYSCFG user register 3
+  fields:
+    - name: BOOT_ADD1
+      description: Boot Address 1
+      bit_offset: 16
+      bit_size: 16
+fieldset/UR4:
+  description: SYSCFG user register 4
+  fields:
+    - name: MEPAD_1
+      description: Mass Erase Protected Area Disabled for bank 1
+      bit_offset: 16
+      bit_size: 1
+fieldset/UR5:
+  description: SYSCFG user register 5
+  fields:
+    - name: MESAD_1
+      description: Mass erase secured area disabled for bank 1
+      bit_offset: 0
+      bit_size: 1
+    - name: WRPN_1
+      description: Write protection for flash bank 1
+      bit_offset: 16
+      bit_size: 8
+fieldset/UR6:
+  description: SYSCFG user register 6
+  fields:
+    - name: PA_BEG_1
+      description: Protected area start address for bank 1
+      bit_offset: 0
+      bit_size: 12
+    - name: PA_END_1
+      description: Protected area end address for bank 1
+      bit_offset: 16
+      bit_size: 12
+fieldset/UR7:
+  description: SYSCFG user register 7
+  fields:
+    - name: SA_BEG_1
+      description: Secured area start address for bank 1
+      bit_offset: 0
+      bit_size: 12
+    - name: SA_END_1
+      description: Secured area end address for bank 1
+      bit_offset: 16
+      bit_size: 12
+fieldset/UR8:
+  description: SYSCFG user register 8
+  fields:
+    - name: MEPAD_2
+      description: Mass erase protected area disabled for bank 2
+      bit_offset: 0
+      bit_size: 1
+    - name: MESAD_2
+      description: Mass erase secured area disabled for bank 2
+      bit_offset: 16
+      bit_size: 1
+fieldset/UR9:
+  description: SYSCFG user register 9
+  fields:
+    - name: WRPN_2
+      description: Write protection for flash bank 2
+      bit_offset: 0
+      bit_size: 8
+    - name: PA_BEG_2
+      description: Protected area start address for bank 2
+      bit_offset: 16
+      bit_size: 12

parse.py

@@ -231,6 +231,7 @@ perimap = [
     ('.*:RNG:rng1_v3_1', 'rng_v1/RNG'),
     ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'),
     ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
+    ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
     ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
 ]