From 445f314531ff63721c1e055a449a9d9f5cc691d7 Mon Sep 17 00:00:00 2001 From: shakencodes Date: Wed, 1 Nov 2023 12:39:09 -0700 Subject: [PATCH 1/2] Add enum/ADCSET to rcc_l5.yaml --- data/registers/rcc_l5.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 2933f71..77e857b 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1383,6 +1383,7 @@ fieldset/CCIPR1: description: ADCs clock source selection bit_offset: 28 bit_size: 2 + enum: ADCSEL fieldset/CCIPR2: description: Peripherals independent clock configuration register fields: @@ -1924,6 +1925,18 @@ fieldset/SECSR: description: RMVFSECF bit_offset: 12 bit_size: 1 +enum/ADCSEL: + bit_size: 2 + variants: + - name: DISABLE + description: No clock selected + value: 0 + - name: PLL1_Q + description: PLLADC1CLK clock selected + value: 1 + - name: SYS + description: SYSCLK clock selected + value: 3 enum/CLK48SEL: bit_size: 2 variants: From 9ba39f0f2dbf4e0626a7eb43cc5dbf52cf109087 Mon Sep 17 00:00:00 2001 From: shakencodes Date: Wed, 1 Nov 2023 13:04:57 -0700 Subject: [PATCH 2/2] Corrects name of enum/ADCSEL::PLLSAI1_R on smt32l5 --- data/registers/rcc_l5.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 77e857b..050f0b7 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1931,7 +1931,7 @@ enum/ADCSEL: - name: DISABLE description: No clock selected value: 0 - - name: PLL1_Q + - name: PLLSAI1_R description: PLLADC1CLK clock selected value: 1 - name: SYS