From ac23a24b9bad4a6758f33f49d59f5e69a23a1819 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 18:30:07 +0800 Subject: [PATCH 01/11] extract lptim_v2h5 from h573 lptim1 --- data/registers/lptim_v2h5.yaml | 524 +++++++++++++++++++++++++++++++++ 1 file changed, 524 insertions(+) create mode 100644 data/registers/lptim_v2h5.yaml diff --git a/data/registers/lptim_v2h5.yaml b/data/registers/lptim_v2h5.yaml new file mode 100644 index 0000000..0728ec4 --- /dev/null +++ b/data/registers/lptim_v2h5.yaml @@ -0,0 +1,524 @@ +block/LPTIM1: + description: Low power timer. + items: + - name: ISR_intput + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR_intput + - name: ISR_output + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR_output + - name: ICR_intput + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR_intput + - name: ICR_output + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR_output + - name: DIER_intput + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER_intput + - name: DIER_output + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER_output + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CCR1 + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CCR1 + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: CFGR2 + description: LPTIM configuration register 2. + byte_offset: 36 + fieldset: CFGR2 + - name: RCR + description: LPTIM repetition register. + byte_offset: 40 + fieldset: RCR + - name: CCMR1 + description: LPTIM capture/compare mode register 1. + byte_offset: 44 + fieldset: CCMR1 + - name: CCR2 + description: LPTIM compare register 2. + byte_offset: 52 + fieldset: CCR2 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CCMR1: + description: LPTIM capture/compare mode register 1. + fields: + - name: CC1SEL + description: Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. + bit_offset: 0 + bit_size: 1 + - name: CC1E + description: Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + bit_offset: 1 + bit_size: 1 + - name: CC1P + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + - name: IC1PSC + description: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + bit_offset: 8 + bit_size: 2 + - name: IC1F + description: Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 12 + bit_size: 2 + - name: CC2SEL + description: Capture/compare 2 selection This bitfield defines the direction of the channel, input (capture) or output mode. + bit_offset: 16 + bit_size: 1 + - name: CC2E + description: Capture/compare 2 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM_CCR2) or not. + bit_offset: 17 + bit_size: 1 + - name: CC2P + description: Capture/compare 2 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC2 polarity for capture operations. + bit_offset: 18 + bit_size: 2 + - name: IC2PSC + description: Input capture 2 prescaler This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). + bit_offset: 24 + bit_size: 2 + - name: IC2F + description: Input capture 2 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 28 + bit_size: 2 +fieldset/CCR1: + description: LPTIM compare register 1. + fields: + - name: CCR1 + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CCR2: + description: LPTIM compare register 2. + fields: + - name: CCR2 + description: 'Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the capture/compare 2 register. Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 2 contains the value to be compared to the counter LPTIM_CNT and signaled on OC2 output. If channel CC2 is configured as input: CCR2 contains the counter value transferred by the last input capture 2 event. The LPTIM_CCR2 register is read-only and cannot be programmed.' + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CFGR2: + description: LPTIM configuration register 2. + fields: + - name: IN1SEL + description: LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + bit_offset: 0 + bit_size: 2 + - name: IN2SEL + description: LPTIM input 2 selection The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. For connection details refer to. + bit_offset: 4 + bit_size: 2 + - name: IC1SEL + description: LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + bit_offset: 16 + bit_size: 2 + - name: IC2SEL + description: LPTIM input capture 2 selection The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture 2 to one of the available inputs. For connection details refer to. + bit_offset: 20 + bit_size: 2 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/DIER_intput: + description: LPTIM interrupt enable register. + fields: + - name: CC1IE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UEIE + description: Update event interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: REPOKIE + description: Repetition register update OK interrupt Enable. + bit_offset: 8 + bit_size: 1 + - name: CC2IE + description: 'Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' + bit_offset: 9 + bit_size: 1 + - name: CC1OIE + description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + - name: CC2OIE + description: 'Capture/compare 2 over-capture interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' + bit_offset: 13 + bit_size: 1 + - name: CC1DE + description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 16 + bit_size: 1 + - name: UEDE + description: 'Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 23 + bit_size: 1 + - name: CC2DE + description: 'Capture/compare 2 DMA request enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' + bit_offset: 25 + bit_size: 1 +fieldset/DIER_output: + description: LPTIM interrupt enable register. + fields: + - name: CC1IE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMP1OKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UEIE + description: Update event interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: REPOKIE + description: Repetition register update OK interrupt Enable. + bit_offset: 8 + bit_size: 1 +fieldset/ICR_intput: + description: LPTIM interrupt clear register. + fields: + - name: CC1CF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UECF + description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + bit_offset: 7 + bit_size: 1 + - name: REPOKCF + description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + bit_offset: 8 + bit_size: 1 + - name: CC2CF + description: 'Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' + bit_offset: 9 + bit_size: 1 + - name: CC1OCF + description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + - name: CC2OCF + description: 'Capture/compare 2 over-capture clear flag Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' + bit_offset: 13 + bit_size: 1 + - name: DIEROKCF + description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + bit_offset: 24 + bit_size: 1 +fieldset/ICR_output: + description: LPTIM interrupt clear register. + fields: + - name: CC1CF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMP1OKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UECF + description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + bit_offset: 7 + bit_size: 1 + - name: REPOKCF + description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + bit_offset: 8 + bit_size: 1 + - name: DIEROKCF + description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + bit_offset: 24 + bit_size: 1 +fieldset/ISR_intput: + description: LPTIM interrupt and status register. + fields: + - name: CC1IF + description: 'capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high.' + bit_offset: 0 + bit_size: 1 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UE + description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + bit_offset: 7 + bit_size: 1 + - name: REPOK + description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + bit_offset: 8 + bit_size: 1 + - name: CC2IF + description: 'Capture 2 interrupt flag If channel CC2 is configured as input: CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' + bit_offset: 9 + bit_size: 1 + - name: CC1OF + description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + - name: CC2OF + description: 'Capture 2 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' + bit_offset: 13 + bit_size: 1 + - name: DIEROK + description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + bit_offset: 24 + bit_size: 1 +fieldset/ISR_output: + description: LPTIM interrupt and status register. + fields: + - name: CC1IF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMP1OK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UE + description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + bit_offset: 7 + bit_size: 1 + - name: REPOK + description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + bit_offset: 8 + bit_size: 1 + - name: DIEROK + description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + bit_offset: 24 + bit_size: 1 +fieldset/RCR: + description: LPTIM repetition register. + fields: + - name: REP + description: Repetition register value REP is the repetition value for the LPTIM. + bit_offset: 0 + bit_size: 8 From 43e02bf3ec62506cb7cc6ee4f91c373f58c448d3 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 20:09:00 +0800 Subject: [PATCH 02/11] apply transform --- data/registers/lptim_v2h5.yaml | 240 +++++++++++++++++---------------- transforms/LPTIM.yaml | 57 ++++++++ 2 files changed, 180 insertions(+), 117 deletions(-) create mode 100644 transforms/LPTIM.yaml diff --git a/data/registers/lptim_v2h5.yaml b/data/registers/lptim_v2h5.yaml index 0728ec4..c11e2bf 100644 --- a/data/registers/lptim_v2h5.yaml +++ b/data/registers/lptim_v2h5.yaml @@ -1,30 +1,26 @@ -block/LPTIM1: +block/Input: + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR_input + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR_input + - name: DIER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER_input +block/LPTIM_Adv: description: Low power timer. items: - - name: ISR_intput - description: LPTIM interrupt and status register. + - name: Input byte_offset: 0 - fieldset: ISR_intput - - name: ISR_output - description: LPTIM interrupt and status register. + block: Input + - name: Output byte_offset: 0 - fieldset: ISR_output - - name: ICR_intput - description: LPTIM interrupt clear register. - byte_offset: 4 - fieldset: ICR_intput - - name: ICR_output - description: LPTIM interrupt clear register. - byte_offset: 4 - fieldset: ICR_output - - name: DIER_intput - description: LPTIM interrupt enable register. - byte_offset: 8 - fieldset: DIER_intput - - name: DIER_output - description: LPTIM interrupt enable register. - byte_offset: 8 - fieldset: DIER_output + block: Output - name: CFGR description: LPTIM configuration register. byte_offset: 12 @@ -33,10 +29,13 @@ block/LPTIM1: description: LPTIM control register. byte_offset: 16 fieldset: CR - - name: CCR1 + - name: CCR description: LPTIM compare register 1. + array: + len: 2 + stride: 32 byte_offset: 20 - fieldset: CCR1 + fieldset: CCR - name: ARR description: LPTIM autoreload register. byte_offset: 24 @@ -57,10 +56,20 @@ block/LPTIM1: description: LPTIM capture/compare mode register 1. byte_offset: 44 fieldset: CCMR1 - - name: CCR2 - description: LPTIM compare register 2. - byte_offset: 52 - fieldset: CCR2 +block/Output: + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR_output + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR_output + - name: DIER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER_output fieldset/ARR: description: LPTIM autoreload register. fields: @@ -71,60 +80,48 @@ fieldset/ARR: fieldset/CCMR1: description: LPTIM capture/compare mode register 1. fields: - - name: CC1SEL + - name: CCSEL description: Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. bit_offset: 0 bit_size: 1 - - name: CC1E + array: + len: 2 + stride: 16 + - name: CCE description: Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. bit_offset: 1 bit_size: 1 - - name: CC1P + array: + len: 2 + stride: 16 + - name: CCP description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. bit_offset: 2 bit_size: 2 - - name: IC1PSC + array: + len: 2 + stride: 16 + - name: ICPSC description: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). bit_offset: 8 bit_size: 2 - - name: IC1F + array: + len: 2 + stride: 16 + - name: ICF description: Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. bit_offset: 12 bit_size: 2 - - name: CC2SEL - description: Capture/compare 2 selection This bitfield defines the direction of the channel, input (capture) or output mode. - bit_offset: 16 - bit_size: 1 - - name: CC2E - description: Capture/compare 2 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM_CCR2) or not. - bit_offset: 17 - bit_size: 1 - - name: CC2P - description: Capture/compare 2 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC2 polarity for capture operations. - bit_offset: 18 - bit_size: 2 - - name: IC2PSC - description: Input capture 2 prescaler This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). - bit_offset: 24 - bit_size: 2 - - name: IC2F - description: Input capture 2 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. - bit_offset: 28 - bit_size: 2 -fieldset/CCR1: + array: + len: 2 + stride: 16 +fieldset/CCR: description: LPTIM compare register 1. fields: - - name: CCR1 + - name: CCR description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' bit_offset: 0 bit_size: 16 -fieldset/CCR2: - description: LPTIM compare register 2. - fields: - - name: CCR2 - description: 'Capture/compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the capture/compare 2 register. Depending on the PRELOAD option, the CCR2 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 2 contains the value to be compared to the counter LPTIM_CNT and signaled on OC2 output. If channel CC2 is configured as input: CCR2 contains the counter value transferred by the last input capture 2 event. The LPTIM_CCR2 register is read-only and cannot be programmed.' - bit_offset: 0 - bit_size: 16 fieldset/CFGR: description: LPTIM configuration register. fields: @@ -183,22 +180,20 @@ fieldset/CFGR: fieldset/CFGR2: description: LPTIM configuration register 2. fields: - - name: IN1SEL + - name: INSEL description: LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. bit_offset: 0 bit_size: 2 - - name: IN2SEL - description: LPTIM input 2 selection The IN2SEL bits control the LPTIM input 2 multiplexer, which connects LPTIM input 2 to one of the available inputs. For connection details refer to. - bit_offset: 4 - bit_size: 2 - - name: IC1SEL + array: + len: 2 + stride: 4 + - name: ICSEL description: LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. bit_offset: 16 bit_size: 2 - - name: IC2SEL - description: LPTIM input capture 2 selection The IC2SEL bits control the LPTIM Input capture 2 multiplexer, which connects LPTIM Input capture 2 to one of the available inputs. For connection details refer to. - bit_offset: 20 - bit_size: 2 + array: + len: 2 + stride: 4 fieldset/CNT: description: LPTIM counter register. fields: @@ -229,13 +224,16 @@ fieldset/CR: description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. bit_offset: 4 bit_size: 1 -fieldset/DIER_intput: +fieldset/DIER_input: description: LPTIM interrupt enable register. fields: - - name: CC1IE + - name: CCIE description: Capture/compare 1 interrupt enable. bit_offset: 0 bit_size: 1 + array: + len: 2 + stride: 9 - name: ARRMIE description: Autoreload match Interrupt Enable. bit_offset: 1 @@ -264,37 +262,34 @@ fieldset/DIER_intput: description: Repetition register update OK interrupt Enable. bit_offset: 8 bit_size: 1 - - name: CC2IE - description: 'Capture/compare 2 interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' - bit_offset: 9 - bit_size: 1 - - name: CC1OIE + - name: CCOIE description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' bit_offset: 12 bit_size: 1 - - name: CC2OIE - description: 'Capture/compare 2 over-capture interrupt enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' - bit_offset: 13 - bit_size: 1 - - name: CC1DE + array: + len: 2 + stride: 1 + - name: CCDE description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' bit_offset: 16 bit_size: 1 + array: + len: 2 + stride: 9 - name: UEDE description: 'Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' bit_offset: 23 bit_size: 1 - - name: CC2DE - description: 'Capture/compare 2 DMA request enable Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' - bit_offset: 25 - bit_size: 1 fieldset/DIER_output: description: LPTIM interrupt enable register. fields: - - name: CC1IE + - name: CCIE description: Capture/compare 1 interrupt enable. bit_offset: 0 bit_size: 1 + array: + len: 1 + stride: 0 - name: ARRMIE description: Autoreload match Interrupt Enable. bit_offset: 1 @@ -303,10 +298,13 @@ fieldset/DIER_output: description: External trigger valid edge Interrupt Enable. bit_offset: 2 bit_size: 1 - - name: CMP1OKIE + - name: CMPOKIE description: Compare register 1 update OK interrupt enable. bit_offset: 3 bit_size: 1 + array: + len: 1 + stride: 0 - name: ARROKIE description: Autoreload register update OK Interrupt Enable. bit_offset: 4 @@ -327,13 +325,16 @@ fieldset/DIER_output: description: Repetition register update OK interrupt Enable. bit_offset: 8 bit_size: 1 -fieldset/ICR_intput: +fieldset/ICR_input: description: LPTIM interrupt clear register. fields: - - name: CC1CF + - name: CCCF description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. bit_offset: 0 bit_size: 1 + array: + len: 2 + stride: 9 - name: ARRMCF description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. bit_offset: 1 @@ -362,18 +363,13 @@ fieldset/ICR_intput: description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. bit_offset: 8 bit_size: 1 - - name: CC2CF - description: 'Capture/compare 2 clear flag Writing 1 to this bit clears the CC2IF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' - bit_offset: 9 - bit_size: 1 - - name: CC1OCF + - name: CCOCF description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' bit_offset: 12 bit_size: 1 - - name: CC2OCF - description: 'Capture/compare 2 over-capture clear flag Writing 1 to this bit clears the CC2OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' - bit_offset: 13 - bit_size: 1 + array: + len: 2 + stride: 1 - name: DIEROKCF description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. bit_offset: 24 @@ -381,10 +377,13 @@ fieldset/ICR_intput: fieldset/ICR_output: description: LPTIM interrupt clear register. fields: - - name: CC1CF + - name: CCCF description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. bit_offset: 0 bit_size: 1 + array: + len: 1 + stride: 0 - name: ARRMCF description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. bit_offset: 1 @@ -393,10 +392,13 @@ fieldset/ICR_output: description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. bit_offset: 2 bit_size: 1 - - name: CMP1OKCF + - name: CMPOKCF description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. bit_offset: 3 bit_size: 1 + array: + len: 1 + stride: 0 - name: ARROKCF description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. bit_offset: 4 @@ -421,13 +423,16 @@ fieldset/ICR_output: description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. bit_offset: 24 bit_size: 1 -fieldset/ISR_intput: +fieldset/ISR_input: description: LPTIM interrupt and status register. fields: - - name: CC1IF + - name: CCIF description: 'capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high.' bit_offset: 0 bit_size: 1 + array: + len: 2 + stride: 9 - name: ARRM description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. bit_offset: 1 @@ -456,18 +461,13 @@ fieldset/ISR_intput: description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. bit_offset: 8 bit_size: 1 - - name: CC2IF - description: 'Capture 2 interrupt flag If channel CC2 is configured as input: CC2IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR2 register. The corresponding interrupt or DMA request is generated if enabled. The CC2OF flag is set if the CC2IF flag was already high. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' - bit_offset: 9 - bit_size: 1 - - name: CC1OF + - name: CCOF description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' bit_offset: 12 bit_size: 1 - - name: CC2OF - description: 'Capture 2 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC2OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 2 channels this bit is reserved. Please refer to.' - bit_offset: 13 - bit_size: 1 + array: + len: 2 + stride: 1 - name: DIEROK description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. bit_offset: 24 @@ -475,10 +475,13 @@ fieldset/ISR_intput: fieldset/ISR_output: description: LPTIM interrupt and status register. fields: - - name: CC1IF + - name: CCIF description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. bit_offset: 0 bit_size: 1 + array: + len: 1 + stride: 0 - name: ARRM description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. bit_offset: 1 @@ -487,10 +490,13 @@ fieldset/ISR_output: description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. bit_offset: 2 bit_size: 1 - - name: CMP1OK + - name: CMPOK description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. bit_offset: 3 bit_size: 1 + array: + len: 1 + stride: 0 - name: ARROK description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. bit_offset: 4 diff --git a/transforms/LPTIM.yaml b/transforms/LPTIM.yaml new file mode 100644 index 0000000..4a2bba1 --- /dev/null +++ b/transforms/LPTIM.yaml @@ -0,0 +1,57 @@ +transforms: + + - !Rename + from: ^LPTIM1$ + to: LPTIM_Adv + + - !RenameRegisters + block: LPTIM_Adv + from: (.*)intput + to: ${1}input + + - !Rename + from: (.*)intput + to: ${1}input + + - !MakeBlock + blocks: ^LPTIM_Adv$ + from: ^(.+)_output$ + to_outer: Output + to_block: Output + to_inner: ${1} + + - !MakeBlock + blocks: ^LPTIM_Adv$ + from: ^(.+)_input$ + to_outer: Input + to_block: Input + to_inner: ${1} + + - !RenameFields + fieldset: CCR\d + from: CCR\d + to: CCR + + - !MergeFieldsets + from: CCR\d + to: CCR + + - !MakeRegisterArray + blocks: LPTIM_Adv + from: CCR\d + to: CCR + + - !MakeFieldArray + fieldsets: CFGR2 + from: (I[CN])\d(SEL) + to: $1$2 + + - !MakeFieldArray + fieldsets: CCMR\d + from: (.*)\d(.*) + to: $1$2 + + - !MakeFieldArray + fieldsets: (ISR|ICR|DIER).* + from: (.*)\d(.*) + to: $1$2 From 8bfe8b90f4e0119f324eecc99bdfb9cc1e3f138c Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 21:15:34 +0800 Subject: [PATCH 03/11] split lptim and bug fix ... LPTIM4 has less function, so it's a LPTIM_Basic, the reset are full feature, thus a LPTIM_Adv. --- data/registers/lptim_v2h5.yaml | 142 ++++++++++++++++++++++++++------- 1 file changed, 112 insertions(+), 30 deletions(-) diff --git a/data/registers/lptim_v2h5.yaml b/data/registers/lptim_v2h5.yaml index c11e2bf..3824522 100644 --- a/data/registers/lptim_v2h5.yaml +++ b/data/registers/lptim_v2h5.yaml @@ -1,26 +1,40 @@ -block/Input: +block/IC: items: - name: ISR description: LPTIM interrupt and status register. byte_offset: 0 - fieldset: ISR_input + fieldset: ISR_IC - name: ICR description: LPTIM interrupt clear register. byte_offset: 4 - fieldset: ICR_input + fieldset: ICR_IC - name: DIER description: LPTIM interrupt enable register. byte_offset: 8 - fieldset: DIER_input + fieldset: DIER_IC block/LPTIM_Adv: - description: Low power timer. + extends: LPTIM_Basic + description: Low power timer with Output Compare items: - - name: Input + - name: InputCapture byte_offset: 0 - block: Input - - name: Output + block: IC + - name: OutputCompare byte_offset: 0 - block: Output + block: OC_Adv + - name: CCR + description: LPTIM compare register 1. + array: + len: 2 + stride: 32 + byte_offset: 20 + fieldset: CCR +block/LPTIM_Basic: + description: Low power timer with Output Compare + items: + - name: OutputCompare + byte_offset: 0 + block: OC_Basic - name: CFGR description: LPTIM configuration register. byte_offset: 12 @@ -32,7 +46,7 @@ block/LPTIM_Adv: - name: CCR description: LPTIM compare register 1. array: - len: 2 + len: 1 stride: 32 byte_offset: 20 fieldset: CCR @@ -52,24 +66,38 @@ block/LPTIM_Adv: description: LPTIM repetition register. byte_offset: 40 fieldset: RCR - - name: CCMR1 - description: LPTIM capture/compare mode register 1. - byte_offset: 44 - fieldset: CCMR1 -block/Output: +block/OC_Adv: items: - name: ISR description: LPTIM interrupt and status register. byte_offset: 0 - fieldset: ISR_output + fieldset: ISR_OC_Adv - name: ICR description: LPTIM interrupt clear register. byte_offset: 4 - fieldset: ICR_output + fieldset: ICR_OC_Adv - name: DIER description: LPTIM interrupt enable register. byte_offset: 8 - fieldset: DIER_output + fieldset: DIER_OC_Adv + - name: CCMR1 + description: LPTIM capture/compare mode register 1. + byte_offset: 44 + fieldset: CCMR1 +block/OC_Basic: + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR_OC_Basic + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR_OC_Basic + - name: DIER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER_OC_Basic fieldset/ARR: description: LPTIM autoreload register. fields: @@ -224,7 +252,7 @@ fieldset/CR: description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. bit_offset: 4 bit_size: 1 -fieldset/DIER_input: +fieldset/DIER_IC: description: LPTIM interrupt enable register. fields: - name: CCIE @@ -280,7 +308,25 @@ fieldset/DIER_input: description: 'Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' bit_offset: 23 bit_size: 1 -fieldset/DIER_output: +fieldset/DIER_OC_Adv: + extends: DIER_OC_Basic + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 9 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/DIER_OC_Basic: description: LPTIM interrupt enable register. fields: - name: CCIE @@ -289,7 +335,7 @@ fieldset/DIER_output: bit_size: 1 array: len: 1 - stride: 0 + stride: 9 - name: ARRMIE description: Autoreload match Interrupt Enable. bit_offset: 1 @@ -304,7 +350,7 @@ fieldset/DIER_output: bit_size: 1 array: len: 1 - stride: 0 + stride: 16 - name: ARROKIE description: Autoreload register update OK Interrupt Enable. bit_offset: 4 @@ -325,7 +371,7 @@ fieldset/DIER_output: description: Repetition register update OK interrupt Enable. bit_offset: 8 bit_size: 1 -fieldset/ICR_input: +fieldset/ICR_IC: description: LPTIM interrupt clear register. fields: - name: CCCF @@ -374,7 +420,25 @@ fieldset/ICR_input: description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. bit_offset: 24 bit_size: 1 -fieldset/ICR_output: +fieldset/ICR_OC_Adv: + extends: ICR_OC_Basic + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 9 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/ICR_OC_Basic: description: LPTIM interrupt clear register. fields: - name: CCCF @@ -383,7 +447,7 @@ fieldset/ICR_output: bit_size: 1 array: len: 1 - stride: 0 + stride: 9 - name: ARRMCF description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. bit_offset: 1 @@ -398,7 +462,7 @@ fieldset/ICR_output: bit_size: 1 array: len: 1 - stride: 0 + stride: 16 - name: ARROKCF description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. bit_offset: 4 @@ -423,7 +487,7 @@ fieldset/ICR_output: description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. bit_offset: 24 bit_size: 1 -fieldset/ISR_input: +fieldset/ISR_IC: description: LPTIM interrupt and status register. fields: - name: CCIF @@ -472,7 +536,25 @@ fieldset/ISR_input: description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. bit_offset: 24 bit_size: 1 -fieldset/ISR_output: +fieldset/ISR_OC_Adv: + extends: ISR_OC_Basic + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 9 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/ISR_OC_Basic: description: LPTIM interrupt and status register. fields: - name: CCIF @@ -481,7 +563,7 @@ fieldset/ISR_output: bit_size: 1 array: len: 1 - stride: 0 + stride: 9 - name: ARRM description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. bit_offset: 1 @@ -496,7 +578,7 @@ fieldset/ISR_output: bit_size: 1 array: len: 1 - stride: 0 + stride: 16 - name: ARROK description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. bit_offset: 4 From 8bd35deb5603bf83345b46d8cad420d1c029d6a3 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 22:21:19 +0800 Subject: [PATCH 04/11] add enum --- data/registers/lptim_v2h5.yaml | 143 ++++++++++++++++++++++++++++++--- 1 file changed, 132 insertions(+), 11 deletions(-) diff --git a/data/registers/lptim_v2h5.yaml b/data/registers/lptim_v2h5.yaml index 3824522..791c1ea 100644 --- a/data/registers/lptim_v2h5.yaml +++ b/data/registers/lptim_v2h5.yaml @@ -80,10 +80,14 @@ block/OC_Adv: description: LPTIM interrupt enable register. byte_offset: 8 fieldset: DIER_OC_Adv - - name: CCMR1 + - name: CCMR_IC description: LPTIM capture/compare mode register 1. byte_offset: 44 - fieldset: CCMR1 + fieldset: CCMR_IC + - name: CCMR_OC + description: LPTIM capture/compare mode register 1. + byte_offset: 44 + fieldset: CCMR_OC block/OC_Basic: items: - name: ISR @@ -105,8 +109,32 @@ fieldset/ARR: description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. bit_offset: 0 bit_size: 16 -fieldset/CCMR1: - description: LPTIM capture/compare mode register 1. +fieldset/CCMR_IC: + extends: CCMR_partial + description: LPTIM input capture mode register 1. + fields: + - name: CCP + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: CCP_IC +fieldset/CCMR_OC: + extends: CCMR_partial + description: LPTIM output compare mode register 1. + fields: + - name: CCP + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: CCP_OC +fieldset/CCMR_partial: + description: internal use only - common fields between CCMR input mode and output mode fields: - name: CCSEL description: Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. @@ -115,6 +143,7 @@ fieldset/CCMR1: array: len: 2 stride: 16 + enum: CCSEL - name: CCE description: Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. bit_offset: 1 @@ -122,13 +151,6 @@ fieldset/CCMR1: array: len: 2 stride: 16 - - name: CCP - description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 16 - name: ICPSC description: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). bit_offset: 8 @@ -136,6 +158,7 @@ fieldset/CCMR1: array: len: 2 stride: 16 + enum: Filter - name: ICF description: Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. bit_offset: 12 @@ -143,6 +166,7 @@ fieldset/CCMR1: array: len: 2 stride: 16 + enum: Filter fieldset/CCR: description: LPTIM compare register 1. fields: @@ -157,22 +181,27 @@ fieldset/CFGR: description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. bit_offset: 0 bit_size: 1 + enum: CKSEL - name: CKPOL description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' bit_offset: 1 bit_size: 2 + enum: CKPOL - name: CKFLT description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. bit_offset: 3 bit_size: 2 + enum: Filter - name: TRGFLT description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. bit_offset: 6 bit_size: 2 + enum: Filter - name: PRESC description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. bit_offset: 9 bit_size: 3 + enum: PRESC - name: TRIGSEL description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' bit_offset: 13 @@ -181,6 +210,7 @@ fieldset/CFGR: description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. bit_offset: 17 bit_size: 2 + enum: TRIGEN - name: TIMOUT description: Timeout enable The TIMOUT bit controls the Timeout feature. bit_offset: 19 @@ -610,3 +640,94 @@ fieldset/RCR: description: Repetition register value REP is the repetition value for the LPTIM. bit_offset: 0 bit_size: 8 +enum/CCP_IC: + bit_size: 2 + variants: + - name: Rising + value: 0 + - name: Falling + value: 1 + - name: Both + value: 3 +enum/CCP_OC: + bit_size: 2 + variants: + - name: ActiveHigh + value: 0 + - name: ActiveLow + value: 1 +enum/CCSEL: + bit_size: 1 + variants: + - name: OutputCompare + description: channel is configured in output PWM mode + value: 0 + - name: InputCapture + description: channel is configured in input capture mode + value: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/CKSEL: + bit_size: 1 + variants: + - name: Internal + description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: LPTIM is clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 From 59cb83596fa2efdcde31acaca7f703d449b9a7c6 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 22:37:04 +0800 Subject: [PATCH 05/11] add to chips.rs --- data/registers/lptim_v2h5.yaml | 60 +++++++++++++++++----------------- stm32-data-gen/src/chips.rs | 6 +++- 2 files changed, 35 insertions(+), 31 deletions(-) diff --git a/data/registers/lptim_v2h5.yaml b/data/registers/lptim_v2h5.yaml index 791c1ea..b2db01b 100644 --- a/data/registers/lptim_v2h5.yaml +++ b/data/registers/lptim_v2h5.yaml @@ -12,8 +12,8 @@ block/IC: description: LPTIM interrupt enable register. byte_offset: 8 fieldset: DIER_IC -block/LPTIM_Adv: - extends: LPTIM_Basic +block/LPTIM_ADV: + extends: LPTIM_BASIC description: Low power timer with Output Compare items: - name: InputCapture @@ -21,7 +21,7 @@ block/LPTIM_Adv: block: IC - name: OutputCompare byte_offset: 0 - block: OC_Adv + block: OC_ADV - name: CCR description: LPTIM compare register 1. array: @@ -29,12 +29,20 @@ block/LPTIM_Adv: stride: 32 byte_offset: 20 fieldset: CCR -block/LPTIM_Basic: + - name: CCMR_IC + description: LPTIM capture/compare mode register 1. + byte_offset: 44 + fieldset: CCMR_IC + - name: CCMR_OC + description: LPTIM capture/compare mode register 1. + byte_offset: 44 + fieldset: CCMR_OC +block/LPTIM_BASIC: description: Low power timer with Output Compare items: - name: OutputCompare byte_offset: 0 - block: OC_Basic + block: OC_BASIC - name: CFGR description: LPTIM configuration register. byte_offset: 12 @@ -66,42 +74,34 @@ block/LPTIM_Basic: description: LPTIM repetition register. byte_offset: 40 fieldset: RCR -block/OC_Adv: +block/OC_ADV: items: - name: ISR description: LPTIM interrupt and status register. byte_offset: 0 - fieldset: ISR_OC_Adv + fieldset: ISR_OC_ADV - name: ICR description: LPTIM interrupt clear register. byte_offset: 4 - fieldset: ICR_OC_Adv + fieldset: ICR_OC_ADV - name: DIER description: LPTIM interrupt enable register. byte_offset: 8 - fieldset: DIER_OC_Adv - - name: CCMR_IC - description: LPTIM capture/compare mode register 1. - byte_offset: 44 - fieldset: CCMR_IC - - name: CCMR_OC - description: LPTIM capture/compare mode register 1. - byte_offset: 44 - fieldset: CCMR_OC -block/OC_Basic: + fieldset: DIER_OC_ADV +block/OC_BASIC: items: - name: ISR description: LPTIM interrupt and status register. byte_offset: 0 - fieldset: ISR_OC_Basic + fieldset: ISR_OC_BASIC - name: ICR description: LPTIM interrupt clear register. byte_offset: 4 - fieldset: ICR_OC_Basic + fieldset: ICR_OC_BASIC - name: DIER description: LPTIM interrupt enable register. byte_offset: 8 - fieldset: DIER_OC_Basic + fieldset: DIER_OC_BASIC fieldset/ARR: description: LPTIM autoreload register. fields: @@ -338,8 +338,8 @@ fieldset/DIER_IC: description: 'Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' bit_offset: 23 bit_size: 1 -fieldset/DIER_OC_Adv: - extends: DIER_OC_Basic +fieldset/DIER_OC_ADV: + extends: DIER_OC_BASIC description: LPTIM interrupt enable register. fields: - name: CCIE @@ -356,7 +356,7 @@ fieldset/DIER_OC_Adv: array: len: 2 stride: 16 -fieldset/DIER_OC_Basic: +fieldset/DIER_OC_BASIC: description: LPTIM interrupt enable register. fields: - name: CCIE @@ -450,8 +450,8 @@ fieldset/ICR_IC: description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. bit_offset: 24 bit_size: 1 -fieldset/ICR_OC_Adv: - extends: ICR_OC_Basic +fieldset/ICR_OC_ADV: + extends: ICR_OC_BASIC description: LPTIM interrupt clear register. fields: - name: CCCF @@ -468,7 +468,7 @@ fieldset/ICR_OC_Adv: array: len: 2 stride: 16 -fieldset/ICR_OC_Basic: +fieldset/ICR_OC_BASIC: description: LPTIM interrupt clear register. fields: - name: CCCF @@ -566,8 +566,8 @@ fieldset/ISR_IC: description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. bit_offset: 24 bit_size: 1 -fieldset/ISR_OC_Adv: - extends: ISR_OC_Basic +fieldset/ISR_OC_ADV: + extends: ISR_OC_BASIC description: LPTIM interrupt and status register. fields: - name: CCIF @@ -584,7 +584,7 @@ fieldset/ISR_OC_Adv: array: len: 2 stride: 16 -fieldset/ISR_OC_Basic: +fieldset/ISR_OC_BASIC: description: LPTIM interrupt and status register. fields: - name: CCIF diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index bacb4b6..fbe912a 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -503,7 +503,11 @@ impl PeriMatcher { ("STM32(C|G0|H7|WB|WL).*:TIM12:.*", ("timer", "v1", "TIM_2CH")), ("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), - ("STM32[CGHUW].*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")), + // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials + ("STM32H5.*:LPTIM[12356]:.*", ("lptim", "v2h5", "LPTIM_ADV")), + ("STM32H5.*:LPTIM4:.*", ("lptim", "v2h5", "LPTIM_BASIC")), + ("STM32(C|G|H7|U|W).*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")), + // HRTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")), // //// TIM mapping ends here //// From 029320446bf99e233da98c0cf7b25f3a0c4bd4e4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 23:09:58 +0800 Subject: [PATCH 06/11] add lptim to u5 wba --- .../{lptim_v2h5.yaml => lptim_v2b.yaml} | 215 +++++++++--------- stm32-data-gen/src/chips.rs | 4 +- 2 files changed, 107 insertions(+), 112 deletions(-) rename data/registers/{lptim_v2h5.yaml => lptim_v2b.yaml} (99%) diff --git a/data/registers/lptim_v2h5.yaml b/data/registers/lptim_v2b.yaml similarity index 99% rename from data/registers/lptim_v2h5.yaml rename to data/registers/lptim_v2b.yaml index b2db01b..5a4213b 100644 --- a/data/registers/lptim_v2h5.yaml +++ b/data/registers/lptim_v2b.yaml @@ -40,9 +40,18 @@ block/LPTIM_ADV: block/LPTIM_BASIC: description: Low power timer with Output Compare items: - - name: OutputCompare + - name: ISR + description: LPTIM interrupt and status register. byte_offset: 0 - block: OC_BASIC + fieldset: ISR_BASIC + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR_BASIC + - name: DIER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER_BASIC - name: CFGR description: LPTIM configuration register. byte_offset: 12 @@ -88,20 +97,6 @@ block/OC_ADV: description: LPTIM interrupt enable register. byte_offset: 8 fieldset: DIER_OC_ADV -block/OC_BASIC: - items: - - name: ISR - description: LPTIM interrupt and status register. - byte_offset: 0 - fieldset: ISR_OC_BASIC - - name: ICR - description: LPTIM interrupt clear register. - byte_offset: 4 - fieldset: ICR_OC_BASIC - - name: DIER - description: LPTIM interrupt enable register. - byte_offset: 8 - fieldset: DIER_OC_BASIC fieldset/ARR: description: LPTIM autoreload register. fields: @@ -282,6 +277,51 @@ fieldset/CR: description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. bit_offset: 4 bit_size: 1 +fieldset/DIER_BASIC: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UEIE + description: Update event interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: REPOKIE + description: Repetition register update OK interrupt Enable. + bit_offset: 8 + bit_size: 1 fieldset/DIER_IC: description: LPTIM interrupt enable register. fields: @@ -339,7 +379,7 @@ fieldset/DIER_IC: bit_offset: 23 bit_size: 1 fieldset/DIER_OC_ADV: - extends: DIER_OC_BASIC + extends: DIER_BASIC description: LPTIM interrupt enable register. fields: - name: CCIE @@ -356,51 +396,55 @@ fieldset/DIER_OC_ADV: array: len: 2 stride: 16 -fieldset/DIER_OC_BASIC: - description: LPTIM interrupt enable register. +fieldset/ICR_BASIC: + description: LPTIM interrupt clear register. fields: - - name: CCIE - description: Capture/compare 1 interrupt enable. + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. bit_offset: 0 bit_size: 1 array: len: 1 stride: 9 - - name: ARRMIE - description: Autoreload match Interrupt Enable. + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. bit_offset: 1 bit_size: 1 - - name: EXTTRIGIE - description: External trigger valid edge Interrupt Enable. + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. bit_offset: 2 bit_size: 1 - - name: CMPOKIE - description: Compare register 1 update OK interrupt enable. + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. bit_offset: 3 bit_size: 1 array: len: 1 stride: 16 - - name: ARROKIE - description: Autoreload register update OK Interrupt Enable. + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. bit_offset: 4 bit_size: 1 - - name: UPIE - description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 5 bit_size: 1 - - name: DOWNIE - description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 6 bit_size: 1 - - name: UEIE - description: Update event interrupt enable. + - name: UECF + description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. bit_offset: 7 bit_size: 1 - - name: REPOKIE - description: Repetition register update OK interrupt Enable. + - name: REPOKCF + description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. bit_offset: 8 bit_size: 1 + - name: DIEROKCF + description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + bit_offset: 24 + bit_size: 1 fieldset/ICR_IC: description: LPTIM interrupt clear register. fields: @@ -451,7 +495,7 @@ fieldset/ICR_IC: bit_offset: 24 bit_size: 1 fieldset/ICR_OC_ADV: - extends: ICR_OC_BASIC + extends: ICR_BASIC description: LPTIM interrupt clear register. fields: - name: CCCF @@ -468,53 +512,53 @@ fieldset/ICR_OC_ADV: array: len: 2 stride: 16 -fieldset/ICR_OC_BASIC: - description: LPTIM interrupt clear register. +fieldset/ISR_BASIC: + description: LPTIM interrupt and status register. fields: - - name: CCCF - description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. bit_offset: 0 bit_size: 1 array: len: 1 stride: 9 - - name: ARRMCF - description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. bit_offset: 1 bit_size: 1 - - name: EXTTRIGCF - description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. bit_offset: 2 bit_size: 1 - - name: CMPOKCF - description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. bit_offset: 3 bit_size: 1 array: len: 1 stride: 16 - - name: ARROKCF - description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. bit_offset: 4 bit_size: 1 - - name: UPCF - description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 5 bit_size: 1 - - name: DOWNCF - description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 6 bit_size: 1 - - name: UECF - description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + - name: UE + description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. bit_offset: 7 bit_size: 1 - - name: REPOKCF - description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + - name: REPOK + description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. bit_offset: 8 bit_size: 1 - - name: DIEROKCF - description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + - name: DIEROK + description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. bit_offset: 24 bit_size: 1 fieldset/ISR_IC: @@ -567,7 +611,7 @@ fieldset/ISR_IC: bit_offset: 24 bit_size: 1 fieldset/ISR_OC_ADV: - extends: ISR_OC_BASIC + extends: ISR_BASIC description: LPTIM interrupt and status register. fields: - name: CCIF @@ -584,55 +628,6 @@ fieldset/ISR_OC_ADV: array: len: 2 stride: 16 -fieldset/ISR_OC_BASIC: - description: LPTIM interrupt and status register. - fields: - - name: CCIF - description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - bit_offset: 0 - bit_size: 1 - array: - len: 1 - stride: 9 - - name: ARRM - description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - bit_offset: 1 - bit_size: 1 - - name: EXTTRIG - description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - bit_offset: 2 - bit_size: 1 - - name: CMPOK - description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 16 - - name: ARROK - description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - bit_offset: 4 - bit_size: 1 - - name: UP - description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' - bit_offset: 5 - bit_size: 1 - - name: DOWN - description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' - bit_offset: 6 - bit_size: 1 - - name: UE - description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. - bit_offset: 7 - bit_size: 1 - - name: REPOK - description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. - bit_offset: 8 - bit_size: 1 - - name: DIEROK - description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. - bit_offset: 24 - bit_size: 1 fieldset/RCR: description: LPTIM repetition register. fields: diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index fbe912a..675fd89 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -504,8 +504,8 @@ impl PeriMatcher { ("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials - ("STM32H5.*:LPTIM[12356]:.*", ("lptim", "v2h5", "LPTIM_ADV")), - ("STM32H5.*:LPTIM4:.*", ("lptim", "v2h5", "LPTIM_BASIC")), + ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2b", "LPTIM_ADV")), + ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2b", "LPTIM_BASIC")), ("STM32(C|G|H7|U|W).*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")), // HRTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")), From c25b401647255a60450b147a8dd3a4401a3951ec Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 23:40:12 +0800 Subject: [PATCH 07/11] extract lptim_v2a from l5 --- data/registers/lptim_v2a.yaml | 280 ++++++++++++++++++++++++++++++++++ 1 file changed, 280 insertions(+) create mode 100644 data/registers/lptim_v2a.yaml diff --git a/data/registers/lptim_v2a.yaml b/data/registers/lptim_v2a.yaml new file mode 100644 index 0000000..1ef25d7 --- /dev/null +++ b/data/registers/lptim_v2a.yaml @@ -0,0 +1,280 @@ +block/LPTIM1: + description: Low power timer. + items: + - name: ISR + description: Interrupt and Status Register. + byte_offset: 0 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt Clear Register. + byte_offset: 4 + access: Write + fieldset: ICR + - name: IER + description: Interrupt Enable Register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: Configuration Register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: Control Register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: Compare Register. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: Autoreload Register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: Counter Register. + byte_offset: 28 + access: Read + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 + fieldset: OR + - name: RCR + description: LPTIM repetition register. + byte_offset: 40 + fieldset: RCR +fieldset/ARR: + description: Autoreload Register. + fields: + - name: ARR + description: Auto reload value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: Configuration Register. + fields: + - name: CKSEL + description: Clock selector. + bit_offset: 0 + bit_size: 1 + - name: CKPOL + description: Clock Polarity. + bit_offset: 1 + bit_size: 2 + - name: CKFLT + description: Configurable digital filter for external clock. + bit_offset: 3 + bit_size: 2 + - name: TRGFLT + description: Configurable digital filter for trigger. + bit_offset: 6 + bit_size: 2 + - name: PRESC + description: Clock prescaler. + bit_offset: 9 + bit_size: 3 + - name: TRIGSEL + description: Trigger selector. + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity. + bit_offset: 17 + bit_size: 2 + - name: TIMOUT + description: Timeout enable. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: Waveform shape polarity. + bit_offset: 21 + bit_size: 1 + - name: PRELOAD + description: Registers update mode. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled. + bit_offset: 23 + bit_size: 1 + - name: ENC + description: Encoder mode enable. + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: Compare Register. + fields: + - name: CMP + description: Compare value. + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: Counter Register. + fields: + - name: CNT + description: Counter value. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: Control Register. + fields: + - name: ENABLE + description: LPTIM Enable. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in single mode. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in continuous mode. + bit_offset: 2 + bit_size: 1 + - name: RSTARE + description: Reset after read enable. + bit_offset: 3 + bit_size: 1 + - name: COUNTRST + description: Counter reset. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: Interrupt Clear Register. + fields: + - name: CMPMCF + description: compare match Clear Flag. + bit_offset: 0 + bit_size: 1 + - name: ARRMCF + description: Autoreload match Clear Flag. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge Clear Flag. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register update OK Clear Flag. + bit_offset: 3 + bit_size: 1 + - name: ARROKCF + description: Autoreload register update OK Clear Flag. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: Direction change to UP Clear Flag. + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: Direction change to down Clear Flag. + bit_offset: 6 + bit_size: 1 + - name: UECF + description: Update event clear flag. + bit_offset: 7 + bit_size: 1 + - name: REPOKCF + description: Repetition register update OK clear flag. + bit_offset: 8 + bit_size: 1 +fieldset/IER: + description: Interrupt Enable Register. + fields: + - name: CMPMIE + description: Compare match Interrupt Enable. + bit_offset: 0 + bit_size: 1 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register update OK Interrupt Enable. + bit_offset: 3 + bit_size: 1 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: Direction change to UP Interrupt Enable. + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: Direction change to down Interrupt Enable. + bit_offset: 6 + bit_size: 1 + - name: UEIE + description: Update event interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: REPOKIE + description: REPOKIE. + bit_offset: 8 + bit_size: 1 +fieldset/ISR: + description: Interrupt and Status Register. + fields: + - name: CMPM + description: Compare match. + bit_offset: 0 + bit_size: 1 + - name: ARRM + description: Autoreload match. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register update OK. + bit_offset: 3 + bit_size: 1 + - name: ARROK + description: Autoreload register update OK. + bit_offset: 4 + bit_size: 1 + - name: UP + description: Counter direction change down to up. + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: Counter direction change up to down. + bit_offset: 6 + bit_size: 1 + - name: UE + description: LPTIM update event occurred. + bit_offset: 7 + bit_size: 1 + - name: REPOK + description: Repetition register update Ok. + bit_offset: 8 + bit_size: 1 +fieldset/OR: + description: LPTIM option register. + fields: + - name: OR_0 + description: Option register bit 0. + bit_offset: 0 + bit_size: 1 + - name: OR_1 + description: Option register bit 1. + bit_offset: 1 + bit_size: 1 +fieldset/RCR: + description: LPTIM repetition register. + fields: + - name: REP + description: Repetition register value. + bit_offset: 0 + bit_size: 8 From 8b036d7f87fe2f5a98e11aaa65f7084811a5330e Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 4 Apr 2024 23:47:06 +0800 Subject: [PATCH 08/11] add enum --- data/registers/lptim_v2a.yaml | 56 +++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/data/registers/lptim_v2a.yaml b/data/registers/lptim_v2a.yaml index 1ef25d7..6957bfc 100644 --- a/data/registers/lptim_v2a.yaml +++ b/data/registers/lptim_v2a.yaml @@ -58,22 +58,27 @@ fieldset/CFGR: description: Clock selector. bit_offset: 0 bit_size: 1 + enum: CKSEL - name: CKPOL description: Clock Polarity. bit_offset: 1 bit_size: 2 + enum: CKPOL - name: CKFLT description: Configurable digital filter for external clock. bit_offset: 3 bit_size: 2 + enum: Filter - name: TRGFLT description: Configurable digital filter for trigger. bit_offset: 6 bit_size: 2 + enum: Filter - name: PRESC description: Clock prescaler. bit_offset: 9 bit_size: 3 + enum: PRESC - name: TRIGSEL description: Trigger selector. bit_offset: 13 @@ -278,3 +283,54 @@ fieldset/RCR: description: Repetition register value. bit_offset: 0 bit_size: 8 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/CKSEL: + bit_size: 1 + variants: + - name: Internal + description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: LPTIM is clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 From d9625637f28d8f6563913b5cd24ddb038f0d6921 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Fri, 5 Apr 2024 00:03:53 +0800 Subject: [PATCH 09/11] add lptim_v2a to chips.rs --- data/registers/lptim_v2a.yaml | 14 +------------- stm32-data-gen/src/chips.rs | 8 ++++---- transforms/LPTIM_v2a.yaml | 8 ++++++++ transforms/{LPTIM.yaml => LPTIM_v2b.yaml} | 0 4 files changed, 13 insertions(+), 17 deletions(-) create mode 100644 transforms/LPTIM_v2a.yaml rename transforms/{LPTIM.yaml => LPTIM_v2b.yaml} (100%) diff --git a/data/registers/lptim_v2a.yaml b/data/registers/lptim_v2a.yaml index 6957bfc..614eb21 100644 --- a/data/registers/lptim_v2a.yaml +++ b/data/registers/lptim_v2a.yaml @@ -1,4 +1,4 @@ -block/LPTIM1: +block/LPTIM: description: Low power timer. items: - name: ISR @@ -39,7 +39,6 @@ block/LPTIM1: - name: OR description: LPTIM option register. byte_offset: 32 - fieldset: OR - name: RCR description: LPTIM repetition register. byte_offset: 40 @@ -265,17 +264,6 @@ fieldset/ISR: description: Repetition register update Ok. bit_offset: 8 bit_size: 1 -fieldset/OR: - description: LPTIM option register. - fields: - - name: OR_0 - description: Option register bit 0. - bit_offset: 0 - bit_size: 1 - - name: OR_1 - description: Option register bit 1. - bit_offset: 1 - bit_size: 1 fieldset/RCR: description: LPTIM repetition register. fields: diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 675fd89..224c924 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -481,6 +481,7 @@ impl PeriMatcher { ("STM32L.*:TIM(9|21|22):.*", ("timer", "v1", "TIM_2CH")), ("STM32L.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32L.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), + ("STM32L5.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")), ("STM32L.*:LPTIM(1|2|3):.*", ("lptim", "v1", "LPTIM")), // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials @@ -493,6 +494,9 @@ impl PeriMatcher { ("STM32(G4|H5|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")), ("STM32(G4|H5|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")), ("STM32(G4|H5|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")), + ("STM32WL.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")), + ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2b", "LPTIM_ADV")), + ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2b", "LPTIM_BASIC")), ("STM32G4.*:HRTIM1:.*", ("hrtim", "v2", "HRTIM")), // timer_v1 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32(C|G0|H7|WB|WL).*:TIM(1|8|20):.*", ("timer", "v1", "TIM_ADV")), @@ -503,11 +507,7 @@ impl PeriMatcher { ("STM32(C|G0|H7|WB|WL).*:TIM12:.*", ("timer", "v1", "TIM_2CH")), ("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), - // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials - ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2b", "LPTIM_ADV")), - ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2b", "LPTIM_BASIC")), ("STM32(C|G|H7|U|W).*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")), - // HRTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")), // //// TIM mapping ends here //// diff --git a/transforms/LPTIM_v2a.yaml b/transforms/LPTIM_v2a.yaml new file mode 100644 index 0000000..7a53546 --- /dev/null +++ b/transforms/LPTIM_v2a.yaml @@ -0,0 +1,8 @@ +transforms: + + - !Rename + from: ^LPTIM1$ + to: LPTIM + + - !DeleteFieldsets + from: OR diff --git a/transforms/LPTIM.yaml b/transforms/LPTIM_v2b.yaml similarity index 100% rename from transforms/LPTIM.yaml rename to transforms/LPTIM_v2b.yaml From f789074a4b0544826fa76ec0e3d57355c5da3845 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Fri, 5 Apr 2024 12:36:35 +0800 Subject: [PATCH 10/11] merge input mode and output mode --- data/registers/lptim_v2b.yaml | 290 +++++++++------------------------- 1 file changed, 71 insertions(+), 219 deletions(-) diff --git a/data/registers/lptim_v2b.yaml b/data/registers/lptim_v2b.yaml index 5a4213b..3182a64 100644 --- a/data/registers/lptim_v2b.yaml +++ b/data/registers/lptim_v2b.yaml @@ -1,27 +1,19 @@ -block/IC: - items: - - name: ISR - description: LPTIM interrupt and status register. - byte_offset: 0 - fieldset: ISR_IC - - name: ICR - description: LPTIM interrupt clear register. - byte_offset: 4 - fieldset: ICR_IC - - name: DIER - description: LPTIM interrupt enable register. - byte_offset: 8 - fieldset: DIER_IC block/LPTIM_ADV: extends: LPTIM_BASIC description: Low power timer with Output Compare items: - - name: InputCapture + - name: ISR + description: LPTIM interrupt and status register. byte_offset: 0 - block: IC - - name: OutputCompare - byte_offset: 0 - block: OC_ADV + fieldset: ISR_ADV + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR_ADV + - name: DIER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER_ADV - name: CCR description: LPTIM compare register 1. array: @@ -83,20 +75,6 @@ block/LPTIM_BASIC: description: LPTIM repetition register. byte_offset: 40 fieldset: RCR -block/OC_ADV: - items: - - name: ISR - description: LPTIM interrupt and status register. - byte_offset: 0 - fieldset: ISR_OC_ADV - - name: ICR - description: LPTIM interrupt clear register. - byte_offset: 4 - fieldset: ICR_OC_ADV - - name: DIER - description: LPTIM interrupt enable register. - byte_offset: 8 - fieldset: DIER_OC_ADV fieldset/ARR: description: LPTIM autoreload register. fields: @@ -277,6 +255,38 @@ fieldset/CR: description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. bit_offset: 4 bit_size: 1 +fieldset/DIER_ADV: + extends: DIER_BASIC + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 9 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CCOIE + description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CCDE + description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 16 + bit_size: 1 + array: + len: 2 + stride: 9 fieldset/DIER_BASIC: description: LPTIM interrupt enable register. fields: @@ -322,80 +332,31 @@ fieldset/DIER_BASIC: description: Repetition register update OK interrupt Enable. bit_offset: 8 bit_size: 1 -fieldset/DIER_IC: - description: LPTIM interrupt enable register. +fieldset/ICR_ADV: + extends: ICR_BASIC + description: LPTIM interrupt clear register. fields: - - name: CCIE - description: Capture/compare 1 interrupt enable. + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. bit_offset: 0 bit_size: 1 array: len: 2 stride: 9 - - name: ARRMIE - description: Autoreload match Interrupt Enable. - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGIE - description: External trigger valid edge Interrupt Enable. - bit_offset: 2 - bit_size: 1 - - name: ARROKIE - description: Autoreload register update OK Interrupt Enable. - bit_offset: 4 - bit_size: 1 - - name: UPIE - description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' - bit_offset: 5 - bit_size: 1 - - name: DOWNIE - description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' - bit_offset: 6 - bit_size: 1 - - name: UEIE - description: Update event interrupt enable. - bit_offset: 7 - bit_size: 1 - - name: REPOKIE - description: Repetition register update OK interrupt Enable. - bit_offset: 8 - bit_size: 1 - - name: CCOIE - description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: CCDE - description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' - bit_offset: 16 - bit_size: 1 - array: - len: 2 - stride: 9 - - name: UEDE - description: 'Update event DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' - bit_offset: 23 - bit_size: 1 -fieldset/DIER_OC_ADV: - extends: DIER_BASIC - description: LPTIM interrupt enable register. - fields: - - name: CCIE - description: Capture/compare 1 interrupt enable. - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 9 - - name: CMPOKIE - description: Compare register 1 update OK interrupt enable. + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. bit_offset: 3 bit_size: 1 array: len: 2 stride: 16 + - name: CCOCF + description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/ICR_BASIC: description: LPTIM interrupt clear register. fields: @@ -445,73 +406,31 @@ fieldset/ICR_BASIC: description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. bit_offset: 24 bit_size: 1 -fieldset/ICR_IC: - description: LPTIM interrupt clear register. +fieldset/ISR_ADV: + extends: ISR_BASIC + description: LPTIM interrupt and status register. fields: - - name: CCCF - description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. bit_offset: 0 bit_size: 1 array: len: 2 stride: 9 - - name: ARRMCF - description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGCF - description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. - bit_offset: 2 - bit_size: 1 - - name: ARROKCF - description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. - bit_offset: 4 - bit_size: 1 - - name: UPCF - description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' - bit_offset: 5 - bit_size: 1 - - name: DOWNCF - description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' - bit_offset: 6 - bit_size: 1 - - name: UECF - description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. - bit_offset: 7 - bit_size: 1 - - name: REPOKCF - description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. - bit_offset: 8 - bit_size: 1 - - name: CCOCF - description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: DIEROKCF - description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. - bit_offset: 24 - bit_size: 1 -fieldset/ICR_OC_ADV: - extends: ICR_BASIC - description: LPTIM interrupt clear register. - fields: - - name: CCCF - description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 9 - - name: CMPOKCF - description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. bit_offset: 3 bit_size: 1 array: len: 2 stride: 16 + - name: CCOF + description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/ISR_BASIC: description: LPTIM interrupt and status register. fields: @@ -561,73 +480,6 @@ fieldset/ISR_BASIC: description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. bit_offset: 24 bit_size: 1 -fieldset/ISR_IC: - description: LPTIM interrupt and status register. - fields: - - name: CCIF - description: 'capture 1 interrupt flag If channel CC1 is configured as input: CC1IF is set by hardware to inform application that the current value of the counter is captured in LPTIM_CCR1 register. The corresponding interrupt or DMA request is generated if enabled. The CC1OF flag is set if the CC1IF flag was already high.' - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 9 - - name: ARRM - description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. - bit_offset: 1 - bit_size: 1 - - name: EXTTRIG - description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. - bit_offset: 2 - bit_size: 1 - - name: ARROK - description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. - bit_offset: 4 - bit_size: 1 - - name: UP - description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' - bit_offset: 5 - bit_size: 1 - - name: DOWN - description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' - bit_offset: 6 - bit_size: 1 - - name: UE - description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. - bit_offset: 7 - bit_size: 1 - - name: REPOK - description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. - bit_offset: 8 - bit_size: 1 - - name: CCOF - description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: DIEROK - description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. - bit_offset: 24 - bit_size: 1 -fieldset/ISR_OC_ADV: - extends: ISR_BASIC - description: LPTIM interrupt and status register. - fields: - - name: CCIF - description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 9 - - name: CMPOK - description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 16 fieldset/RCR: description: LPTIM repetition register. fields: From 16b4fd12c155776007e50d947fd3e02e70a3b052 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Fri, 5 Apr 2024 14:59:42 +0800 Subject: [PATCH 11/11] merge lptim CCMR output and input move overlap to field level --- data/registers/lptim_v2b.yaml | 56 ++++++++++++++--------------------- 1 file changed, 22 insertions(+), 34 deletions(-) diff --git a/data/registers/lptim_v2b.yaml b/data/registers/lptim_v2b.yaml index 3182a64..de86cb0 100644 --- a/data/registers/lptim_v2b.yaml +++ b/data/registers/lptim_v2b.yaml @@ -21,14 +21,10 @@ block/LPTIM_ADV: stride: 32 byte_offset: 20 fieldset: CCR - - name: CCMR_IC + - name: CCMR description: LPTIM capture/compare mode register 1. byte_offset: 44 - fieldset: CCMR_IC - - name: CCMR_OC - description: LPTIM capture/compare mode register 1. - byte_offset: 44 - fieldset: CCMR_OC + fieldset: CCMR block/LPTIM_BASIC: description: Low power timer with Output Compare items: @@ -82,32 +78,8 @@ fieldset/ARR: description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. bit_offset: 0 bit_size: 16 -fieldset/CCMR_IC: - extends: CCMR_partial - description: LPTIM input capture mode register 1. - fields: - - name: CCP - description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 16 - enum: CCP_IC -fieldset/CCMR_OC: - extends: CCMR_partial - description: LPTIM output compare mode register 1. - fields: - - name: CCP - description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 16 - enum: CCP_OC -fieldset/CCMR_partial: - description: internal use only - common fields between CCMR input mode and output mode +fieldset/CCMR: + description: LPTIM capture/compare mode register 1. fields: - name: CCSEL description: Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. @@ -124,6 +96,22 @@ fieldset/CCMR_partial: array: len: 2 stride: 16 + - name: CCP_Input + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: CCP_Input + - name: CCP_Output + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: CCP_Output - name: ICPSC description: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). bit_offset: 8 @@ -487,7 +475,7 @@ fieldset/RCR: description: Repetition register value REP is the repetition value for the LPTIM. bit_offset: 0 bit_size: 8 -enum/CCP_IC: +enum/CCP_Input: bit_size: 2 variants: - name: Rising @@ -496,7 +484,7 @@ enum/CCP_IC: value: 1 - name: Both value: 3 -enum/CCP_OC: +enum/CCP_Output: bit_size: 2 variants: - name: ActiveHigh