timadv, enum level
This commit is contained in:
eZio Pan
parent
1cd8d830f3
commit
70282b4d94
@ -168,7 +168,7 @@ fieldset/AF2:
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array:
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len: 1
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stride: 4
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enum: BKxINP
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enum: BKINP
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- name: OCRSEL
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description: ocref_clr source selection
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bit_offset: 16
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@ -385,14 +385,22 @@ fieldset/CCMR_Output:
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fieldset/CCR:
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description: capture/compare register x (x=1-4,6)
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fields:
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- name: CCR
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description: Capture/Compare x (x=1-4,6) value (Dither mode disabled)
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- name: CCR_INPUT
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description: Input capture x (x=1-4,6) value (Dither mode disabled)
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bit_offset: 0
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bit_size: 16
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- name: CCR_DITHER
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description: Capture/Compare x (x=1-4,6) value (Dither mode enabled)
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- name: CCR_OUTPUT
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description: Output compare x (x=1-4,6) value (Dither mode disabled)
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bit_offset: 0
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bit_size: 16
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- name: CCR_OUTPUT_DITHER
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description: Output compare x (x=1-4,6) value (Dither mode enabled)
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bit_offset: 0
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bit_size: 20
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- name: CCR_INPUT_DITHER
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description: Input capture x (x=1-4,6) value (Dither mode enabled)
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bit_offset: 4
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bit_size: 16
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fieldset/CCR5:
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extends: CCR
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description: capture/compare register 5
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@ -488,7 +496,7 @@ fieldset/CR2:
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description: TI1 selection
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bit_offset: 7
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bit_size: 1
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enum: TIS
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enum: TI1S
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- name: OIS
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description: Output Idle state 1(N)-4(N)
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bit_offset: 8
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@ -621,6 +629,11 @@ fieldset/ECR:
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bit_offset: 1
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bit_size: 2
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enum: IDIR
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- name: IBLK
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description: Index blanking
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bit_offset: 3
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bit_size: 2
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enum: IBLK
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- name: FIDX
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description: First index
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bit_offset: 5
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@ -690,10 +703,10 @@ fieldset/SMCR:
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bit_size: 3
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enum: SMS
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- name: OCCS
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description: a????????
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description: OCREF clear selection
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bit_offset: 3
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bit_size: 1
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enum: SMS
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enum: OCCS
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- name: TS
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description: Trigger selection
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bit_offset: 4
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@ -708,7 +721,7 @@ fieldset/SMCR:
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description: External trigger filter
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bit_offset: 8
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bit_size: 4
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enum: ETF
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enum: FilterValue
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- name: ETPS
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description: External trigger prescaler
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bit_offset: 12
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@ -802,3 +815,489 @@ fieldset/TISEL:
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array:
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len: 4
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stride: 8
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enum/BKBID:
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bit_size: 1
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variants:
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- name: Input
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description: Break input tim_brk in input mode
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value: 0
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- name: Bidirectional
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description: Break input tim_brk in bidirectional mode
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value: 1
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enum/BKDSRM:
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bit_size: 1
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variants:
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- name: Armed
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description: Break input tim_brk is armed
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value: 0
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- name: Disarmed
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description: Break input tim_brk is disarmed
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value: 1
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enum/BKINP:
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bit_size: 1
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variants:
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- name: NotInverted
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description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1)
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value: 0
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- name: Inverted
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description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1)
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value: 1
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enum/BKP:
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bit_size: 1
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variants:
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- name: ActiveLow
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description: Break input tim_brk is active low
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value: 0
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- name: ActiveHigh
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description: Break input tim_brk is active high
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value: 1
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enum/CCDS:
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bit_size: 1
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variants:
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- name: OnCompare
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description: CCx DMA request sent when CCx event occurs
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value: 0
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- name: OnUpdate
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description: CCx DMA request sent when update event occurs
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value: 1
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enum/CCMR_Input_CCS:
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bit_size: 2
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variants:
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- name: TI4
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description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx'
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value: 1
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- name: TI3
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description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)
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value: 2
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- name: TRC
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description: CCx channel is configured as input, ICx is mapped on TRC
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value: 3
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enum/CCMR_Output_CCS:
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bit_size: 2
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variants:
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- name: Output
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description: CCx channel is configured as output
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value: 0
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enum/CKD:
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bit_size: 2
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variants:
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- name: Div1
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description: t_DTS = t_CK_INT
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value: 0
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- name: Div2
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description: t_DTS = 2 × t_CK_INT
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value: 1
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- name: Div4
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description: t_DTS = 4 × t_CK_INT
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value: 2
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enum/CMS:
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bit_size: 2
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variants:
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- name: EdgeAligned
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description: The counter counts up or down depending on the direction bit
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value: 0
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- name: CenterAligned1
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description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
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value: 1
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- name: CenterAligned2
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description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
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value: 2
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- name: CenterAligned3
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description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
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value: 3
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enum/DBSS:
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bit_size: 4
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variants:
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- name: Update
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description: Update
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value: 1
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- name: CC1
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description: CC1
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value: 2
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- name: CC2
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description: CC2
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value: 3
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- name: CC3
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description: CC3
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value: 4
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- name: CC4
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description: CC4
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value: 5
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- name: COM
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description: COM
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value: 6
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- name: Trigger
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description: Trigger
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value: 7
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enum/DIR:
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bit_size: 1
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variants:
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- name: Up
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description: Counter used as upcounter
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value: 0
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- name: Down
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description: Counter used as downcounter
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value: 1
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enum/DTAE:
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bit_size: 1
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variants:
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- name: Identical
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description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register
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value: 0
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- name: Distinct
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description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits.
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value: 1
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enum/ETP:
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bit_size: 1
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variants:
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- name: NotInverted
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description: ETR is noninverted, active at high level or rising edge
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value: 0
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- name: Inverted
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description: ETR is inverted, active at low level or falling edge
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value: 1
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enum/ETPS:
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bit_size: 2
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variants:
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- name: Div1
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description: Prescaler OFF
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value: 0
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- name: Div2
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description: ETRP frequency divided by 2
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value: 1
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- name: Div4
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description: ETRP frequency divided by 4
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value: 2
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- name: Div8
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description: ETRP frequency divided by 8
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value: 3
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enum/FIDX:
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bit_size: 1
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variants:
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- name: AlwaysActive
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description: Index is always active
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value: 0
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- name: FirstOnly
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description: the first Index only resets the counter
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value: 1
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enum/FilterValue:
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bit_size: 4
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variants:
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- name: NoFilter
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description: No filter, sampling is done at fDTS
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value: 0
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- name: FCK_INT_N2
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description: fSAMPLING=fCK_INT, N=2
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value: 1
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- name: FCK_INT_N4
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description: fSAMPLING=fCK_INT, N=4
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value: 2
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- name: FCK_INT_N8
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description: fSAMPLING=fCK_INT, N=8
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value: 3
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- name: FDTS_Div2_N6
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description: fSAMPLING=fDTS/2, N=6
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value: 4
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- name: FDTS_Div2_N8
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description: fSAMPLING=fDTS/2, N=8
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value: 5
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- name: FDTS_Div4_N6
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description: fSAMPLING=fDTS/4, N=6
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value: 6
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- name: FDTS_Div4_N8
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description: fSAMPLING=fDTS/4, N=8
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value: 7
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- name: FDTS_Div8_N6
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description: fSAMPLING=fDTS/8, N=6
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value: 8
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- name: FDTS_Div8_N8
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description: fSAMPLING=fDTS/8, N=8
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value: 9
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- name: FDTS_Div16_N5
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description: fSAMPLING=fDTS/16, N=5
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value: 10
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- name: FDTS_Div16_N6
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description: fSAMPLING=fDTS/16, N=6
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value: 11
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- name: FDTS_Div16_N8
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description: fSAMPLING=fDTS/16, N=8
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value: 12
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- name: FDTS_Div32_N5
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description: fSAMPLING=fDTS/32, N=5
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value: 13
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- name: FDTS_Div32_N6
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description: fSAMPLING=fDTS/32, N=6
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value: 14
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- name: FDTS_Div32_N8
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description: fSAMPLING=fDTS/32, N=8
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value: 15
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enum/GC5C:
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bit_size: 1
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variants:
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- name: NoEffect
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description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3)
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value: 0
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- name: LogicalAND
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description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF
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value: 1
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enum/IBLK:
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bit_size: 2
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variants:
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- name: AlwaysActive
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description: Index always active
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value: 0
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- name: CC3P
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description: Index disabled when tim_ti3 input is active, as per CC3P bitfield
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value: 1
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- name: CC4P
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description: Index disabled when tim_ti4 input is active, as per CC4P bitfield
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value: 2
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enum/IDIR:
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bit_size: 2
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variants:
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- name: Both
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description: Index resets the counter whatever the direction
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value: 0
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- name: Up
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description: Index resets the counter when up-counting only
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value: 1
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- name: Down
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description: Index resets the counter when down-counting only
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value: 2
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enum/LOCK:
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bit_size: 2
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variants:
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- name: Disabled
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description: No bit is write protected
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value: 0
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- name: Level1
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description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
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value: 1
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- name: Level2
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description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
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value: 2
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- name: Level3
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description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
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value: 3
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enum/MMS:
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bit_size: 3
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variants:
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- name: Reset
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description: The UG bit from the TIMx_EGR register is used as trigger output
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value: 0
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- name: Enable
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description: The counter enable signal, CNT_EN, is used as trigger output
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value: 1
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- name: Update
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description: The update event is selected as trigger output
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value: 2
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- name: ComparePulse
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description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
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value: 3
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- name: CompareOC1
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description: OC1REF signal is used as trigger output
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value: 4
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- name: CompareOC2
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description: OC2REF signal is used as trigger output
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value: 5
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- name: CompareOC3
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description: OC3REF signal is used as trigger output
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value: 6
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- name: CompareOC4
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description: OC4REF signal is used as trigger output
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value: 7
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enum/MMS2:
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bit_size: 4
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variants:
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- name: Reset
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description: The UG bit from the TIMx_EGR register is used as TRGO2
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value: 0
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- name: Enable
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description: The counter enable signal, CNT_EN, is used as TRGO2
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value: 1
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- name: Update
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description: The update event is selected as TRGO2
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value: 2
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- name: ComparePulse
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description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
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value: 3
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- name: CompareOC1
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description: OC1REF signal is used as TRGO2
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value: 4
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- name: CompareOC2
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description: OC2REF signal is used as TRGO2
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value: 5
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- name: CompareOC3
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description: OC3REF signal is used as TRGO2
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value: 6
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- name: CompareOC4
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description: OC4REF signal is used as TRGO2
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value: 7
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- name: CompareOC5
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description: OC5REF signal is used as TRGO2
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value: 8
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- name: CompareOC6
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description: OC6REF signal is used as TRGO2
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value: 9
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- name: ComparePulse_OC4
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description: OC4REF rising or falling edges generate pulses on TRGO2
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value: 10
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- name: ComparePulse_OC6
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description: OC6REF rising or falling edges generate pulses on TRGO2
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value: 11
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- name: ComparePulse_OC4_Or_OC6_Rising
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description: OC4REF or OC6REF rising edges generate pulses on TRGO2
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value: 12
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- name: ComparePulse_OC4_Rising_Or_OC6_Falling
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description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2
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value: 13
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- name: ComparePulse_OC5_Or_OC6_Rising
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description: OC5REF or OC6REF rising edges generate pulses on TRGO2
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value: 14
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- name: ComparePulse_OC5_Rising_Or_OC6_Falling
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description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2
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value: 15
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enum/MSM:
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bit_size: 1
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variants:
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- name: NoSync
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description: No action
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value: 0
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- name: Sync
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description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
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value: 1
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enum/OCCS:
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bit_size: 1
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variants:
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- name: Input
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description: tim_ocref_clr_int is connected to the tim_ocref_clr input
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value: 0
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- name: ETRF
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description: tim_ocref_clr_int is connected to tim_etrf
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value: 1
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enum/OCM:
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bit_size: 3
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variants:
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- name: Frozen
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description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
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value: 0
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- name: ActiveOnMatch
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description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
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value: 1
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- name: InactiveOnMatch
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description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
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value: 2
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- name: Toggle
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description: OCyREF toggles when TIMx_CNT=TIMx_CCRy
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value: 3
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- name: ForceInactive
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description: OCyREF is forced low
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value: 4
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- name: ForceActive
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description: OCyREF is forced high
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value: 5
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- name: PwmMode1
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description: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
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value: 6
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- name: PwmMode2
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description: Inversely to PwmMode1
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value: 7
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enum/OSSI:
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bit_size: 1
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variants:
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- name: Disabled
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description: When inactive, OC/OCN outputs are disabled
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value: 0
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- name: IdleLevel
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description: When inactive, OC/OCN outputs are forced to idle level
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value: 1
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enum/OSSR:
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bit_size: 1
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variants:
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- name: Disabled
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description: When inactive, OC/OCN outputs are disabled
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value: 0
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- name: IdleLevel
|
||||
description: When inactive, OC/OCN outputs are enabled with their inactive level
|
||||
value: 1
|
||||
enum/SMS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
|
||||
value: 0
|
||||
- name: Encoder_Mode_1
|
||||
description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
|
||||
value: 1
|
||||
- name: Encoder_Mode_2
|
||||
description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
|
||||
value: 2
|
||||
- name: Encoder_Mode_3
|
||||
description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
|
||||
value: 3
|
||||
- name: Reset_Mode
|
||||
description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
|
||||
value: 4
|
||||
- name: Gated_Mode
|
||||
description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
|
||||
value: 5
|
||||
- name: Trigger_Mode
|
||||
description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
|
||||
value: 6
|
||||
- name: Ext_Clock_Mode
|
||||
description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
|
||||
value: 7
|
||||
enum/SMSPS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Update
|
||||
description: The transfer is triggered by the Timer’s Update event
|
||||
value: 0
|
||||
- name: Index
|
||||
description: The transfer is triggered by the Index event
|
||||
value: 1
|
||||
enum/TI1S:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Normal
|
||||
description: The TIMx_CH1 pin is connected to TI1 input
|
||||
value: 0
|
||||
- name: XOR
|
||||
description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
|
||||
value: 1
|
||||
enum/TS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: ITR0
|
||||
description: Internal Trigger 0 (ITR0)
|
||||
value: 0
|
||||
- name: ITR1
|
||||
description: Internal Trigger 1 (ITR1)
|
||||
value: 1
|
||||
- name: ITR2
|
||||
description: Internal Trigger 2 (ITR2)
|
||||
value: 2
|
||||
- name: ITR3
|
||||
description: Internal Trigger 3 (ITR3)
|
||||
value: 3
|
||||
- name: TI1F_ED
|
||||
description: TI1 Edge Detector (TI1F_ED)
|
||||
value: 4
|
||||
- name: TI1FP1
|
||||
description: Filtered Timer Input 1 (TI1FP1)
|
||||
value: 5
|
||||
- name: TI2FP2
|
||||
description: Filtered Timer Input 2 (TI2FP2)
|
||||
value: 6
|
||||
- name: ETRF
|
||||
description: External Trigger input (ETRF)
|
||||
value: 7
|
||||
enum/URS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: AnyEvent
|
||||
description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
|
||||
value: 0
|
||||
- name: CounterOnly
|
||||
description: Only counter overflow/underflow generates an update interrupt or DMA request
|
||||
value: 1
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user