diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml index 7ebc58c..596fbd4 100644 --- a/data/registers/rcc_f0.yaml +++ b/data/registers/rcc_f0.yaml @@ -1048,7 +1048,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 2 - name: HSI48 @@ -1075,6 +1075,6 @@ enum/USBSW: - name: HSI48 description: NOT ALLOWED IN F0x0 - HSI48 selected as USB clock source value: 0 - - name: PLLCLK + - name: PLL1_P description: PLL clock selected as USB clock source value: 1 diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index bb96d81..d600c9f 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -822,7 +822,7 @@ enum/SW: - name: HSE description: HSE selected as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL selected as system clock value: 2 enum/USBPRE: diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml index f0ea9aa..72cfc99 100644 --- a/data/registers/rcc_f100.yaml +++ b/data/registers/rcc_f100.yaml @@ -844,6 +844,6 @@ enum/SW: - name: HSE description: HSE selected as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL selected as system clock value: 2 diff --git a/data/registers/rcc_f2.yaml b/data/registers/rcc_f2.yaml index 468c7c2..97fadee 100644 --- a/data/registers/rcc_f2.yaml +++ b/data/registers/rcc_f2.yaml @@ -1980,6 +1980,6 @@ enum/SW: - name: HSE description: HSE selected as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL selected as system clock value: 2 diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index 9535cdd..6a39586 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -1238,16 +1238,16 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 2 enum/TIMSW: bit_size: 1 variants: - - name: PCLK2 + - name: PCLK2_TIM description: PCLK2 clock (doubled frequency when prescaled) value: 0 - - name: PLL + - name: PLL1_P description: PLL vco output (running up to 144 MHz) value: 1 enum/USARTSW: diff --git a/data/registers/rcc_f3_v2.yaml b/data/registers/rcc_f3_v2.yaml index b70f0b2..f6d0105 100644 --- a/data/registers/rcc_f3_v2.yaml +++ b/data/registers/rcc_f3_v2.yaml @@ -1214,16 +1214,16 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 2 enum/TIMSW: bit_size: 1 variants: - - name: PCLK2 + - name: PCLK2_TIM description: PCLK2 clock (doubled frequency when prescaled) value: 0 - - name: PLL + - name: PLL1_P description: PLL vco output (running up to 144 MHz) value: 1 enum/USARTSW: diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 6d5dd66..1bef641 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -3467,7 +3467,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 2 enum/TIMPRE: diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml index 1803c7b..1ed702f 100644 --- a/data/registers/rcc_f410.yaml +++ b/data/registers/rcc_f410.yaml @@ -1926,7 +1926,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 2 enum/TIMPRE: diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index be1e481..faefb96 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -3144,7 +3144,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 1 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 2 enum/TIMPRE: diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index 25da0e6..cd7d5f8 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -1848,7 +1848,7 @@ enum/SW: enum/TIM15SEL: bit_size: 1 variants: - - name: TIMPCLK + - name: PCLK1_TIM description: TIMPCLK used as TIM15 clock source value: 0 - name: PLL1_Q @@ -1857,7 +1857,7 @@ enum/TIM15SEL: enum/TIM1SEL: bit_size: 1 variants: - - name: TIMPCLK + - name: PCLK1_TIM description: TIMPCLK used as TIM1 clock source value: 0 - name: PLL1_Q diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 22c6bcd..1baeb1f 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -3697,7 +3697,7 @@ enum/LPTIM2SEL: enum/LPUARTSEL: bit_size: 3 variants: - - name: RCC_PCLK_D3 + - name: PCLK3 description: rcc_pclk_d3 selected as peripheral clock value: 0 - name: PLL2_Q diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index cc55415..23b482d 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -2632,7 +2632,7 @@ enum/LPTIM2SEL: enum/LPUARTSEL: bit_size: 3 variants: - - name: RCC_PCLK_D3 + - name: PCLK3 description: rcc_pclk_d3 selected as peripheral clock value: 0 - name: PLL2_Q diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index 09f11ad..0116ae9 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -3697,7 +3697,7 @@ enum/LPTIM2SEL: enum/LPUARTSEL: bit_size: 3 variants: - - name: RCC_PCLK_D3 + - name: PCLK3 description: rcc_pclk_d3 selected as peripheral clock value: 0 - name: PLL2_Q diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index e183b5a..cd369fe 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -1201,7 +1201,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 2 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 3 enum/UARTSEL: diff --git a/data/registers/rcc_l0_v2.yaml b/data/registers/rcc_l0_v2.yaml index 646d231..14a5d1a 100644 --- a/data/registers/rcc_l0_v2.yaml +++ b/data/registers/rcc_l0_v2.yaml @@ -1240,7 +1240,7 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 2 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 3 enum/UARTSEL: diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml index 42e6402..7f168b0 100644 --- a/data/registers/rcc_l1.yaml +++ b/data/registers/rcc_l1.yaml @@ -1045,6 +1045,6 @@ enum/SW: - name: HSE description: HSE oscillator used as system clock value: 2 - - name: PLL + - name: PLL1_P description: PLL used as system clock value: 3 diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index c9e7437..3a674af 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -2267,7 +2267,7 @@ enum/SW: - name: HSE description: HSE selected as system clock value: 2 - - name: PLL + - name: PLL1_P description: PLL selected as system clock value: 3 enum/SWPMI1SEL: diff --git a/data/registers/rcc_l4plus.yaml b/data/registers/rcc_l4plus.yaml index 7e13da1..10105cc 100644 --- a/data/registers/rcc_l4plus.yaml +++ b/data/registers/rcc_l4plus.yaml @@ -1668,7 +1668,7 @@ enum/ADCSEL: - name: DISABLE description: No clock selected value: 0 - - name: PLLADC1CLK + - name: PLLSAI1_R description: PLLADC1CLK clock selected value: 1 - name: SYS @@ -1716,7 +1716,7 @@ enum/DSISEL: - name: DSIPHY description: DSI-PHY is selected as DSI byte lane clock source (usual case) value: 0 - - name: PLLDSICLK + - name: PLLSAI2_Q description: PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSIPHY are off (low-power mode) value: 1 enum/HPRE: @@ -1971,7 +1971,7 @@ enum/OSPISEL: - name: MSI description: MSI clock selected as OctoSPI kernel clock value: 1 - - name: PLL48M1CLK + - name: PLL1_Q description: PLL48M1CLK clock selected as OctoSPI kernel clock value: 2 enum/PLLM: @@ -2434,7 +2434,7 @@ enum/SDMMCSEL: - name: HSI48 description: 48 MHz clock is selected as SDMMC kernel clock value: 0 - - name: PLLSAI3CLK + - name: PLL1_P description: PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode) value: 1 enum/STOPWUCK: @@ -2458,7 +2458,7 @@ enum/SW: - name: HSE description: HSE selected as system clock value: 2 - - name: PLL + - name: PLL1_R description: PLL selected as system clock value: 3 enum/UART4SEL: diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 921fece..e4bcc3b 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -1933,7 +1933,7 @@ enum/CLK48SEL: - name: PLLSAI1_Q description: PLLSAI1_Q aka PLL48M1CLK clock selected value: 1 - - name: PLL_Q + - name: PLL1_Q description: PLL_Q aka PLL48M2CLK clock selected value: 2 - name: MSI @@ -2468,7 +2468,7 @@ enum/PLLSRC: - name: MSI description: MSI selected as PLL input clock value: 1 - - name: HSI16 + - name: HSI description: HSI selected as PLL input clock value: 2 - name: HSE @@ -2513,7 +2513,7 @@ enum/STOPWUCK: - name: MSI description: MSI oscillator selected as wake-up from Stop clock and CSS backup clock value: 0 - - name: HSI16 + - name: HSI description: HSI oscillator selected as wake-up from stop clock and CSS backup clock value: 1 enum/SW: @@ -2522,12 +2522,12 @@ enum/SW: - name: MSI description: MSI selected as system clock value: 0 - - name: HSI16 + - name: HSI description: HSI selected as system clock value: 1 - name: HSE description: HSE selected as system clock value: 2 - - name: PLL + - name: PLL1_R description: PLL selected as system clock value: 3 diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index b0ab22a..6fb0c79 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -17,7 +17,7 @@ impl PeripheralToClock { let mut peripheral_to_clock = HashMap::new(); let checked_rccs = HashSet::from([ "c0", "f0", "f1", "f100", "f1c1", "f2", "f3", "f3_v2", "f4", "f410", "f7", "g0", "g4", "h5", "h50", "h7", - "h7ab", "h7rm0433", "l0", "l0_v2", "l1", "l4", + "h7ab", "h7rm0433", "l0", "l0_v2", "l1", "l4", "l4plus", "l5", ]); let allowed_variants = HashSet::from([ "DISABLE", @@ -73,22 +73,17 @@ impl PeripheralToClock { "SAI2_EXTCLK", "B_0x0", "B_0x1", - "PLL", - "PLLCLK", - "RCC_PCLK_D3", "I2S_CKIN", "DAC_HOLD", "DAC_HOLD_2", - "TIMPCLK", "RTCCLK", "RTC_WKUP", "DSIPHY", - "PLLDSICLK", ]); for (rcc_name, ir) in ®isters.registers { if let Some(rcc_name) = rcc_name.strip_prefix("rcc_") { - let rcc_enum_map: HashMap<&String, HashMap<&String, &Enum>> = { + let rcc_enum_map: HashMap<&String, HashMap<&String, (&String, &Enum)>> = { let rcc_blocks = &ir.blocks.get("RCC").unwrap().items; rcc_blocks @@ -101,10 +96,10 @@ impl PeripheralToClock { f.fields .iter() .filter_map(|f| { - let enumm = f.enumm.as_ref()?; - let enumm = ir.enums.get(enumm)?; + let enumm_name = f.enumm.as_ref()?; + let enumm = ir.enums.get(enumm_name)?; - Some((&f.name, enumm)) + Some((&f.name, (enumm_name, enumm))) }) .collect(), ) @@ -124,7 +119,7 @@ impl PeripheralToClock { _ => return Ok(()), }; - let enumm = match block_map.get(field) { + let (enumm_name, enumm) = match block_map.get(field) { Some(enumm) => enumm, _ => return Ok(()), }; @@ -135,15 +130,17 @@ impl PeripheralToClock { if !allowed_variants.contains(name.as_str()) { return Err(anyhow!( - "rcc: prohibited variant name {} for rcc_{}", + "rcc: prohibited variant name {} in enum {} for rcc_{}", v.name.as_str(), + enumm_name, rcc_name )); } } else if !allowed_variants.contains(v.name.as_str()) { return Err(anyhow!( - "rcc: prohibited variant name {} for rcc_{}", + "rcc: prohibited variant name {} in enum {} for rcc_{}", v.name.as_str(), + enumm_name, rcc_name )); }