From 6f45c8c9b2ccc1a891e3aa40a31d56b545a9c61f Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 19:34:56 +0800 Subject: [PATCH] tailoring from saes_v1a to saes_v1b --- data/registers/saes_v1b.yaml | 28 ++++------------------------ 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/data/registers/saes_v1b.yaml b/data/registers/saes_v1b.yaml index 44b4d83..26881aa 100644 --- a/data/registers/saes_v1b.yaml +++ b/data/registers/saes_v1b.yaml @@ -86,11 +86,6 @@ fieldset/CR: description: 'DMA output enable This bit enables/disables data transferring with DMA, in the output phase: When the bit is set, DMA requests are automatically generated by SAES during the output data phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is not effective for Mode 2 (key derivation).' bit_offset: 12 bit_size: 1 - - name: GCMPH - description: 'GCM or CCM phase selection This bitfield selects the phase of GCM, GMAC or CCM algorithm: The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the ALGOMODE bitfield).' - bit_offset: 13 - bit_size: 2 - enum: GCMPH - name: KEYSIZE description: 'Key size selection This bitfield defines the length of the key used in the SAES cryptographic core, in bits: When KMOD[1:0]=01 or 10 KEYSIZE also defines the length of the key to encrypt or decrypt. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 18 @@ -100,10 +95,6 @@ fieldset/CR: description: Key protection When set, hardware-based key protection is enabled. Attempts to write the bit are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access. bit_offset: 19 bit_size: 1 - - name: NPBLB - description: 'Number of padding bytes in last block The bitfield sets the number of padding bytes in last block of payload: ...' - bit_offset: 20 - bit_size: 4 - name: KMOD description: 'Key mode selection The bitfield defines how the SAES key can be used by the application: Others: Reserved With normal key selection, the key registers are freely usable, no specific usage or protection applies to SAES_DIN and SAES_DOUT registers. With wrapped key selection, the key loaded in key registers can only be used to encrypt or decrypt AES keys. Hence, when a decryption is selected in Wrapped-key mode read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With shared key selection, after a successful decryption process, SAES key registers are shared with the peripheral described in KSHAREID(1:0] bitfield. This sharing is valid only while KMOD[1:0]=10 and KEYVALID = 1. When a decryption is selected, read-as-zero SAES_DOUT register is automatically loaded into SAES key registers after a successful decryption process. With KMOD[1:0] other than zero, any attempt to configure the SAES peripheral for use by an application belonging to a different security domain (secure or non-secure) results in automatic key erasure and setting of the KEIF flag.\nAttempts to write the bitfield are ignored when the BUSY flag of SAES_SR register is set, as well as when the EN bit of the SAES_CR register is set before the write access and it is not cleared by that write access.' bit_offset: 24 @@ -183,6 +174,10 @@ fieldset/ISR: fieldset/SR: description: SAES status register. fields: + - name: CCF + description: Computation completed flag. This bit mirrors the CCF bit of the SAES_ISR register. + bit_offset: 1 + bit_size: 1 - name: RDERR description: 'Read error flag This flag indicates the detection of an unexpected read operation from the SAES_DOUTR register (during computation or data input phase): The flag is set by hardware. It is cleared by software upon setting the RWEIF bit of the SAES_ICR register. Upon the flag setting, an interrupt is generated if enabled through the RWEIE bit of the SAES_ICR register. The flag setting has no impact on the SAES operation. Unexpected read returns zero.' bit_offset: 1 @@ -232,21 +227,6 @@ enum/DATATYPE: - name: Bit description: Bit-level swapping value: 3 -enum/GCMPH: - bit_size: 2 - variants: - - name: InitPhase - description: Initialization phase - value: 0 - - name: HeaderPhase - description: Header phase - value: 1 - - name: PayloadPhase - description: Payload phase - value: 2 - - name: FinalPhase - description: Final phase - value: 3 enum/KEYSEL: bit_size: 3 variants: