From ad291b5af3aa5cdcf48a10d47efc7ebbfde68373 Mon Sep 17 00:00:00 2001 From: Joonas Javanainen Date: Tue, 26 Apr 2022 20:19:15 +0300 Subject: [PATCH] Map spi2s1_v2_1 used on F2 devices This seems identical to v2_2 (as used by F429) with one naming exception in status register SR bit 8 (TI frame format error): v2_1 data names the bit "TIFRFE" and the enum TIFRERR v2_2 data names the bit "FRE" and the enum FRER The register bit layout is identical. --- stm32data/__main__.py | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 1834e51..b25c0bb 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -105,6 +105,7 @@ perimap = [ ('.*:RNG:rng1_v2_1', ('rng', 'v1', 'RNG')), ('.*:RNG:rng1_v3_1', ('rng', 'v1', 'RNG')), ('.*:SPI:spi2_v1_4', ('spi', 'f1', 'SPI')), + ('.*:SPI:spi2s1_v2_1', ('spi', 'v1', 'SPI')), ('.*:SPI:spi2s1_v2_2', ('spi', 'v1', 'SPI')), ('.*:SPI:spi2s1_v3_2', ('spi', 'v2', 'SPI')), ('.*:SPI:spi2s1_v3_3', ('spi', 'v2', 'SPI')),