u5 RCC additions for U5[9A].
This commit is contained in:
Dario Nieuwenhuis
parent
a924ee2093
commit
6de9d585b0
@ -237,6 +237,10 @@ fieldset/AHB1ENR:
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description: "CRC clock enable\r Set and cleared by software."
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bit_offset: 12
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bit_size: 1
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- name: JPEGEN
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description: "JPEG clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 15
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bit_size: 1
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- name: TSCEN
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description: "Touch sensing controller clock enable\r Set and cleared by software."
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bit_offset: 16
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@ -249,6 +253,18 @@ fieldset/AHB1ENR:
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description: "DMA2D clock enable\r Set and cleared by software."
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bit_offset: 18
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bit_size: 1
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- name: GFXMMUEN
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description: "GFXMMU clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 19
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bit_size: 1
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- name: GPU2DEN
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description: "GPU2D clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 20
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bit_size: 1
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- name: DCACHE2EN
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description: "DCACHE2 clock enable \r This bit is set and reset by software.\r Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 21
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bit_size: 1
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- name: GTZC1EN
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description: "GTZC1 clock enable\r Set and reset by software."
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bit_offset: 24
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@ -288,6 +304,10 @@ fieldset/AHB1RSTR:
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description: "CRC reset\r Set and cleared by software."
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bit_offset: 12
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bit_size: 1
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- name: JPEGRST
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description: "JPEG reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 15
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bit_size: 1
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- name: TSCRST
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description: "TSC reset\r Set and cleared by software."
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bit_offset: 16
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@ -300,6 +320,14 @@ fieldset/AHB1RSTR:
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description: "DMA2D reset\r Set and cleared by software."
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bit_offset: 18
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bit_size: 1
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- name: GFXMMURST
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description: "GFXMMU reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 19
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bit_size: 1
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- name: GPU2DRST
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description: "GPU2D reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 20
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bit_size: 1
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fieldset/AHB1SMENR:
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description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
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fields:
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@ -327,6 +355,10 @@ fieldset/AHB1SMENR:
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description: "CRC clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 12
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bit_size: 1
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- name: JPEGSMEN
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description: "JPEG clocks enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 15
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bit_size: 1
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- name: TSCSMEN
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description: "TSC clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 16
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@ -339,6 +371,18 @@ fieldset/AHB1SMENR:
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description: "DMA2D clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 18
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bit_size: 1
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- name: GFXMMUSMEN
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description: "GFXMMU clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 19
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bit_size: 1
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- name: GPU2DSMEN
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description: "GPU2D clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 20
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bit_size: 1
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- name: DCACHE2SMEN
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description: "DCACHE2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 21
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bit_size: 1
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- name: GTZC1SMEN
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description: "GTZC1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 24
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@ -398,8 +442,12 @@ fieldset/AHB2ENR1:
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description: "IO port I clock enable\r Set and cleared by software."
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bit_offset: 8
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bit_size: 1
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- name: ADC1EN
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description: "ADC1 clock enable\r Set and cleared by software."
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- name: GPIOJEN
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description: "I/O port J clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 9
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bit_size: 1
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- name: ADC12EN
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description: "ADC1 and ADC2 clock enable\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in<69>STM32U59x/5Ax/5Fx/5Gx."
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bit_offset: 10
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bit_size: 1
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- name: DCMIEN
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@ -410,6 +458,14 @@ fieldset/AHB2ENR1:
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description: "OTG_FS clock enable\r Set and cleared by software."
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bit_offset: 14
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bit_size: 1
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- name: USB_OTG_HSEN
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description: "OTG_HS clock enable\r Set and cleared by software."
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bit_offset: 14
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bit_size: 1
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- name: USB_OTG_HS_PHYEN
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description: "OTG_HS PHY clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 15
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bit_size: 1
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- name: AESEN
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description: "AES clock enable\r Set and cleared by software."
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bit_offset: 16
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@ -473,6 +529,18 @@ fieldset/AHB2ENR2:
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description: "OCTOSPI2 clock enable\r Set and cleared by software."
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bit_offset: 8
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bit_size: 1
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- name: HSPI1EN
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description: "HSPI1 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 12
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bit_size: 1
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- name: SRAM6EN
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description: "SRAM6 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 30
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bit_size: 1
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- name: SRAM5EN
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description: "SRAM5 clock enable \r This bit is set and reset by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 31
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bit_size: 1
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fieldset/AHB2RSTR1:
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description: RCC AHB2 peripheral reset register 1
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fields:
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@ -512,8 +580,12 @@ fieldset/AHB2RSTR1:
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description: "IO port I reset\r Set and cleared by software."
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bit_offset: 8
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bit_size: 1
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- name: ADC1RST
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description: "ADC1 reset\r Set and cleared by software."
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- name: GPIOJRST
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description: "I/O port J reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 9
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bit_size: 1
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- name: ADC12RST
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description: "ADC1 and ADC2 reset\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in<69>STM32U59x/5Ax/5Fx/5Gx."
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bit_offset: 10
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bit_size: 1
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- name: DCMIRST
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@ -524,6 +596,10 @@ fieldset/AHB2RSTR1:
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description: "OTG_FS reset\r Set and cleared by software."
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bit_offset: 14
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bit_size: 1
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- name: USB_OTG_HSRST
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description: "OTG_HS reset\r Set and cleared by software."
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bit_offset: 14
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bit_size: 1
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- name: AESRST
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description: "AES hardware accelerator reset\r Set and cleared by software."
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bit_offset: 16
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@ -579,6 +655,10 @@ fieldset/AHB2RSTR2:
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description: "OCTOSPI2 reset\r Set and cleared by software."
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bit_offset: 8
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bit_size: 1
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- name: HSPI1RST
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description: "HSPI1 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 12
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bit_size: 1
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fieldset/AHB2SMENR1:
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description: "RCC AHB2 peripheral clocks enable in Sleep and\tStop modes register 1"
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fields:
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@ -618,8 +698,12 @@ fieldset/AHB2SMENR1:
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description: "IO port I clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 8
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bit_size: 1
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- name: ADC1SMEN
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description: "ADC1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
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- name: GPIOJSMEN
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description: "I/O port J clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 9
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bit_size: 1
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- name: ADC12SMEN
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description: "ADC1 and ADC2 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in<69>STM32U59x/5Ax/5Fx/5Gx."
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bit_offset: 10
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bit_size: 1
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- name: DCMISMEN
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@ -630,6 +714,14 @@ fieldset/AHB2SMENR1:
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description: "OTG_FS clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 14
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bit_size: 1
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- name: USB_OTG_HSSMEN
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description: "OTG_HS clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 14
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bit_size: 1
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- name: USB_OTG_HS_PHYSMEN
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description: "OTG_HS PHY clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 15
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bit_size: 1
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- name: AESSMEN
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description: "AES clock enable during Sleep and Stop modes\r Set and cleared by software"
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bit_offset: 16
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@ -693,6 +785,18 @@ fieldset/AHB2SMENR2:
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description: "OCTOSPI2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 8
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bit_size: 1
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- name: HSPI1SMEN
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description: "HSPI1 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 12
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bit_size: 1
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- name: SRAM6SMEN
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description: "SRAM6 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 30
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bit_size: 1
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- name: SRAM5SMEN
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description: "SRAM5 clock enable during Sleep and Stop modes \r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 31
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bit_size: 1
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fieldset/AHB3ENR:
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description: RCC AHB3 peripheral clock enable register
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fields:
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@ -849,6 +953,10 @@ fieldset/APB1ENR1:
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description: "CRS clock enable\r Set and cleared by software."
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bit_offset: 24
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bit_size: 1
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- name: USART6EN
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description: "USART6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 25
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bit_size: 1
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fieldset/APB1ENR2:
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description: RCC APB1 peripheral clock enable register 2
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fields:
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@ -860,6 +968,14 @@ fieldset/APB1ENR2:
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description: "LPTIM2 clock enable\r Set and cleared by software."
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bit_offset: 5
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bit_size: 1
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- name: I2C5EN
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description: "I2C5 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 6
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bit_size: 1
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- name: I2C6EN
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description: "I2C6 clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 7
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bit_size: 1
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- name: FDCAN1EN
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description: "FDCAN1 clock enable\r Set and cleared by software."
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bit_offset: 9
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@ -927,6 +1043,10 @@ fieldset/APB1RSTR1:
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description: "CRS reset\r Set and cleared by software."
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bit_offset: 24
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bit_size: 1
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- name: USART6RST
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description: "USART6 reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 25
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bit_size: 1
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fieldset/APB1RSTR2:
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description: RCC APB1 peripheral reset register 2
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fields:
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@ -938,6 +1058,14 @@ fieldset/APB1RSTR2:
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description: "LPTIM2 reset\r Set and cleared by software."
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bit_offset: 5
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bit_size: 1
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- name: I2C5RST
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description: "I2C5 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 6
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bit_size: 1
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- name: I2C6RST
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description: "I2C6 reset\r This bit is set and cleared by software\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 7
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bit_size: 1
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- name: FDCAN1RST
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description: "FDCAN1 reset\r Set and cleared by software."
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bit_offset: 9
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@ -1009,6 +1137,10 @@ fieldset/APB1SMENR1:
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description: "CRS clock enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 24
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bit_size: 1
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- name: USART6SMEN
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description: "USART6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 25
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bit_size: 1
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fieldset/APB1SMENR2:
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description: "RCC APB1 peripheral clocks enable in Sleep and\tStop modes register 2"
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fields:
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@ -1020,6 +1152,14 @@ fieldset/APB1SMENR2:
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description: "LPTIM2 clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
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bit_offset: 5
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bit_size: 1
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- name: I2C5SMEN
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description: "I2C5 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 6
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bit_size: 1
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- name: I2C6SMEN
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description: "I2C6 clock enable during Sleep and Stop modes\r This bit is set and cleared by software\r Note: This bit must be set to allow the peripheral to wake up from Stop modes.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 7
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bit_size: 1
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- name: FDCAN1SMEN
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description: "FDCAN1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
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bit_offset: 9
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@ -1067,6 +1207,22 @@ fieldset/APB2ENR:
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description: "SAI2 clock enable\r Set and cleared by software."
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bit_offset: 22
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bit_size: 1
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- name: USBEN
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description: "USB clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 24
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bit_size: 1
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- name: GFXTIMEN
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description: "GFXTIM clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 25
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bit_size: 1
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- name: LTDCEN
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description: "LTDC clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 26
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bit_size: 1
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- name: DSIEN
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description: "DSI clock enable\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
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bit_offset: 27
|
||||
bit_size: 1
|
||||
fieldset/APB2RSTR:
|
||||
description: RCC APB2 peripheral reset register
|
||||
fields:
|
||||
@ -1106,6 +1262,22 @@ fieldset/APB2RSTR:
|
||||
description: "SAI2 reset\r Set and cleared by software."
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: USBRST
|
||||
description: "USB reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: GFXTIMRST
|
||||
description: "GFXTIM reset\r This bit is set and cleared by software.\r Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LTDCRST
|
||||
description: "LTDC reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: DSIRST
|
||||
description: "DSI reset\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
fieldset/APB2SMENR:
|
||||
description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
|
||||
fields:
|
||||
@ -1145,6 +1317,22 @@ fieldset/APB2SMENR:
|
||||
description: "SAI2 clocks enable during Sleep and Stop modes\r Set and cleared by software."
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: USBSMEN
|
||||
description: "USB clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: GFXTIMSMEN
|
||||
description: "GFXTIM clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LTDCSMEN
|
||||
description: "LTDC clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: DSISMEN
|
||||
description: "DSI clock enable during Sleep and Stop modes\r This bit is set and cleared by software.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
fieldset/APB3ENR:
|
||||
description: RCC APB3 peripheral clock enable register
|
||||
fields:
|
||||
@ -1468,11 +1656,46 @@ fieldset/CCIPR2:
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
enum: SDMMCSEL
|
||||
- name: DSISEL
|
||||
description: "DSI kernel clock source selection\r This bit is used to select the DSI kernel clock source.\r This bit is only available on some devices in the STM32U5 Series. \r Refer to the device datasheet for availability of its associated peripheral. \r Note: If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: DSISEL
|
||||
- name: USART6SEL
|
||||
description: "USART6 kernel clock source selection\r These bits are used to select the USART6 kernel clock source.\r The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
enum: USARTSEL
|
||||
- name: LTDCSEL
|
||||
description: "LTDC kernel clock source selection\r This bit is used to select the LTDC kernel clock source.\r Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value."
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: LTDCSEL
|
||||
- name: OCTOSPISEL
|
||||
description: "OCTOSPI1 and OCTOSPI2 kernel clock source selection\r These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source."
|
||||
bit_offset: 20
|
||||
bit_size: 2
|
||||
enum: OCTOSPISEL
|
||||
- name: HSPI1SEL
|
||||
description: "HSPI1 kernel clock source selection\r These bits are used to select the HSPI1 kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
|
||||
bit_offset: 22
|
||||
bit_size: 2
|
||||
enum: HSPISEL
|
||||
- name: I2C5SEL
|
||||
description: "I2C5 kernel clock source selection\r These bits are used to select the I2C5 kernel clock source.\r The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16<31>or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
|
||||
bit_offset: 24
|
||||
bit_size: 2
|
||||
enum: ICSEL
|
||||
- name: I2C6SEL
|
||||
description: "I2C6 kernel clock source selection\r These bits are used to select the I2C6 kernel clock source.\r The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16<31>or MSIK.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
|
||||
bit_offset: 26
|
||||
bit_size: 2
|
||||
enum: ICSEL
|
||||
- name: OTGHSSEL
|
||||
description: "OTG_HS PHY kernel clock source selection\r These bits are used to select the OTG_HS PHY kernel clock source.\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
|
||||
bit_offset: 30
|
||||
bit_size: 2
|
||||
enum: OTGHSSEL
|
||||
fieldset/CCIPR3:
|
||||
description: RCC peripherals independent clock configuration register 3
|
||||
fields:
|
||||
@ -1567,6 +1790,11 @@ fieldset/CFGR2:
|
||||
bit_offset: 8
|
||||
bit_size: 3
|
||||
enum: PPRE
|
||||
- name: DPRE
|
||||
description: "DSI PHY prescaler\r This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK).\r 0xx: DCLK not divided\r Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value."
|
||||
bit_offset: 12
|
||||
bit_size: 3
|
||||
enum: DPRE
|
||||
- name: AHB1DIS
|
||||
description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1."
|
||||
bit_offset: 16
|
||||
@ -2335,6 +2563,33 @@ enum/DACSEL:
|
||||
- name: LSI
|
||||
description: LSI selected
|
||||
value: 1
|
||||
enum/DPRE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NONE
|
||||
description: DCLK not divided
|
||||
value: 0
|
||||
- name: DIV2
|
||||
description: DCLK divided by 2
|
||||
value: 4
|
||||
- name: DIV4
|
||||
description: DCLK divided by 4
|
||||
value: 5
|
||||
- name: DIV8
|
||||
description: DCLK divided by 8
|
||||
value: 6
|
||||
- name: DIV16
|
||||
description: DCLK divided by 16
|
||||
value: 7
|
||||
enum/DSISEL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: PLL3_P
|
||||
description: PLL3 “P” (pll3_p_ck) selected
|
||||
value: 0
|
||||
- name: DCLK
|
||||
description: DSI PHY PLL output selected
|
||||
value: 1
|
||||
enum/FDCANSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -2386,6 +2641,21 @@ enum/HSEEXT:
|
||||
- name: DIGITAL
|
||||
description: external HSE clock digital mode (through I/O Schmitt trigger)
|
||||
value: 1
|
||||
enum/HSPISEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: SYSCLK
|
||||
description: SYSCLK selected
|
||||
value: 0
|
||||
- name: PLL1_Q
|
||||
description: "PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz"
|
||||
value: 1
|
||||
- name: PLL2_Q
|
||||
description: "PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz"
|
||||
value: 2
|
||||
- name: PLL3_R
|
||||
description: "PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz"
|
||||
value: 3
|
||||
enum/ICLKSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -2482,6 +2752,15 @@ enum/LSIPREDIV:
|
||||
- name: DIV_128
|
||||
description: LSI divided by 128
|
||||
value: 1
|
||||
enum/LTDCSEL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: PLL3_R
|
||||
description: PLL3 “R” (pll3_r_ck) selected
|
||||
value: 0
|
||||
- name: PLL2_R
|
||||
description: PLL2 “R” (pll2_r_ck) selected
|
||||
value: 1
|
||||
enum/MCOPRE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
@ -2671,6 +2950,21 @@ enum/OCTOSPISEL:
|
||||
- name: PLL2_Q
|
||||
description: "PLL2 Q (pll2_q_ck) selected, can be up to 200 MHz"
|
||||
value: 3
|
||||
enum/OTGHSSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: HSE
|
||||
description: HSE selected
|
||||
value: 0
|
||||
- name: PLL1_P
|
||||
description: "PLL1 “P” (pll1_q_ck) selected,"
|
||||
value: 1
|
||||
- name: HSE_DIV2
|
||||
description: HSE/2 selected
|
||||
value: 2
|
||||
- name: PLL1_P_DIV2
|
||||
description: PLL1 “P” divided by 2 (pll1_p_ck/2) selected
|
||||
value: 3
|
||||
enum/PLLM:
|
||||
bit_size: 4
|
||||
variants:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user