diff --git a/data/registers/rcc_wb55.yaml b/data/registers/rcc_wb55.yaml
new file mode 100644
index 0000000..08dc99b
--- /dev/null
+++ b/data/registers/rcc_wb55.yaml
@@ -0,0 +1,1638 @@
+---
+block/RCC:
+  description: Reset and clock control
+  items:
+    - name: CR
+      description: Clock control register
+      byte_offset: 0
+      fieldset: CR
+    - name: ICSCR
+      description: Internal clock sources calibration register
+      byte_offset: 4
+      fieldset: ICSCR
+    - name: CFGR
+      description: Clock configuration register
+      byte_offset: 8
+      fieldset: CFGR
+    - name: PLLCFGR
+      description: PLLSYS configuration register
+      byte_offset: 12
+      fieldset: PLLCFGR
+    - name: PLLSAI1CFGR
+      description: PLLSAI1 configuration register
+      byte_offset: 16
+      fieldset: PLLSAI1CFGR
+    - name: CIER
+      description: Clock interrupt enable register
+      byte_offset: 24
+      fieldset: CIER
+    - name: CIFR
+      description: Clock interrupt flag register
+      byte_offset: 28
+      access: Read
+      fieldset: CIFR
+    - name: CICR
+      description: Clock interrupt clear register
+      byte_offset: 32
+      access: Write
+      fieldset: CICR
+    - name: SMPSCR
+      description: Step Down converter control register
+      byte_offset: 36
+      fieldset: SMPSCR
+    - name: AHB1RSTR
+      description: AHB1 peripheral reset register
+      byte_offset: 40
+      fieldset: AHB1RSTR
+    - name: AHB2RSTR
+      description: AHB2 peripheral reset register
+      byte_offset: 44
+      fieldset: AHB2RSTR
+    - name: AHB3RSTR
+      description: AHB3 peripheral reset register
+      byte_offset: 48
+      fieldset: AHB3RSTR
+    - name: APB1RSTR1
+      description: APB1 peripheral reset register 1
+      byte_offset: 56
+      fieldset: APB1RSTR1
+    - name: APB1RSTR2
+      description: APB1 peripheral reset register 2
+      byte_offset: 60
+      fieldset: APB1RSTR2
+    - name: APB2RSTR
+      description: APB2 peripheral reset register
+      byte_offset: 64
+      fieldset: APB2RSTR
+    - name: APB3RSTR
+      description: APB3 peripheral reset register
+      byte_offset: 68
+      fieldset: APB3RSTR
+    - name: AHB1ENR
+      description: AHB1 peripheral clock enable register
+      byte_offset: 72
+      fieldset: AHB1ENR
+    - name: AHB2ENR
+      description: AHB2 peripheral clock enable register
+      byte_offset: 76
+      fieldset: AHB2ENR
+    - name: AHB3ENR
+      description: AHB3 peripheral clock enable register
+      byte_offset: 80
+      fieldset: AHB3ENR
+    - name: APB1ENR1
+      description: APB1ENR1
+      byte_offset: 88
+      fieldset: APB1ENR1
+    - name: APB1ENR2
+      description: APB1 peripheral clock enable register 2
+      byte_offset: 92
+      fieldset: APB1ENR2
+    - name: APB2ENR
+      description: APB2ENR
+      byte_offset: 96
+      fieldset: APB2ENR
+    - name: AHB1SMENR
+      description: AHB1 peripheral clocks enable in Sleep and Stop modes register
+      byte_offset: 104
+      fieldset: AHB1SMENR
+    - name: AHB2SMENR
+      description: AHB2 peripheral clocks enable in Sleep and Stop modes register
+      byte_offset: 108
+      fieldset: AHB2SMENR
+    - name: AHB3SMENR
+      description: AHB3 peripheral clocks enable in Sleep and Stop modes register
+      byte_offset: 112
+      fieldset: AHB3SMENR
+    - name: APB1SMENR1
+      description: APB1SMENR1
+      byte_offset: 120
+      fieldset: APB1SMENR1
+    - name: APB1SMENR2
+      description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
+      byte_offset: 124
+      fieldset: APB1SMENR2
+    - name: APB2SMENR
+      description: APB2SMENR
+      byte_offset: 128
+      fieldset: APB2SMENR
+    - name: CCIPR
+      description: CCIPR
+      byte_offset: 136
+      fieldset: CCIPR
+    - name: BDCR
+      description: BDCR
+      byte_offset: 144
+      fieldset: BDCR
+    - name: CSR
+      description: CSR
+      byte_offset: 148
+      fieldset: CSR
+    - name: CRRCR
+      description: Clock recovery RC register
+      byte_offset: 152
+      fieldset: CRRCR
+    - name: HSECR
+      description: Clock HSE register
+      byte_offset: 156
+      fieldset: HSECR
+    - name: EXTCFGR
+      description: Extended clock recovery register
+      byte_offset: 264
+      fieldset: EXTCFGR
+    - name: C2AHB1ENR
+      description: CPU2 AHB1 peripheral clock enable register
+      byte_offset: 328
+      fieldset: C2AHB1ENR
+    - name: C2AHB2ENR
+      description: CPU2 AHB2 peripheral clock enable register
+      byte_offset: 332
+      fieldset: C2AHB2ENR
+    - name: C2AHB3ENR
+      description: CPU2 AHB3 peripheral clock enable register
+      byte_offset: 336
+      fieldset: C2AHB3ENR
+    - name: C2APB1ENR1
+      description: CPU2 APB1ENR1
+      byte_offset: 344
+      fieldset: C2APB1ENR1
+    - name: C2APB1ENR2
+      description: CPU2 APB1 peripheral clock enable register 2
+      byte_offset: 348
+      fieldset: C2APB1ENR2
+    - name: C2APB2ENR
+      description: CPU2 APB2ENR
+      byte_offset: 352
+      fieldset: C2APB2ENR
+    - name: C2APB3ENR
+      description: CPU2 APB3ENR
+      byte_offset: 356
+      fieldset: C2APB3ENR
+    - name: C2AHB1SMENR
+      description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
+      byte_offset: 360
+      fieldset: C2AHB1SMENR
+    - name: C2AHB2SMENR
+      description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
+      byte_offset: 364
+      fieldset: C2AHB2SMENR
+    - name: C2AHB3SMENR
+      description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
+      byte_offset: 368
+      fieldset: C2AHB3SMENR
+    - name: C2APB1SMENR1
+      description: CPU2 APB1SMENR1
+      byte_offset: 376
+      fieldset: C2APB1SMENR1
+    - name: C2APB1SMENR2
+      description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
+      byte_offset: 380
+      fieldset: C2APB1SMENR2
+    - name: C2APB2SMENR
+      description: CPU2 APB2SMENR
+      byte_offset: 384
+      fieldset: C2APB2SMENR
+    - name: C2APB3SMENR
+      description: CPU2 APB3SMENR
+      byte_offset: 388
+      fieldset: C2APB3SMENR
+fieldset/AHB1ENR:
+  description: AHB1 peripheral clock enable register
+  fields:
+    - name: DMA1EN
+      description: DMA1 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA2EN
+      description: DMA2 clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: DMAMUXEN
+      description: DMAMUX clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: CRCEN
+      description: CPU1 CRC clock enable
+      bit_offset: 12
+      bit_size: 1
+    - name: TSCEN
+      description: Touch Sensing Controller clock enable
+      bit_offset: 16
+      bit_size: 1
+fieldset/AHB1RSTR:
+  description: AHB1 peripheral reset register
+  fields:
+    - name: DMA1RST
+      description: DMA1 reset
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA2RST
+      description: DMA2 reset
+      bit_offset: 1
+      bit_size: 1
+    - name: DMAMUXRST
+      description: DMAMUX reset
+      bit_offset: 2
+      bit_size: 1
+    - name: CRCRST
+      description: CRC reset
+      bit_offset: 12
+      bit_size: 1
+    - name: TSCRST
+      description: Touch Sensing Controller reset
+      bit_offset: 16
+      bit_size: 1
+fieldset/AHB1SMENR:
+  description: AHB1 peripheral clocks enable in Sleep and Stop modes register
+  fields:
+    - name: DMA1SMEN
+      description: CPU1 DMA1 clocks enable during Sleep and Stop modes
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA2SMEN
+      description: CPU1 DMA2 clocks enable during Sleep and Stop modes
+      bit_offset: 1
+      bit_size: 1
+    - name: DMAMUXSMEN
+      description: CPU1 DMAMUX clocks enable during Sleep and Stop modes
+      bit_offset: 2
+      bit_size: 1
+    - name: SRAM1SMEN
+      description: CPU1 SRAM1 interface clocks enable during Sleep and Stop modes
+      bit_offset: 9
+      bit_size: 1
+    - name: CRCSMEN
+      description: CPU1 CRCSMEN
+      bit_offset: 12
+      bit_size: 1
+    - name: TSCSMEN
+      description: CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes
+      bit_offset: 16
+      bit_size: 1
+fieldset/AHB2ENR:
+  description: AHB2 peripheral clock enable register
+  fields:
+    - name: GPIOAEN
+      description: IO port A clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: GPIOBEN
+      description: IO port B clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: GPIOCEN
+      description: IO port C clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: GPIODEN
+      description: IO port D clock enable
+      bit_offset: 3
+      bit_size: 1
+    - name: GPIOEEN
+      description: IO port E clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: GPIOHEN
+      description: IO port H clock enable
+      bit_offset: 7
+      bit_size: 1
+    - name: ADCEN
+      description: ADC clock enable
+      bit_offset: 13
+      bit_size: 1
+    - name: AES1EN
+      description: AES1 accelerator clock enable
+      bit_offset: 16
+      bit_size: 1
+fieldset/AHB2RSTR:
+  description: AHB2 peripheral reset register
+  fields:
+    - name: GPIOARST
+      description: IO port A reset
+      bit_offset: 0
+      bit_size: 1
+    - name: GPIOBRST
+      description: IO port B reset
+      bit_offset: 1
+      bit_size: 1
+    - name: GPIOCRST
+      description: IO port C reset
+      bit_offset: 2
+      bit_size: 1
+    - name: GPIODRST
+      description: IO port D reset
+      bit_offset: 3
+      bit_size: 1
+    - name: GPIOERST
+      description: IO port E reset
+      bit_offset: 4
+      bit_size: 1
+    - name: GPIOHRST
+      description: IO port H reset
+      bit_offset: 7
+      bit_size: 1
+    - name: ADCRST
+      description: ADC reset
+      bit_offset: 13
+      bit_size: 1
+    - name: AES1RST
+      description: AES1 hardware accelerator reset
+      bit_offset: 16
+      bit_size: 1
+fieldset/AHB2SMENR:
+  description: AHB2 peripheral clocks enable in Sleep and Stop modes register
+  fields:
+    - name: GPIOASMEN
+      description: CPU1 IO port A clocks enable during Sleep and Stop modes
+      bit_offset: 0
+      bit_size: 1
+    - name: GPIOBSMEN
+      description: CPU1 IO port B clocks enable during Sleep and Stop modes
+      bit_offset: 1
+      bit_size: 1
+    - name: GPIOCSMEN
+      description: CPU1 IO port C clocks enable during Sleep and Stop modes
+      bit_offset: 2
+      bit_size: 1
+    - name: GPIODSMEN
+      description: CPU1 IO port D clocks enable during Sleep and Stop modes
+      bit_offset: 3
+      bit_size: 1
+    - name: GPIOESMEN
+      description: CPU1 IO port E clocks enable during Sleep and Stop modes
+      bit_offset: 4
+      bit_size: 1
+    - name: GPIOHSMEN
+      description: CPU1 IO port H clocks enable during Sleep and Stop modes
+      bit_offset: 7
+      bit_size: 1
+    - name: ADCFSSMEN
+      description: CPU1 ADC clocks enable during Sleep and Stop modes
+      bit_offset: 13
+      bit_size: 1
+    - name: AES1SMEN
+      description: CPU1 AES1 accelerator clocks enable during Sleep and Stop modes
+      bit_offset: 16
+      bit_size: 1
+fieldset/AHB3ENR:
+  description: AHB3 peripheral clock enable register
+  fields:
+    - name: QSPIEN
+      description: QSPIEN
+      bit_offset: 8
+      bit_size: 1
+    - name: PKAEN
+      description: PKAEN
+      bit_offset: 16
+      bit_size: 1
+    - name: AES2EN
+      description: AES2EN
+      bit_offset: 17
+      bit_size: 1
+    - name: RNGEN
+      description: RNGEN
+      bit_offset: 18
+      bit_size: 1
+    - name: HSEMEN
+      description: HSEMEN
+      bit_offset: 19
+      bit_size: 1
+    - name: IPCCEN
+      description: IPCCEN
+      bit_offset: 20
+      bit_size: 1
+    - name: FLASHEN
+      description: FLASHEN
+      bit_offset: 25
+      bit_size: 1
+fieldset/AHB3RSTR:
+  description: AHB3 peripheral reset register
+  fields:
+    - name: QSPIRST
+      description: Quad SPI memory interface reset
+      bit_offset: 8
+      bit_size: 1
+    - name: PKARST
+      description: PKA interface reset
+      bit_offset: 16
+      bit_size: 1
+    - name: AES2RST
+      description: AES2 interface reset
+      bit_offset: 17
+      bit_size: 1
+    - name: RNGRST
+      description: RNG interface reset
+      bit_offset: 18
+      bit_size: 1
+    - name: HSEMRST
+      description: HSEM interface reset
+      bit_offset: 19
+      bit_size: 1
+    - name: IPCCRST
+      description: IPCC interface reset
+      bit_offset: 20
+      bit_size: 1
+    - name: FLASHRST
+      description: Flash interface reset
+      bit_offset: 25
+      bit_size: 1
+fieldset/AHB3SMENR:
+  description: AHB3 peripheral clocks enable in Sleep and Stop modes register
+  fields:
+    - name: QSPISMEN
+      description: QSPISMEN
+      bit_offset: 8
+      bit_size: 1
+    - name: PKASMEN
+      description: PKA accelerator clocks enable during CPU1 sleep mode
+      bit_offset: 16
+      bit_size: 1
+    - name: AES2SMEN
+      description: AES2 accelerator clocks enable during CPU1 sleep mode
+      bit_offset: 17
+      bit_size: 1
+    - name: RNGSMEN
+      description: True RNG clocks enable during CPU1 sleep mode
+      bit_offset: 18
+      bit_size: 1
+    - name: SRAM2SMEN
+      description: SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode
+      bit_offset: 24
+      bit_size: 1
+    - name: FLASHSMEN
+      description: Flash interface clocks enable during CPU1 sleep mode
+      bit_offset: 25
+      bit_size: 1
+fieldset/APB1ENR1:
+  description: APB1ENR1
+  fields:
+    - name: TIM2EN
+      description: CPU1 TIM2 timer clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LCDEN
+      description: CPU1 LCD clock enable
+      bit_offset: 9
+      bit_size: 1
+    - name: RTCAPBEN
+      description: CPU1 RTC APB clock enable
+      bit_offset: 10
+      bit_size: 1
+    - name: WWDGEN
+      description: CPU1 Window watchdog clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI2EN
+      description: CPU1 SPI2 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: I2C1EN
+      description: CPU1 I2C1 clock enable
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C3EN
+      description: CPU1 I2C3 clock enable
+      bit_offset: 23
+      bit_size: 1
+    - name: CRSEN
+      description: CPU1 CRS clock enable
+      bit_offset: 24
+      bit_size: 1
+    - name: USBEN
+      description: CPU1 USB clock enable
+      bit_offset: 26
+      bit_size: 1
+    - name: LPTIM1EN
+      description: CPU1 Low power timer 1 clock enable
+      bit_offset: 31
+      bit_size: 1
+fieldset/APB1ENR2:
+  description: APB1 peripheral clock enable register 2
+  fields:
+    - name: LPUART1EN
+      description: CPU1 Low power UART 1 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LPTIM2EN
+      description: CPU1 LPTIM2EN
+      bit_offset: 5
+      bit_size: 1
+fieldset/APB1RSTR1:
+  description: APB1 peripheral reset register 1
+  fields:
+    - name: TIM2RST
+      description: TIM2 timer reset
+      bit_offset: 0
+      bit_size: 1
+    - name: LCDRST
+      description: LCD interface reset
+      bit_offset: 9
+      bit_size: 1
+    - name: SPI2RST
+      description: SPI2 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: I2C1RST
+      description: I2C1 reset
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C3RST
+      description: I2C3 reset
+      bit_offset: 23
+      bit_size: 1
+    - name: CRSRST
+      description: CRS reset
+      bit_offset: 24
+      bit_size: 1
+    - name: USBFSRST
+      description: USB FS reset
+      bit_offset: 26
+      bit_size: 1
+    - name: LPTIM1RST
+      description: Low Power Timer 1 reset
+      bit_offset: 31
+      bit_size: 1
+fieldset/APB1RSTR2:
+  description: APB1 peripheral reset register 2
+  fields:
+    - name: LPUART1RST
+      description: Low-power UART 1 reset
+      bit_offset: 0
+      bit_size: 1
+    - name: LPTIM2RST
+      description: Low-power timer 2 reset
+      bit_offset: 5
+      bit_size: 1
+fieldset/APB1SMENR1:
+  description: APB1SMENR1
+  fields:
+    - name: TIM2SMEN
+      description: TIM2 timer clocks enable during CPU1 Sleep mode
+      bit_offset: 0
+      bit_size: 1
+    - name: LCDSMEN
+      description: LCD clocks enable during CPU1 Sleep mode
+      bit_offset: 9
+      bit_size: 1
+    - name: RTCAPBSMEN
+      description: RTC APB clocks enable during CPU1 Sleep mode
+      bit_offset: 10
+      bit_size: 1
+    - name: WWDGSMEN
+      description: Window watchdog clocks enable during CPU1 Sleep mode
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI2SMEN
+      description: SPI2 clocks enable during CPU1 Sleep mode
+      bit_offset: 14
+      bit_size: 1
+    - name: I2C1SMEN
+      description: I2C1 clocks enable during CPU1 Sleep mode
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C3SMEN
+      description: I2C3 clocks enable during CPU1 Sleep mode
+      bit_offset: 23
+      bit_size: 1
+    - name: CRSMEN
+      description: CRS clocks enable during CPU1 Sleep mode
+      bit_offset: 24
+      bit_size: 1
+    - name: USBSMEN
+      description: USB FS clocks enable during CPU1 Sleep mode
+      bit_offset: 26
+      bit_size: 1
+    - name: LPTIM1SMEN
+      description: Low power timer 1 clocks enable during CPU1 Sleep mode
+      bit_offset: 31
+      bit_size: 1
+fieldset/APB1SMENR2:
+  description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
+  fields:
+    - name: LPUART1SMEN
+      description: Low power UART 1 clocks enable during CPU1 Sleep mode
+      bit_offset: 0
+      bit_size: 1
+    - name: LPTIM2SMEN
+      description: Low power timer 2 clocks enable during CPU1 Sleep mode
+      bit_offset: 5
+      bit_size: 1
+fieldset/APB2ENR:
+  description: APB2ENR
+  fields:
+    - name: TIM1EN
+      description: CPU1 TIM1 timer clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1EN
+      description: CPU1 SPI1 clock enable
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1EN
+      description: CPU1 USART1clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM16EN
+      description: CPU1 TIM16 timer clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17EN
+      description: CPU1 TIM17 timer clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: SAI1EN
+      description: CPU1 SAI1 clock enable
+      bit_offset: 21
+      bit_size: 1
+fieldset/APB2RSTR:
+  description: APB2 peripheral reset register
+  fields:
+    - name: TIM1RST
+      description: TIM1 timer reset
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1RST
+      description: SPI1 reset
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1RST
+      description: USART1 reset
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM16RST
+      description: TIM16 timer reset
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17RST
+      description: TIM17 timer reset
+      bit_offset: 18
+      bit_size: 1
+    - name: SAI1RST
+      description: Serial audio interface 1 (SAI1) reset
+      bit_offset: 21
+      bit_size: 1
+fieldset/APB2SMENR:
+  description: APB2SMENR
+  fields:
+    - name: TIM1SMEN
+      description: TIM1 timer clocks enable during CPU1 Sleep mode
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1SMEN
+      description: SPI1 clocks enable during CPU1 Sleep mode
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1SMEN
+      description: USART1clocks enable during CPU1 Sleep mode
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM16SMEN
+      description: TIM16 timer clocks enable during CPU1 Sleep mode
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17SMEN
+      description: TIM17 timer clocks enable during CPU1 Sleep mode
+      bit_offset: 18
+      bit_size: 1
+    - name: SAI1SMEN
+      description: SAI1 clocks enable during CPU1 Sleep mode
+      bit_offset: 21
+      bit_size: 1
+fieldset/APB3RSTR:
+  description: APB3 peripheral reset register
+  fields:
+    - name: RFRST
+      description: Radio system BLE reset
+      bit_offset: 0
+      bit_size: 1
+fieldset/BDCR:
+  description: BDCR
+  fields:
+    - name: LSEON
+      description: LSE oscillator enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LSERDY
+      description: LSE oscillator ready
+      bit_offset: 1
+      bit_size: 1
+    - name: LSEBYP
+      description: LSE oscillator bypass
+      bit_offset: 2
+      bit_size: 1
+    - name: LSEDRV
+      description: SE oscillator drive capability
+      bit_offset: 3
+      bit_size: 2
+    - name: LSECSSON
+      description: LSECSSON
+      bit_offset: 5
+      bit_size: 1
+    - name: LSECSSD_
+      description: CSS on LSE failure detection
+      bit_offset: 6
+      bit_size: 1
+    - name: RTCSEL
+      description: RTC clock source selection
+      bit_offset: 8
+      bit_size: 2
+    - name: RTCEN
+      description: RTC clock enable
+      bit_offset: 15
+      bit_size: 1
+    - name: BDRST
+      description: Backup domain software reset
+      bit_offset: 16
+      bit_size: 1
+    - name: LSCOEN
+      description: Low speed clock output enable
+      bit_offset: 24
+      bit_size: 1
+    - name: LSCOSEL
+      description: Low speed clock output selection
+      bit_offset: 25
+      bit_size: 2
+fieldset/C2AHB1ENR:
+  description: CPU2 AHB1 peripheral clock enable register
+  fields:
+    - name: DMA1EN
+      description: CPU2 DMA1 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA2EN
+      description: CPU2 DMA2 clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: DMAMUXEN
+      description: CPU2 DMAMUX clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: SRAM1EN
+      description: CPU2 SRAM1 clock enable
+      bit_offset: 9
+      bit_size: 1
+    - name: CRCEN
+      description: CPU2 CRC clock enable
+      bit_offset: 12
+      bit_size: 1
+    - name: TSCEN
+      description: CPU2 Touch Sensing Controller clock enable
+      bit_offset: 16
+      bit_size: 1
+fieldset/C2AHB1SMENR:
+  description: CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register
+  fields:
+    - name: DMA1SMEN
+      description: CPU2 DMA1 clocks enable during Sleep and Stop modes
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA2SMEN
+      description: CPU2 DMA2 clocks enable during Sleep and Stop modes
+      bit_offset: 1
+      bit_size: 1
+    - name: DMAMUXSMEN
+      description: CPU2 DMAMUX clocks enable during Sleep and Stop modes
+      bit_offset: 2
+      bit_size: 1
+    - name: SRAM1SMEN
+      description: SRAM1 interface clock enable during CPU1 CSleep mode
+      bit_offset: 9
+      bit_size: 1
+    - name: CRCSMEN
+      description: CPU2 CRCSMEN
+      bit_offset: 12
+      bit_size: 1
+    - name: TSCSMEN
+      description: CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes
+      bit_offset: 16
+      bit_size: 1
+fieldset/C2AHB2ENR:
+  description: CPU2 AHB2 peripheral clock enable register
+  fields:
+    - name: GPIOAEN
+      description: CPU2 IO port A clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: GPIOBEN
+      description: CPU2 IO port B clock enable
+      bit_offset: 1
+      bit_size: 1
+    - name: GPIOCEN
+      description: CPU2 IO port C clock enable
+      bit_offset: 2
+      bit_size: 1
+    - name: GPIODEN
+      description: CPU2 IO port D clock enable
+      bit_offset: 3
+      bit_size: 1
+    - name: GPIOEEN
+      description: CPU2 IO port E clock enable
+      bit_offset: 4
+      bit_size: 1
+    - name: GPIOHEN
+      description: CPU2 IO port H clock enable
+      bit_offset: 7
+      bit_size: 1
+    - name: ADCEN
+      description: CPU2 ADC clock enable
+      bit_offset: 13
+      bit_size: 1
+    - name: AES1EN
+      description: CPU2 AES1 accelerator clock enable
+      bit_offset: 16
+      bit_size: 1
+fieldset/C2AHB2SMENR:
+  description: CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register
+  fields:
+    - name: GPIOASMEN
+      description: CPU2 IO port A clocks enable during Sleep and Stop modes
+      bit_offset: 0
+      bit_size: 1
+    - name: GPIOBSMEN
+      description: CPU2 IO port B clocks enable during Sleep and Stop modes
+      bit_offset: 1
+      bit_size: 1
+    - name: GPIOCSMEN
+      description: CPU2 IO port C clocks enable during Sleep and Stop modes
+      bit_offset: 2
+      bit_size: 1
+    - name: GPIODSMEN
+      description: CPU2 IO port D clocks enable during Sleep and Stop modes
+      bit_offset: 3
+      bit_size: 1
+    - name: GPIOESMEN
+      description: CPU2 IO port E clocks enable during Sleep and Stop modes
+      bit_offset: 4
+      bit_size: 1
+    - name: GPIOHSMEN
+      description: CPU2 IO port H clocks enable during Sleep and Stop modes
+      bit_offset: 7
+      bit_size: 1
+    - name: ADCFSSMEN
+      description: CPU2 ADC clocks enable during Sleep and Stop modes
+      bit_offset: 13
+      bit_size: 1
+    - name: AES1SMEN
+      description: CPU2 AES1 accelerator clocks enable during Sleep and Stop modes
+      bit_offset: 16
+      bit_size: 1
+fieldset/C2AHB3ENR:
+  description: CPU2 AHB3 peripheral clock enable register
+  fields:
+    - name: PKAEN
+      description: CPU2 PKAEN
+      bit_offset: 16
+      bit_size: 1
+    - name: AES2EN
+      description: CPU2 AES2EN
+      bit_offset: 17
+      bit_size: 1
+    - name: RNGEN
+      description: CPU2 RNGEN
+      bit_offset: 18
+      bit_size: 1
+    - name: HSEMEN
+      description: CPU2 HSEMEN
+      bit_offset: 19
+      bit_size: 1
+    - name: IPCCEN
+      description: CPU2 IPCCEN
+      bit_offset: 20
+      bit_size: 1
+    - name: FLASHEN
+      description: CPU2 FLASHEN
+      bit_offset: 25
+      bit_size: 1
+fieldset/C2AHB3SMENR:
+  description: CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register
+  fields:
+    - name: PKASMEN
+      description: PKA accelerator clocks enable during CPU2 sleep modes
+      bit_offset: 16
+      bit_size: 1
+    - name: AES2SMEN
+      description: AES2 accelerator clocks enable during CPU2 sleep modes
+      bit_offset: 17
+      bit_size: 1
+    - name: RNGSMEN
+      description: True RNG clocks enable during CPU2 sleep modes
+      bit_offset: 18
+      bit_size: 1
+    - name: SRAM2SMEN
+      description: SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes
+      bit_offset: 24
+      bit_size: 1
+    - name: FLASHSMEN
+      description: Flash interface clocks enable during CPU2 sleep modes
+      bit_offset: 25
+      bit_size: 1
+fieldset/C2APB1ENR1:
+  description: CPU2 APB1ENR1
+  fields:
+    - name: TIM2EN
+      description: CPU2 TIM2 timer clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LCDEN
+      description: CPU2 LCD clock enable
+      bit_offset: 9
+      bit_size: 1
+    - name: RTCAPBEN
+      description: CPU2 RTC APB clock enable
+      bit_offset: 10
+      bit_size: 1
+    - name: SPI2EN
+      description: CPU2 SPI2 clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: I2C1EN
+      description: CPU2 I2C1 clock enable
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C3EN
+      description: CPU2 I2C3 clock enable
+      bit_offset: 23
+      bit_size: 1
+    - name: CRSEN
+      description: CPU2 CRS clock enable
+      bit_offset: 24
+      bit_size: 1
+    - name: USBEN
+      description: CPU2 USB clock enable
+      bit_offset: 26
+      bit_size: 1
+    - name: LPTIM1EN
+      description: CPU2 Low power timer 1 clock enable
+      bit_offset: 31
+      bit_size: 1
+fieldset/C2APB1ENR2:
+  description: CPU2 APB1 peripheral clock enable register 2
+  fields:
+    - name: LPUART1EN
+      description: CPU2 Low power UART 1 clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LPTIM2EN
+      description: CPU2 LPTIM2EN
+      bit_offset: 5
+      bit_size: 1
+fieldset/C2APB1SMENR1:
+  description: CPU2 APB1SMENR1
+  fields:
+    - name: TIM2SMEN
+      description: TIM2 timer clocks enable during CPU2 Sleep mode
+      bit_offset: 0
+      bit_size: 1
+    - name: LCDSMEN
+      description: LCD clocks enable during CPU2 Sleep mode
+      bit_offset: 9
+      bit_size: 1
+    - name: RTCAPBSMEN
+      description: RTC APB clocks enable during CPU2 Sleep mode
+      bit_offset: 10
+      bit_size: 1
+    - name: SPI2SMEN
+      description: SPI2 clocks enable during CPU2 Sleep mode
+      bit_offset: 14
+      bit_size: 1
+    - name: I2C1SMEN
+      description: I2C1 clocks enable during CPU2 Sleep mode
+      bit_offset: 21
+      bit_size: 1
+    - name: I2C3SMEN
+      description: I2C3 clocks enable during CPU2 Sleep mode
+      bit_offset: 23
+      bit_size: 1
+    - name: CRSMEN
+      description: CRS clocks enable during CPU2 Sleep mode
+      bit_offset: 24
+      bit_size: 1
+    - name: USBSMEN
+      description: USB FS clocks enable during CPU2 Sleep mode
+      bit_offset: 26
+      bit_size: 1
+    - name: LPTIM1SMEN
+      description: Low power timer 1 clocks enable during CPU2 Sleep mode
+      bit_offset: 31
+      bit_size: 1
+fieldset/C2APB1SMENR2:
+  description: CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2
+  fields:
+    - name: LPUART1SMEN
+      description: Low power UART 1 clocks enable during CPU2 Sleep mode
+      bit_offset: 0
+      bit_size: 1
+    - name: LPTIM2SMEN
+      description: Low power timer 2 clocks enable during CPU2 Sleep mode
+      bit_offset: 5
+      bit_size: 1
+fieldset/C2APB2ENR:
+  description: CPU2 APB2ENR
+  fields:
+    - name: TIM1EN
+      description: CPU2 TIM1 timer clock enable
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1EN
+      description: CPU2 SPI1 clock enable
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1EN
+      description: CPU2 USART1clock enable
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM16EN
+      description: CPU2 TIM16 timer clock enable
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17EN
+      description: CPU2 TIM17 timer clock enable
+      bit_offset: 18
+      bit_size: 1
+    - name: SAI1EN
+      description: CPU2 SAI1 clock enable
+      bit_offset: 21
+      bit_size: 1
+fieldset/C2APB2SMENR:
+  description: CPU2 APB2SMENR
+  fields:
+    - name: TIM1SMEN
+      description: TIM1 timer clocks enable during CPU2 Sleep mode
+      bit_offset: 11
+      bit_size: 1
+    - name: SPI1SMEN
+      description: SPI1 clocks enable during CPU2 Sleep mode
+      bit_offset: 12
+      bit_size: 1
+    - name: USART1SMEN
+      description: USART1clocks enable during CPU2 Sleep mode
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM16SMEN
+      description: TIM16 timer clocks enable during CPU2 Sleep mode
+      bit_offset: 17
+      bit_size: 1
+    - name: TIM17SMEN
+      description: TIM17 timer clocks enable during CPU2 Sleep mode
+      bit_offset: 18
+      bit_size: 1
+    - name: SAI1SMEN
+      description: SAI1 clocks enable during CPU2 Sleep mode
+      bit_offset: 21
+      bit_size: 1
+fieldset/C2APB3ENR:
+  description: CPU2 APB3ENR
+  fields:
+    - name: BLEEN
+      description: CPU2 BLE interface clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: EN802
+      description: CPU2 802.15.4 interface clock enable
+      bit_offset: 1
+      bit_size: 1
+fieldset/C2APB3SMENR:
+  description: CPU2 APB3SMENR
+  fields:
+    - name: BLESMEN
+      description: BLE interface clocks enable during CPU2 Sleep mode
+      bit_offset: 0
+      bit_size: 1
+    - name: SMEN802
+      description: 802.15.4 interface clocks enable during CPU2 Sleep modes
+      bit_offset: 1
+      bit_size: 1
+fieldset/CCIPR:
+  description: CCIPR
+  fields:
+    - name: USART1SEL
+      description: USART1 clock source selection
+      bit_offset: 0
+      bit_size: 2
+    - name: LPUART1SEL
+      description: LPUART1 clock source selection
+      bit_offset: 10
+      bit_size: 2
+    - name: I2C1SEL
+      description: I2C1 clock source selection
+      bit_offset: 12
+      bit_size: 2
+    - name: I2C3SEL
+      description: I2C3 clock source selection
+      bit_offset: 16
+      bit_size: 2
+    - name: LPTIM1SEL
+      description: Low power timer 1 clock source selection
+      bit_offset: 18
+      bit_size: 2
+    - name: LPTIM2SEL
+      description: Low power timer 2 clock source selection
+      bit_offset: 20
+      bit_size: 2
+    - name: SAI1SEL
+      description: SAI1 clock source selection
+      bit_offset: 22
+      bit_size: 2
+    - name: CLK48SEL
+      description: 48 MHz clock source selection
+      bit_offset: 26
+      bit_size: 2
+    - name: ADCSEL
+      description: ADCs clock source selection
+      bit_offset: 28
+      bit_size: 2
+    - name: RNGSEL
+      description: RNG clock source selection
+      bit_offset: 30
+      bit_size: 2
+fieldset/CFGR:
+  description: Clock configuration register
+  fields:
+    - name: SW
+      description: System clock switch
+      bit_offset: 0
+      bit_size: 2
+    - name: SWS
+      description: System clock switch status
+      bit_offset: 2
+      bit_size: 2
+    - name: HPRE
+      description: AHB prescaler
+      bit_offset: 4
+      bit_size: 4
+    - name: PPRE1
+      description: PB low-speed prescaler (APB1)
+      bit_offset: 8
+      bit_size: 3
+    - name: PPRE2
+      description: APB high-speed prescaler (APB2)
+      bit_offset: 11
+      bit_size: 3
+    - name: STOPWUCK
+      description: Wakeup from Stop and CSS backup clock selection
+      bit_offset: 15
+      bit_size: 1
+    - name: HPREF
+      description: AHB prescaler flag
+      bit_offset: 16
+      bit_size: 1
+    - name: PPRE1F
+      description: APB1 prescaler flag
+      bit_offset: 17
+      bit_size: 1
+    - name: PPRE2F
+      description: APB2 prescaler flag
+      bit_offset: 18
+      bit_size: 1
+    - name: MCOSEL
+      description: Microcontroller clock output
+      bit_offset: 24
+      bit_size: 4
+    - name: MCOPRE
+      description: Microcontroller clock output prescaler
+      bit_offset: 28
+      bit_size: 3
+fieldset/CICR:
+  description: Clock interrupt clear register
+  fields:
+    - name: LSI1RDYC
+      description: LSI1 ready interrupt clear
+      bit_offset: 0
+      bit_size: 1
+    - name: LSERDYC
+      description: LSE ready interrupt clear
+      bit_offset: 1
+      bit_size: 1
+    - name: MSIRDYC
+      description: MSI ready interrupt clear
+      bit_offset: 2
+      bit_size: 1
+    - name: HSIRDYC
+      description: HSI ready interrupt clear
+      bit_offset: 3
+      bit_size: 1
+    - name: HSERDYC
+      description: HSE ready interrupt clear
+      bit_offset: 4
+      bit_size: 1
+    - name: PLLRDYC
+      description: PLL ready interrupt clear
+      bit_offset: 5
+      bit_size: 1
+    - name: PLLSAI1RDYC
+      description: PLLSAI1 ready interrupt clear
+      bit_offset: 6
+      bit_size: 1
+    - name: HSECSSC
+      description: HSE Clock security system interrupt clear
+      bit_offset: 8
+      bit_size: 1
+    - name: LSECSSC
+      description: LSE Clock security system interrupt clear
+      bit_offset: 9
+      bit_size: 1
+    - name: HSI48RDYC
+      description: HSI48 ready interrupt clear
+      bit_offset: 10
+      bit_size: 1
+    - name: LSI2RDYC
+      description: LSI2 ready interrupt clear
+      bit_offset: 11
+      bit_size: 1
+fieldset/CIER:
+  description: Clock interrupt enable register
+  fields:
+    - name: LSI1RDYIE
+      description: LSI1 ready interrupt enable
+      bit_offset: 0
+      bit_size: 1
+    - name: LSERDYIE
+      description: LSE ready interrupt enable
+      bit_offset: 1
+      bit_size: 1
+    - name: MSIRDYIE
+      description: MSI ready interrupt enable
+      bit_offset: 2
+      bit_size: 1
+    - name: HSIRDYIE
+      description: HSI ready interrupt enable
+      bit_offset: 3
+      bit_size: 1
+    - name: HSERDYIE
+      description: HSE ready interrupt enable
+      bit_offset: 4
+      bit_size: 1
+    - name: PLLRDYIE
+      description: PLLSYS ready interrupt enable
+      bit_offset: 5
+      bit_size: 1
+    - name: PLLSAI1RDYIE
+      description: PLLSAI1 ready interrupt enable
+      bit_offset: 6
+      bit_size: 1
+    - name: LSECSSIE
+      description: LSE clock security system interrupt enable
+      bit_offset: 9
+      bit_size: 1
+    - name: HSI48RDYIE
+      description: HSI48 ready interrupt enable
+      bit_offset: 10
+      bit_size: 1
+    - name: LSI2RDYIE
+      description: LSI2 ready interrupt enable
+      bit_offset: 11
+      bit_size: 1
+fieldset/CIFR:
+  description: Clock interrupt flag register
+  fields:
+    - name: LSI1RDYF
+      description: LSI1 ready interrupt flag
+      bit_offset: 0
+      bit_size: 1
+    - name: LSERDYF
+      description: LSE ready interrupt flag
+      bit_offset: 1
+      bit_size: 1
+    - name: MSIRDYF
+      description: MSI ready interrupt flag
+      bit_offset: 2
+      bit_size: 1
+    - name: HSIRDYF
+      description: HSI ready interrupt flag
+      bit_offset: 3
+      bit_size: 1
+    - name: HSERDYF
+      description: HSE ready interrupt flag
+      bit_offset: 4
+      bit_size: 1
+    - name: PLLRDYF
+      description: PLL ready interrupt flag
+      bit_offset: 5
+      bit_size: 1
+    - name: PLLSAI1RDYF
+      description: PLLSAI1 ready interrupt flag
+      bit_offset: 6
+      bit_size: 1
+    - name: HSECSSF
+      description: HSE Clock security system interrupt flag
+      bit_offset: 8
+      bit_size: 1
+    - name: LSECSSF
+      description: LSE Clock security system interrupt flag
+      bit_offset: 9
+      bit_size: 1
+    - name: HSI48RDYF
+      description: HSI48 ready interrupt flag
+      bit_offset: 10
+      bit_size: 1
+    - name: LSI2RDYF
+      description: LSI2 ready interrupt flag
+      bit_offset: 11
+      bit_size: 1
+fieldset/CR:
+  description: Clock control register
+  fields:
+    - name: MSION
+      description: MSI clock enable
+      bit_offset: 0
+      bit_size: 1
+    - name: MSIRDY
+      description: MSI clock ready flag
+      bit_offset: 1
+      bit_size: 1
+    - name: MSIPLLEN
+      description: MSI clock PLL enable
+      bit_offset: 2
+      bit_size: 1
+    - name: MSIRANGE
+      description: MSI clock ranges
+      bit_offset: 4
+      bit_size: 4
+    - name: HSION
+      description: HSI clock enabled
+      bit_offset: 8
+      bit_size: 1
+    - name: HSIKERON
+      description: HSI always enable for peripheral kernels
+      bit_offset: 9
+      bit_size: 1
+    - name: HSIRDY
+      description: HSI clock ready flag
+      bit_offset: 10
+      bit_size: 1
+    - name: HSIASFS
+      description: HSI automatic start from Stop
+      bit_offset: 11
+      bit_size: 1
+    - name: HSIKERDY
+      description: HSI kernel clock ready flag for peripherals requests
+      bit_offset: 12
+      bit_size: 1
+    - name: HSEON
+      description: HSE clock enabled
+      bit_offset: 16
+      bit_size: 1
+    - name: HSERDY
+      description: HSE clock ready flag
+      bit_offset: 17
+      bit_size: 1
+    - name: HSEBYP
+      description: HSE crystal oscillator bypass
+      bit_offset: 18
+      bit_size: 1
+    - name: CSSON
+      description: HSE Clock security system enable
+      bit_offset: 19
+      bit_size: 1
+    - name: HSEPRE
+      description: HSE sysclk and PLL M divider prescaler
+      bit_offset: 20
+      bit_size: 1
+    - name: PLLON
+      description: Main PLL enable
+      bit_offset: 24
+      bit_size: 1
+    - name: PLLRDY
+      description: Main PLL clock ready flag
+      bit_offset: 25
+      bit_size: 1
+    - name: PLLSAI1ON
+      description: SAI1 PLL enable
+      bit_offset: 26
+      bit_size: 1
+    - name: PLLSAI1RDY
+      description: SAI1 PLL clock ready flag
+      bit_offset: 27
+      bit_size: 1
+fieldset/CRRCR:
+  description: Clock recovery RC register
+  fields:
+    - name: HSI48ON
+      description: HSI48 oscillator enabled
+      bit_offset: 0
+      bit_size: 1
+    - name: HSI48RDY
+      description: HSI48 clock ready
+      bit_offset: 1
+      bit_size: 1
+    - name: HSI48CAL
+      description: HSI48 clock calibration
+      bit_offset: 7
+      bit_size: 9
+fieldset/CSR:
+  description: CSR
+  fields:
+    - name: LSI1ON
+      description: LSI1 oscillator enabled
+      bit_offset: 0
+      bit_size: 1
+    - name: LSI1RDY
+      description: LSI1 oscillator ready
+      bit_offset: 1
+      bit_size: 1
+    - name: LSI2ON
+      description: LSI2 oscillator enabled
+      bit_offset: 2
+      bit_size: 1
+    - name: LSI2RDY
+      description: LSI2 oscillator ready
+      bit_offset: 3
+      bit_size: 1
+    - name: LSI2TRIMEN
+      description: LSI2 oscillator trimming enable
+      bit_offset: 4
+      bit_size: 1
+    - name: LSI2TRIMOK
+      description: LSI2 oscillator trim OK
+      bit_offset: 5
+      bit_size: 1
+    - name: LSI2BW
+      description: LSI2 oscillator bias configuration
+      bit_offset: 8
+      bit_size: 4
+    - name: RFWKPSEL
+      description: RF system wakeup clock source selection
+      bit_offset: 14
+      bit_size: 2
+    - name: RFRSTS
+      description: Radio system BLE and 802.15.4 reset status
+      bit_offset: 16
+      bit_size: 1
+    - name: RMVF
+      description: Remove reset flag
+      bit_offset: 23
+      bit_size: 1
+    - name: OBLRSTF
+      description: Option byte loader reset flag
+      bit_offset: 25
+      bit_size: 1
+    - name: PINRSTF
+      description: Pin reset flag
+      bit_offset: 26
+      bit_size: 1
+    - name: BORRSTF
+      description: BOR flag
+      bit_offset: 27
+      bit_size: 1
+    - name: SFTRSTF
+      description: Software reset flag
+      bit_offset: 28
+      bit_size: 1
+    - name: IWDGRSTF
+      description: Independent window watchdog reset flag
+      bit_offset: 29
+      bit_size: 1
+    - name: WWDGRSTF
+      description: Window watchdog reset flag
+      bit_offset: 30
+      bit_size: 1
+    - name: LPWRRSTF
+      description: Low-power reset flag
+      bit_offset: 31
+      bit_size: 1
+fieldset/EXTCFGR:
+  description: Extended clock recovery register
+  fields:
+    - name: SHDHPRE
+      description: Shared AHB prescaler
+      bit_offset: 0
+      bit_size: 4
+    - name: C2HPRE
+      description: CPU2 AHB prescaler
+      bit_offset: 4
+      bit_size: 4
+    - name: SHDHPREF
+      description: Shared AHB prescaler flag
+      bit_offset: 16
+      bit_size: 1
+    - name: C2HPREF
+      description: CPU2 AHB prescaler flag
+      bit_offset: 17
+      bit_size: 1
+    - name: RFCSS
+      description: RF clock source selected
+      bit_offset: 20
+      bit_size: 1
+fieldset/HSECR:
+  description: Clock HSE register
+  fields:
+    - name: UNLOCKED
+      description: Register lock system
+      bit_offset: 0
+      bit_size: 1
+    - name: HSES
+      description: HSE Sense amplifier threshold
+      bit_offset: 3
+      bit_size: 1
+    - name: HSEGMC
+      description: HSE current control
+      bit_offset: 4
+      bit_size: 3
+    - name: HSETUNE
+      description: HSE capacitor tuning
+      bit_offset: 8
+      bit_size: 6
+fieldset/ICSCR:
+  description: Internal clock sources calibration register
+  fields:
+    - name: MSICAL
+      description: MSI clock calibration
+      bit_offset: 0
+      bit_size: 8
+    - name: MSITRIM
+      description: MSI clock trimming
+      bit_offset: 8
+      bit_size: 8
+    - name: HSICAL
+      description: HSI clock calibration
+      bit_offset: 16
+      bit_size: 8
+    - name: HSITRIM
+      description: HSI clock trimming
+      bit_offset: 24
+      bit_size: 7
+fieldset/PLLCFGR:
+  description: PLLSYS configuration register
+  fields:
+    - name: PLLSRC
+      description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source"
+      bit_offset: 0
+      bit_size: 2
+    - name: PLLM
+      description: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
+      bit_offset: 4
+      bit_size: 3
+    - name: PLLN
+      description: Main PLLSYS multiplication factor N
+      bit_offset: 8
+      bit_size: 7
+    - name: PLLPEN
+      description: Main PLLSYSP output enable
+      bit_offset: 16
+      bit_size: 1
+    - name: PLLP
+      description: Main PLL division factor P for PPLSYSSAICLK
+      bit_offset: 17
+      bit_size: 5
+    - name: PLLQEN
+      description: Main PLLSYSQ output enable
+      bit_offset: 24
+      bit_size: 1
+    - name: PLLQ
+      description: Main PLLSYS division factor Q for PLLSYSUSBCLK
+      bit_offset: 25
+      bit_size: 3
+    - name: PLLREN
+      description: Main PLLSYSR PLLCLK output enable
+      bit_offset: 28
+      bit_size: 1
+    - name: PLLR
+      description: Main PLLSYS division factor R for SYSCLK (system clock)
+      bit_offset: 29
+      bit_size: 3
+fieldset/PLLSAI1CFGR:
+  description: PLLSAI1 configuration register
+  fields:
+    - name: PLLN
+      description: SAIPLL multiplication factor for VCO
+      bit_offset: 8
+      bit_size: 7
+    - name: PLLPEN
+      description: SAIPLL PLLSAI1CLK output enable
+      bit_offset: 16
+      bit_size: 1
+    - name: PLLP
+      description: SAI1PLL division factor P for PLLSAICLK (SAI1clock)
+      bit_offset: 17
+      bit_size: 5
+    - name: PLLQEN
+      description: SAIPLL PLLSAIUSBCLK output enable
+      bit_offset: 24
+      bit_size: 1
+    - name: PLLQ
+      description: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)
+      bit_offset: 25
+      bit_size: 3
+    - name: PLLREN
+      description: PLLSAI PLLADC1CLK output enable
+      bit_offset: 28
+      bit_size: 1
+    - name: PLLR
+      description: PLLSAI division factor R for PLLADC1CLK (ADC clock)
+      bit_offset: 29
+      bit_size: 3
+fieldset/SMPSCR:
+  description: Step Down converter control register
+  fields:
+    - name: SMPSSEL
+      description: Step Down converter clock selection
+      bit_offset: 0
+      bit_size: 2
+    - name: SMPSDIV
+      description: Step Down converter clock prescaler
+      bit_offset: 4
+      bit_size: 2
+    - name: SMPSSWS
+      description: Step Down converter clock switch status
+      bit_offset: 8
+      bit_size: 2
diff --git a/data/registers/syscfg_wb55.yaml b/data/registers/syscfg_wb55.yaml
new file mode 100644
index 0000000..5d18269
--- /dev/null
+++ b/data/registers/syscfg_wb55.yaml
@@ -0,0 +1,400 @@
+---
+block/SYSCFG:
+  description: System configuration controller
+  items:
+    - name: MEMRMP
+      description: memory remap register
+      byte_offset: 0
+      fieldset: MEMRMP
+    - name: CFGR1
+      description: configuration register 1
+      byte_offset: 4
+      fieldset: CFGR1
+    - name: EXTICR
+      description: external interrupt configuration register 1
+      array:
+        len: 4
+        stride: 4
+      byte_offset: 8
+      fieldset: EXTICR
+    - name: SCSR
+      description: SCSR
+      byte_offset: 24
+      fieldset: SCSR
+    - name: CFGR2
+      description: CFGR2
+      byte_offset: 28
+      fieldset: CFGR2
+    - name: SWPR
+      description: SRAM2 write protection register
+      byte_offset: 32
+      access: Write
+      fieldset: SWPR
+    - name: SKR
+      description: SKR
+      byte_offset: 36
+      access: Write
+      fieldset: SKR
+    - name: SWPR2
+      description: SRAM2 write protection register 2
+      byte_offset: 40
+      access: Write
+      fieldset: SWPR2
+    - name: IMR1
+      description: CPU1 interrupt mask register 1
+      byte_offset: 44
+      fieldset: IMR1
+    - name: IMR2
+      description: CPU1 interrupt mask register 2
+      byte_offset: 48
+      fieldset: IMR2
+    - name: C2IMR1
+      description: CPU2 interrupt mask register 1
+      byte_offset: 52
+      fieldset: C2IMR1
+    - name: C2IMR2
+      description: CPU2 interrupt mask register 1
+      byte_offset: 56
+      fieldset: C2IMR2
+    - name: SIPCR
+      description: secure IP control register
+      byte_offset: 60
+      fieldset: SIPCR
+fieldset/C2IMR1:
+  description: CPU2 interrupt mask register 1
+  fields:
+    - name: RTCSTAMP
+      description: Peripheral RTCSTAMP interrupt mask to CPU2
+      bit_offset: 0
+      bit_size: 1
+    - name: RTCWKUP
+      description: Peripheral RTCWKUP interrupt mask to CPU2
+      bit_offset: 3
+      bit_size: 1
+    - name: RTCALARM
+      description: Peripheral RTCALARM interrupt mask to CPU2
+      bit_offset: 4
+      bit_size: 1
+    - name: RCC
+      description: Peripheral RCC interrupt mask to CPU2
+      bit_offset: 5
+      bit_size: 1
+    - name: FLASH
+      description: Peripheral FLASH interrupt mask to CPU2
+      bit_offset: 6
+      bit_size: 1
+    - name: PKA
+      description: Peripheral PKA interrupt mask to CPU2
+      bit_offset: 8
+      bit_size: 1
+    - name: RNG
+      description: Peripheral RNG interrupt mask to CPU2
+      bit_offset: 9
+      bit_size: 1
+    - name: AES
+      description: Peripheral AES1 interrupt mask to CPU2
+      bit_offset: 10
+      bit_size: 1
+      array:
+        len: 1
+        stride: 0
+    - name: COMP
+      description: Peripheral COMP interrupt mask to CPU2
+      bit_offset: 11
+      bit_size: 1
+    - name: ADC
+      description: Peripheral ADC interrupt mask to CPU2
+      bit_offset: 12
+      bit_size: 1
+fieldset/C2IMR2:
+  description: CPU2 interrupt mask register 1
+  fields:
+    - name: DMA1_CH1_IM
+      description: Peripheral DMA1 CH1 interrupt mask to CPU2
+      bit_offset: 0
+      bit_size: 1
+    - name: DMA1_CH2_IM
+      description: Peripheral DMA1 CH2 interrupt mask to CPU2
+      bit_offset: 1
+      bit_size: 1
+    - name: DMA1_CH3_IM
+      description: Peripheral DMA1 CH3 interrupt mask to CPU2
+      bit_offset: 2
+      bit_size: 1
+    - name: DMA1_CH4_IM
+      description: Peripheral DMA1 CH4 interrupt mask to CPU2
+      bit_offset: 3
+      bit_size: 1
+    - name: DMA1_CH5_IM
+      description: Peripheral DMA1 CH5 interrupt mask to CPU2
+      bit_offset: 4
+      bit_size: 1
+    - name: DMA1_CH6_IM
+      description: Peripheral DMA1 CH6 interrupt mask to CPU2
+      bit_offset: 5
+      bit_size: 1
+    - name: DMA1_CH7_IM
+      description: Peripheral DMA1 CH7 interrupt mask to CPU2
+      bit_offset: 6
+      bit_size: 1
+    - name: DMA2_CH1_IM
+      description: Peripheral DMA2 CH1 interrupt mask to CPU1
+      bit_offset: 8
+      bit_size: 1
+    - name: DMA2_CH2_IM
+      description: Peripheral DMA2 CH2 interrupt mask to CPU1
+      bit_offset: 9
+      bit_size: 1
+    - name: DMA2_CH3_IM
+      description: Peripheral DMA2 CH3 interrupt mask to CPU1
+      bit_offset: 10
+      bit_size: 1
+    - name: DMA2_CH4_IM
+      description: Peripheral DMA2 CH4 interrupt mask to CPU1
+      bit_offset: 11
+      bit_size: 1
+    - name: DMA2_CH5_IM
+      description: Peripheral DMA2 CH5 interrupt mask to CPU1
+      bit_offset: 12
+      bit_size: 1
+    - name: DMA2_CH6_IM
+      description: Peripheral DMA2 CH6 interrupt mask to CPU1
+      bit_offset: 13
+      bit_size: 1
+    - name: DMA2_CH7_IM
+      description: Peripheral DMA2 CH7 interrupt mask to CPU1
+      bit_offset: 14
+      bit_size: 1
+    - name: DMAM_UX1_IM
+      description: Peripheral DMAM UX1 interrupt mask to CPU1
+      bit_offset: 15
+      bit_size: 1
+    - name: PVM1IM
+      description: Peripheral PVM1IM interrupt mask to CPU1
+      bit_offset: 16
+      bit_size: 1
+    - name: PVM3IM
+      description: Peripheral PVM3IM interrupt mask to CPU1
+      bit_offset: 18
+      bit_size: 1
+    - name: PVDIM
+      description: Peripheral PVDIM interrupt mask to CPU1
+      bit_offset: 20
+      bit_size: 1
+    - name: TSCIM
+      description: Peripheral TSCIM interrupt mask to CPU1
+      bit_offset: 21
+      bit_size: 1
+    - name: LCDIM
+      description: Peripheral LCDIM interrupt mask to CPU1
+      bit_offset: 22
+      bit_size: 1
+fieldset/CFGR1:
+  description: configuration register 1
+  fields:
+    - name: BOOSTEN
+      description: I/O analog switch voltage booster enable
+      bit_offset: 8
+      bit_size: 1
+    - name: I2C_PB6_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB6
+      bit_offset: 16
+      bit_size: 1
+    - name: I2C_PB7_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB7
+      bit_offset: 17
+      bit_size: 1
+    - name: I2C_PB8_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB8
+      bit_offset: 18
+      bit_size: 1
+    - name: I2C_PB9_FMP
+      description: Fast-mode Plus (Fm+) driving capability activation on PB9
+      bit_offset: 19
+      bit_size: 1
+    - name: I2C1_FMP
+      description: I2C1 Fast-mode Plus driving capability activation
+      bit_offset: 20
+      bit_size: 1
+    - name: I2C3_FMP
+      description: I2C3 Fast-mode Plus driving capability activation
+      bit_offset: 22
+      bit_size: 1
+    - name: FPU_IE
+      description: Floating Point Unit interrupts enable bits
+      bit_offset: 26
+      bit_size: 6
+fieldset/CFGR2:
+  description: CFGR2
+  fields:
+    - name: CLL
+      description: Cortex-M4 LOCKUP (Hardfault) output enable bit
+      bit_offset: 0
+      bit_size: 1
+    - name: SPL
+      description: SRAM2 parity lock bit
+      bit_offset: 1
+      bit_size: 1
+    - name: PVDL
+      description: PVD lock enable bit
+      bit_offset: 2
+      bit_size: 1
+    - name: ECCL
+      description: ECC Lock
+      bit_offset: 3
+      bit_size: 1
+    - name: SPF
+      description: SRAM2 parity error flag
+      bit_offset: 8
+      bit_size: 1
+fieldset/EXTICR:
+  description: external interrupt configuration register 1
+  fields:
+    - name: EXTI
+      description: EXTI 0 configuration bits
+      bit_offset: 0
+      bit_size: 3
+      array:
+        len: 4
+        stride: 4
+fieldset/IMR1:
+  description: CPU1 interrupt mask register 1
+  fields:
+    - name: TIM1IM
+      description: Peripheral TIM1 interrupt mask to CPU1
+      bit_offset: 13
+      bit_size: 1
+    - name: TIM16IM
+      description: Peripheral TIM16 interrupt mask to CPU1
+      bit_offset: 14
+      bit_size: 1
+    - name: TIM17IM
+      description: Peripheral TIM17 interrupt mask to CPU1
+      bit_offset: 15
+      bit_size: 1
+    - name: EXIT5IM
+      description: Peripheral EXIT5 interrupt mask to CPU1
+      bit_offset: 21
+      bit_size: 1
+    - name: EXIT6IM
+      description: Peripheral EXIT6 interrupt mask to CPU1
+      bit_offset: 22
+      bit_size: 1
+    - name: EXIT7IM
+      description: Peripheral EXIT7 interrupt mask to CPU1
+      bit_offset: 23
+      bit_size: 1
+    - name: EXIT8IM
+      description: Peripheral EXIT8 interrupt mask to CPU1
+      bit_offset: 24
+      bit_size: 1
+    - name: EXIT9IM
+      description: Peripheral EXIT9 interrupt mask to CPU1
+      bit_offset: 25
+      bit_size: 1
+    - name: EXIT10IM
+      description: Peripheral EXIT10 interrupt mask to CPU1
+      bit_offset: 26
+      bit_size: 1
+    - name: EXIT11IM
+      description: Peripheral EXIT11 interrupt mask to CPU1
+      bit_offset: 27
+      bit_size: 1
+    - name: EXIT12IM
+      description: Peripheral EXIT12 interrupt mask to CPU1
+      bit_offset: 28
+      bit_size: 1
+    - name: EXIT13IM
+      description: Peripheral EXIT13 interrupt mask to CPU1
+      bit_offset: 29
+      bit_size: 1
+    - name: EXIT14IM
+      description: Peripheral EXIT14 interrupt mask to CPU1
+      bit_offset: 30
+      bit_size: 1
+    - name: EXIT15IM
+      description: Peripheral EXIT15 interrupt mask to CPU1
+      bit_offset: 31
+      bit_size: 1
+fieldset/IMR2:
+  description: CPU1 interrupt mask register 2
+  fields:
+    - name: PVM1IM
+      description: Peripheral PVM1 interrupt mask to CPU1
+      bit_offset: 16
+      bit_size: 1
+    - name: PVM3IM
+      description: Peripheral PVM3 interrupt mask to CPU1
+      bit_offset: 18
+      bit_size: 1
+    - name: PVDIM
+      description: Peripheral PVD interrupt mask to CPU1
+      bit_offset: 20
+      bit_size: 1
+fieldset/MEMRMP:
+  description: memory remap register
+  fields:
+    - name: MEM_MODE
+      description: Memory mapping selection
+      bit_offset: 0
+      bit_size: 3
+fieldset/SCSR:
+  description: SCSR
+  fields:
+    - name: SRAM2ER
+      description: SRAM2 Erase
+      bit_offset: 0
+      bit_size: 1
+    - name: SRAM2BSY
+      description: SRAM2 busy by erase operation
+      bit_offset: 1
+      bit_size: 1
+    - name: C2RFD
+      description: CPU2 SRAM fetch (execution) disable.
+      bit_offset: 31
+      bit_size: 1
+fieldset/SIPCR:
+  description: secure IP control register
+  fields:
+    - name: SAES
+      description: "Enable AES1 KEY[7:0] security."
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 2
+        stride: 1
+    - name: SPKA
+      description: Enable PKA security
+      bit_offset: 2
+      bit_size: 1
+    - name: SRNG
+      description: Enable True RNG security
+      bit_offset: 3
+      bit_size: 1
+fieldset/SKR:
+  description: SKR
+  fields:
+    - name: KEY
+      description: SRAM2 write protection key for software erase
+      bit_offset: 0
+      bit_size: 8
+fieldset/SWPR:
+  description: SRAM2 write protection register
+  fields:
+    - name: PWP
+      description: P0WP
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
+fieldset/SWPR2:
+  description: SRAM2 write protection register 2
+  fields:
+    - name: PWP
+      description: P32WP
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 32
+        stride: 1
diff --git a/parse.py b/parse.py
index 9014f11..4cb4bd7 100644
--- a/parse.py
+++ b/parse.py
@@ -242,11 +242,13 @@ perimap = [
     ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'),
     ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'),
     ('STM32H7.*:SYS:.*', 'syscfg_h7/SYSCFG'),
+    ('STM32WB55.*:SYS:.*', 'syscfg_wb55/SYSCFG'),
     ('STM32L0.*:RCC:.*', 'rcc_l0/RCC'),
     ('STM32L4.*:RCC:.*', 'rcc_l4/RCC'),
     ('STM32F4.*:RCC:.*', 'rcc_f4/RCC'),
     ('.*:STM32H7AB_rcc_v1_0', ''),  # rcc_h7ab/RCC
     ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
+    ('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
     ('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'),
     ('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
     ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
@@ -261,6 +263,7 @@ rng_clock_map = [
     ('STM32L4.*:RNG:.*', 'AHB2'),
     ('STM32F4.*:RNG:.*', 'AHB2'),
     ('STM32H7.*:RNG:.*', 'AHB2'),
+    ('STM32WB55.*:RNG:.*', 'AHB3')
 ]