diff --git a/data/registers/rcc_c0.yaml b/data/registers/rcc_c0.yaml index e5072d4..18e7dd2 100644 --- a/data/registers/rcc_c0.yaml +++ b/data/registers/rcc_c0.yaml @@ -380,12 +380,12 @@ fieldset/CFGR: bit_offset: 20 bit_size: 4 enum: MCOPRE - - name: MCOSEL + - name: MCO1SEL description: "Microcontroller clock output clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO." bit_offset: 24 bit_size: 4 enum: MCOSEL - - name: MCOPRE + - name: MCO1PRE description: "Microcontroller clock output prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows:\r ...\r It is highly recommended to set this field before the MCO output is enabled." bit_offset: 28 bit_size: 4 diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml index ecc6758..263c33f 100644 --- a/data/registers/rcc_f0.yaml +++ b/data/registers/rcc_f0.yaml @@ -474,11 +474,11 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: PLLMUL - - name: MCO + - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 3 - enum: MCO + enum: MCOSEL - name: MCOPRE description: Microcontroller Clock Output Prescaler bit_offset: 28 @@ -817,7 +817,34 @@ enum/LSEDRV: - name: High description: High driving capability value: 3 -enum/MCO: +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 +enum/MCOSEL: bit_size: 3 variants: - name: NoMCO @@ -847,33 +874,6 @@ enum/MCO: - name: HSI48 description: Internal RC 48 MHz (HSI48) oscillator clock selected value: 8 -enum/MCOPRE: - bit_size: 3 - variants: - - name: Div1 - description: MCO is divided by 1 - value: 0 - - name: Div2 - description: MCO is divided by 2 - value: 1 - - name: Div4 - description: MCO is divided by 4 - value: 2 - - name: Div8 - description: MCO is divided by 8 - value: 3 - - name: Div16 - description: MCO is divided by 16 - value: 4 - - name: Div32 - description: MCO is divided by 32 - value: 5 - - name: Div64 - description: MCO is divided by 64 - value: 6 - - name: Div128 - description: MCO is divided by 128 - value: 7 enum/PLLMUL: bit_size: 4 variants: diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 901c896..30d7117 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -493,11 +493,11 @@ fieldset/CFGR: bit_offset: 22 bit_size: 1 enum: USBPRE - - name: MCO + - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 3 - enum: MCO + enum: MCOSEL fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: @@ -696,7 +696,7 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/MCO: +enum/MCOSEL: bit_size: 3 variants: - name: NoMCO diff --git a/data/registers/rcc_f100.yaml b/data/registers/rcc_f100.yaml index 3162335..6303bf8 100644 --- a/data/registers/rcc_f100.yaml +++ b/data/registers/rcc_f100.yaml @@ -456,11 +456,11 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: PLLMUL - - name: MCO + - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 3 - enum: MCO + enum: MCOSEL fieldset/CFGR2: description: Clock configuration register 2 fields: @@ -667,7 +667,7 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/MCO: +enum/MCOSEL: bit_size: 3 variants: - name: NoMCO diff --git a/data/registers/rcc_f1cl.yaml b/data/registers/rcc_f1cl.yaml index 6dd0090..91f13fa 100644 --- a/data/registers/rcc_f1cl.yaml +++ b/data/registers/rcc_f1cl.yaml @@ -440,11 +440,11 @@ fieldset/CFGR: bit_offset: 22 bit_size: 1 enum: USBPRE - - name: MCO + - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 4 - enum: MCO + enum: MCOSEL fieldset/CFGR2: description: Clock configuration register2 (RCC_CFGR2) fields: @@ -730,7 +730,7 @@ enum/I2S2SRC: - name: PLL3 description: PLL3 VCO clock selected as I2S clock entry value: 1 -enum/MCO: +enum/MCOSEL: bit_size: 4 variants: - name: NoMCO diff --git a/data/registers/rcc_f2.yaml b/data/registers/rcc_f2.yaml index 955d03a..23463ff 100644 --- a/data/registers/rcc_f2.yaml +++ b/data/registers/rcc_f2.yaml @@ -914,11 +914,11 @@ fieldset/CFGR: description: HSE division factor for RTC clock bit_offset: 16 bit_size: 5 - - name: MCO1 + - name: MCO1SEL description: Microcontroller clock output 1 bit_offset: 21 bit_size: 2 - enum: MCO1 + enum: MCO1SEL - name: I2SSRC description: I2S clock selection bit_offset: 23 @@ -934,11 +934,11 @@ fieldset/CFGR: bit_offset: 27 bit_size: 3 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: Microcontroller clock output 2 bit_offset: 30 bit_size: 2 - enum: MCO2 + enum: MCO2SEL fieldset/CIR: description: clock interrupt register fields: @@ -1211,7 +1211,7 @@ enum/ISSRC: - name: CKIN description: External clock mapped on the I2S_CKIN pin used as I2S clock source value: 1 -enum/MCO1: +enum/MCO1SEL: bit_size: 2 variants: - name: HSI @@ -1226,7 +1226,7 @@ enum/MCO1: - name: PLL description: PLL clock selected value: 3 -enum/MCO2: +enum/MCO2SEL: bit_size: 2 variants: - name: SYSCLK diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index e213d03..b359337 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -542,11 +542,11 @@ fieldset/CFGR: bit_offset: 23 bit_size: 1 enum: ISSRC - - name: MCO + - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 3 - enum: MCO + enum: MCOSEL - name: SDPRE description: SDADC prescaler bit_offset: 27 @@ -968,30 +968,6 @@ enum/LSEDRV: - name: High description: High driving capability value: 3 -enum/MCO: - bit_size: 3 - variants: - - name: NoMCO - description: MCO output disabled, no clock on MCO - value: 0 - - name: LSI - description: Internal low speed (LSI) oscillator clock selected - value: 2 - - name: LSE - description: External low speed (LSE) oscillator clock selected - value: 3 - - name: SYSCLK - description: System clock selected - value: 4 - - name: HSI - description: Internal RC 8 MHz (HSI) oscillator clock selected - value: 5 - - name: HSE - description: External 4-32 MHz (HSE) oscillator clock selected - value: 6 - - name: PLL - description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) - value: 7 enum/MCOPRE: bit_size: 3 variants: @@ -1019,6 +995,30 @@ enum/MCOPRE: - name: Div128 description: MCO is divided by 128 value: 7 +enum/MCOSEL: + bit_size: 3 + variants: + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) + value: 7 enum/PLLMUL: bit_size: 4 variants: diff --git a/data/registers/rcc_f3_v2.yaml b/data/registers/rcc_f3_v2.yaml index 2d9679a..7b3d376 100644 --- a/data/registers/rcc_f3_v2.yaml +++ b/data/registers/rcc_f3_v2.yaml @@ -518,11 +518,11 @@ fieldset/CFGR: bit_offset: 23 bit_size: 1 enum: ISSRC - - name: MCO + - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 3 - enum: MCO + enum: MCOSEL - name: SDPRE description: SDADC prescaler bit_offset: 27 @@ -944,30 +944,6 @@ enum/LSEDRV: - name: High description: High driving capability value: 3 -enum/MCO: - bit_size: 3 - variants: - - name: NoMCO - description: MCO output disabled, no clock on MCO - value: 0 - - name: LSI - description: Internal low speed (LSI) oscillator clock selected - value: 2 - - name: LSE - description: External low speed (LSE) oscillator clock selected - value: 3 - - name: SYSCLK - description: System clock selected - value: 4 - - name: HSI - description: Internal RC 8 MHz (HSI) oscillator clock selected - value: 5 - - name: HSE - description: External 4-32 MHz (HSE) oscillator clock selected - value: 6 - - name: PLL - description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) - value: 7 enum/MCOPRE: bit_size: 3 variants: @@ -995,6 +971,30 @@ enum/MCOPRE: - name: Div128 description: MCO is divided by 128 value: 7 +enum/MCOSEL: + bit_size: 3 + variants: + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYSCLK + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: PLL clock selected (divided by 1 or 2, depending en PLLNODIV) + value: 7 enum/PLLMUL: bit_size: 4 variants: diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 8b044dc..81c61ec 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -1251,11 +1251,11 @@ fieldset/CFGR: description: HSE division factor for RTC clock bit_offset: 16 bit_size: 5 - - name: MCO1 + - name: MCO1SEL description: Microcontroller clock output 1 bit_offset: 21 bit_size: 2 - enum: MCO1 + enum: MCO1SEL - name: I2SSRC description: I2S clock selection bit_offset: 23 @@ -1271,11 +1271,11 @@ fieldset/CFGR: bit_offset: 27 bit_size: 3 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: Microcontroller clock output 2 bit_offset: 30 bit_size: 2 - enum: MCO2 + enum: MCO2SEL fieldset/CIR: description: clock interrupt register fields: @@ -1876,7 +1876,7 @@ enum/LSEMOD: - name: High description: LSE oscillator high drive mode selection value: 1 -enum/MCO1: +enum/MCO1SEL: bit_size: 2 variants: - name: HSI @@ -1891,7 +1891,7 @@ enum/MCO1: - name: PLL description: PLL clock selected value: 3 -enum/MCO2: +enum/MCO2SEL: bit_size: 2 variants: - name: SYSCLK diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml index 98ee613..e092d8d 100644 --- a/data/registers/rcc_f410.yaml +++ b/data/registers/rcc_f410.yaml @@ -532,11 +532,11 @@ fieldset/CFGR: description: HSE division factor for RTC clock bit_offset: 16 bit_size: 5 - - name: MCO1 + - name: MCO1SEL description: Microcontroller clock output 1 bit_offset: 21 bit_size: 2 - enum: MCO1 + enum: MCO1SEL - name: MCO1PRE description: MCO1 prescaler bit_offset: 24 @@ -547,11 +547,11 @@ fieldset/CFGR: bit_offset: 27 bit_size: 3 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: Microcontroller clock output 2 bit_offset: 30 bit_size: 2 - enum: MCO2 + enum: MCO2SEL fieldset/CIR: description: clock interrupt register fields: @@ -857,7 +857,7 @@ enum/LPTIMSEL: - name: LSE description: LSE clock is selected as LPTILM1 clock value: 3 -enum/MCO1: +enum/MCO1SEL: bit_size: 2 variants: - name: HSI @@ -872,7 +872,7 @@ enum/MCO1: - name: PLL description: PLL clock selected value: 3 -enum/MCO2: +enum/MCO2SEL: bit_size: 2 variants: - name: SYSCLK diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index fbf3400..bd25ce3 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -1235,11 +1235,11 @@ fieldset/CFGR: description: HSE division factor for RTC clock bit_offset: 16 bit_size: 5 - - name: MCO1 + - name: MCO1SEL description: Microcontroller clock output 1 bit_offset: 21 bit_size: 2 - enum: MCO1 + enum: MCO1SEL - name: I2SSRC description: I2S clock selection bit_offset: 23 @@ -1255,11 +1255,11 @@ fieldset/CFGR: bit_offset: 27 bit_size: 3 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: Microcontroller clock output 2 bit_offset: 30 bit_size: 2 - enum: MCO2 + enum: MCO2SEL fieldset/CIR: description: clock interrupt register fields: @@ -1808,7 +1808,7 @@ enum/LSEDRV: - name: High description: High driving capability value: 3 -enum/MCO1: +enum/MCO1SEL: bit_size: 2 variants: - name: HSI @@ -1823,7 +1823,7 @@ enum/MCO1: - name: PLL description: PLL clock selected value: 3 -enum/MCO2: +enum/MCO2SEL: bit_size: 2 variants: - name: SYSCLK diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index c6856dc..7502d7c 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -846,12 +846,12 @@ fieldset/CFGR: bit_offset: 20 bit_size: 4 enum: MCOPRE - - name: MCOSEL + - name: MCO1SEL description: Microcontroller clock output bit_offset: 24 bit_size: 3 enum: MCOSEL - - name: MCOPRE + - name: MCO1PRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml index 7e88186..4eaa94e 100644 --- a/data/registers/rcc_h5.yaml +++ b/data/registers/rcc_h5.yaml @@ -1668,21 +1668,21 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: MCOPRE - - name: MCO1 + - name: MCO1SEL description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" bit_offset: 22 bit_size: 3 - enum: MCO1 + enum: MCO1SEL - name: MCO2PRE description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." bit_offset: 25 bit_size: 4 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" bit_offset: 29 bit_size: 3 - enum: MCO2 + enum: MCO2SEL fieldset/CFGR2: description: RCC CPU domain clock configuration register 2 fields: @@ -2327,7 +2327,7 @@ enum/LSEEXT: - name: Digital description: LSE in digital mode (do not use if RTC is active). value: 1 -enum/MCO1: +enum/MCO1SEL: bit_size: 3 variants: - name: HSI @@ -2345,7 +2345,7 @@ enum/MCO1: - name: HSI48 description: HSI48 selected for micro-controller clock output value: 4 -enum/MCO2: +enum/MCO2SEL: bit_size: 3 variants: - name: SYSCLK diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index 236b4e6..580f974 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -952,21 +952,21 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: MCOPRE - - name: MCO1 + - name: MCO1SEL description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" bit_offset: 22 bit_size: 3 - enum: MCO1 + enum: MCO1SEL - name: MCO2PRE description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." bit_offset: 25 bit_size: 4 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" bit_offset: 29 bit_size: 3 - enum: MCO2 + enum: MCO2SEL fieldset/CFGR2: description: RCC CPU domain clock configuration register 2 fields: @@ -1519,7 +1519,7 @@ enum/LSEEXT: - name: Digital description: LSE in digital mode (do not use if RTC is active). value: 1 -enum/MCO1: +enum/MCO1SEL: bit_size: 3 variants: - name: HSI @@ -1537,7 +1537,7 @@ enum/MCO1: - name: HSI48 description: HSI48 selected for micro-controller clock output value: 4 -enum/MCO2: +enum/MCO2SEL: bit_size: 3 variants: - name: SYSCLK diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index 1140c6f..6baaede 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -2790,21 +2790,21 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: MCOPRE - - name: MCO1 + - name: MCO1SEL description: Micro-controller clock output 1 bit_offset: 22 bit_size: 3 - enum: MCO1 + enum: MCO1SEL - name: MCO2PRE description: MCO2 prescaler bit_offset: 25 bit_size: 4 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: Micro-controller clock output 2 bit_offset: 29 bit_size: 3 - enum: MCO2 + enum: MCO2SEL fieldset/CICR: description: RCC Clock Source Interrupt Clear Register fields: @@ -3725,7 +3725,7 @@ enum/LSEDRV: - name: High description: High driving capability value: 3 -enum/MCO1: +enum/MCO1SEL: bit_size: 3 variants: - name: HSI @@ -3743,7 +3743,7 @@ enum/MCO1: - name: HSI48 description: HSI48 selected for micro-controller clock output value: 4 -enum/MCO2: +enum/MCO2SEL: bit_size: 3 variants: - name: SYSCLK diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index f9e3e4f..6a890a8 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -1757,21 +1757,21 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: MCOPRE - - name: MCO1 + - name: MCO1SEL description: Micro-controller clock output 1 bit_offset: 22 bit_size: 3 - enum: MCO1 + enum: MCO1SEL - name: MCO2PRE description: MCO2 prescaler bit_offset: 25 bit_size: 4 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: Micro-controller clock output 2 bit_offset: 29 bit_size: 3 - enum: MCO2 + enum: MCO2SEL fieldset/CICR: description: RCC Clock Source Interrupt Clear Register fields: @@ -2660,7 +2660,7 @@ enum/LSEDRV: - name: High description: High driving capability value: 3 -enum/MCO1: +enum/MCO1SEL: bit_size: 3 variants: - name: HSI @@ -2678,7 +2678,7 @@ enum/MCO1: - name: HSI48 description: HSI48 selected for micro-controller clock output value: 4 -enum/MCO2: +enum/MCO2SEL: bit_size: 3 variants: - name: SYSCLK diff --git a/data/registers/rcc_h7rm0433.yaml b/data/registers/rcc_h7rm0433.yaml index ada0743..cb857785 100644 --- a/data/registers/rcc_h7rm0433.yaml +++ b/data/registers/rcc_h7rm0433.yaml @@ -2790,21 +2790,21 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: MCOPRE - - name: MCO1 + - name: MCO1SEL description: Micro-controller clock output 1 bit_offset: 22 bit_size: 3 - enum: MCO1 + enum: MCO1SEL - name: MCO2PRE description: MCO2 prescaler bit_offset: 25 bit_size: 4 enum: MCOPRE - - name: MCO2 + - name: MCO2SEL description: Micro-controller clock output 2 bit_offset: 29 bit_size: 3 - enum: MCO2 + enum: MCO2SEL fieldset/CICR: description: RCC Clock Source Interrupt Clear Register fields: @@ -3725,7 +3725,7 @@ enum/LSEDRV: - name: High description: High driving capability value: 3 -enum/MCO1: +enum/MCO1SEL: bit_size: 3 variants: - name: HSI @@ -3743,7 +3743,7 @@ enum/MCO1: - name: HSI48 description: HSI48 selected for micro-controller clock output value: 4 -enum/MCO2: +enum/MCO2SEL: bit_size: 3 variants: - name: SYSCLK