From 2e1302c4e8e72d5fd7e2d77c0691bc428768b33a Mon Sep 17 00:00:00 2001 From: Matous Hybl Date: Thu, 21 Oct 2021 14:54:44 +0200 Subject: [PATCH] Support for STM32F767ZI and basic support for the rest of the family. --- README.md | 35 +- data/registers/adc_v2.yaml | 737 ++++ data/registers/adccommon_v2.yaml | 272 ++ data/registers/dac_v1.yaml | 366 ++ data/registers/dcmi_v1.yaml | 286 ++ data/registers/dma2d_v1.yaml | 728 ++++ data/registers/dma2d_v2.yaml | 919 +++++ data/registers/eth_v1c.yaml | 1025 ++++++ data/registers/flash_f7.yaml | 382 ++ data/registers/iwdg_v2.yaml | 110 + data/registers/jpeg_v1.yaml | 5849 ++++++++++++++++++++++++++++++ data/registers/lptim_v1.yaml | 223 ++ data/registers/ltdc_v1.yaml | 774 ++++ data/registers/mdios_v1.yaml | 1193 ++++++ data/registers/otgfs_v1.yaml | 936 +++++ data/registers/otghs_v1.yaml | 931 +++++ data/registers/pwr_f7.yaml | 182 + data/registers/quadspi_v1.yaml | 296 ++ data/registers/rcc_f7.yaml | 263 +- data/registers/rtc_v2.yaml | 1173 ++++++ data/registers/sai_v1.yaml | 755 ++++ data/registers/sdmmc_v1.yaml | 507 +++ data/registers/spdifrx_v1.yaml | 241 ++ data/registers/spi_v2.yaml | 814 +++-- data/registers/syscfg_f7.yaml | 111 + data/registers/wwdg_v1.yaml | 99 + parse.py | 30 +- 27 files changed, 18829 insertions(+), 408 deletions(-) create mode 100644 data/registers/adc_v2.yaml create mode 100644 data/registers/adccommon_v2.yaml create mode 100644 data/registers/dac_v1.yaml create mode 100644 data/registers/dcmi_v1.yaml create mode 100644 data/registers/dma2d_v1.yaml create mode 100644 data/registers/dma2d_v2.yaml create mode 100644 data/registers/eth_v1c.yaml create mode 100644 data/registers/flash_f7.yaml create mode 100644 data/registers/iwdg_v2.yaml create mode 100644 data/registers/jpeg_v1.yaml create mode 100644 data/registers/lptim_v1.yaml create mode 100644 data/registers/ltdc_v1.yaml create mode 100644 data/registers/mdios_v1.yaml create mode 100644 data/registers/otgfs_v1.yaml create mode 100644 data/registers/otghs_v1.yaml create mode 100644 data/registers/pwr_f7.yaml create mode 100644 data/registers/quadspi_v1.yaml create mode 100644 data/registers/rtc_v2.yaml create mode 100644 data/registers/sai_v1.yaml create mode 100644 data/registers/sdmmc_v1.yaml create mode 100644 data/registers/spdifrx_v1.yaml create mode 100644 data/registers/syscfg_f7.yaml create mode 100644 data/registers/wwdg_v1.yaml diff --git a/README.md b/README.md index 2de36b3..47d2441 100644 --- a/README.md +++ b/README.md @@ -40,6 +40,9 @@ In order to run the generator, you will need to install the following tools: This generates all the YAMLs in `data/` except those in `data/registers/`, which are manually extracted and cleaned up. +> Do not manually edit the files in `data/chips`, contents of these files are autogenerated. +> Assignments of registers to peripherals is done in the file `parse.py` and fixes to registers can be done in the files located in `data/registers`. + ## Extracting new register blocks For instance, to add support for the G0 series first download all the source @@ -53,7 +56,10 @@ Now extract the RCC peripheral registers: ./d extract-all RCC --transform ./transform-RCC.yaml ``` Note that we have used a transform to mechanically clean up some of the RCC -definitions. This will produce a YAML file for each chip model in `./tmp/RCC` +definitions. This will produce a YAML file for each chip model in `./tmp/RCC`. + +Sometimes the peripheral name will not match the name defined in the SVD files, check the SVD file for the correct peripheral name. + At this point we need to choose the model with the largest peripheral set (e.g. the STM32G081) and compare its YAML against each of the other models' to verify that they are all mutually consistent. @@ -67,3 +73,30 @@ place: ``` mv regs_merged.yaml data/registers/rcc_g0.yaml ``` + +To assign these newly generated registers to peripherals, utilize the mapping done in `parse.py`. +An example mapping can be seen in the following snippet +``` +('STM32G0.*:RCC:.*', 'rcc_g0/RCC'), +``` +such mapping assignes the `rcc_g0/RCC` register block to the `RCC` peripheral in every device from the `STM32G0` family. + +The pattern for matching is as follows: +``` +CHIP:PERIPHERAL:PERIPHERAL_KIND +``` +Thanks to this, you can for example match peripherals with the same name, but different versions. +``` +('.*:SPI:spi2s1_v2_2', 'spi_v1/SPI'), +('.*:SPI:spi2s1_v3_2', 'spi_v2/SPI'), +``` + +When matching the peripherals using the pattern, the first defined pattern is applied if more of the patterns would match. +``` +('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'), +('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'), +('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'), +``` + +### Peripheral versions +The versions of peripherals can be found in the table [here](https://docs.google.com/spreadsheets/d/1-R-AjYrMLL2_623G-AFN2A9THMf8FFMpFD4Kq-owPmI/edit#gid=0). diff --git a/data/registers/adc_v2.yaml b/data/registers/adc_v2.yaml new file mode 100644 index 0000000..6391a0f --- /dev/null +++ b/data/registers/adc_v2.yaml @@ -0,0 +1,737 @@ +--- +block/ADC: + description: Analog-to-digital converter + items: + - byte_offset: 0 + description: status register + fieldset: SR + name: SR + - byte_offset: 4 + description: control register 1 + fieldset: CR1 + name: CR1 + - byte_offset: 8 + description: control register 2 + fieldset: CR2 + name: CR2 + - byte_offset: 12 + description: sample time register 1 + fieldset: SMPR1 + name: SMPR1 + - byte_offset: 16 + description: sample time register 2 + fieldset: SMPR2 + name: SMPR2 + - array: + len: 4 + stride: 4 + byte_offset: 20 + description: injected channel data offset register x + fieldset: JOFR + name: JOFR + - byte_offset: 36 + description: watchdog higher threshold register + fieldset: HTR + name: HTR + - byte_offset: 40 + description: watchdog lower threshold register + fieldset: LTR + name: LTR + - byte_offset: 44 + description: regular sequence register 1 + fieldset: SQR1 + name: SQR1 + - byte_offset: 48 + description: regular sequence register 2 + fieldset: SQR2 + name: SQR2 + - byte_offset: 52 + description: regular sequence register 3 + fieldset: SQR3 + name: SQR3 + - byte_offset: 56 + description: injected sequence register + fieldset: JSQR + name: JSQR + - access: Read + array: + len: 4 + stride: 4 + byte_offset: 60 + description: injected data register x + fieldset: JDR + name: JDR + - access: Read + byte_offset: 76 + description: regular data register + fieldset: DR + name: DR +enum/ADON: + bit_size: 1 + variants: + - description: Disable ADC conversion and go to power down mode + name: Disabled + value: 0 + - description: Enable ADC + name: Enabled + value: 1 +enum/ALIGN: + bit_size: 1 + variants: + - description: Right alignment + name: Right + value: 0 + - description: Left alignment + name: Left + value: 1 +enum/AWD: + bit_size: 1 + variants: + - description: No analog watchdog event occurred + name: NoEvent + value: 0 + - description: Analog watchdog event occurred + name: Event + value: 1 +enum/AWDEN: + bit_size: 1 + variants: + - description: Analog watchdog disabled on regular channels + name: Disabled + value: 0 + - description: Analog watchdog enabled on regular channels + name: Enabled + value: 1 +enum/AWDIE: + bit_size: 1 + variants: + - description: Analogue watchdog interrupt disabled + name: Disabled + value: 0 + - description: Analogue watchdog interrupt enabled + name: Enabled + value: 1 +enum/AWDSGL: + bit_size: 1 + variants: + - description: Analog watchdog enabled on all channels + name: AllChannels + value: 0 + - description: Analog watchdog enabled on a single channel + name: SingleChannel + value: 1 +enum/CONT: + bit_size: 1 + variants: + - description: Single conversion mode + name: Single + value: 0 + - description: Continuous conversion mode + name: Continuous + value: 1 +enum/DDS: + bit_size: 1 + variants: + - description: No new DMA request is issued after the last transfer + name: Single + value: 0 + - description: DMA requests are issued as long as data are converted and DMA=1 + name: Continuous + value: 1 +enum/DISCEN: + bit_size: 1 + variants: + - description: Discontinuous mode on regular channels disabled + name: Disabled + value: 0 + - description: Discontinuous mode on regular channels enabled + name: Enabled + value: 1 +enum/DMA: + bit_size: 1 + variants: + - description: DMA mode disabled + name: Disabled + value: 0 + - description: DMA mode enabled + name: Enabled + value: 1 +enum/EOC: + bit_size: 1 + variants: + - description: Conversion is not complete + name: NotComplete + value: 0 + - description: Conversion complete + name: Complete + value: 1 +enum/EOCIE: + bit_size: 1 + variants: + - description: EOC interrupt disabled + name: Disabled + value: 0 + - description: EOC interrupt enabled + name: Enabled + value: 1 +enum/EOCS: + bit_size: 1 + variants: + - description: The EOC bit is set at the end of each sequence of regular conversions + name: EachSequence + value: 0 + - description: The EOC bit is set at the end of each regular conversion + name: EachConversion + value: 1 +enum/EXTEN: + bit_size: 2 + variants: + - description: Trigger detection disabled + name: Disabled + value: 0 + - description: Trigger detection on the rising edge + name: RisingEdge + value: 1 + - description: Trigger detection on the falling edge + name: FallingEdge + value: 2 + - description: Trigger detection on both the rising and falling edges + name: BothEdges + value: 3 +enum/EXTSEL: + bit_size: 4 + variants: + - description: Timer 1 CC1 event + name: TIM1CC1 + value: 0 + - description: Timer 1 CC2 event + name: TIM1CC2 + value: 1 + - description: Timer 1 CC3 event + name: TIM1CC3 + value: 2 + - description: Timer 2 CC2 event + name: TIM2CC2 + value: 3 + - description: Timer 2 CC3 event + name: TIM2CC3 + value: 4 + - description: Timer 2 CC4 event + name: TIM2CC4 + value: 5 + - description: Timer 2 TRGO event + name: TIM2TRGO + value: 6 +enum/JAUTO: + bit_size: 1 + variants: + - description: Automatic injected group conversion disabled + name: Disabled + value: 0 + - description: Automatic injected group conversion enabled + name: Enabled + value: 1 +enum/JAWDEN: + bit_size: 1 + variants: + - description: Analog watchdog disabled on injected channels + name: Disabled + value: 0 + - description: Analog watchdog enabled on injected channels + name: Enabled + value: 1 +enum/JDISCEN: + bit_size: 1 + variants: + - description: Discontinuous mode on injected channels disabled + name: Disabled + value: 0 + - description: Discontinuous mode on injected channels enabled + name: Enabled + value: 1 +enum/JEOC: + bit_size: 1 + variants: + - description: Conversion is not complete + name: NotComplete + value: 0 + - description: Conversion complete + name: Complete + value: 1 +enum/JEOCIE: + bit_size: 1 + variants: + - description: JEOC interrupt disabled + name: Disabled + value: 0 + - description: JEOC interrupt enabled + name: Enabled + value: 1 +enum/JEXTEN: + bit_size: 2 + variants: + - description: Trigger detection disabled + name: Disabled + value: 0 + - description: Trigger detection on the rising edge + name: RisingEdge + value: 1 + - description: Trigger detection on the falling edge + name: FallingEdge + value: 2 + - description: Trigger detection on both the rising and falling edges + name: BothEdges + value: 3 +enum/JEXTSEL: + bit_size: 4 + variants: + - description: Timer 1 TRGO event + name: TIM1TRGO + value: 0 + - description: Timer 1 CC4 event + name: TIM1CC4 + value: 1 + - description: Timer 2 TRGO event + name: TIM2TRGO + value: 2 + - description: Timer 2 CC1 event + name: TIM2CC1 + value: 3 + - description: Timer 3 CC4 event + name: TIM3CC4 + value: 4 + - description: Timer 4 TRGO event + name: TIM4TRGO + value: 5 + - description: Timer 8 CC4 event + name: TIM8CC4 + value: 7 + - description: Timer 1 TRGO(2) event + name: TIM1TRGO2 + value: 8 + - description: Timer 8 TRGO event + name: TIM8TRGO + value: 9 + - description: Timer 8 TRGO(2) event + name: TIM8TRGO2 + value: 10 + - description: Timer 3 CC3 event + name: TIM3CC3 + value: 11 + - description: Timer 5 TRGO event + name: TIM5TRGO + value: 12 + - description: Timer 3 CC1 event + name: TIM3CC1 + value: 13 + - description: Timer 6 TRGO event + name: TIM6TRGO + value: 14 +enum/JSTRT: + bit_size: 1 + variants: + - description: No injected channel conversion started + name: NotStarted + value: 0 + - description: Injected channel conversion has started + name: Started + value: 1 +enum/JSWSTARTW: + bit_size: 1 + variants: + - description: Starts conversion of injected channels + name: Start + value: 1 +enum/OVR: + bit_size: 1 + variants: + - description: No overrun occurred + name: NoOverrun + value: 0 + - description: Overrun occurred + name: Overrun + value: 1 +enum/OVRIE: + bit_size: 1 + variants: + - description: Overrun interrupt disabled + name: Disabled + value: 0 + - description: Overrun interrupt enabled + name: Enabled + value: 1 +enum/RES: + bit_size: 2 + variants: + - description: 12-bit (15 ADCCLK cycles) + name: TwelveBit + value: 0 + - description: 10-bit (13 ADCCLK cycles) + name: TenBit + value: 1 + - description: 8-bit (11 ADCCLK cycles) + name: EightBit + value: 2 + - description: 6-bit (9 ADCCLK cycles) + name: SixBit + value: 3 +enum/SCAN: + bit_size: 1 + variants: + - description: Scan mode disabled + name: Disabled + value: 0 + - description: Scan mode enabled + name: Enabled + value: 1 +enum/SMP: + bit_size: 3 + variants: + - description: 3 cycles + name: Cycles3 + value: 0 + - description: 15 cycles + name: Cycles15 + value: 1 + - description: 28 cycles + name: Cycles28 + value: 2 + - description: 56 cycles + name: Cycles56 + value: 3 + - description: 84 cycles + name: Cycles84 + value: 4 + - description: 112 cycles + name: Cycles112 + value: 5 + - description: 144 cycles + name: Cycles144 + value: 6 + - description: 480 cycles + name: Cycles480 + value: 7 +enum/SMPR_SMPx_x: + bit_size: 32 + variants: + - description: 3 cycles + name: Cycles3 + value: 0 + - description: 15 cycles + name: Cycles15 + value: 1 + - description: 28 cycles + name: Cycles28 + value: 2 + - description: 56 cycles + name: Cycles56 + value: 3 + - description: 84 cycles + name: Cycles84 + value: 4 + - description: 112 cycles + name: Cycles112 + value: 5 + - description: 144 cycles + name: Cycles144 + value: 6 + - description: 480 cycles + name: Cycles480 + value: 7 +enum/STRT: + bit_size: 1 + variants: + - description: No regular channel conversion started + name: NotStarted + value: 0 + - description: Regular channel conversion has started + name: Started + value: 1 +enum/SWSTARTW: + bit_size: 1 + variants: + - description: Starts conversion of regular channels + name: Start + value: 1 +fieldset/CR1: + description: control register 1 + fields: + - bit_offset: 0 + bit_size: 5 + description: Analog watchdog channel select bits + name: AWDCH + - bit_offset: 5 + bit_size: 1 + description: Interrupt enable for EOC + enum: EOCIE + name: EOCIE + - bit_offset: 6 + bit_size: 1 + description: Analog watchdog interrupt enable + enum: AWDIE + name: AWDIE + - bit_offset: 7 + bit_size: 1 + description: Interrupt enable for injected channels + enum: JEOCIE + name: JEOCIE + - bit_offset: 8 + bit_size: 1 + description: Scan mode + enum: SCAN + name: SCAN + - bit_offset: 9 + bit_size: 1 + description: Enable the watchdog on a single channel in scan mode + enum: AWDSGL + name: AWDSGL + - bit_offset: 10 + bit_size: 1 + description: Automatic injected group conversion + enum: JAUTO + name: JAUTO + - bit_offset: 11 + bit_size: 1 + description: Discontinuous mode on regular channels + enum: DISCEN + name: DISCEN + - bit_offset: 12 + bit_size: 1 + description: Discontinuous mode on injected channels + enum: JDISCEN + name: JDISCEN + - bit_offset: 13 + bit_size: 3 + description: Discontinuous mode channel count + name: DISCNUM + - bit_offset: 22 + bit_size: 1 + description: Analog watchdog enable on injected channels + enum: JAWDEN + name: JAWDEN + - bit_offset: 23 + bit_size: 1 + description: Analog watchdog enable on regular channels + enum: AWDEN + name: AWDEN + - bit_offset: 24 + bit_size: 2 + description: Resolution + enum: RES + name: RES + - bit_offset: 26 + bit_size: 1 + description: Overrun interrupt enable + enum: OVRIE + name: OVRIE +fieldset/CR2: + description: control register 2 + fields: + - bit_offset: 0 + bit_size: 1 + description: A/D Converter ON / OFF + enum: ADON + name: ADON + - bit_offset: 1 + bit_size: 1 + description: Continuous conversion + enum: CONT + name: CONT + - bit_offset: 8 + bit_size: 1 + description: Direct memory access mode (for single ADC mode) + enum: DMA + name: DMA + - bit_offset: 9 + bit_size: 1 + description: DMA disable selection (for single ADC mode) + enum: DDS + name: DDS + - bit_offset: 10 + bit_size: 1 + description: End of conversion selection + enum: EOCS + name: EOCS + - bit_offset: 11 + bit_size: 1 + description: Data alignment + enum: ALIGN + name: ALIGN + - bit_offset: 16 + bit_size: 4 + description: External event select for injected group + enum: JEXTSEL + name: JEXTSEL + - bit_offset: 20 + bit_size: 2 + description: External trigger enable for injected channels + enum: JEXTEN + name: JEXTEN + - bit_offset: 22 + bit_size: 1 + description: Start conversion of injected channels + enum_write: JSWSTARTW + name: JSWSTART + - bit_offset: 24 + bit_size: 4 + description: External event select for regular group + enum: EXTSEL + name: EXTSEL + - bit_offset: 28 + bit_size: 2 + description: External trigger enable for regular channels + enum: EXTEN + name: EXTEN + - bit_offset: 30 + bit_size: 1 + description: Start conversion of regular channels + enum_write: SWSTARTW + name: SWSTART +fieldset/DR: + description: regular data register + fields: + - bit_offset: 0 + bit_size: 16 + description: Regular data + name: DATA +fieldset/HTR: + description: watchdog higher threshold register + fields: + - bit_offset: 0 + bit_size: 12 + description: Analog watchdog higher threshold + name: HT +fieldset/JDR: + description: injected data register x + fields: + - bit_offset: 0 + bit_size: 16 + description: Injected data + name: JDATA +fieldset/JOFR: + description: injected channel data offset register x + fields: + - bit_offset: 0 + bit_size: 12 + description: Data offset for injected channel x + name: JOFFSET +fieldset/JSQR: + description: injected sequence register + fields: + - array: + len: 4 + stride: 5 + bit_offset: 0 + bit_size: 5 + description: 1st conversion in injected sequence + name: JSQ + - bit_offset: 20 + bit_size: 2 + description: Injected sequence length + name: JL +fieldset/LTR: + description: watchdog lower threshold register + fields: + - bit_offset: 0 + bit_size: 12 + description: Analog watchdog lower threshold + name: LT +fieldset/SMPR1: + description: sample time register 1 + fields: + - array: + len: 9 + stride: 3 + bit_offset: 0 + bit_size: 3 + description: Channel 10 sampling time selection + enum: SMP + name: SMP + - bit_offset: 0 + bit_size: 32 + description: Sample time bits + enum: SMPR_SMPx_x + name: SMPx_x +fieldset/SMPR2: + description: sample time register 2 + fields: + - array: + len: 10 + stride: 3 + bit_offset: 0 + bit_size: 3 + description: Channel 0 sampling time selection + enum: SMP + name: SMP + - bit_offset: 0 + bit_size: 32 + description: Sample time bits + enum: SMPR_SMPx_x + name: SMPx_x +fieldset/SQR1: + description: regular sequence register 1 + fields: + - array: + len: 4 + stride: 5 + bit_offset: 0 + bit_size: 5 + description: 13th conversion in regular sequence + name: SQ + - bit_offset: 20 + bit_size: 4 + description: Regular channel sequence length + name: L +fieldset/SQR2: + description: regular sequence register 2 + fields: + - array: + len: 6 + stride: 5 + bit_offset: 0 + bit_size: 5 + description: 7th conversion in regular sequence + name: SQ +fieldset/SQR3: + description: regular sequence register 3 + fields: + - array: + len: 6 + stride: 5 + bit_offset: 0 + bit_size: 5 + description: 1st conversion in regular sequence + name: SQ +fieldset/SR: + description: status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Analog watchdog flag + enum: AWD + name: AWD + - bit_offset: 1 + bit_size: 1 + description: Regular channel end of conversion + enum: EOC + name: EOC + - bit_offset: 2 + bit_size: 1 + description: Injected channel end of conversion + enum: JEOC + name: JEOC + - bit_offset: 3 + bit_size: 1 + description: Injected channel start flag + enum: JSTRT + name: JSTRT + - bit_offset: 4 + bit_size: 1 + description: Regular channel start flag + enum: STRT + name: STRT + - bit_offset: 5 + bit_size: 1 + description: Overrun + enum: OVR + name: OVR diff --git a/data/registers/adccommon_v2.yaml b/data/registers/adccommon_v2.yaml new file mode 100644 index 0000000..512e946 --- /dev/null +++ b/data/registers/adccommon_v2.yaml @@ -0,0 +1,272 @@ +--- +block/ADC_COMMON: + description: ADC common registers + items: + - access: Read + byte_offset: 0 + description: ADC Common status register + fieldset: CSR + name: CSR + - byte_offset: 4 + description: ADC common control register + fieldset: CCR + name: CCR + - access: Read + byte_offset: 8 + description: ADC common regular data register for dual and triple modes + fieldset: CDR + name: CDR +enum/ADCPRE: + bit_size: 2 + variants: + - description: PCLK2 divided by 2 + name: Div2 + value: 0 + - description: PCLK2 divided by 4 + name: Div4 + value: 1 + - description: PCLK2 divided by 6 + name: Div6 + value: 2 + - description: PCLK2 divided by 8 + name: Div8 + value: 3 +enum/AWD: + bit_size: 1 + variants: + - description: No analog watchdog event occurred + name: NoEvent + value: 0 + - description: Analog watchdog event occurred + name: Event + value: 1 +enum/DDS: + bit_size: 1 + variants: + - description: No new DMA request is issued after the last transfer + name: Single + value: 0 + - description: DMA requests are issued as long as data are converted and DMA=01, + 10 or 11 + name: Continuous + value: 1 +enum/DMA: + bit_size: 2 + variants: + - description: DMA mode disabled + name: Disabled + value: 0 + - description: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) + name: Mode1 + value: 1 + - description: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then + 3&2) + name: Mode2 + value: 2 + - description: DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then + 3&2) + name: Mode3 + value: 3 +enum/EOC: + bit_size: 1 + variants: + - description: Conversion is not complete + name: NotComplete + value: 0 + - description: Conversion complete + name: Complete + value: 1 +enum/JEOC: + bit_size: 1 + variants: + - description: Conversion is not complete + name: NotComplete + value: 0 + - description: Conversion complete + name: Complete + value: 1 +enum/JSTRT: + bit_size: 1 + variants: + - description: No injected channel conversion started + name: NotStarted + value: 0 + - description: Injected channel conversion has started + name: Started + value: 1 +enum/MULTI: + bit_size: 5 + variants: + - description: 'All the ADCs independent: independent mode' + name: Independent + value: 0 + - description: Dual ADC1 and ADC2, combined regular and injected simultaneous mode + name: DualRJ + value: 1 + - description: Dual ADC1 and ADC2, combined regular and alternate trigger mode + name: DualRA + value: 2 + - description: Dual ADC1 and ADC2, injected simultaneous mode only + name: DualJ + value: 5 + - description: Dual ADC1 and ADC2, regular simultaneous mode only + name: DualR + value: 6 + - description: Dual ADC1 and ADC2, interleaved mode only + name: DualI + value: 7 + - description: Dual ADC1 and ADC2, alternate trigger mode only + name: DualA + value: 9 + - description: Triple ADC, regular and injected simultaneous mode + name: TripleRJ + value: 17 + - description: Triple ADC, regular and alternate trigger mode + name: TripleRA + value: 18 + - description: Triple ADC, injected simultaneous mode only + name: TripleJ + value: 21 + - description: Triple ADC, regular simultaneous mode only + name: TripleR + value: 22 + - description: Triple ADC, interleaved mode only + name: TripleI + value: 23 + - description: Triple ADC, alternate trigger mode only + name: TripleA + value: 24 +enum/OVR: + bit_size: 1 + variants: + - description: No overrun occurred + name: NoOverrun + value: 0 + - description: Overrun occurred + name: Overrun + value: 1 +enum/STRT: + bit_size: 1 + variants: + - description: No regular channel conversion started + name: NotStarted + value: 0 + - description: Regular channel conversion has started + name: Started + value: 1 +enum/TSVREFE: + bit_size: 1 + variants: + - description: Temperature sensor and V_REFINT channel disabled + name: Disabled + value: 0 + - description: Temperature sensor and V_REFINT channel enabled + name: Enabled + value: 1 +enum/VBATE: + bit_size: 1 + variants: + - description: V_BAT channel disabled + name: Disabled + value: 0 + - description: V_BAT channel enabled + name: Enabled + value: 1 +fieldset/CCR: + description: ADC common control register + fields: + - bit_offset: 0 + bit_size: 5 + description: Multi ADC mode selection + enum: MULTI + name: MULTI + - bit_offset: 8 + bit_size: 4 + description: Delay between 2 sampling phases + name: DELAY + - bit_offset: 13 + bit_size: 1 + description: DMA disable selection for multi-ADC mode + enum: DDS + name: DDS + - bit_offset: 14 + bit_size: 2 + description: Direct memory access mode for multi ADC mode + enum: DMA + name: DMA + - bit_offset: 16 + bit_size: 2 + description: ADC prescaler + enum: ADCPRE + name: ADCPRE + - bit_offset: 22 + bit_size: 1 + description: VBAT enable + enum: VBATE + name: VBATE + - bit_offset: 23 + bit_size: 1 + description: Temperature sensor and VREFINT enable + enum: TSVREFE + name: TSVREFE +fieldset/CDR: + description: ADC common regular data register for dual and triple modes + fields: + - array: + len: 2 + stride: 16 + bit_offset: 0 + bit_size: 16 + description: 1st data item of a pair of regular conversions + name: DATA +fieldset/CSR: + description: ADC common status register + fields: + - array: + len: 3 + stride: 8 + bit_offset: 0 + bit_size: 1 + description: Analog watchdog flag of ADC 1 + enum: AWD + name: AWD + - array: + len: 3 + stride: 8 + bit_offset: 1 + bit_size: 1 + description: End of conversion of ADC 1 + enum: EOC + name: EOC + - array: + len: 3 + stride: 8 + bit_offset: 2 + bit_size: 1 + description: Injected channel end of conversion of ADC 1 + enum: JEOC + name: JEOC + - array: + len: 3 + stride: 8 + bit_offset: 3 + bit_size: 1 + description: Injected channel Start flag of ADC 1 + enum: JSTRT + name: JSTRT + - array: + len: 3 + stride: 8 + bit_offset: 4 + bit_size: 1 + description: Regular channel Start flag of ADC 1 + enum: STRT + name: STRT + - array: + len: 3 + stride: 8 + bit_offset: 5 + bit_size: 1 + description: Overrun flag of ADC 1 + enum: OVR + name: OVR diff --git a/data/registers/dac_v1.yaml b/data/registers/dac_v1.yaml new file mode 100644 index 0000000..d081aa0 --- /dev/null +++ b/data/registers/dac_v1.yaml @@ -0,0 +1,366 @@ +--- +block/DAC: + description: Digital-to-analog converter + items: + - byte_offset: 0 + description: control register + fieldset: CR + name: CR + - access: Write + byte_offset: 4 + description: software trigger register + fieldset: SWTRIGR + name: SWTRIGR + - byte_offset: 8 + description: channel1 12-bit right-aligned data holding register + fieldset: DHR12R1 + name: DHR12R1 + - byte_offset: 12 + description: channel1 12-bit left aligned data holding register + fieldset: DHR12L1 + name: DHR12L1 + - byte_offset: 16 + description: channel1 8-bit right aligned data holding register + fieldset: DHR8R1 + name: DHR8R1 + - byte_offset: 20 + description: channel2 12-bit right aligned data holding register + fieldset: DHR12R2 + name: DHR12R2 + - byte_offset: 24 + description: channel2 12-bit left aligned data holding register + fieldset: DHR12L2 + name: DHR12L2 + - byte_offset: 28 + description: channel2 8-bit right-aligned data holding register + fieldset: DHR8R2 + name: DHR8R2 + - byte_offset: 32 + description: Dual DAC 12-bit right-aligned data holding register + fieldset: DHR12RD + name: DHR12RD + - byte_offset: 36 + description: DUAL DAC 12-bit left aligned data holding register + fieldset: DHR12LD + name: DHR12LD + - byte_offset: 40 + description: DUAL DAC 8-bit right aligned data holding register + fieldset: DHR8RD + name: DHR8RD + - access: Read + byte_offset: 44 + description: channel1 data output register + fieldset: DOR1 + name: DOR1 + - access: Read + byte_offset: 48 + description: channel2 data output register + fieldset: DOR2 + name: DOR2 + - byte_offset: 52 + description: status register + fieldset: SR + name: SR +enum/BOFF: + bit_size: 1 + variants: + - description: DAC channel X output buffer enabled + name: Enabled + value: 0 + - description: DAC channel X output buffer disabled + name: Disabled + value: 1 +enum/DMAEN: + bit_size: 1 + variants: + - description: DAC channel X DMA mode disabled + name: Disabled + value: 0 + - description: DAC channel X DMA mode enabled + name: Enabled + value: 1 +enum/DMAUDR: + bit_size: 1 + variants: + - description: No DMA underrun error condition occurred for DAC channel X + name: NoUnderrun + value: 0 + - description: DMA underrun error condition occurred for DAC channel X + name: Underrun + value: 1 +enum/DMAUDRIE: + bit_size: 1 + variants: + - description: DAC channel X DMA Underrun Interrupt disabled + name: Disabled + value: 0 + - description: DAC channel X DMA Underrun Interrupt enabled + name: Enabled + value: 1 +enum/EN: + bit_size: 1 + variants: + - description: DAC channel X disabled + name: Disabled + value: 0 + - description: DAC channel X enabled + name: Enabled + value: 1 +enum/SWTRIG: + bit_size: 1 + variants: + - description: DAC channel X software trigger disabled + name: Disabled + value: 0 + - description: DAC channel X software trigger enabled + name: Enabled + value: 1 +enum/TEN: + bit_size: 1 + variants: + - description: DAC channel X trigger disabled + name: Disabled + value: 0 + - description: DAC channel X trigger enabled + name: Enabled + value: 1 +enum/TSEL1: + bit_size: 3 + variants: + - description: Timer 6 TRGO event + name: TIM6_TRGO + value: 0 + - description: Timer 3 TRGO event + name: TIM3_TRGO + value: 1 + - description: Timer 7 TRGO event + name: TIM7_TRGO + value: 2 + - description: Timer 15 TRGO event + name: TIM15_TRGO + value: 3 + - description: Timer 2 TRGO event + name: TIM2_TRGO + value: 4 + - description: EXTI line9 + name: EXTI9 + value: 6 + - description: Software trigger + name: SOFTWARE + value: 7 +enum/TSEL2: + bit_size: 3 + variants: + - description: Timer 6 TRGO event + name: TIM6_TRGO + value: 0 + - description: Timer 8 TRGO event + name: TIM8_TRGO + value: 1 + - description: Timer 7 TRGO event + name: TIM7_TRGO + value: 2 + - description: Timer 5 TRGO event + name: TIM5_TRGO + value: 3 + - description: Timer 2 TRGO event + name: TIM2_TRGO + value: 4 + - description: Timer 4 TRGO event + name: TIM4_TRGO + value: 5 + - description: EXTI line9 + name: EXTI9 + value: 6 + - description: Software trigger + name: SOFTWARE + value: 7 +enum/WAVE: + bit_size: 2 + variants: + - description: Wave generation disabled + name: Disabled + value: 0 + - description: Noise wave generation enabled + name: Noise + value: 1 + - description: Triangle wave generation enabled + name: Triangle + value: 2 +fieldset/CR: + description: control register + fields: + - array: + len: 2 + stride: 16 + bit_offset: 0 + bit_size: 1 + description: DAC channel1 enable + enum: EN + name: EN + - array: + len: 2 + stride: 16 + bit_offset: 1 + bit_size: 1 + description: DAC channel1 output buffer disable + enum: BOFF + name: BOFF + - array: + len: 2 + stride: 16 + bit_offset: 2 + bit_size: 1 + description: DAC channel1 trigger enable + enum: TEN + name: TEN + - array: + len: 2 + stride: 16 + bit_offset: 3 + bit_size: 3 + description: DAC channel1 trigger selection + enum: TSEL1 + name: TSEL + - array: + len: 2 + stride: 16 + bit_offset: 6 + bit_size: 2 + description: DAC channel1 noise/triangle wave generation enable + enum: WAVE + name: WAVE + - array: + len: 2 + stride: 16 + bit_offset: 8 + bit_size: 4 + description: DAC channel1 mask/amplitude selector + name: MAMP + - array: + len: 2 + stride: 16 + bit_offset: 12 + bit_size: 1 + description: DAC channel1 DMA enable + enum: DMAEN + name: DMAEN + - array: + len: 2 + stride: 16 + bit_offset: 13 + bit_size: 1 + description: DAC channel1 DMA Underrun Interrupt enable + enum: DMAUDRIE + name: DMAUDRIE +fieldset/DHR12L1: + description: channel1 12-bit left aligned data holding register + fields: + - bit_offset: 4 + bit_size: 12 + description: DAC channel1 12-bit left-aligned data + name: DACC1DHR +fieldset/DHR12L2: + description: channel2 12-bit left aligned data holding register + fields: + - bit_offset: 4 + bit_size: 12 + description: DAC channel2 12-bit left-aligned data + name: DACC2DHR +fieldset/DHR12LD: + description: DUAL DAC 12-bit left aligned data holding register + fields: + - bit_offset: 4 + bit_size: 12 + description: DAC channel1 12-bit left-aligned data + name: DACC1DHR + - bit_offset: 20 + bit_size: 12 + description: DAC channel2 12-bit left-aligned data + name: DACC2DHR +fieldset/DHR12R1: + description: channel1 12-bit right-aligned data holding register + fields: + - bit_offset: 0 + bit_size: 12 + description: DAC channel1 12-bit right-aligned data + name: DACC1DHR +fieldset/DHR12R2: + description: channel2 12-bit right aligned data holding register + fields: + - bit_offset: 0 + bit_size: 12 + description: DAC channel2 12-bit right-aligned data + name: DACC2DHR +fieldset/DHR12RD: + description: Dual DAC 12-bit right-aligned data holding register + fields: + - bit_offset: 0 + bit_size: 12 + description: DAC channel1 12-bit right-aligned data + name: DACC1DHR + - bit_offset: 16 + bit_size: 12 + description: DAC channel2 12-bit right-aligned data + name: DACC2DHR +fieldset/DHR8R1: + description: channel1 8-bit right aligned data holding register + fields: + - bit_offset: 0 + bit_size: 8 + description: DAC channel1 8-bit right-aligned data + name: DACC1DHR +fieldset/DHR8R2: + description: channel2 8-bit right-aligned data holding register + fields: + - bit_offset: 0 + bit_size: 8 + description: DAC channel2 8-bit right-aligned data + name: DACC2DHR +fieldset/DHR8RD: + description: DUAL DAC 8-bit right aligned data holding register + fields: + - bit_offset: 0 + bit_size: 8 + description: DAC channel1 8-bit right-aligned data + name: DACC1DHR + - bit_offset: 8 + bit_size: 8 + description: DAC channel2 8-bit right-aligned data + name: DACC2DHR +fieldset/DOR1: + description: channel1 data output register + fields: + - bit_offset: 0 + bit_size: 12 + description: DAC channel1 data output + name: DACC1DOR +fieldset/DOR2: + description: channel2 data output register + fields: + - bit_offset: 0 + bit_size: 12 + description: DAC channel2 data output + name: DACC2DOR +fieldset/SR: + description: status register + fields: + - array: + len: 2 + stride: 16 + bit_offset: 13 + bit_size: 1 + description: DAC channel1 DMA underrun flag + enum: DMAUDR + name: DMAUDR +fieldset/SWTRIGR: + description: software trigger register + fields: + - array: + len: 2 + stride: 1 + bit_offset: 0 + bit_size: 1 + description: DAC channel1 software trigger + enum: SWTRIG + name: SWTRIG diff --git a/data/registers/dcmi_v1.yaml b/data/registers/dcmi_v1.yaml new file mode 100644 index 0000000..d9c69ed --- /dev/null +++ b/data/registers/dcmi_v1.yaml @@ -0,0 +1,286 @@ +--- +block/DCMI: + description: Digital camera interface + items: + - byte_offset: 0 + description: control register 1 + fieldset: CR + name: CR + - access: Read + byte_offset: 4 + description: status register + fieldset: SR + name: SR + - access: Read + byte_offset: 8 + description: raw interrupt status register + fieldset: RIS + name: RIS + - byte_offset: 12 + description: interrupt enable register + fieldset: IER + name: IER + - access: Read + byte_offset: 16 + description: masked interrupt status register + fieldset: MIS + name: MIS + - access: Write + byte_offset: 20 + description: interrupt clear register + fieldset: ICR + name: ICR + - byte_offset: 24 + description: embedded synchronization code register + fieldset: ESCR + name: ESCR + - byte_offset: 28 + description: embedded synchronization unmask register + fieldset: ESUR + name: ESUR + - byte_offset: 32 + description: crop window start + fieldset: CWSTRT + name: CWSTRT + - byte_offset: 36 + description: crop window size + fieldset: CWSIZE + name: CWSIZE + - access: Read + byte_offset: 40 + description: data register + fieldset: DR + name: DR +fieldset/CR: + description: control register 1 + fields: + - bit_offset: 0 + bit_size: 1 + description: Capture enable + name: CAPTURE + - bit_offset: 1 + bit_size: 1 + description: Capture mode + name: CM + - bit_offset: 2 + bit_size: 1 + description: Crop feature + name: CROP + - bit_offset: 3 + bit_size: 1 + description: JPEG format + name: JPEG + - bit_offset: 4 + bit_size: 1 + description: Embedded synchronization select + name: ESS + - bit_offset: 5 + bit_size: 1 + description: Pixel clock polarity + name: PCKPOL + - bit_offset: 6 + bit_size: 1 + description: Horizontal synchronization polarity + name: HSPOL + - bit_offset: 7 + bit_size: 1 + description: Vertical synchronization polarity + name: VSPOL + - bit_offset: 8 + bit_size: 2 + description: Frame capture rate control + name: FCRC + - bit_offset: 10 + bit_size: 2 + description: Extended data mode + name: EDM + - bit_offset: 14 + bit_size: 1 + description: DCMI enable + name: ENABLE +fieldset/CWSIZE: + description: crop window size + fields: + - bit_offset: 0 + bit_size: 14 + description: Capture count + name: CAPCNT + - bit_offset: 16 + bit_size: 14 + description: Vertical line count + name: VLINE +fieldset/CWSTRT: + description: crop window start + fields: + - bit_offset: 0 + bit_size: 14 + description: Horizontal offset count + name: HOFFCNT + - bit_offset: 16 + bit_size: 13 + description: Vertical start line count + name: VST +fieldset/DR: + description: data register + fields: + - bit_offset: 0 + bit_size: 8 + description: Data byte 0 + name: Byte0 + - bit_offset: 8 + bit_size: 8 + description: Data byte 1 + name: Byte1 + - bit_offset: 16 + bit_size: 8 + description: Data byte 2 + name: Byte2 + - bit_offset: 24 + bit_size: 8 + description: Data byte 3 + name: Byte3 +fieldset/ESCR: + description: embedded synchronization code register + fields: + - bit_offset: 0 + bit_size: 8 + description: Frame start delimiter code + name: FSC + - bit_offset: 8 + bit_size: 8 + description: Line start delimiter code + name: LSC + - bit_offset: 16 + bit_size: 8 + description: Line end delimiter code + name: LEC + - bit_offset: 24 + bit_size: 8 + description: Frame end delimiter code + name: FEC +fieldset/ESUR: + description: embedded synchronization unmask register + fields: + - bit_offset: 0 + bit_size: 8 + description: Frame start delimiter unmask + name: FSU + - bit_offset: 8 + bit_size: 8 + description: Line start delimiter unmask + name: LSU + - bit_offset: 16 + bit_size: 8 + description: Line end delimiter unmask + name: LEU + - bit_offset: 24 + bit_size: 8 + description: Frame end delimiter unmask + name: FEU +fieldset/ICR: + description: interrupt clear register + fields: + - bit_offset: 0 + bit_size: 1 + description: Capture complete interrupt status clear + name: FRAME_ISC + - bit_offset: 1 + bit_size: 1 + description: Overrun interrupt status clear + name: OVR_ISC + - bit_offset: 2 + bit_size: 1 + description: Synchronization error interrupt status clear + name: ERR_ISC + - bit_offset: 3 + bit_size: 1 + description: Vertical synch interrupt status clear + name: VSYNC_ISC + - bit_offset: 4 + bit_size: 1 + description: line interrupt status clear + name: LINE_ISC +fieldset/IER: + description: interrupt enable register + fields: + - bit_offset: 0 + bit_size: 1 + description: Capture complete interrupt enable + name: FRAME_IE + - bit_offset: 1 + bit_size: 1 + description: Overrun interrupt enable + name: OVR_IE + - bit_offset: 2 + bit_size: 1 + description: Synchronization error interrupt enable + name: ERR_IE + - bit_offset: 3 + bit_size: 1 + description: VSYNC interrupt enable + name: VSYNC_IE + - bit_offset: 4 + bit_size: 1 + description: Line interrupt enable + name: LINE_IE +fieldset/MIS: + description: masked interrupt status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Capture complete masked interrupt status + name: FRAME_MIS + - bit_offset: 1 + bit_size: 1 + description: Overrun masked interrupt status + name: OVR_MIS + - bit_offset: 2 + bit_size: 1 + description: Synchronization error masked interrupt status + name: ERR_MIS + - bit_offset: 3 + bit_size: 1 + description: VSYNC masked interrupt status + name: VSYNC_MIS + - bit_offset: 4 + bit_size: 1 + description: Line masked interrupt status + name: LINE_MIS +fieldset/RIS: + description: raw interrupt status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Capture complete raw interrupt status + name: FRAME_RIS + - bit_offset: 1 + bit_size: 1 + description: Overrun raw interrupt status + name: OVR_RIS + - bit_offset: 2 + bit_size: 1 + description: Synchronization error raw interrupt status + name: ERR_RIS + - bit_offset: 3 + bit_size: 1 + description: VSYNC raw interrupt status + name: VSYNC_RIS + - bit_offset: 4 + bit_size: 1 + description: Line raw interrupt status + name: LINE_RIS +fieldset/SR: + description: status register + fields: + - bit_offset: 0 + bit_size: 1 + description: HSYNC + name: HSYNC + - bit_offset: 1 + bit_size: 1 + description: VSYNC + name: VSYNC + - bit_offset: 2 + bit_size: 1 + description: FIFO not empty + name: FNE diff --git a/data/registers/dma2d_v1.yaml b/data/registers/dma2d_v1.yaml new file mode 100644 index 0000000..5acc5fe --- /dev/null +++ b/data/registers/dma2d_v1.yaml @@ -0,0 +1,728 @@ +--- +block/DMA2D: + description: DMA2D controller + items: + - byte_offset: 0 + description: control register + fieldset: CR + name: CR + - access: Read + byte_offset: 4 + description: Interrupt Status Register + fieldset: ISR + name: ISR + - byte_offset: 8 + description: interrupt flag clear register + fieldset: IFCR + name: IFCR + - byte_offset: 12 + description: foreground memory address register + fieldset: FGMAR + name: FGMAR + - byte_offset: 16 + description: foreground offset register + fieldset: FGOR + name: FGOR + - byte_offset: 20 + description: background memory address register + fieldset: BGMAR + name: BGMAR + - byte_offset: 24 + description: background offset register + fieldset: BGOR + name: BGOR + - byte_offset: 28 + description: foreground PFC control register + fieldset: FGPFCCR + name: FGPFCCR + - byte_offset: 32 + description: foreground color register + fieldset: FGCOLR + name: FGCOLR + - byte_offset: 36 + description: background PFC control register + fieldset: BGPFCCR + name: BGPFCCR + - byte_offset: 40 + description: background color register + fieldset: BGCOLR + name: BGCOLR + - byte_offset: 44 + description: foreground CLUT memory address register + fieldset: FGCMAR + name: FGCMAR + - byte_offset: 48 + description: background CLUT memory address register + fieldset: BGCMAR + name: BGCMAR + - byte_offset: 52 + description: output PFC control register + fieldset: OPFCCR + name: OPFCCR + - byte_offset: 56 + description: output color register + fieldset: OCOLR + name: OCOLR + - byte_offset: 60 + description: output memory address register + fieldset: OMAR + name: OMAR + - byte_offset: 64 + description: output offset register + fieldset: OOR + name: OOR + - byte_offset: 68 + description: number of line register + fieldset: NLR + name: NLR + - byte_offset: 72 + description: line watermark register + fieldset: LWR + name: LWR + - byte_offset: 76 + description: AHB master timer configuration register + fieldset: AMTCR + name: AMTCR + - byte_offset: 1024 + description: FGCLUT + fieldset: FGCLUT + name: FGCLUT + - byte_offset: 2048 + description: BGCLUT + fieldset: BGCLUT + name: BGCLUT +enum/ABORT: + bit_size: 1 + variants: + - description: Transfer abort requested + name: AbortRequest + value: 1 +enum/BGPFCCR_AM: + bit_size: 2 + variants: + - description: No modification of alpha channel + name: NoModify + value: 0 + - description: Replace with value in ALPHA[7:0] + name: Replace + value: 1 + - description: Multiply with value in ALPHA[7:0] + name: Multiply + value: 2 +enum/BGPFCCR_CCM: + bit_size: 1 + variants: + - description: CLUT color format ARGB8888 + name: ARGB8888 + value: 0 + - description: CLUT color format RGB888 + name: RGB888 + value: 1 +enum/BGPFCCR_CM: + bit_size: 4 + variants: + - description: Color mode ARGB8888 + name: ARGB8888 + value: 0 + - description: Color mode RGB888 + name: RGB888 + value: 1 + - description: Color mode RGB565 + name: RGB565 + value: 2 + - description: Color mode ARGB1555 + name: ARGB1555 + value: 3 + - description: Color mode ARGB4444 + name: ARGB4444 + value: 4 + - description: Color mode L8 + name: L8 + value: 5 + - description: Color mode AL44 + name: AL44 + value: 6 + - description: Color mode AL88 + name: AL88 + value: 7 + - description: Color mode L4 + name: L4 + value: 8 + - description: Color mode A8 + name: A8 + value: 9 + - description: Color mode A4 + name: A4 + value: 10 +enum/BGPFCCR_START: + bit_size: 1 + variants: + - description: Start the automatic loading of the CLUT + name: Start + value: 1 +enum/CAECIF: + bit_size: 1 + variants: + - description: Clear the CAEIF flag in the ISR register + name: Clear + value: 1 +enum/CAEIE: + bit_size: 1 + variants: + - description: CAE interrupt disabled + name: Disabled + value: 0 + - description: CAE interrupt enabled + name: Enabled + value: 1 +enum/CCEIF: + bit_size: 1 + variants: + - description: Clear the CEIF flag in the ISR register + name: Clear + value: 1 +enum/CCTCIF: + bit_size: 1 + variants: + - description: Clear the CTCIF flag in the ISR register + name: Clear + value: 1 +enum/CEIE: + bit_size: 1 + variants: + - description: CE interrupt disabled + name: Disabled + value: 0 + - description: CE interrupt enabled + name: Enabled + value: 1 +enum/CR_START: + bit_size: 1 + variants: + - description: Launch the DMA2D + name: Start + value: 1 +enum/CTCIE: + bit_size: 1 + variants: + - description: CTC interrupt disabled + name: Disabled + value: 0 + - description: CTC interrupt enabled + name: Enabled + value: 1 +enum/CTCIF: + bit_size: 1 + variants: + - description: Clear the TCIF flag in the ISR register + name: Clear + value: 1 +enum/CTEIF: + bit_size: 1 + variants: + - description: Clear the TEIF flag in the ISR register + name: Clear + value: 1 +enum/CTWIF: + bit_size: 1 + variants: + - description: Clear the TWIF flag in the ISR register + name: Clear + value: 1 +enum/EN: + bit_size: 1 + variants: + - description: Disabled AHB/AXI dead-time functionality + name: Disabled + value: 0 + - description: Enabled AHB/AXI dead-time functionality + name: Enabled + value: 1 +enum/FGPFCCR_AM: + bit_size: 2 + variants: + - description: No modification of alpha channel + name: NoModify + value: 0 + - description: Replace with value in ALPHA[7:0] + name: Replace + value: 1 + - description: Multiply with value in ALPHA[7:0] + name: Multiply + value: 2 +enum/FGPFCCR_CCM: + bit_size: 1 + variants: + - description: CLUT color format ARGB8888 + name: ARGB8888 + value: 0 + - description: CLUT color format RGB888 + name: RGB888 + value: 1 +enum/FGPFCCR_CM: + bit_size: 4 + variants: + - description: Color mode ARGB8888 + name: ARGB8888 + value: 0 + - description: Color mode RGB888 + name: RGB888 + value: 1 + - description: Color mode RGB565 + name: RGB565 + value: 2 + - description: Color mode ARGB1555 + name: ARGB1555 + value: 3 + - description: Color mode ARGB4444 + name: ARGB4444 + value: 4 + - description: Color mode L8 + name: L8 + value: 5 + - description: Color mode AL44 + name: AL44 + value: 6 + - description: Color mode AL88 + name: AL88 + value: 7 + - description: Color mode L4 + name: L4 + value: 8 + - description: Color mode A8 + name: A8 + value: 9 + - description: Color mode A4 + name: A4 + value: 10 +enum/FGPFCCR_START: + bit_size: 1 + variants: + - description: Start the automatic loading of the CLUT + name: Start + value: 1 +enum/MODE: + bit_size: 2 + variants: + - description: Memory-to-memory (FG fetch only) + name: MemoryToMemory + value: 0 + - description: Memory-to-memory with PFC (FG fetch only with FG PFC active) + name: MemoryToMemoryPFC + value: 1 + - description: Memory-to-memory with blending (FG and BG fetch with PFC and blending) + name: MemoryToMemoryPFCBlending + value: 2 + - description: Register-to-memory + name: RegisterToMemory + value: 3 +enum/OPFCCR_CM: + bit_size: 3 + variants: + - description: ARGB8888 + name: ARGB8888 + value: 0 + - description: RGB888 + name: RGB888 + value: 1 + - description: RGB565 + name: RGB565 + value: 2 + - description: ARGB1555 + name: ARGB1555 + value: 3 + - description: ARGB4444 + name: ARGB4444 + value: 4 +enum/SUSP: + bit_size: 1 + variants: + - description: Transfer not suspended + name: NotSuspended + value: 0 + - description: Transfer suspended + name: Suspended + value: 1 +enum/TCIE: + bit_size: 1 + variants: + - description: TC interrupt disabled + name: Disabled + value: 0 + - description: TC interrupt enabled + name: Enabled + value: 1 +enum/TEIE: + bit_size: 1 + variants: + - description: TE interrupt disabled + name: Disabled + value: 0 + - description: TE interrupt enabled + name: Enabled + value: 1 +enum/TWIE: + bit_size: 1 + variants: + - description: TW interrupt disabled + name: Disabled + value: 0 + - description: TW interrupt enabled + name: Enabled + value: 1 +fieldset/AMTCR: + description: AHB master timer configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Enable + enum: EN + name: EN + - bit_offset: 8 + bit_size: 8 + description: Dead Time + name: DT +fieldset/BGCLUT: + description: BGCLUT + fields: + - bit_offset: 0 + bit_size: 8 + description: BLUE + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: GREEN + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: RED + name: RED + - bit_offset: 24 + bit_size: 8 + description: APLHA + name: APLHA +fieldset/BGCMAR: + description: background CLUT memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory address + name: MA +fieldset/BGCOLR: + description: background color register + fields: + - bit_offset: 0 + bit_size: 8 + description: Blue Value + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: Green Value + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: Red Value + name: RED +fieldset/BGMAR: + description: background memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory address + name: MA +fieldset/BGOR: + description: background offset register + fields: + - bit_offset: 0 + bit_size: 14 + description: Line offset + name: LO +fieldset/BGPFCCR: + description: background PFC control register + fields: + - bit_offset: 0 + bit_size: 4 + description: Color mode + enum: BGPFCCR_CM + name: CM + - bit_offset: 4 + bit_size: 1 + description: CLUT Color mode + enum: BGPFCCR_CCM + name: CCM + - bit_offset: 5 + bit_size: 1 + description: Start + enum: BGPFCCR_START + name: START + - bit_offset: 8 + bit_size: 8 + description: CLUT size + name: CS + - bit_offset: 16 + bit_size: 2 + description: Alpha mode + enum: BGPFCCR_AM + name: AM + - bit_offset: 24 + bit_size: 8 + description: Alpha value + name: ALPHA +fieldset/CR: + description: control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Start + enum: CR_START + name: START + - bit_offset: 1 + bit_size: 1 + description: Suspend + enum: SUSP + name: SUSP + - bit_offset: 2 + bit_size: 1 + description: Abort + enum: ABORT + name: ABORT + - bit_offset: 8 + bit_size: 1 + description: Transfer error interrupt enable + enum: TEIE + name: TEIE + - bit_offset: 9 + bit_size: 1 + description: Transfer complete interrupt enable + enum: TCIE + name: TCIE + - bit_offset: 10 + bit_size: 1 + description: Transfer watermark interrupt enable + enum: TWIE + name: TWIE + - bit_offset: 11 + bit_size: 1 + description: CLUT access error interrupt enable + enum: CAEIE + name: CAEIE + - bit_offset: 12 + bit_size: 1 + description: CLUT transfer complete interrupt enable + enum: CTCIE + name: CTCIE + - bit_offset: 13 + bit_size: 1 + description: Configuration Error Interrupt Enable + enum: CEIE + name: CEIE + - bit_offset: 16 + bit_size: 2 + description: DMA2D mode + enum: MODE + name: MODE +fieldset/FGCLUT: + description: FGCLUT + fields: + - bit_offset: 0 + bit_size: 8 + description: BLUE + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: GREEN + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: RED + name: RED + - bit_offset: 24 + bit_size: 8 + description: APLHA + name: APLHA +fieldset/FGCMAR: + description: foreground CLUT memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory Address + name: MA +fieldset/FGCOLR: + description: foreground color register + fields: + - bit_offset: 0 + bit_size: 8 + description: Blue Value + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: Green Value + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: Red Value + name: RED +fieldset/FGMAR: + description: foreground memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory address + name: MA +fieldset/FGOR: + description: foreground offset register + fields: + - bit_offset: 0 + bit_size: 14 + description: Line offset + name: LO +fieldset/FGPFCCR: + description: foreground PFC control register + fields: + - bit_offset: 0 + bit_size: 4 + description: Color mode + enum: FGPFCCR_CM + name: CM + - bit_offset: 4 + bit_size: 1 + description: CLUT color mode + enum: FGPFCCR_CCM + name: CCM + - bit_offset: 5 + bit_size: 1 + description: Start + enum: FGPFCCR_START + name: START + - bit_offset: 8 + bit_size: 8 + description: CLUT size + name: CS + - bit_offset: 16 + bit_size: 2 + description: Alpha mode + enum: FGPFCCR_AM + name: AM + - bit_offset: 24 + bit_size: 8 + description: Alpha value + name: ALPHA +fieldset/IFCR: + description: interrupt flag clear register + fields: + - bit_offset: 0 + bit_size: 1 + description: Clear Transfer error interrupt flag + enum: CTEIF + name: CTEIF + - bit_offset: 1 + bit_size: 1 + description: Clear transfer complete interrupt flag + enum: CTCIF + name: CTCIF + - bit_offset: 2 + bit_size: 1 + description: Clear transfer watermark interrupt flag + enum: CTWIF + name: CTWIF + - bit_offset: 3 + bit_size: 1 + description: Clear CLUT access error interrupt flag + enum: CAECIF + name: CAECIF + - bit_offset: 4 + bit_size: 1 + description: Clear CLUT transfer complete interrupt flag + enum: CCTCIF + name: CCTCIF + - bit_offset: 5 + bit_size: 1 + description: Clear configuration error interrupt flag + enum: CCEIF + name: CCEIF +fieldset/ISR: + description: Interrupt Status Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Transfer error interrupt flag + name: TEIF + - bit_offset: 1 + bit_size: 1 + description: Transfer complete interrupt flag + name: TCIF + - bit_offset: 2 + bit_size: 1 + description: Transfer watermark interrupt flag + name: TWIF + - bit_offset: 3 + bit_size: 1 + description: CLUT access error interrupt flag + name: CAEIF + - bit_offset: 4 + bit_size: 1 + description: CLUT transfer complete interrupt flag + name: CTCIF + - bit_offset: 5 + bit_size: 1 + description: Configuration error interrupt flag + name: CEIF +fieldset/LWR: + description: line watermark register + fields: + - bit_offset: 0 + bit_size: 16 + description: Line watermark + name: LW +fieldset/NLR: + description: number of line register + fields: + - bit_offset: 0 + bit_size: 16 + description: Number of lines + name: NL + - bit_offset: 16 + bit_size: 14 + description: Pixel per lines + name: PL +fieldset/OCOLR: + description: output color register + fields: + - bit_offset: 0 + bit_size: 8 + description: Blue Value + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: Green Value + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: Red Value + name: RED + - bit_offset: 24 + bit_size: 8 + description: Alpha Channel Value + name: APLHA +fieldset/OMAR: + description: output memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory Address + name: MA +fieldset/OOR: + description: output offset register + fields: + - bit_offset: 0 + bit_size: 14 + description: Line Offset + name: LO +fieldset/OPFCCR: + description: output PFC control register + fields: + - bit_offset: 0 + bit_size: 3 + description: Color mode + enum: OPFCCR_CM + name: CM diff --git a/data/registers/dma2d_v2.yaml b/data/registers/dma2d_v2.yaml new file mode 100644 index 0000000..a48a27b --- /dev/null +++ b/data/registers/dma2d_v2.yaml @@ -0,0 +1,919 @@ +block/DMA2D: + description: DMA2D + items: + - byte_offset: 0 + description: DMA2D control register + fieldset: CR + name: CR + - access: Read + byte_offset: 4 + description: DMA2D Interrupt Status Register + fieldset: ISR + name: ISR + - byte_offset: 8 + description: DMA2D interrupt flag clear register + fieldset: IFCR + name: IFCR + - byte_offset: 12 + description: DMA2D foreground memory address register + fieldset: FGMAR + name: FGMAR + - byte_offset: 16 + description: DMA2D foreground offset register + fieldset: FGOR + name: FGOR + - byte_offset: 20 + description: DMA2D background memory address register + fieldset: BGMAR + name: BGMAR + - byte_offset: 24 + description: DMA2D background offset register + fieldset: BGOR + name: BGOR + - byte_offset: 28 + description: DMA2D foreground PFC control register + fieldset: FGPFCCR + name: FGPFCCR + - byte_offset: 32 + description: DMA2D foreground color register + fieldset: FGCOLR + name: FGCOLR + - byte_offset: 36 + description: DMA2D background PFC control register + fieldset: BGPFCCR + name: BGPFCCR + - byte_offset: 40 + description: DMA2D background color register + fieldset: BGCOLR + name: BGCOLR + - byte_offset: 44 + description: DMA2D foreground CLUT memory address register + fieldset: FGCMAR + name: FGCMAR + - byte_offset: 48 + description: DMA2D background CLUT memory address register + fieldset: BGCMAR + name: BGCMAR + - byte_offset: 52 + description: DMA2D output PFC control register + fieldset: OPFCCR + name: OPFCCR + - byte_offset: 56 + description: DMA2D output color register + fieldset: OCOLR + name: OCOLR + - byte_offset: 60 + description: DMA2D output memory address register + fieldset: OMAR + name: OMAR + - byte_offset: 64 + description: DMA2D output offset register + fieldset: OOR + name: OOR + - byte_offset: 68 + description: DMA2D number of line register + fieldset: NLR + name: NLR + - byte_offset: 72 + description: DMA2D line watermark register + fieldset: LWR + name: LWR + - byte_offset: 76 + description: DMA2D AXI master timer configuration register + fieldset: AMTCR + name: AMTCR +enum/ABORT: + bit_size: 1 + variants: + - description: Transfer abort requested + name: AbortRequest + value: 1 +enum/BGPFCCR_AI: + bit_size: 1 + variants: + - description: Regular alpha + name: RegularAlpha + value: 0 + - description: Inverted alpha + name: InvertedAlpha + value: 1 +enum/BGPFCCR_AM: + bit_size: 2 + variants: + - description: No modification of alpha channel + name: NoModify + value: 0 + - description: Replace with value in ALPHA[7:0] + name: Replace + value: 1 + - description: Multiply with value in ALPHA[7:0] + name: Multiply + value: 2 +enum/BGPFCCR_CCM: + bit_size: 1 + variants: + - description: CLUT color format ARGB8888 + name: ARGB8888 + value: 0 + - description: CLUT color format RGB888 + name: RGB888 + value: 1 +enum/BGPFCCR_CM: + bit_size: 4 + variants: + - description: Color mode ARGB8888 + name: ARGB8888 + value: 0 + - description: Color mode RGB888 + name: RGB888 + value: 1 + - description: Color mode RGB565 + name: RGB565 + value: 2 + - description: Color mode ARGB1555 + name: ARGB1555 + value: 3 + - description: Color mode ARGB4444 + name: ARGB4444 + value: 4 + - description: Color mode L8 + name: L8 + value: 5 + - description: Color mode AL44 + name: AL44 + value: 6 + - description: Color mode AL88 + name: AL88 + value: 7 + - description: Color mode L4 + name: L4 + value: 8 + - description: Color mode A8 + name: A8 + value: 9 + - description: Color mode A4 + name: A4 + value: 10 +enum/BGPFCCR_RBS: + bit_size: 1 + variants: + - description: No Red Blue Swap (RGB or ARGB) + name: Regular + value: 0 + - description: Red Blue Swap (BGR or ABGR) + name: Swap + value: 1 +enum/BGPFCCR_START: + bit_size: 1 + variants: + - description: Start the automatic loading of the CLUT + name: Start + value: 1 +enum/CAECIF: + bit_size: 1 + variants: + - description: Clear the CAEIF flag in the ISR register + name: Clear + value: 1 +enum/CAEIE: + bit_size: 1 + variants: + - description: CAE interrupt disabled + name: Disabled + value: 0 + - description: CAE interrupt enabled + name: Enabled + value: 1 +enum/CCEIF: + bit_size: 1 + variants: + - description: Clear the CEIF flag in the ISR register + name: Clear + value: 1 +enum/CCTCIF: + bit_size: 1 + variants: + - description: Clear the CTCIF flag in the ISR register + name: Clear + value: 1 +enum/CEIE: + bit_size: 1 + variants: + - description: CE interrupt disabled + name: Disabled + value: 0 + - description: CE interrupt enabled + name: Enabled + value: 1 +enum/CR_START: + bit_size: 1 + variants: + - description: Launch the DMA2D + name: Start + value: 1 +enum/CTCIE: + bit_size: 1 + variants: + - description: CTC interrupt disabled + name: Disabled + value: 0 + - description: CTC interrupt enabled + name: Enabled + value: 1 +enum/CTCIF: + bit_size: 1 + variants: + - description: Clear the TCIF flag in the ISR register + name: Clear + value: 1 +enum/CTEIF: + bit_size: 1 + variants: + - description: Clear the TEIF flag in the ISR register + name: Clear + value: 1 +enum/CTWIF: + bit_size: 1 + variants: + - description: Clear the TWIF flag in the ISR register + name: Clear + value: 1 +enum/EN: + bit_size: 1 + variants: + - description: Disabled AHB/AXI dead-time functionality + name: Disabled + value: 0 + - description: Enabled AHB/AXI dead-time functionality + name: Enabled + value: 1 +enum/FGPFCCR_AI: + bit_size: 1 + variants: + - description: Regular alpha + name: RegularAlpha + value: 0 + - description: Inverted alpha + name: InvertedAlpha + value: 1 +enum/FGPFCCR_AM: + bit_size: 2 + variants: + - description: No modification of alpha channel + name: NoModify + value: 0 + - description: Replace with value in ALPHA[7:0] + name: Replace + value: 1 + - description: Multiply with value in ALPHA[7:0] + name: Multiply + value: 2 +enum/FGPFCCR_CCM: + bit_size: 1 + variants: + - description: CLUT color format ARGB8888 + name: ARGB8888 + value: 0 + - description: CLUT color format RGB888 + name: RGB888 + value: 1 +enum/FGPFCCR_CM: + bit_size: 4 + variants: + - description: Color mode ARGB8888 + name: ARGB8888 + value: 0 + - description: Color mode RGB888 + name: RGB888 + value: 1 + - description: Color mode RGB565 + name: RGB565 + value: 2 + - description: Color mode ARGB1555 + name: ARGB1555 + value: 3 + - description: Color mode ARGB4444 + name: ARGB4444 + value: 4 + - description: Color mode L8 + name: L8 + value: 5 + - description: Color mode AL44 + name: AL44 + value: 6 + - description: Color mode AL88 + name: AL88 + value: 7 + - description: Color mode L4 + name: L4 + value: 8 + - description: Color mode A8 + name: A8 + value: 9 + - description: Color mode A4 + name: A4 + value: 10 + - description: Color mode YCbCr + name: YCbCr + value: 11 +enum/FGPFCCR_RBS: + bit_size: 1 + variants: + - description: No Red Blue Swap (RGB or ARGB) + name: Regular + value: 0 + - description: Red Blue Swap (BGR or ABGR) + name: Swap + value: 1 +enum/FGPFCCR_START: + bit_size: 1 + variants: + - description: Start the automatic loading of the CLUT + name: Start + value: 1 +enum/MODE: + bit_size: 2 + variants: + - description: Memory-to-memory (FG fetch only) + name: MemoryToMemory + value: 0 + - description: Memory-to-memory with PFC (FG fetch only with FG PFC active) + name: MemoryToMemoryPFC + value: 1 + - description: Memory-to-memory with blending (FG and BG fetch with PFC and blending) + name: MemoryToMemoryPFCBlending + value: 2 + - description: Register-to-memory + name: RegisterToMemory + value: 3 +enum/OPFCCR_AI: + bit_size: 1 + variants: + - description: Regular alpha + name: RegularAlpha + value: 0 + - description: Inverted alpha + name: InvertedAlpha + value: 1 +enum/OPFCCR_CM: + bit_size: 3 + variants: + - description: ARGB8888 + name: ARGB8888 + value: 0 + - description: RGB888 + name: RGB888 + value: 1 + - description: RGB565 + name: RGB565 + value: 2 + - description: ARGB1555 + name: ARGB1555 + value: 3 + - description: ARGB4444 + name: ARGB4444 + value: 4 +enum/OPFCCR_RBS: + bit_size: 1 + variants: + - description: No Red Blue Swap (RGB or ARGB) + name: Regular + value: 0 + - description: Red Blue Swap (BGR or ABGR) + name: Swap + value: 1 +enum/SB: + bit_size: 1 + variants: + - description: Regular byte order + name: Regular + value: 0 + - description: Bytes are swapped two by two + name: SwapBytes + value: 1 +enum/SUSP: + bit_size: 1 + variants: + - description: Transfer not suspended + name: NotSuspended + value: 0 + - description: Transfer suspended + name: Suspended + value: 1 +enum/TCIE: + bit_size: 1 + variants: + - description: TC interrupt disabled + name: Disabled + value: 0 + - description: TC interrupt enabled + name: Enabled + value: 1 +enum/TEIE: + bit_size: 1 + variants: + - description: TE interrupt disabled + name: Disabled + value: 0 + - description: TE interrupt enabled + name: Enabled + value: 1 +enum/TWIE: + bit_size: 1 + variants: + - description: TW interrupt disabled + name: Disabled + value: 0 + - description: TW interrupt enabled + name: Enabled + value: 1 +fieldset/AMTCR: + description: DMA2D AXI master timer configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Enable Enables the dead time functionality. + enum: EN + name: EN + - bit_offset: 8 + bit_size: 8 + description: Dead Time Dead time value in the AXI clock cycle inserted between + two consecutive accesses on the AXI master port. These bits represent the minimum + guaranteed number of cycles between two consecutive AXI accesses. + name: DT +fieldset/BGCMAR: + description: DMA2D background CLUT memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory address Address of the data used for the CLUT address dedicated + to the background image. This register can only be written when no transfer + is on going. Once the CLUT transfer has started, this register is read-only. + If the background CLUT format is 32-bit, the address must be 32-bit aligned. + name: MA +fieldset/BGCOLR: + description: DMA2D background color register + fields: + - bit_offset: 0 + bit_size: 8 + description: Blue Value These bits define the blue value for the A4 or A8 mode + of the background. These bits can only be written when data transfers are disabled. + Once the transfer has started, they are read-only. + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: Green Value These bits define the green value for the A4 or A8 mode + of the background. These bits can only be written when data transfers are disabled. + Once the transfer has started, they are read-only. + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: Red Value These bits define the red value for the A4 or A8 mode of + the background. These bits can only be written when data transfers are disabled. + Once the transfer has started, they are read-only. + name: RED +fieldset/BGMAR: + description: DMA2D background memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory address Address of the data used for the background image. + This register can only be written when data transfers are disabled. Once a data + transfer has started, this register is read-only. The address alignment must + match the image format selected e.g. a 32-bit per pixel format must be 32-bit + aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel + format must be 8-bit aligned. + name: MA +fieldset/BGOR: + description: DMA2D background offset register + fields: + - bit_offset: 0 + bit_size: 16 + description: Line offset Line offset used for the background image (expressed + in pixel). This value is used for the address generation. It is added at the + end of each line to determine the starting address of the next line. These bits + can only be written when data transfers are disabled. Once data transfer has + started, they become read-only. If the image format is 4-bit per pixel, the + line offset must be even. + name: LO +fieldset/BGPFCCR: + description: DMA2D background PFC control register + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Color mode These bits define the color format of the foreground + image. These bits can only be written when data transfers are disabled. Once + the transfer has started, they are read-only. others: meaningless' + enum: BGPFCCR_CM + name: CM + - bit_offset: 4 + bit_size: 1 + description: CLUT Color mode These bits define the color format of the CLUT. This + register can only be written when the transfer is disabled. Once the CLUT transfer + has started, this bit is read-only. + enum: BGPFCCR_CCM + name: CCM + - bit_offset: 5 + bit_size: 1 + description: 'Start This bit is set to start the automatic loading of the CLUT. + This bit is automatically reset: ** at the end of the transfer ** when the transfer + is aborted by the user application by setting the ABORT bit in the DMA2D_CR + ** when a transfer error occurs ** when the transfer has not started due to + a configuration error or another transfer operation already on going (data transfer + or automatic BackGround CLUT transfer).' + enum: BGPFCCR_START + name: START + - bit_offset: 8 + bit_size: 8 + description: CLUT size These bits define the size of the CLUT used for the BG. + Once the CLUT transfer has started, this field is read-only. The number of CLUT + entries is equal to CS[7:0] + 1. + name: CS + - bit_offset: 16 + bit_size: 2 + description: 'Alpha mode These bits define which alpha channel value to be used + for the background image. These bits can only be written when data transfers + are disabled. Once the transfer has started, they are read-only. others: meaningless' + enum: BGPFCCR_AM + name: AM + - bit_offset: 20 + bit_size: 1 + description: Alpha Inverted This bit inverts the alpha value. Once the transfer + has started, this bit is read-only. + enum: BGPFCCR_AI + name: AI + - bit_offset: 21 + bit_size: 1 + description: Red Blue Swap This bit allows to swap the R & B to support BGR + or ABGR color formats. Once the transfer has started, this bit is read-only. + enum: BGPFCCR_RBS + name: RBS + - bit_offset: 24 + bit_size: 8 + description: 'Alpha value These bits define a fixed alpha channel value which + can replace the original alpha value or be multiplied with the original alpha + value according to the alpha mode selected with bits AM[1: 0]. These bits can + only be written when data transfers are disabled. Once the transfer has started, + they are read-only.' + name: ALPHA +fieldset/CR: + description: DMA2D control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Start This bit can be used to launch the DMA2D according to the parameters + loaded in the various configuration registers + enum: CR_START + name: START + - bit_offset: 1 + bit_size: 1 + description: Suspend This bit can be used to suspend the current transfer. This + bit is set and reset by software. It is automatically reset by hardware when + the START bit is reset. + enum: SUSP + name: SUSP + - bit_offset: 2 + bit_size: 1 + description: Abort This bit can be used to abort the current transfer. This bit + is set by software and is automatically reset by hardware when the START bit + is reset. + enum: ABORT + name: ABORT + - bit_offset: 8 + bit_size: 1 + description: Transfer error interrupt enable This bit is set and cleared by software. + enum: TEIE + name: TEIE + - bit_offset: 9 + bit_size: 1 + description: Transfer complete interrupt enable This bit is set and cleared by + software. + enum: TCIE + name: TCIE + - bit_offset: 10 + bit_size: 1 + description: Transfer watermark interrupt enable This bit is set and cleared by + software. + enum: TWIE + name: TWIE + - bit_offset: 11 + bit_size: 1 + description: CLUT access error interrupt enable This bit is set and cleared by + software. + enum: CAEIE + name: CAEIE + - bit_offset: 12 + bit_size: 1 + description: CLUT transfer complete interrupt enable This bit is set and cleared + by software. + enum: CTCIE + name: CTCIE + - bit_offset: 13 + bit_size: 1 + description: Configuration Error Interrupt Enable This bit is set and cleared + by software. + enum: CEIE + name: CEIE + - bit_offset: 16 + bit_size: 2 + description: DMA2D mode This bit is set and cleared by software. It cannot be + modified while a transfer is ongoing. + enum: MODE + name: MODE +fieldset/FGCMAR: + description: DMA2D foreground CLUT memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory Address Address of the data used for the CLUT address dedicated + to the foreground image. This register can only be written when no transfer + is ongoing. Once the CLUT transfer has started, this register is read-only. + If the foreground CLUT format is 32-bit, the address must be 32-bit aligned. + name: MA +fieldset/FGCOLR: + description: DMA2D foreground color register + fields: + - bit_offset: 0 + bit_size: 8 + description: Blue Value These bits defines the blue value for the A4 or A8 mode + of the foreground image. They can only be written when data transfers are disabled. + Once the transfer has started, They are read-only. + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: Green Value These bits defines the green value for the A4 or A8 mode + of the foreground image. They can only be written when data transfers are disabled. + Once the transfer has started, They are read-only. + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: Red Value These bits defines the red value for the A4 or A8 mode + of the foreground image. They can only be written when data transfers are disabled. + Once the transfer has started, they are read-only. + name: RED +fieldset/FGMAR: + description: DMA2D foreground memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory address Address of the data used for the foreground image. + This register can only be written when data transfers are disabled. Once the + data transfer has started, this register is read-only. The address alignment + must match the image format selected e.g. a 32-bit per pixel format must be + 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit + per pixel format must be 8-bit aligned. + name: MA +fieldset/FGOR: + description: DMA2D foreground offset register + fields: + - bit_offset: 0 + bit_size: 16 + description: Line offset Line offset used for the foreground expressed in pixel. + This value is used to generate the address. It is added at the end of each line + to determine the starting address of the next line. These bits can only be written + when data transfers are disabled. Once a data transfer has started, they become + read-only. If the image format is 4-bit per pixel, the line offset must be even. + name: LO +fieldset/FGPFCCR: + description: DMA2D foreground PFC control register + fields: + - bit_offset: 0 + bit_size: 4 + description: 'Color mode These bits defines the color format of the foreground + image. They can only be written when data transfers are disabled. Once the transfer + has started, they are read-only. others: meaningless' + enum: FGPFCCR_CM + name: CM + - bit_offset: 4 + bit_size: 1 + description: CLUT color mode This bit defines the color format of the CLUT. It + can only be written when the transfer is disabled. Once the CLUT transfer has + started, this bit is read-only. + enum: FGPFCCR_CCM + name: CCM + - bit_offset: 5 + bit_size: 1 + description: 'Start This bit can be set to start the automatic loading of the + CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer + is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when + a transfer error occurs ** when the transfer has not started due to a configuration + error or another transfer operation already ongoing (data transfer or automatic + background CLUT transfer).' + enum: FGPFCCR_START + name: START + - bit_offset: 8 + bit_size: 8 + description: CLUT size These bits define the size of the CLUT used for the foreground + image. Once the CLUT transfer has started, this field is read-only. The number + of CLUT entries is equal to CS[7:0] + 1. + name: CS + - bit_offset: 16 + bit_size: 2 + description: Alpha mode These bits select the alpha channel value to be used for + the foreground image. They can only be written data the transfer are disabled. + Once the transfer has started, they become read-only. other configurations are + meaningless + enum: FGPFCCR_AM + name: AM + - bit_offset: 18 + bit_size: 2 + description: 'Chroma Sub-Sampling These bits define the chroma sub-sampling mode + for YCbCr color mode. Once the transfer has started, these bits are read-only. + others: meaningless' + name: CSS + - bit_offset: 20 + bit_size: 1 + description: Alpha Inverted This bit inverts the alpha value. Once the transfer + has started, this bit is read-only. + enum: FGPFCCR_AI + name: AI + - bit_offset: 21 + bit_size: 1 + description: Red Blue Swap This bit allows to swap the R & B to support BGR + or ABGR color formats. Once the transfer has started, this bit is read-only. + enum: FGPFCCR_RBS + name: RBS + - bit_offset: 24 + bit_size: 8 + description: Alpha value These bits define a fixed alpha channel value which can + replace the original alpha value or be multiplied by the original alpha value + according to the alpha mode selected through the AM[1:0] bits. These bits can + only be written when data transfers are disabled. Once a transfer has started, + they become read-only. + name: ALPHA +fieldset/IFCR: + description: DMA2D interrupt flag clear register + fields: + - bit_offset: 0 + bit_size: 1 + description: Clear Transfer error interrupt flag Programming this bit to 1 clears + the TEIF flag in the DMA2D_ISR register + enum: CTEIF + name: CTEIF + - bit_offset: 1 + bit_size: 1 + description: Clear transfer complete interrupt flag Programming this bit to 1 + clears the TCIF flag in the DMA2D_ISR register + enum: CTCIF + name: CTCIF + - bit_offset: 2 + bit_size: 1 + description: Clear transfer watermark interrupt flag Programming this bit to 1 + clears the TWIF flag in the DMA2D_ISR register + enum: CTWIF + name: CTWIF + - bit_offset: 3 + bit_size: 1 + description: Clear CLUT access error interrupt flag Programming this bit to 1 + clears the CAEIF flag in the DMA2D_ISR register + enum: CAECIF + name: CAECIF + - bit_offset: 4 + bit_size: 1 + description: Clear CLUT transfer complete interrupt flag Programming this bit + to 1 clears the CTCIF flag in the DMA2D_ISR register + enum: CCTCIF + name: CCTCIF + - bit_offset: 5 + bit_size: 1 + description: Clear configuration error interrupt flag Programming this bit to + 1 clears the CEIF flag in the DMA2D_ISR register + enum: CCEIF + name: CCEIF +fieldset/ISR: + description: DMA2D Interrupt Status Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Transfer error interrupt flag This bit is set when an error occurs + during a DMA transfer (data transfer or automatic CLUT loading). + name: TEIF + - bit_offset: 1 + bit_size: 1 + description: Transfer complete interrupt flag This bit is set when a DMA2D transfer + operation is complete (data transfer only). + name: TCIF + - bit_offset: 2 + bit_size: 1 + description: Transfer watermark interrupt flag This bit is set when the last pixel + of the watermarked line has been transferred. + name: TWIF + - bit_offset: 3 + bit_size: 1 + description: CLUT access error interrupt flag This bit is set when the CPU accesses + the CLUT while the CLUT is being automatically copied from a system memory to + the internal DMA2D. + name: CAEIF + - bit_offset: 4 + bit_size: 1 + description: CLUT transfer complete interrupt flag This bit is set when the CLUT + copy from a system memory area to the internal DMA2D memory is complete. + name: CTCIF + - bit_offset: 5 + bit_size: 1 + description: Configuration error interrupt flag This bit is set when the START + bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration + has been programmed. + name: CEIF +fieldset/LWR: + description: DMA2D line watermark register + fields: + - bit_offset: 0 + bit_size: 16 + description: Line watermark These bits allow to configure the line watermark for + interrupt generation. An interrupt is raised when the last pixel of the watermarked + line has been transferred. These bits can only be written when data transfers + are disabled. Once the transfer has started, they are read-only. + name: LW +fieldset/NLR: + description: DMA2D number of line register + fields: + - bit_offset: 0 + bit_size: 16 + description: Number of lines Number of lines of the area to be transferred. These + bits can only be written when data transfers are disabled. Once the transfer + has started, they are read-only. + name: NL + - bit_offset: 16 + bit_size: 14 + description: Pixel per lines Number of pixels per lines of the area to be transferred. + These bits can only be written when data transfers are disabled. Once the transfer + has started, they are read-only. If any of the input image format is 4-bit per + pixel, pixel per lines must be even. + name: PL +fieldset/OCOLR: + description: DMA2D output color register + fields: + - bit_offset: 0 + bit_size: 8 + description: Blue Value These bits define the blue value of the output image. + These bits can only be written when data transfers are disabled. Once the transfer + has started, they are read-only. + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: Green Value These bits define the green value of the output image. + These bits can only be written when data transfers are disabled. Once the transfer + has started, they are read-only. + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: Red Value These bits define the red value of the output image. These + bits can only be written when data transfers are disabled. Once the transfer + has started, they are read-only. + name: RED + - bit_offset: 24 + bit_size: 8 + description: Alpha Channel Value These bits define the alpha channel of the output + color. These bits can only be written when data transfers are disabled. Once + the transfer has started, they are read-only. + name: ALPHA +fieldset/OMAR: + description: DMA2D output memory address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Memory Address Address of the data used for the output FIFO. These + bits can only be written when data transfers are disabled. Once the transfer + has started, they are read-only. The address alignment must match the image + format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a + 16-bit per pixel format must be 16-bit aligned. + name: MA +fieldset/OOR: + description: DMA2D output offset register + fields: + - bit_offset: 0 + bit_size: 16 + description: Line Offset Line offset used for the output (expressed in pixels). + This value is used for the address generation. It is added at the end of each + line to determine the starting address of the next line. These bits can only + be written when data transfers are disabled. Once the transfer has started, + they are read-only. + name: LO +fieldset/OPFCCR: + description: DMA2D output PFC control register + fields: + - bit_offset: 0 + bit_size: 3 + description: 'Color mode These bits define the color format of the output image. + These bits can only be written when data transfers are disabled. Once the transfer + has started, they are read-only. others: meaningless' + enum: OPFCCR_CM + name: CM + - bit_offset: 8 + bit_size: 1 + description: Swap Bytes + enum: SB + name: SB + - bit_offset: 20 + bit_size: 1 + description: Alpha Inverted This bit inverts the alpha value. Once the transfer + has started, this bit is read-only. + enum: OPFCCR_AI + name: AI + - bit_offset: 21 + bit_size: 1 + description: Red Blue Swap This bit allows to swap the R & B to support BGR + or ABGR color formats. Once the transfer has started, this bit is read-only. + enum: OPFCCR_RBS + name: RBS diff --git a/data/registers/eth_v1c.yaml b/data/registers/eth_v1c.yaml new file mode 100644 index 0000000..e757089 --- /dev/null +++ b/data/registers/eth_v1c.yaml @@ -0,0 +1,1025 @@ +--- +block/ETH: + description: 'Ethernet: media access control (MAC)' + items: + - byte_offset: 0 + description: Ethernet MAC configuration register + fieldset: MACCR + name: MACCR + - byte_offset: 4 + description: Ethernet MAC frame filter register + fieldset: MACFFR + name: MACFFR + - byte_offset: 8 + description: Ethernet MAC hash table high register + fieldset: MACHTHR + name: MACHTHR + - byte_offset: 12 + description: Ethernet MAC hash table low register + fieldset: MACHTLR + name: MACHTLR + - byte_offset: 16 + description: Ethernet MAC MII address register + fieldset: MACMIIAR + name: MACMIIAR + - byte_offset: 20 + description: Ethernet MAC MII data register + fieldset: MACMIIDR + name: MACMIIDR + - byte_offset: 24 + description: Ethernet MAC flow control register + fieldset: MACFCR + name: MACFCR + - byte_offset: 28 + description: Ethernet MAC VLAN tag register + fieldset: MACVLANTR + name: MACVLANTR + - byte_offset: 44 + description: Ethernet MAC PMT control and status register + fieldset: MACPMTCSR + name: MACPMTCSR + - access: Read + byte_offset: 52 + description: Ethernet MAC debug register + fieldset: MACDBGR + name: MACDBGR + - byte_offset: 56 + description: Ethernet MAC interrupt status register + fieldset: MACSR + name: MACSR + - byte_offset: 60 + description: Ethernet MAC interrupt mask register + fieldset: MACIMR + name: MACIMR + - byte_offset: 64 + description: Ethernet MAC address 0 high register + fieldset: MACA0HR + name: MACA0HR + - byte_offset: 68 + description: Ethernet MAC address 0 low register + fieldset: MACA0LR + name: MACA0LR + - byte_offset: 72 + description: Ethernet MAC address 1 high register + fieldset: MACA1HR + name: MACA1HR + - byte_offset: 76 + description: Ethernet MAC address1 low register + fieldset: MACA1LR + name: MACA1LR + - byte_offset: 80 + description: Ethernet MAC address 2 high register + fieldset: MACA2HR + name: MACA2HR + - byte_offset: 84 + description: Ethernet MAC address 2 low register + fieldset: MACA2LR + name: MACA2LR + - byte_offset: 88 + description: Ethernet MAC address 3 high register + fieldset: MACA3HR + name: MACA3HR + - byte_offset: 92 + description: Ethernet MAC address 3 low register + fieldset: MACA3LR + name: MACA3LR + - byte_offset: 96 + description: Ethernet MAC remote wakeup frame filter register + name: MACRWUFFER +enum/APCS: + bit_size: 1 + variants: + - description: MAC passes all incoming frames unmodified + name: Disabled + value: 0 + - description: MAC strips the Pad/FCS field on incoming frames only for lengths + less than or equal to 1500 bytes + name: Strip + value: 1 +enum/BFD: + bit_size: 1 + variants: + - description: Address filters pass all received broadcast frames + name: Enabled + value: 0 + - description: Address filters filter all incoming broadcast frames + name: Disabled + value: 1 +enum/BL: + bit_size: 2 + variants: + - description: For retransmission n, wait up to 2^min(n, 10) time slots + name: BL10 + value: 0 + - description: For retransmission n, wait up to 2^min(n, 8) time slots + name: BL8 + value: 1 + - description: For retransmission n, wait up to 2^min(n, 4) time slots + name: BL4 + value: 2 + - description: For retransmission n, wait up to 2^min(n, 1) time slots + name: BL1 + value: 3 +enum/CR: + bit_size: 3 + variants: + - description: 60-100MHz HCLK/42 + name: CR_60_100 + value: 0 + - description: 100-150 MHz HCLK/62 + name: CR_100_150 + value: 1 + - description: 20-35MHz HCLK/16 + name: CR_20_35 + value: 2 + - description: 35-60MHz HCLK/16 + name: CR_35_60 + value: 3 + - description: 150-168MHz HCLK/102 + name: CR_150_168 + value: 4 +enum/CSD: + bit_size: 1 + variants: + - description: Errors generated due to loss of carrier + name: Enabled + value: 0 + - description: No error generated due to loss of carrier + name: Disabled + value: 1 +enum/CSTF: + bit_size: 1 + variants: + - description: CRC not stripped + name: Disabled + value: 0 + - description: CRC stripped + name: Enabled + value: 1 +enum/DAIF: + bit_size: 1 + variants: + - description: Normal filtering of frames + name: Normal + value: 0 + - description: Address check block operates in inverse filtering mode for the DA + address comparison + name: Invert + value: 1 +enum/DC: + bit_size: 1 + variants: + - description: MAC defers until CRS signal goes inactive + name: Disabled + value: 0 + - description: Deferral check function enabled + name: Enabled + value: 1 +enum/DM: + bit_size: 1 + variants: + - description: MAC operates in half-duplex mode + name: HalfDuplex + value: 0 + - description: MAC operates in full-duplex mode + name: FullDuplex + value: 1 +enum/FCB: + bit_size: 1 + variants: + - description: In half duplex only, deasserts back pressure + name: DisableBackPressure + value: 0 + - description: In full duplex, initiate a Pause control frame. In half duplex, assert + back pressure + name: PauseOrBackPressure + value: 1 +enum/FES: + bit_size: 1 + variants: + - description: 10 Mbit/s + name: FES10 + value: 0 + - description: 100 Mbit/s + name: FES100 + value: 1 +enum/GU: + bit_size: 1 + variants: + - description: Normal operation + name: Disabled + value: 0 + - description: Any unicast packet filtered by the MAC address recognition may be + a wakeup frame + name: Enabled + value: 1 +enum/HM: + bit_size: 1 + variants: + - description: MAC performs a perfect destination address filtering for multicast + frames + name: Perfect + value: 0 + - description: MAC performs destination address filtering of received multicast + frames according to the hash table + name: Hash + value: 1 +enum/HPF: + bit_size: 1 + variants: + - description: If HM or HU is set, only frames that match the Hash filter are passed + name: HashOnly + value: 0 + - description: If HM or HU is set, frames that match either the perfect filter or + the hash filter are passed + name: HashOrPerfect + value: 1 +enum/HU: + bit_size: 1 + variants: + - description: MAC performs a perfect destination address filtering for unicast + frames + name: Perfect + value: 0 + - description: MAC performs destination address filtering of received unicast frames + according to the hash table + name: Hash + value: 1 +enum/IFG: + bit_size: 3 + variants: + - description: 96 bit times + name: IFG96 + value: 0 + - description: 88 bit times + name: IFG88 + value: 1 + - description: 80 bit times + name: IFG80 + value: 2 + - description: 72 bit times + name: IFG72 + value: 3 + - description: 64 bit times + name: IFG64 + value: 4 + - description: 56 bit times + name: IFG56 + value: 5 + - description: 48 bit times + name: IFG48 + value: 6 + - description: 40 bit times + name: IFG40 + value: 7 +enum/IPCO: + bit_size: 1 + variants: + - description: IPv4 checksum offload disabled + name: Disabled + value: 0 + - description: IPv4 checksums are checked in received frames + name: Offload + value: 1 +enum/JD: + bit_size: 1 + variants: + - description: Jabber enabled, transmit frames up to 2048 bytes + name: Enabled + value: 0 + - description: Jabber disabled, transmit frames up to 16384 bytes + name: Disabled + value: 1 +enum/LM: + bit_size: 1 + variants: + - description: Normal mode + name: Normal + value: 0 + - description: MAC operates in loopback mode at the MII + name: Loopback + value: 1 +enum/MACAHR_AE: + bit_size: 1 + variants: + - description: Address filters ignore this address + name: Disabled + value: 0 + - description: Address filters use this address + name: Enabled + value: 1 +enum/MACAHR_SA: + bit_size: 1 + variants: + - description: This address is used for comparison with DA fields of the received + frame + name: Destination + value: 0 + - description: This address is used for comparison with SA fields of received frames + name: Source + value: 1 +enum/MB: + bit_size: 1 + variants: + - description: This bit is set to 1 by the application to indicate that a read or + write access is in progress + name: Busy + value: 1 +enum/MPE: + bit_size: 1 + variants: + - description: No power management event generated due to Magic Packet reception + name: Disabled + value: 0 + - description: Enable generation of a power management event due to Magic Packet + reception + name: Enabled + value: 1 +enum/MW: + bit_size: 1 + variants: + - description: Read operation + name: Read + value: 0 + - description: Write operation + name: Write + value: 1 +enum/PAM: + bit_size: 1 + variants: + - description: Filtering of multicast frames depends on HM + name: Disabled + value: 0 + - description: All received frames with a multicast destination address are passed + name: Enabled + value: 1 +enum/PCF: + bit_size: 2 + variants: + - description: MAC prevents all control frames from reaching the application + name: PreventAll + value: 0 + - description: MAC forwards all control frames to application except Pause + name: ForwardAllExceptPause + value: 1 + - description: MAC forwards all control frames to application even if they fail + the address filter + name: ForwardAll + value: 2 + - description: MAC forwards control frames that pass the address filter + name: ForwardAllFiltered + value: 3 +enum/PD: + bit_size: 1 + variants: + - description: All received frames will be dropped. Cleared automatically when a + magic packet or wakeup frame is received + name: Enabled + value: 1 +enum/PLT: + bit_size: 2 + variants: + - description: Pause time minus 4 slot times + name: PLT4 + value: 0 + - description: Pause time minus 28 slot times + name: PLT28 + value: 1 + - description: Pause time minus 144 slot times + name: PLT144 + value: 2 + - description: Pause time minus 256 slot times + name: PLT256 + value: 3 +enum/PM: + bit_size: 1 + variants: + - description: Normal address filtering + name: Disabled + value: 0 + - description: Address filters pass all incoming frames regardless of their destination + or source address + name: Enabled + value: 1 +enum/PMTIM: + bit_size: 1 + variants: + - description: PMT Status interrupt generation enabled + name: Unmasked + value: 0 + - description: PMT Status interrupt generation disabled + name: Masked + value: 1 +enum/RA: + bit_size: 1 + variants: + - description: MAC receiver passes on to the application only those frames that + have passed the SA/DA address file + name: Disabled + value: 0 + - description: MAC receiver passes oll received frames on to the application + name: Enabled + value: 1 +enum/RD: + bit_size: 1 + variants: + - description: MAC attempts retries based on the settings of BL + name: Enabled + value: 0 + - description: MAC attempts only 1 transmission + name: Disabled + value: 1 +enum/RE: + bit_size: 1 + variants: + - description: MAC receive state machine is disabled after the completion of the + reception of the current frame + name: Disabled + value: 0 + - description: MAC receive state machine is enabled + name: Enabled + value: 1 +enum/RFCE: + bit_size: 1 + variants: + - description: Pause frames are not decoded + name: Disabled + value: 0 + - description: MAC decodes received Pause frames and disables its transmitted for + a specified time + name: Enabled + value: 1 +enum/ROD: + bit_size: 1 + variants: + - description: MAC receives all packets from PHY while transmitting + name: Enabled + value: 0 + - description: MAC disables reception of frames in half-duplex mode + name: Disabled + value: 1 +enum/SAF: + bit_size: 1 + variants: + - description: Source address ignored + name: Disabled + value: 0 + - description: MAC drops frames that fail the source address filter + name: Enabled + value: 1 +enum/SAIF: + bit_size: 1 + variants: + - description: Source address filter operates normally + name: Normal + value: 0 + - description: Source address filter operation inverted + name: Invert + value: 1 +enum/TE: + bit_size: 1 + variants: + - description: MAC transmit state machine is disabled after completion of the transmission + of the current frame + name: Disabled + value: 0 + - description: MAC transmit state machine is enabled + name: Enabled + value: 1 +enum/TFCE: + bit_size: 1 + variants: + - description: In full duplex, flow control is disabled. In half duplex, back pressure + is disabled + name: Disabled + value: 0 + - description: In full duplex, flow control is enabled. In half duplex, back pressure + is enabled + name: Enabled + value: 1 +enum/TSTIM: + bit_size: 1 + variants: + - description: Time stamp interrupt generation enabled + name: Unmasked + value: 0 + - description: Time stamp interrupt generation disabled + name: Masked + value: 1 +enum/UPFD: + bit_size: 1 + variants: + - description: MAC detects only a Pause frame with the multicast address specified + in the 802.3x standard + name: Disabled + value: 0 + - description: MAC additionally detects Pause frames with the station's unicast + address + name: Enabled + value: 1 +enum/VLANTC: + bit_size: 1 + variants: + - description: Full 16 bit VLAN identifiers are used for comparison and filtering + name: VLANTC16 + value: 0 + - description: 12 bit VLAN identifies are used for comparison and filtering + name: VLANTC12 + value: 1 +enum/WD: + bit_size: 1 + variants: + - description: Watchdog enabled, receive frames limited to 2048 bytes + name: Enabled + value: 0 + - description: Watchdog disabled, receive frames may be up to to 16384 bytes + name: Disabled + value: 1 +enum/WFE: + bit_size: 1 + variants: + - description: No power management event generated due to wakeup frame reception + name: Disabled + value: 0 + - description: Enable generation of a power management event due to wakeup frame + reception + name: Enabled + value: 1 +enum/WFFRPR: + bit_size: 1 + variants: + - description: Reset wakeup frame filter register point to 0b000. Automatically + cleared + name: Reset + value: 1 +enum/ZQPD: + bit_size: 1 + variants: + - description: Normal operation with automatic zero-quanta pause control frame generation + name: Enabled + value: 0 + - description: Automatic generation of zero-quanta pause control frames is disabled + name: Disabled + value: 1 +fieldset/MACA0HR: + description: Ethernet MAC address 0 high register + fields: + - bit_offset: 0 + bit_size: 16 + description: MAC address0 high + name: MACA0H + - bit_offset: 31 + bit_size: 1 + description: Always 1 + name: MO +fieldset/MACA0LR: + description: Ethernet MAC address 0 low register + fields: + - bit_offset: 0 + bit_size: 32 + description: '0' + name: MACA0L +fieldset/MACA1HR: + description: Ethernet MAC address 1 high register + fields: + - bit_offset: 0 + bit_size: 16 + description: MACA1H + name: MACA1H + - bit_offset: 24 + bit_size: 6 + description: MBC + name: MBC + - bit_offset: 30 + bit_size: 1 + description: SA + enum: MACAHR_SA + name: SA + - bit_offset: 31 + bit_size: 1 + description: AE + enum: MACAHR_AE + name: AE +fieldset/MACA1LR: + description: Ethernet MAC address1 low register + fields: + - bit_offset: 0 + bit_size: 32 + description: MACA1LR + name: MACA1L +fieldset/MACA2HR: + description: Ethernet MAC address 2 high register + fields: + - bit_offset: 0 + bit_size: 16 + description: MAC2AH + name: MACA2H + - bit_offset: 24 + bit_size: 6 + description: MBC + name: MBC + - bit_offset: 30 + bit_size: 1 + description: SA + enum: MACAHR_SA + name: SA + - bit_offset: 31 + bit_size: 1 + description: AE + enum: MACAHR_AE + name: AE +fieldset/MACA2LR: + description: Ethernet MAC address 2 low register + fields: + - bit_offset: 0 + bit_size: 32 + description: MACA2L + name: MACA2L +fieldset/MACA3HR: + description: Ethernet MAC address 3 high register + fields: + - bit_offset: 0 + bit_size: 16 + description: MACA3H + name: MACA3H + - bit_offset: 24 + bit_size: 6 + description: MBC + name: MBC + - bit_offset: 30 + bit_size: 1 + description: SA + enum: MACAHR_SA + name: SA + - bit_offset: 31 + bit_size: 1 + description: AE + enum: MACAHR_AE + name: AE +fieldset/MACA3LR: + description: Ethernet MAC address 3 low register + fields: + - bit_offset: 0 + bit_size: 32 + description: MBCA3L + name: MACA3L +fieldset/MACCR: + description: Ethernet MAC configuration register + fields: + - bit_offset: 2 + bit_size: 1 + description: Receiver enable + enum: RE + name: RE + - bit_offset: 3 + bit_size: 1 + description: Transmitter enable + enum: TE + name: TE + - bit_offset: 4 + bit_size: 1 + description: Deferral check + enum: DC + name: DC + - bit_offset: 5 + bit_size: 2 + description: Back-off limit + enum: BL + name: BL + - bit_offset: 7 + bit_size: 1 + description: Automatic pad/CRC stripping + enum: APCS + name: APCS + - bit_offset: 9 + bit_size: 1 + description: Retry disable + enum: RD + name: RD + - bit_offset: 10 + bit_size: 1 + description: IPv4 checksum offload + enum: IPCO + name: IPCO + - bit_offset: 11 + bit_size: 1 + description: Duplex mode + enum: DM + name: DM + - bit_offset: 12 + bit_size: 1 + description: Loopback mode + enum: LM + name: LM + - bit_offset: 13 + bit_size: 1 + description: Receive own disable + enum: ROD + name: ROD + - bit_offset: 14 + bit_size: 1 + description: Fast Ethernet speed + enum: FES + name: FES + - bit_offset: 16 + bit_size: 1 + description: Carrier sense disable + enum: CSD + name: CSD + - bit_offset: 17 + bit_size: 3 + description: Interframe gap + enum: IFG + name: IFG + - bit_offset: 22 + bit_size: 1 + description: Jabber disable + enum: JD + name: JD + - bit_offset: 23 + bit_size: 1 + description: Watchdog disable + enum: WD + name: WD + - bit_offset: 25 + bit_size: 1 + description: CRC stripping for type frames + enum: CSTF + name: CSTF +fieldset/MACDBGR: + description: Ethernet MAC debug register + fields: + - bit_offset: 0 + bit_size: 1 + description: MAC MII receive protocol engine active + name: MMRPEA + - bit_offset: 1 + bit_size: 2 + description: MAC small FIFO read/write controllers status + name: MSFRWCS + - bit_offset: 4 + bit_size: 1 + description: Rx FIFO write controller active + name: RFWRA + - bit_offset: 5 + bit_size: 2 + description: Rx FIFO read controller status + name: RFRCS + - bit_offset: 8 + bit_size: 2 + description: Rx FIFO fill level + name: RFFL + - bit_offset: 16 + bit_size: 1 + description: MAC MII transmit engine active + name: MMTEA + - bit_offset: 17 + bit_size: 2 + description: MAC transmit frame controller status + name: MTFCS + - bit_offset: 19 + bit_size: 1 + description: MAC transmitter in pause + name: MTP + - bit_offset: 20 + bit_size: 2 + description: Tx FIFO read status + name: TFRS + - bit_offset: 22 + bit_size: 1 + description: Tx FIFO write active + name: TFWA + - bit_offset: 24 + bit_size: 1 + description: Tx FIFO not empty + name: TFNE + - bit_offset: 25 + bit_size: 1 + description: Tx FIFO full + name: TFF +fieldset/MACFCR: + description: Ethernet MAC flow control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Flow control busy/back pressure activate + enum: FCB + name: FCB + - bit_offset: 1 + bit_size: 1 + description: Transmit flow control enable + enum: TFCE + name: TFCE + - bit_offset: 2 + bit_size: 1 + description: Receive flow control enable + enum: RFCE + name: RFCE + - bit_offset: 3 + bit_size: 1 + description: Unicast pause frame detect + enum: UPFD + name: UPFD + - bit_offset: 4 + bit_size: 2 + description: Pause low threshold + enum: PLT + name: PLT + - bit_offset: 7 + bit_size: 1 + description: Zero-quanta pause disable + enum: ZQPD + name: ZQPD + - bit_offset: 16 + bit_size: 16 + description: Pause time + name: PT +fieldset/MACFFR: + description: Ethernet MAC frame filter register + fields: + - bit_offset: 0 + bit_size: 1 + description: Promiscuous mode + enum: PM + name: PM + - bit_offset: 1 + bit_size: 1 + description: Hash unicast + enum: HU + name: HU + - bit_offset: 2 + bit_size: 1 + description: Hash multicast + enum: HM + name: HM + - bit_offset: 3 + bit_size: 1 + description: Destination address unique filtering + enum: DAIF + name: DAIF + - bit_offset: 4 + bit_size: 1 + description: Pass all multicast + enum: PAM + name: PAM + - bit_offset: 5 + bit_size: 1 + description: Broadcast frames disable + enum: BFD + name: BFD + - bit_offset: 6 + bit_size: 2 + description: Pass control frames + enum: PCF + name: PCF + - bit_offset: 7 + bit_size: 1 + description: Source address inverse filtering + enum: SAIF + name: SAIF + - bit_offset: 8 + bit_size: 1 + description: Source address filter + enum: SAF + name: SAF + - bit_offset: 9 + bit_size: 1 + description: Hash or perfect filter + enum: HPF + name: HPF + - bit_offset: 31 + bit_size: 1 + description: Receive all + enum: RA + name: RA +fieldset/MACHTHR: + description: Ethernet MAC hash table high register + fields: + - bit_offset: 0 + bit_size: 32 + description: Upper 32 bits of hash table + name: HTH +fieldset/MACHTLR: + description: Ethernet MAC hash table low register + fields: + - bit_offset: 0 + bit_size: 32 + description: Lower 32 bits of hash table + name: HTL +fieldset/MACIMR: + description: Ethernet MAC interrupt mask register + fields: + - bit_offset: 3 + bit_size: 1 + description: PMT interrupt mask + enum: PMTIM + name: PMTIM + - bit_offset: 9 + bit_size: 1 + description: Time stamp trigger interrupt mask + enum: TSTIM + name: TSTIM +fieldset/MACMIIAR: + description: Ethernet MAC MII address register + fields: + - bit_offset: 0 + bit_size: 1 + description: MII busy + enum: MB + name: MB + - bit_offset: 1 + bit_size: 1 + description: MII write + enum: MW + name: MW + - bit_offset: 2 + bit_size: 3 + description: Clock range + enum: CR + name: CR + - bit_offset: 6 + bit_size: 5 + description: MII register - select the desired MII register in the PHY device + name: MR + - bit_offset: 11 + bit_size: 5 + description: PHY address - select which of possible 32 PHYs is being accessed + name: PA +fieldset/MACMIIDR: + description: Ethernet MAC MII data register + fields: + - bit_offset: 0 + bit_size: 16 + description: MII data read from/written to the PHY + name: MD +fieldset/MACPMTCSR: + description: Ethernet MAC PMT control and status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Power down + enum: PD + name: PD + - bit_offset: 1 + bit_size: 1 + description: Magic packet enable + enum: MPE + name: MPE + - bit_offset: 2 + bit_size: 1 + description: Wakeup frame enable + enum: WFE + name: WFE + - bit_offset: 5 + bit_size: 1 + description: Magic packet received + name: MPR + - bit_offset: 6 + bit_size: 1 + description: Wakeup frame received + name: WFR + - bit_offset: 9 + bit_size: 1 + description: Global unicast + enum: GU + name: GU + - bit_offset: 31 + bit_size: 1 + description: Wakeup frame filter register pointer reset + enum: WFFRPR + name: WFFRPR +fieldset/MACSR: + description: Ethernet MAC interrupt status register + fields: + - bit_offset: 3 + bit_size: 1 + description: PMT status + name: PMTS + - bit_offset: 4 + bit_size: 1 + description: MMC status + name: MMCS + - bit_offset: 5 + bit_size: 1 + description: MMC receive status + name: MMCRS + - bit_offset: 6 + bit_size: 1 + description: MMC transmit status + name: MMCTS + - bit_offset: 9 + bit_size: 1 + description: Time stamp trigger status + name: TSTS +fieldset/MACVLANTR: + description: Ethernet MAC VLAN tag register + fields: + - bit_offset: 0 + bit_size: 16 + description: VLAN tag identifier (for receive frames) + name: VLANTI + - bit_offset: 16 + bit_size: 1 + description: 12-bit VLAN tag comparison + enum: VLANTC + name: VLANTC diff --git a/data/registers/flash_f7.yaml b/data/registers/flash_f7.yaml new file mode 100644 index 0000000..e58e05d --- /dev/null +++ b/data/registers/flash_f7.yaml @@ -0,0 +1,382 @@ +--- +block/FLASH: + description: FLASH + items: + - byte_offset: 0 + description: Flash access control register + fieldset: ACR + name: ACR + - access: Write + byte_offset: 4 + description: Flash key register + fieldset: KEYR + name: KEYR + - access: Write + byte_offset: 8 + description: Flash option key register + fieldset: OPTKEYR + name: OPTKEYR + - byte_offset: 12 + description: Status register + fieldset: SR + name: SR + - byte_offset: 16 + description: Control register + fieldset: CR + name: CR + - byte_offset: 20 + description: Flash option control register + fieldset: OPTCR + name: OPTCR + - byte_offset: 24 + description: Flash option control register 1 + fieldset: OPTCR1 + name: OPTCR1 + - byte_offset: 28 + description: Flash option control register + fieldset: OPTCR2 + name: OPTCR2 +enum/ARTEN: + bit_size: 1 + variants: + - description: ART Accelerator is disabled + name: Disabled + value: 0 + - description: ART Accelerator is enabled + name: Enabled + value: 1 +enum/ARTRST: + bit_size: 1 + variants: + - description: Accelerator is not reset + name: NotReset + value: 0 + - description: Accelerator is reset + name: Reset + value: 1 +enum/EOPIE: + bit_size: 1 + variants: + - description: End of operation interrupt disabled + name: Disabled + value: 0 + - description: End of operation interrupt enabled + name: Enabled + value: 1 +enum/ERRIE: + bit_size: 1 + variants: + - description: Error interrupt generation disabled + name: Disabled + value: 0 + - description: Error interrupt generation enabled + name: Enabled + value: 1 +enum/LATENCY: + bit_size: 4 + variants: + - description: 0 wait states + name: WS0 + value: 0 + - description: 1 wait states + name: WS1 + value: 1 + - description: 2 wait states + name: WS2 + value: 2 + - description: 3 wait states + name: WS3 + value: 3 + - description: 4 wait states + name: WS4 + value: 4 + - description: 5 wait states + name: WS5 + value: 5 + - description: 6 wait states + name: WS6 + value: 6 + - description: 7 wait states + name: WS7 + value: 7 + - description: 8 wait states + name: WS8 + value: 8 + - description: 9 wait states + name: WS9 + value: 9 + - description: 10 wait states + name: WS10 + value: 10 + - description: 11 wait states + name: WS11 + value: 11 + - description: 12 wait states + name: WS12 + value: 12 + - description: 13 wait states + name: WS13 + value: 13 + - description: 14 wait states + name: WS14 + value: 14 + - description: 15 wait states + name: WS15 + value: 15 +enum/LOCK: + bit_size: 1 + variants: + - description: FLASH_CR register is unlocked + name: Unlocked + value: 0 + - description: FLASH_CR register is locked + name: Locked + value: 1 +enum/MER: + bit_size: 1 + variants: + - description: Erase activated for all user sectors + name: MassErase + value: 1 +enum/PG: + bit_size: 1 + variants: + - description: Flash programming activated + name: Program + value: 1 +enum/PRFTEN: + bit_size: 1 + variants: + - description: Prefetch is disabled + name: Disabled + value: 0 + - description: Prefetch is enabled + name: Enabled + value: 1 +enum/PSIZE: + bit_size: 2 + variants: + - description: Program x8 + name: PSIZE8 + value: 0 + - description: Program x16 + name: PSIZE16 + value: 1 + - description: Program x32 + name: PSIZE32 + value: 2 + - description: Program x64 + name: PSIZE64 + value: 3 +enum/SER: + bit_size: 1 + variants: + - description: Erase activated for selected sector + name: SectorErase + value: 1 +enum/STRT: + bit_size: 1 + variants: + - description: Trigger an erase operation + name: Start + value: 1 +fieldset/ACR: + description: Flash access control register + fields: + - bit_offset: 0 + bit_size: 4 + description: Latency + enum: LATENCY + name: LATENCY + - bit_offset: 8 + bit_size: 1 + description: Prefetch enable + enum: PRFTEN + name: PRFTEN + - bit_offset: 9 + bit_size: 1 + description: ART Accelerator Enable + enum: ARTEN + name: ARTEN + - bit_offset: 11 + bit_size: 1 + description: ART Accelerator reset + enum: ARTRST + name: ARTRST +fieldset/CR: + description: Control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Programming + enum: PG + name: PG + - bit_offset: 1 + bit_size: 1 + description: Sector Erase + enum: SER + name: SER + - bit_offset: 2 + bit_size: 1 + description: Mass Erase of sectors 0 to 11 + enum: MER + name: MER + - bit_offset: 3 + bit_size: 4 + description: Sector number + name: SNB + - bit_offset: 8 + bit_size: 2 + description: Program size + enum: PSIZE + name: PSIZE + - bit_offset: 16 + bit_size: 1 + description: Start + enum: STRT + name: STRT + - bit_offset: 24 + bit_size: 1 + description: End of operation interrupt enable + enum: EOPIE + name: EOPIE + - bit_offset: 25 + bit_size: 1 + description: Error interrupt enable + enum: ERRIE + name: ERRIE + - bit_offset: 26 + bit_size: 1 + description: PCROP error interrupt enable + name: RDERRIE + - bit_offset: 31 + bit_size: 1 + description: Lock + enum: LOCK + name: LOCK +fieldset/KEYR: + description: Flash key register + fields: + - bit_offset: 0 + bit_size: 32 + description: FPEC key + name: KEY +fieldset/OPTCR: + description: Flash option control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Option lock + name: OPTLOCK + - bit_offset: 1 + bit_size: 1 + description: Option start + name: OPTSTRT + - bit_offset: 2 + bit_size: 2 + description: BOR reset Level + name: BOR_LEV + - bit_offset: 4 + bit_size: 1 + description: User option bytes + name: WWDG_SW + - bit_offset: 5 + bit_size: 1 + description: WDG_SW User option bytes + name: IWDG_SW + - bit_offset: 6 + bit_size: 1 + description: nRST_STOP User option bytes + name: nRST_STOP + - bit_offset: 7 + bit_size: 1 + description: nRST_STDBY User option bytes + name: nRST_STDBY + - bit_offset: 8 + bit_size: 8 + description: Read protect + name: RDP + - bit_offset: 16 + bit_size: 8 + description: Not write protect + name: nWRP + - bit_offset: 28 + bit_size: 1 + description: Dual Boot mode (valid only when nDBANK=0) + name: nDBOOT + - bit_offset: 29 + bit_size: 1 + description: Not dual bank mode + name: nDBANK + - bit_offset: 30 + bit_size: 1 + description: Independent watchdog counter freeze in standby mode + name: IWDG_STDBY + - bit_offset: 31 + bit_size: 1 + description: Independent watchdog counter freeze in Stop mode + name: IWDG_STOP +fieldset/OPTCR1: + description: Flash option control register 1 + fields: + - bit_offset: 0 + bit_size: 16 + description: Boot base address when Boot pin =0 + name: BOOT_ADD0 + - bit_offset: 16 + bit_size: 16 + description: Boot base address when Boot pin =1 + name: BOOT_ADD1 +fieldset/OPTCR2: + description: Flash option control register + fields: + - bit_offset: 0 + bit_size: 8 + description: PCROP option byte + name: PCROPi + - bit_offset: 31 + bit_size: 1 + description: PCROP zone preserved when RDP level decreased + name: PCROP_RDP +fieldset/OPTKEYR: + description: Flash option key register + fields: + - bit_offset: 0 + bit_size: 32 + description: Option byte key + name: OPTKEYR +fieldset/SR: + description: Status register + fields: + - bit_offset: 0 + bit_size: 1 + description: End of operation + name: EOP + - bit_offset: 1 + bit_size: 1 + description: Operation error + name: OPERR + - bit_offset: 4 + bit_size: 1 + description: Write protection error + name: WRPERR + - bit_offset: 5 + bit_size: 1 + description: Programming alignment error + name: PGAERR + - bit_offset: 6 + bit_size: 1 + description: Programming parallelism error + name: PGPERR + - bit_offset: 7 + bit_size: 1 + description: Erase Sequence Error + name: ERSERR + - bit_offset: 8 + bit_size: 1 + description: RDERR + name: RDERR + - bit_offset: 16 + bit_size: 1 + description: Busy + name: BSY diff --git a/data/registers/iwdg_v2.yaml b/data/registers/iwdg_v2.yaml new file mode 100644 index 0000000..1ca5c4d --- /dev/null +++ b/data/registers/iwdg_v2.yaml @@ -0,0 +1,110 @@ +--- +block/IWDG: + description: Independent watchdog + items: + - access: Write + byte_offset: 0 + description: Key register + fieldset: KR + name: KR + - byte_offset: 4 + description: Prescaler register + fieldset: PR + name: PR + - byte_offset: 8 + description: Reload register + fieldset: RLR + name: RLR + - access: Read + byte_offset: 12 + description: Status register + fieldset: SR + name: SR + - byte_offset: 16 + description: Window register + fieldset: WINR + name: WINR +enum/KEY: + bit_size: 16 + variants: + - description: Enable access to PR, RLR and WINR registers (0x5555) + name: Enable + value: 21845 + - description: Reset the watchdog value (0xAAAA) + name: Reset + value: 43690 + - description: Start the watchdog (0xCCCC) + name: Start + value: 52428 +enum/PR: + bit_size: 3 + variants: + - description: Divider /4 + name: DivideBy4 + value: 0 + - description: Divider /8 + name: DivideBy8 + value: 1 + - description: Divider /16 + name: DivideBy16 + value: 2 + - description: Divider /32 + name: DivideBy32 + value: 3 + - description: Divider /64 + name: DivideBy64 + value: 4 + - description: Divider /128 + name: DivideBy128 + value: 5 + - description: Divider /256 + name: DivideBy256 + value: 6 + - description: Divider /256 + name: DivideBy256bis + value: 7 +fieldset/KR: + description: Key register + fields: + - bit_offset: 0 + bit_size: 16 + description: Key value (write only, read 0000h) + enum: KEY + name: KEY +fieldset/PR: + description: Prescaler register + fields: + - bit_offset: 0 + bit_size: 3 + description: Prescaler divider + enum: PR + name: PR +fieldset/RLR: + description: Reload register + fields: + - bit_offset: 0 + bit_size: 12 + description: Watchdog counter reload value + name: RL +fieldset/SR: + description: Status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Watchdog prescaler value update + name: PVU + - bit_offset: 1 + bit_size: 1 + description: Watchdog counter reload value update + name: RVU + - bit_offset: 2 + bit_size: 1 + description: Watchdog counter window value update + name: WVU +fieldset/WINR: + description: Window register + fields: + - bit_offset: 0 + bit_size: 12 + description: Watchdog counter window value + name: WIN diff --git a/data/registers/jpeg_v1.yaml b/data/registers/jpeg_v1.yaml new file mode 100644 index 0000000..6ea011e --- /dev/null +++ b/data/registers/jpeg_v1.yaml @@ -0,0 +1,5849 @@ +--- +block/JPEG: + description: JPEG codec + items: + - access: Write + byte_offset: 0 + description: JPEG codec configuration register 0 + fieldset: JPEG_CONFR0 + name: JPEG_CONFR0 + - byte_offset: 4 + description: JPEG codec configuration register 1 + fieldset: JPEG_CONFR1 + name: JPEG_CONFR1 + - byte_offset: 8 + description: JPEG codec configuration register 2 + fieldset: JPEG_CONFR2 + name: JPEG_CONFR2 + - byte_offset: 12 + description: JPEG codec configuration register 3 + fieldset: JPEG_CONFR3 + name: JPEG_CONFR3 + - byte_offset: 16 + description: JPEG codec configuration register 4 + fieldset: JPEG_CONFR4 + name: JPEG_CONFR4 + - byte_offset: 20 + description: JPEG codec configuration register 5 + fieldset: JPEG_CONFR5 + name: JPEG_CONFR5 + - byte_offset: 24 + description: JPEG codec configuration register 6 + fieldset: JPEG_CONFR6 + name: JPEG_CONFR6 + - byte_offset: 28 + description: JPEG codec configuration register 7 + fieldset: JPEG_CONFR7 + name: JPEG_CONFR7 + - byte_offset: 48 + description: JPEG control register + fieldset: JPEG_CR + name: JPEG_CR + - access: Read + byte_offset: 52 + description: JPEG status register + fieldset: JPEG_SR + name: JPEG_SR + - access: Write + byte_offset: 56 + description: JPEG clear flag register + fieldset: JPEG_CFR + name: JPEG_CFR + - access: Write + byte_offset: 64 + description: JPEG data input register + fieldset: JPEG_DIR + name: JPEG_DIR + - access: Read + byte_offset: 68 + description: JPEG data output register + fieldset: JPEG_DOR + name: JPEG_DOR + - byte_offset: 80 + description: JPEG quantization tables + fieldset: QMEM0_0 + name: QMEM0_0 + - byte_offset: 84 + description: JPEG quantization tables + fieldset: QMEM0_1 + name: QMEM0_1 + - byte_offset: 88 + description: JPEG quantization tables + fieldset: QMEM0_2 + name: QMEM0_2 + - byte_offset: 92 + description: JPEG quantization tables + fieldset: QMEM0_3 + name: QMEM0_3 + - byte_offset: 96 + description: JPEG quantization tables + fieldset: QMEM0_4 + name: QMEM0_4 + - byte_offset: 100 + description: JPEG quantization tables + fieldset: QMEM0_5 + name: QMEM0_5 + - byte_offset: 104 + description: JPEG quantization tables + fieldset: QMEM0_6 + name: QMEM0_6 + - byte_offset: 108 + description: JPEG quantization tables + fieldset: QMEM0_7 + name: QMEM0_7 + - byte_offset: 112 + description: JPEG quantization tables + fieldset: QMEM0_8 + name: QMEM0_8 + - byte_offset: 116 + description: JPEG quantization tables + fieldset: QMEM0_9 + name: QMEM0_9 + - byte_offset: 120 + description: JPEG quantization tables + fieldset: QMEM0_10 + name: QMEM0_10 + - byte_offset: 124 + description: JPEG quantization tables + fieldset: QMEM0_11 + name: QMEM0_11 + - byte_offset: 128 + description: JPEG quantization tables + fieldset: QMEM0_12 + name: QMEM0_12 + - byte_offset: 132 + description: JPEG quantization tables + fieldset: QMEM0_13 + name: QMEM0_13 + - byte_offset: 136 + description: JPEG quantization tables + fieldset: QMEM0_14 + name: QMEM0_14 + - byte_offset: 140 + description: JPEG quantization tables + fieldset: QMEM0_15 + name: QMEM0_15 + - byte_offset: 144 + description: JPEG quantization tables + fieldset: QMEM1_0 + name: QMEM1_0 + - byte_offset: 148 + description: JPEG quantization tables + fieldset: QMEM1_1 + name: QMEM1_1 + - byte_offset: 152 + description: JPEG quantization tables + fieldset: QMEM1_2 + name: QMEM1_2 + - byte_offset: 156 + description: JPEG quantization tables + fieldset: QMEM1_3 + name: QMEM1_3 + - byte_offset: 160 + description: JPEG quantization tables + fieldset: QMEM1_4 + name: QMEM1_4 + - byte_offset: 164 + description: JPEG quantization tables + fieldset: QMEM1_5 + name: QMEM1_5 + - byte_offset: 168 + description: JPEG quantization tables + fieldset: QMEM1_6 + name: QMEM1_6 + - byte_offset: 172 + description: JPEG quantization tables + fieldset: QMEM1_7 + name: QMEM1_7 + - byte_offset: 176 + description: JPEG quantization tables + fieldset: QMEM1_8 + name: QMEM1_8 + - byte_offset: 180 + description: JPEG quantization tables + fieldset: QMEM1_9 + name: QMEM1_9 + - byte_offset: 184 + description: JPEG quantization tables + fieldset: QMEM1_10 + name: QMEM1_10 + - byte_offset: 188 + description: JPEG quantization tables + fieldset: QMEM1_11 + name: QMEM1_11 + - byte_offset: 192 + description: JPEG quantization tables + fieldset: QMEM1_12 + name: QMEM1_12 + - byte_offset: 196 + description: JPEG quantization tables + fieldset: QMEM1_13 + name: QMEM1_13 + - byte_offset: 200 + description: JPEG quantization tables + fieldset: QMEM1_14 + name: QMEM1_14 + - byte_offset: 204 + description: JPEG quantization tables + fieldset: QMEM1_15 + name: QMEM1_15 + - byte_offset: 208 + description: JPEG quantization tables + fieldset: QMEM2_0 + name: QMEM2_0 + - byte_offset: 212 + description: JPEG quantization tables + fieldset: QMEM2_1 + name: QMEM2_1 + - byte_offset: 216 + description: JPEG quantization tables + fieldset: QMEM2_2 + name: QMEM2_2 + - byte_offset: 220 + description: JPEG quantization tables + fieldset: QMEM2_3 + name: QMEM2_3 + - byte_offset: 224 + description: JPEG quantization tables + fieldset: QMEM2_4 + name: QMEM2_4 + - byte_offset: 228 + description: JPEG quantization tables + fieldset: QMEM2_5 + name: QMEM2_5 + - byte_offset: 232 + description: JPEG quantization tables + fieldset: QMEM2_6 + name: QMEM2_6 + - byte_offset: 236 + description: JPEG quantization tables + fieldset: QMEM2_7 + name: QMEM2_7 + - byte_offset: 240 + description: JPEG quantization tables + fieldset: QMEM2_8 + name: QMEM2_8 + - byte_offset: 244 + description: JPEG quantization tables + fieldset: QMEM2_9 + name: QMEM2_9 + - byte_offset: 248 + description: JPEG quantization tables + fieldset: QMEM2_10 + name: QMEM2_10 + - byte_offset: 252 + description: JPEG quantization tables + fieldset: QMEM2_11 + name: QMEM2_11 + - byte_offset: 256 + description: JPEG quantization tables + fieldset: QMEM2_12 + name: QMEM2_12 + - byte_offset: 260 + description: JPEG quantization tables + fieldset: QMEM2_13 + name: QMEM2_13 + - byte_offset: 264 + description: JPEG quantization tables + fieldset: QMEM2_14 + name: QMEM2_14 + - byte_offset: 268 + description: JPEG quantization tables + fieldset: QMEM2_15 + name: QMEM2_15 + - byte_offset: 272 + description: JPEG quantization tables + fieldset: QMEM3_0 + name: QMEM3_0 + - byte_offset: 276 + description: JPEG quantization tables + fieldset: QMEM3_1 + name: QMEM3_1 + - byte_offset: 280 + description: JPEG quantization tables + fieldset: QMEM3_2 + name: QMEM3_2 + - byte_offset: 284 + description: JPEG quantization tables + fieldset: QMEM3_3 + name: QMEM3_3 + - byte_offset: 288 + description: JPEG quantization tables + fieldset: QMEM3_4 + name: QMEM3_4 + - byte_offset: 292 + description: JPEG quantization tables + fieldset: QMEM3_5 + name: QMEM3_5 + - byte_offset: 296 + description: JPEG quantization tables + fieldset: QMEM3_6 + name: QMEM3_6 + - byte_offset: 300 + description: JPEG quantization tables + fieldset: QMEM3_7 + name: QMEM3_7 + - byte_offset: 304 + description: JPEG quantization tables + fieldset: QMEM3_8 + name: QMEM3_8 + - byte_offset: 308 + description: JPEG quantization tables + fieldset: QMEM3_9 + name: QMEM3_9 + - byte_offset: 312 + description: JPEG quantization tables + fieldset: QMEM3_10 + name: QMEM3_10 + - byte_offset: 316 + description: JPEG quantization tables + fieldset: QMEM3_11 + name: QMEM3_11 + - byte_offset: 320 + description: JPEG quantization tables + fieldset: QMEM3_12 + name: QMEM3_12 + - byte_offset: 324 + description: JPEG quantization tables + fieldset: QMEM3_13 + name: QMEM3_13 + - byte_offset: 328 + description: JPEG quantization tables + fieldset: QMEM3_14 + name: QMEM3_14 + - byte_offset: 332 + description: JPEG quantization tables + fieldset: QMEM3_15 + name: QMEM3_15 + - byte_offset: 336 + description: JPEG HuffMin tables + fieldset: HUFFMIN_0 + name: HUFFMIN_0 + - byte_offset: 340 + description: JPEG HuffMin tables + fieldset: HUFFMIN_1 + name: HUFFMIN_1 + - byte_offset: 344 + description: JPEG HuffMin tables + fieldset: HUFFMIN_2 + name: HUFFMIN_2 + - byte_offset: 348 + description: JPEG HuffMin tables + fieldset: HUFFMIN_3 + name: HUFFMIN_3 + - byte_offset: 352 + description: JPEG HuffMin tables + fieldset: HUFFMIN_4 + name: HUFFMIN_4 + - byte_offset: 356 + description: JPEG HuffMin tables + fieldset: HUFFMIN_5 + name: HUFFMIN_5 + - byte_offset: 360 + description: JPEG HuffMin tables + fieldset: HUFFMIN_6 + name: HUFFMIN_6 + - byte_offset: 364 + description: JPEG HuffMin tables + fieldset: HUFFMIN_7 + name: HUFFMIN_7 + - byte_offset: 368 + description: JPEG HuffMin tables + fieldset: HUFFMIN_8 + name: HUFFMIN_8 + - byte_offset: 372 + description: JPEG HuffMin tables + fieldset: HUFFMIN_9 + name: HUFFMIN_9 + - byte_offset: 376 + description: JPEG HuffMin tables + fieldset: HUFFMIN_10 + name: HUFFMIN_10 + - byte_offset: 380 + description: JPEG HuffMin tables + fieldset: HUFFMIN_11 + name: HUFFMIN_11 + - byte_offset: 384 + description: JPEG HuffMin tables + fieldset: HUFFMIN_12 + name: HUFFMIN_12 + - byte_offset: 388 + description: JPEG HuffMin tables + fieldset: HUFFMIN_13 + name: HUFFMIN_13 + - byte_offset: 392 + description: JPEG HuffMin tables + fieldset: HUFFMIN_14 + name: HUFFMIN_14 + - byte_offset: 396 + description: JPEG HuffMin tables + fieldset: HUFFMIN_15 + name: HUFFMIN_15 + - byte_offset: 400 + description: JPEG HuffSymb tables + fieldset: HUFFBASE0 + name: HUFFBASE0 + - byte_offset: 404 + description: JPEG HuffSymb tables + fieldset: HUFFBASE1 + name: HUFFBASE1 + - byte_offset: 408 + description: JPEG HuffSymb tables + fieldset: HUFFBASE2 + name: HUFFBASE2 + - byte_offset: 412 + description: JPEG HuffSymb tables + fieldset: HUFFBASE3 + name: HUFFBASE3 + - byte_offset: 416 + description: JPEG HuffSymb tables + fieldset: HUFFBASE4 + name: HUFFBASE4 + - byte_offset: 420 + description: JPEG HuffSymb tables + fieldset: HUFFBASE5 + name: HUFFBASE5 + - byte_offset: 424 + description: JPEG HuffSymb tables + fieldset: HUFFBASE6 + name: HUFFBASE6 + - byte_offset: 428 + description: JPEG HuffSymb tables + fieldset: HUFFBASE7 + name: HUFFBASE7 + - byte_offset: 432 + description: JPEG HuffSymb tables + fieldset: HUFFBASE8 + name: HUFFBASE8 + - byte_offset: 436 + description: JPEG HuffSymb tables + fieldset: HUFFBASE9 + name: HUFFBASE9 + - byte_offset: 440 + description: JPEG HuffSymb tables + fieldset: HUFFBASE10 + name: HUFFBASE10 + - byte_offset: 444 + description: JPEG HuffSymb tables + fieldset: HUFFBASE11 + name: HUFFBASE11 + - byte_offset: 448 + description: JPEG HuffSymb tables + fieldset: HUFFBASE12 + name: HUFFBASE12 + - byte_offset: 452 + description: JPEG HuffSymb tables + fieldset: HUFFBASE13 + name: HUFFBASE13 + - byte_offset: 456 + description: JPEG HuffSymb tables + fieldset: HUFFBASE14 + name: HUFFBASE14 + - byte_offset: 460 + description: JPEG HuffSymb tables + fieldset: HUFFBASE15 + name: HUFFBASE15 + - byte_offset: 464 + description: JPEG HuffSymb tables + fieldset: HUFFBASE16 + name: HUFFBASE16 + - byte_offset: 468 + description: JPEG HuffSymb tables + fieldset: HUFFBASE17 + name: HUFFBASE17 + - byte_offset: 472 + description: JPEG HuffSymb tables + fieldset: HUFFBASE18 + name: HUFFBASE18 + - byte_offset: 476 + description: JPEG HuffSymb tables + fieldset: HUFFBASE19 + name: HUFFBASE19 + - byte_offset: 480 + description: JPEG HuffSymb tables + fieldset: HUFFBASE20 + name: HUFFBASE20 + - byte_offset: 484 + description: JPEG HuffSymb tables + fieldset: HUFFBASE21 + name: HUFFBASE21 + - byte_offset: 488 + description: JPEG HuffSymb tables + fieldset: HUFFBASE22 + name: HUFFBASE22 + - byte_offset: 492 + description: JPEG HuffSymb tables + fieldset: HUFFBASE23 + name: HUFFBASE23 + - byte_offset: 496 + description: JPEG HuffSymb tables + fieldset: HUFFBASE24 + name: HUFFBASE24 + - byte_offset: 500 + description: JPEG HuffSymb tables + fieldset: HUFFBASE25 + name: HUFFBASE25 + - byte_offset: 504 + description: JPEG HuffSymb tables + fieldset: HUFFBASE26 + name: HUFFBASE26 + - byte_offset: 508 + description: JPEG HuffSymb tables + fieldset: HUFFBASE27 + name: HUFFBASE27 + - byte_offset: 512 + description: JPEG HuffSymb tables + fieldset: HUFFBASE28 + name: HUFFBASE28 + - byte_offset: 516 + description: JPEG HuffSymb tables + fieldset: HUFFBASE29 + name: HUFFBASE29 + - byte_offset: 520 + description: JPEG HuffSymb tables + fieldset: HUFFBASE30 + name: HUFFBASE30 + - byte_offset: 524 + description: JPEG HuffSymb tables + fieldset: HUFFBASE31 + name: HUFFBASE31 + - byte_offset: 528 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB0 + name: HUFFSYMB0 + - byte_offset: 532 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB1 + name: HUFFSYMB1 + - byte_offset: 536 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB2 + name: HUFFSYMB2 + - byte_offset: 540 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB3 + name: HUFFSYMB3 + - byte_offset: 544 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB4 + name: HUFFSYMB4 + - byte_offset: 548 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB5 + name: HUFFSYMB5 + - byte_offset: 552 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB6 + name: HUFFSYMB6 + - byte_offset: 556 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB7 + name: HUFFSYMB7 + - byte_offset: 560 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB8 + name: HUFFSYMB8 + - byte_offset: 564 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB9 + name: HUFFSYMB9 + - byte_offset: 568 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB10 + name: HUFFSYMB10 + - byte_offset: 572 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB11 + name: HUFFSYMB11 + - byte_offset: 576 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB12 + name: HUFFSYMB12 + - byte_offset: 580 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB13 + name: HUFFSYMB13 + - byte_offset: 584 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB14 + name: HUFFSYMB14 + - byte_offset: 588 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB15 + name: HUFFSYMB15 + - byte_offset: 592 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB16 + name: HUFFSYMB16 + - byte_offset: 596 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB17 + name: HUFFSYMB17 + - byte_offset: 600 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB18 + name: HUFFSYMB18 + - byte_offset: 604 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB19 + name: HUFFSYMB19 + - byte_offset: 608 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB20 + name: HUFFSYMB20 + - byte_offset: 612 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB21 + name: HUFFSYMB21 + - byte_offset: 616 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB22 + name: HUFFSYMB22 + - byte_offset: 620 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB23 + name: HUFFSYMB23 + - byte_offset: 624 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB24 + name: HUFFSYMB24 + - byte_offset: 628 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB25 + name: HUFFSYMB25 + - byte_offset: 632 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB26 + name: HUFFSYMB26 + - byte_offset: 636 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB27 + name: HUFFSYMB27 + - byte_offset: 640 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB28 + name: HUFFSYMB28 + - byte_offset: 644 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB29 + name: HUFFSYMB29 + - byte_offset: 648 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB30 + name: HUFFSYMB30 + - byte_offset: 652 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB31 + name: HUFFSYMB31 + - byte_offset: 656 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB32 + name: HUFFSYMB32 + - byte_offset: 660 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB33 + name: HUFFSYMB33 + - byte_offset: 664 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB34 + name: HUFFSYMB34 + - byte_offset: 668 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB35 + name: HUFFSYMB35 + - byte_offset: 672 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB36 + name: HUFFSYMB36 + - byte_offset: 676 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB37 + name: HUFFSYMB37 + - byte_offset: 680 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB38 + name: HUFFSYMB38 + - byte_offset: 684 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB39 + name: HUFFSYMB39 + - byte_offset: 688 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB40 + name: HUFFSYMB40 + - byte_offset: 692 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB41 + name: HUFFSYMB41 + - byte_offset: 696 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB42 + name: HUFFSYMB42 + - byte_offset: 700 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB43 + name: HUFFSYMB43 + - byte_offset: 704 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB44 + name: HUFFSYMB44 + - byte_offset: 708 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB45 + name: HUFFSYMB45 + - byte_offset: 712 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB46 + name: HUFFSYMB46 + - byte_offset: 716 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB47 + name: HUFFSYMB47 + - byte_offset: 720 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB48 + name: HUFFSYMB48 + - byte_offset: 724 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB49 + name: HUFFSYMB49 + - byte_offset: 728 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB50 + name: HUFFSYMB50 + - byte_offset: 732 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB51 + name: HUFFSYMB51 + - byte_offset: 736 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB52 + name: HUFFSYMB52 + - byte_offset: 740 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB53 + name: HUFFSYMB53 + - byte_offset: 744 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB54 + name: HUFFSYMB54 + - byte_offset: 748 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB55 + name: HUFFSYMB55 + - byte_offset: 752 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB56 + name: HUFFSYMB56 + - byte_offset: 756 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB57 + name: HUFFSYMB57 + - byte_offset: 760 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB58 + name: HUFFSYMB58 + - byte_offset: 764 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB59 + name: HUFFSYMB59 + - byte_offset: 768 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB60 + name: HUFFSYMB60 + - byte_offset: 772 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB61 + name: HUFFSYMB61 + - byte_offset: 776 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB62 + name: HUFFSYMB62 + - byte_offset: 780 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB63 + name: HUFFSYMB63 + - byte_offset: 784 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB64 + name: HUFFSYMB64 + - byte_offset: 788 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB65 + name: HUFFSYMB65 + - byte_offset: 792 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB66 + name: HUFFSYMB66 + - byte_offset: 796 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB67 + name: HUFFSYMB67 + - byte_offset: 800 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB68 + name: HUFFSYMB68 + - byte_offset: 804 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB69 + name: HUFFSYMB69 + - byte_offset: 808 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB70 + name: HUFFSYMB70 + - byte_offset: 812 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB71 + name: HUFFSYMB71 + - byte_offset: 816 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB72 + name: HUFFSYMB72 + - byte_offset: 820 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB73 + name: HUFFSYMB73 + - byte_offset: 824 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB74 + name: HUFFSYMB74 + - byte_offset: 828 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB75 + name: HUFFSYMB75 + - byte_offset: 832 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB76 + name: HUFFSYMB76 + - byte_offset: 836 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB77 + name: HUFFSYMB77 + - byte_offset: 840 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB78 + name: HUFFSYMB78 + - byte_offset: 844 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB79 + name: HUFFSYMB79 + - byte_offset: 848 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB80 + name: HUFFSYMB80 + - byte_offset: 852 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB81 + name: HUFFSYMB81 + - byte_offset: 856 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB82 + name: HUFFSYMB82 + - byte_offset: 860 + description: JPEG HUFFSYMB tables + fieldset: HUFFSYMB83 + name: HUFFSYMB83 + - byte_offset: 864 + description: JPEG DHTMem tables + fieldset: DHTMEM0 + name: DHTMEM0 + - byte_offset: 868 + description: JPEG DHTMem tables + fieldset: DHTMEM2 + name: DHTMEM2 + - byte_offset: 872 + description: JPEG DHTMem tables + fieldset: DHTMEM3 + name: DHTMEM3 + - byte_offset: 876 + description: JPEG DHTMem tables + fieldset: DHTMEM4 + name: DHTMEM4 + - byte_offset: 880 + description: JPEG DHTMem tables + fieldset: DHTMEM5 + name: DHTMEM5 + - byte_offset: 884 + description: JPEG DHTMem tables + fieldset: DHTMEM6 + name: DHTMEM6 + - byte_offset: 888 + description: JPEG DHTMem tables + fieldset: DHTMEM7 + name: DHTMEM7 + - byte_offset: 892 + description: JPEG DHTMem tables + fieldset: DHTMEM8 + name: DHTMEM8 + - byte_offset: 896 + description: JPEG DHTMem tables + fieldset: DHTMEM9 + name: DHTMEM9 + - byte_offset: 900 + description: JPEG DHTMem tables + fieldset: DHTMEM10 + name: DHTMEM10 + - byte_offset: 904 + description: JPEG DHTMem tables + fieldset: DHTMEM11 + name: DHTMEM11 + - byte_offset: 908 + description: JPEG DHTMem tables + fieldset: DHTMEM12 + name: DHTMEM12 + - byte_offset: 912 + description: JPEG DHTMem tables + fieldset: DHTMEM13 + name: DHTMEM13 + - byte_offset: 916 + description: JPEG DHTMem tables + fieldset: DHTMEM14 + name: DHTMEM14 + - byte_offset: 920 + description: JPEG DHTMem tables + fieldset: DHTMEM15 + name: DHTMEM15 + - byte_offset: 924 + description: JPEG DHTMem tables + fieldset: DHTMEM16 + name: DHTMEM16 + - byte_offset: 928 + description: JPEG DHTMem tables + fieldset: DHTMEM17 + name: DHTMEM17 + - byte_offset: 932 + description: JPEG DHTMem tables + fieldset: DHTMEM18 + name: DHTMEM18 + - byte_offset: 936 + description: JPEG DHTMem tables + fieldset: DHTMEM19 + name: DHTMEM19 + - byte_offset: 940 + description: JPEG DHTMem tables + fieldset: DHTMEM20 + name: DHTMEM20 + - byte_offset: 944 + description: JPEG DHTMem tables + fieldset: DHTMEM21 + name: DHTMEM21 + - byte_offset: 948 + description: JPEG DHTMem tables + fieldset: DHTMEM22 + name: DHTMEM22 + - byte_offset: 952 + description: JPEG DHTMem tables + fieldset: DHTMEM23 + name: DHTMEM23 + - byte_offset: 956 + description: JPEG DHTMem tables + fieldset: DHTMEM24 + name: DHTMEM24 + - byte_offset: 960 + description: JPEG DHTMem tables + fieldset: DHTMEM25 + name: DHTMEM25 + - byte_offset: 964 + description: JPEG DHTMem tables + fieldset: DHTMEM26 + name: DHTMEM26 + - byte_offset: 968 + description: JPEG DHTMem tables + fieldset: DHTMEM27 + name: DHTMEM27 + - byte_offset: 972 + description: JPEG DHTMem tables + fieldset: DHTMEM28 + name: DHTMEM28 + - byte_offset: 976 + description: JPEG DHTMem tables + fieldset: DHTMEM29 + name: DHTMEM29 + - byte_offset: 980 + description: JPEG DHTMem tables + fieldset: DHTMEM30 + name: DHTMEM30 + - byte_offset: 984 + description: JPEG DHTMem tables + fieldset: DHTMEM31 + name: DHTMEM31 + - byte_offset: 988 + description: JPEG DHTMem tables + fieldset: DHTMEM32 + name: DHTMEM32 + - byte_offset: 992 + description: JPEG DHTMem tables + fieldset: DHTMEM33 + name: DHTMEM33 + - byte_offset: 996 + description: JPEG DHTMem tables + fieldset: DHTMEM34 + name: DHTMEM34 + - byte_offset: 1000 + description: JPEG DHTMem tables + fieldset: DHTMEM35 + name: DHTMEM35 + - byte_offset: 1004 + description: JPEG DHTMem tables + fieldset: DHTMEM36 + name: DHTMEM36 + - byte_offset: 1008 + description: JPEG DHTMem tables + fieldset: DHTMEM37 + name: DHTMEM37 + - byte_offset: 1012 + description: JPEG DHTMem tables + fieldset: DHTMEM38 + name: DHTMEM38 + - byte_offset: 1016 + description: JPEG DHTMem tables + fieldset: DHTMEM39 + name: DHTMEM39 + - byte_offset: 1020 + description: JPEG DHTMem tables + fieldset: DHTMEM40 + name: DHTMEM40 + - byte_offset: 1024 + description: JPEG DHTMem tables + fieldset: DHTMEM41 + name: DHTMEM41 + - byte_offset: 1028 + description: JPEG DHTMem tables + fieldset: DHTMEM42 + name: DHTMEM42 + - byte_offset: 1032 + description: JPEG DHTMem tables + fieldset: DHTMEM43 + name: DHTMEM43 + - byte_offset: 1036 + description: JPEG DHTMem tables + fieldset: DHTMEM44 + name: DHTMEM44 + - byte_offset: 1040 + description: JPEG DHTMem tables + fieldset: DHTMEM45 + name: DHTMEM45 + - byte_offset: 1044 + description: JPEG DHTMem tables + fieldset: DHTMEM46 + name: DHTMEM46 + - byte_offset: 1048 + description: JPEG DHTMem tables + fieldset: DHTMEM47 + name: DHTMEM47 + - byte_offset: 1052 + description: JPEG DHTMem tables + fieldset: DHTMEM48 + name: DHTMEM48 + - byte_offset: 1056 + description: JPEG DHTMem tables + fieldset: DHTMEM49 + name: DHTMEM49 + - byte_offset: 1060 + description: JPEG DHTMem tables + fieldset: DHTMEM50 + name: DHTMEM50 + - byte_offset: 1064 + description: JPEG DHTMem tables + fieldset: DHTMEM51 + name: DHTMEM51 + - byte_offset: 1068 + description: JPEG DHTMem tables + fieldset: DHTMEM52 + name: DHTMEM52 + - byte_offset: 1072 + description: JPEG DHTMem tables + fieldset: DHTMEM53 + name: DHTMEM53 + - byte_offset: 1076 + description: JPEG DHTMem tables + fieldset: DHTMEM54 + name: DHTMEM54 + - byte_offset: 1080 + description: JPEG DHTMem tables + fieldset: DHTMEM55 + name: DHTMEM55 + - byte_offset: 1084 + description: JPEG DHTMem tables + fieldset: DHTMEM56 + name: DHTMEM56 + - byte_offset: 1088 + description: JPEG DHTMem tables + fieldset: DHTMEM57 + name: DHTMEM57 + - byte_offset: 1092 + description: JPEG DHTMem tables + fieldset: DHTMEM58 + name: DHTMEM58 + - byte_offset: 1096 + description: JPEG DHTMem tables + fieldset: DHTMEM59 + name: DHTMEM59 + - byte_offset: 1100 + description: JPEG DHTMem tables + fieldset: DHTMEM60 + name: DHTMEM60 + - byte_offset: 1104 + description: JPEG DHTMem tables + fieldset: DHTMEM61 + name: DHTMEM61 + - byte_offset: 1108 + description: JPEG DHTMem tables + fieldset: DHTMEM62 + name: DHTMEM62 + - byte_offset: 1112 + description: JPEG DHTMem tables + fieldset: DHTMEM63 + name: DHTMEM63 + - byte_offset: 1116 + description: JPEG DHTMem tables + fieldset: DHTMEM64 + name: DHTMEM64 + - byte_offset: 1120 + description: JPEG DHTMem tables + fieldset: DHTMEM65 + name: DHTMEM65 + - byte_offset: 1124 + description: JPEG DHTMem tables + fieldset: DHTMEM66 + name: DHTMEM66 + - byte_offset: 1128 + description: JPEG DHTMem tables + fieldset: DHTMEM67 + name: DHTMEM67 + - byte_offset: 1132 + description: JPEG DHTMem tables + fieldset: DHTMEM68 + name: DHTMEM68 + - byte_offset: 1136 + description: JPEG DHTMem tables + fieldset: DHTMEM69 + name: DHTMEM69 + - byte_offset: 1140 + description: JPEG DHTMem tables + fieldset: DHTMEM70 + name: DHTMEM70 + - byte_offset: 1144 + description: JPEG DHTMem tables + fieldset: DHTMEM71 + name: DHTMEM71 + - byte_offset: 1148 + description: JPEG DHTMem tables + fieldset: DHTMEM72 + name: DHTMEM72 + - byte_offset: 1152 + description: JPEG DHTMem tables + fieldset: DHTMEM73 + name: DHTMEM73 + - byte_offset: 1156 + description: JPEG DHTMem tables + fieldset: DHTMEM74 + name: DHTMEM74 + - byte_offset: 1160 + description: JPEG DHTMem tables + fieldset: DHTMEM75 + name: DHTMEM75 + - byte_offset: 1164 + description: JPEG DHTMem tables + fieldset: DHTMEM76 + name: DHTMEM76 + - byte_offset: 1168 + description: JPEG DHTMem tables + fieldset: DHTMEM77 + name: DHTMEM77 + - byte_offset: 1172 + description: JPEG DHTMem tables + fieldset: DHTMEM78 + name: DHTMEM78 + - byte_offset: 1176 + description: JPEG DHTMem tables + fieldset: DHTMEM79 + name: DHTMEM79 + - byte_offset: 1180 + description: JPEG DHTMem tables + fieldset: DHTMEM80 + name: DHTMEM80 + - byte_offset: 1184 + description: JPEG DHTMem tables + fieldset: DHTMEM81 + name: DHTMEM81 + - byte_offset: 1188 + description: JPEG DHTMem tables + fieldset: DHTMEM82 + name: DHTMEM82 + - byte_offset: 1192 + description: JPEG DHTMem tables + fieldset: DHTMEM83 + name: DHTMEM83 + - byte_offset: 1196 + description: JPEG DHTMem tables + fieldset: DHTMEM84 + name: DHTMEM84 + - byte_offset: 1200 + description: JPEG DHTMem tables + fieldset: DHTMEM85 + name: DHTMEM85 + - byte_offset: 1204 + description: JPEG DHTMem tables + fieldset: DHTMEM86 + name: DHTMEM86 + - byte_offset: 1208 + description: JPEG DHTMem tables + fieldset: DHTMEM87 + name: DHTMEM87 + - byte_offset: 1212 + description: JPEG DHTMem tables + fieldset: DHTMEM88 + name: DHTMEM88 + - byte_offset: 1216 + description: JPEG DHTMem tables + fieldset: DHTMEM89 + name: DHTMEM89 + - byte_offset: 1220 + description: JPEG DHTMem tables + fieldset: DHTMEM90 + name: DHTMEM90 + - byte_offset: 1224 + description: JPEG DHTMem tables + fieldset: DHTMEM91 + name: DHTMEM91 + - byte_offset: 1228 + description: JPEG DHTMem tables + fieldset: DHTMEM92 + name: DHTMEM92 + - byte_offset: 1232 + description: JPEG DHTMem tables + fieldset: DHTMEM93 + name: DHTMEM93 + - byte_offset: 1236 + description: JPEG DHTMem tables + fieldset: DHTMEM94 + name: DHTMEM94 + - byte_offset: 1240 + description: JPEG DHTMem tables + fieldset: DHTMEM95 + name: DHTMEM95 + - byte_offset: 1244 + description: JPEG DHTMem tables + fieldset: DHTMEM96 + name: DHTMEM96 + - byte_offset: 1248 + description: JPEG DHTMem tables + fieldset: DHTMEM97 + name: DHTMEM97 + - byte_offset: 1252 + description: JPEG DHTMem tables + fieldset: DHTMEM98 + name: DHTMEM98 + - byte_offset: 1256 + description: JPEG DHTMem tables + fieldset: DHTMEM99 + name: DHTMEM99 + - byte_offset: 1260 + description: JPEG DHTMem tables + fieldset: DHTMEM100 + name: DHTMEM100 + - byte_offset: 1264 + description: JPEG DHTMem tables + fieldset: DHTMEM101 + name: DHTMEM101 + - byte_offset: 1268 + description: JPEG DHTMem tables + fieldset: DHTMEM102 + name: DHTMEM102 + - byte_offset: 1272 + description: JPEG DHTMem tables + fieldset: DHTMEM103 + name: DHTMEM103 + - byte_offset: 1280 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_0 + name: HUFFENC_AC0_0 + - byte_offset: 1284 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_1 + name: HUFFENC_AC0_1 + - byte_offset: 1288 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_2 + name: HUFFENC_AC0_2 + - byte_offset: 1292 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_3 + name: HUFFENC_AC0_3 + - byte_offset: 1296 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_4 + name: HUFFENC_AC0_4 + - byte_offset: 1300 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_5 + name: HUFFENC_AC0_5 + - byte_offset: 1304 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_6 + name: HUFFENC_AC0_6 + - byte_offset: 1308 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_7 + name: HUFFENC_AC0_7 + - byte_offset: 1312 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_8 + name: HUFFENC_AC0_8 + - byte_offset: 1316 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_9 + name: HUFFENC_AC0_9 + - byte_offset: 1320 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_10 + name: HUFFENC_AC0_10 + - byte_offset: 1324 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_11 + name: HUFFENC_AC0_11 + - byte_offset: 1328 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_12 + name: HUFFENC_AC0_12 + - byte_offset: 1332 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_13 + name: HUFFENC_AC0_13 + - byte_offset: 1336 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_14 + name: HUFFENC_AC0_14 + - byte_offset: 1340 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_15 + name: HUFFENC_AC0_15 + - byte_offset: 1344 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_16 + name: HUFFENC_AC0_16 + - byte_offset: 1348 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_17 + name: HUFFENC_AC0_17 + - byte_offset: 1352 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_18 + name: HUFFENC_AC0_18 + - byte_offset: 1356 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_19 + name: HUFFENC_AC0_19 + - byte_offset: 1360 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_20 + name: HUFFENC_AC0_20 + - byte_offset: 1364 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_21 + name: HUFFENC_AC0_21 + - byte_offset: 1368 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_22 + name: HUFFENC_AC0_22 + - byte_offset: 1372 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_23 + name: HUFFENC_AC0_23 + - byte_offset: 1376 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_24 + name: HUFFENC_AC0_24 + - byte_offset: 1380 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_25 + name: HUFFENC_AC0_25 + - byte_offset: 1384 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_26 + name: HUFFENC_AC0_26 + - byte_offset: 1388 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_27 + name: HUFFENC_AC0_27 + - byte_offset: 1392 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_28 + name: HUFFENC_AC0_28 + - byte_offset: 1396 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_29 + name: HUFFENC_AC0_29 + - byte_offset: 1400 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_30 + name: HUFFENC_AC0_30 + - byte_offset: 1404 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_31 + name: HUFFENC_AC0_31 + - byte_offset: 1408 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_32 + name: HUFFENC_AC0_32 + - byte_offset: 1412 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_33 + name: HUFFENC_AC0_33 + - byte_offset: 1416 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_34 + name: HUFFENC_AC0_34 + - byte_offset: 1420 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_35 + name: HUFFENC_AC0_35 + - byte_offset: 1424 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_36 + name: HUFFENC_AC0_36 + - byte_offset: 1428 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_37 + name: HUFFENC_AC0_37 + - byte_offset: 1432 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_38 + name: HUFFENC_AC0_38 + - byte_offset: 1436 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_39 + name: HUFFENC_AC0_39 + - byte_offset: 1440 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_40 + name: HUFFENC_AC0_40 + - byte_offset: 1444 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_41 + name: HUFFENC_AC0_41 + - byte_offset: 1448 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_42 + name: HUFFENC_AC0_42 + - byte_offset: 1452 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_43 + name: HUFFENC_AC0_43 + - byte_offset: 1456 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_44 + name: HUFFENC_AC0_44 + - byte_offset: 1460 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_45 + name: HUFFENC_AC0_45 + - byte_offset: 1464 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_46 + name: HUFFENC_AC0_46 + - byte_offset: 1468 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_47 + name: HUFFENC_AC0_47 + - byte_offset: 1472 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_48 + name: HUFFENC_AC0_48 + - byte_offset: 1476 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_49 + name: HUFFENC_AC0_49 + - byte_offset: 1480 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_50 + name: HUFFENC_AC0_50 + - byte_offset: 1484 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_51 + name: HUFFENC_AC0_51 + - byte_offset: 1488 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_52 + name: HUFFENC_AC0_52 + - byte_offset: 1492 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_53 + name: HUFFENC_AC0_53 + - byte_offset: 1496 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_54 + name: HUFFENC_AC0_54 + - byte_offset: 1500 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_55 + name: HUFFENC_AC0_55 + - byte_offset: 1504 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_56 + name: HUFFENC_AC0_56 + - byte_offset: 1508 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_57 + name: HUFFENC_AC0_57 + - byte_offset: 1512 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_58 + name: HUFFENC_AC0_58 + - byte_offset: 1516 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_59 + name: HUFFENC_AC0_59 + - byte_offset: 1520 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_60 + name: HUFFENC_AC0_60 + - byte_offset: 1524 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_61 + name: HUFFENC_AC0_61 + - byte_offset: 1528 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_62 + name: HUFFENC_AC0_62 + - byte_offset: 1532 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_63 + name: HUFFENC_AC0_63 + - byte_offset: 1536 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_64 + name: HUFFENC_AC0_64 + - byte_offset: 1540 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_65 + name: HUFFENC_AC0_65 + - byte_offset: 1544 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_66 + name: HUFFENC_AC0_66 + - byte_offset: 1548 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_67 + name: HUFFENC_AC0_67 + - byte_offset: 1552 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_68 + name: HUFFENC_AC0_68 + - byte_offset: 1556 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_69 + name: HUFFENC_AC0_69 + - byte_offset: 1560 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_70 + name: HUFFENC_AC0_70 + - byte_offset: 1564 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_71 + name: HUFFENC_AC0_71 + - byte_offset: 1568 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_72 + name: HUFFENC_AC0_72 + - byte_offset: 1572 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_73 + name: HUFFENC_AC0_73 + - byte_offset: 1576 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_74 + name: HUFFENC_AC0_74 + - byte_offset: 1580 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_75 + name: HUFFENC_AC0_75 + - byte_offset: 1584 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_76 + name: HUFFENC_AC0_76 + - byte_offset: 1588 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_77 + name: HUFFENC_AC0_77 + - byte_offset: 1592 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_78 + name: HUFFENC_AC0_78 + - byte_offset: 1596 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_79 + name: HUFFENC_AC0_79 + - byte_offset: 1600 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_80 + name: HUFFENC_AC0_80 + - byte_offset: 1604 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_81 + name: HUFFENC_AC0_81 + - byte_offset: 1608 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_82 + name: HUFFENC_AC0_82 + - byte_offset: 1612 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_83 + name: HUFFENC_AC0_83 + - byte_offset: 1616 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_84 + name: HUFFENC_AC0_84 + - byte_offset: 1620 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_85 + name: HUFFENC_AC0_85 + - byte_offset: 1624 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_86 + name: HUFFENC_AC0_86 + - byte_offset: 1628 + description: JPEG encoder, AC Huffman table 0 + fieldset: HUFFENC_AC0_87 + name: HUFFENC_AC0_87 + - byte_offset: 1632 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_0 + name: HUFFENC_AC1_0 + - byte_offset: 1636 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_1 + name: HUFFENC_AC1_1 + - byte_offset: 1640 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_2 + name: HUFFENC_AC1_2 + - byte_offset: 1644 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_3 + name: HUFFENC_AC1_3 + - byte_offset: 1648 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_4 + name: HUFFENC_AC1_4 + - byte_offset: 1652 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_5 + name: HUFFENC_AC1_5 + - byte_offset: 1656 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_6 + name: HUFFENC_AC1_6 + - byte_offset: 1660 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_7 + name: HUFFENC_AC1_7 + - byte_offset: 1664 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_8 + name: HUFFENC_AC1_8 + - byte_offset: 1668 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_9 + name: HUFFENC_AC1_9 + - byte_offset: 1672 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_10 + name: HUFFENC_AC1_10 + - byte_offset: 1676 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_11 + name: HUFFENC_AC1_11 + - byte_offset: 1680 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_12 + name: HUFFENC_AC1_12 + - byte_offset: 1684 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_13 + name: HUFFENC_AC1_13 + - byte_offset: 1688 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_14 + name: HUFFENC_AC1_14 + - byte_offset: 1692 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_15 + name: HUFFENC_AC1_15 + - byte_offset: 1696 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_16 + name: HUFFENC_AC1_16 + - byte_offset: 1700 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_17 + name: HUFFENC_AC1_17 + - byte_offset: 1704 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_18 + name: HUFFENC_AC1_18 + - byte_offset: 1708 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_19 + name: HUFFENC_AC1_19 + - byte_offset: 1712 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_20 + name: HUFFENC_AC1_20 + - byte_offset: 1716 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_21 + name: HUFFENC_AC1_21 + - byte_offset: 1720 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_22 + name: HUFFENC_AC1_22 + - byte_offset: 1724 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_23 + name: HUFFENC_AC1_23 + - byte_offset: 1728 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_24 + name: HUFFENC_AC1_24 + - byte_offset: 1732 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_25 + name: HUFFENC_AC1_25 + - byte_offset: 1736 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_26 + name: HUFFENC_AC1_26 + - byte_offset: 1740 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_27 + name: HUFFENC_AC1_27 + - byte_offset: 1744 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_28 + name: HUFFENC_AC1_28 + - byte_offset: 1748 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_29 + name: HUFFENC_AC1_29 + - byte_offset: 1752 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_30 + name: HUFFENC_AC1_30 + - byte_offset: 1756 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_31 + name: HUFFENC_AC1_31 + - byte_offset: 1760 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_32 + name: HUFFENC_AC1_32 + - byte_offset: 1764 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_33 + name: HUFFENC_AC1_33 + - byte_offset: 1768 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_34 + name: HUFFENC_AC1_34 + - byte_offset: 1772 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_35 + name: HUFFENC_AC1_35 + - byte_offset: 1776 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_36 + name: HUFFENC_AC1_36 + - byte_offset: 1780 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_37 + name: HUFFENC_AC1_37 + - byte_offset: 1784 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_38 + name: HUFFENC_AC1_38 + - byte_offset: 1788 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_39 + name: HUFFENC_AC1_39 + - byte_offset: 1792 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_40 + name: HUFFENC_AC1_40 + - byte_offset: 1796 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_41 + name: HUFFENC_AC1_41 + - byte_offset: 1800 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_42 + name: HUFFENC_AC1_42 + - byte_offset: 1804 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_43 + name: HUFFENC_AC1_43 + - byte_offset: 1808 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_44 + name: HUFFENC_AC1_44 + - byte_offset: 1812 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_45 + name: HUFFENC_AC1_45 + - byte_offset: 1816 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_46 + name: HUFFENC_AC1_46 + - byte_offset: 1820 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_47 + name: HUFFENC_AC1_47 + - byte_offset: 1824 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_48 + name: HUFFENC_AC1_48 + - byte_offset: 1828 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_49 + name: HUFFENC_AC1_49 + - byte_offset: 1832 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_50 + name: HUFFENC_AC1_50 + - byte_offset: 1836 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_51 + name: HUFFENC_AC1_51 + - byte_offset: 1840 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_52 + name: HUFFENC_AC1_52 + - byte_offset: 1844 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_53 + name: HUFFENC_AC1_53 + - byte_offset: 1848 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_54 + name: HUFFENC_AC1_54 + - byte_offset: 1852 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_55 + name: HUFFENC_AC1_55 + - byte_offset: 1856 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_56 + name: HUFFENC_AC1_56 + - byte_offset: 1860 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_57 + name: HUFFENC_AC1_57 + - byte_offset: 1864 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_58 + name: HUFFENC_AC1_58 + - byte_offset: 1868 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_59 + name: HUFFENC_AC1_59 + - byte_offset: 1872 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_60 + name: HUFFENC_AC1_60 + - byte_offset: 1876 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_61 + name: HUFFENC_AC1_61 + - byte_offset: 1880 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_62 + name: HUFFENC_AC1_62 + - byte_offset: 1884 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_63 + name: HUFFENC_AC1_63 + - byte_offset: 1888 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_64 + name: HUFFENC_AC1_64 + - byte_offset: 1892 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_65 + name: HUFFENC_AC1_65 + - byte_offset: 1896 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_66 + name: HUFFENC_AC1_66 + - byte_offset: 1900 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_67 + name: HUFFENC_AC1_67 + - byte_offset: 1904 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_68 + name: HUFFENC_AC1_68 + - byte_offset: 1908 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_69 + name: HUFFENC_AC1_69 + - byte_offset: 1912 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_70 + name: HUFFENC_AC1_70 + - byte_offset: 1916 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_71 + name: HUFFENC_AC1_71 + - byte_offset: 1920 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_72 + name: HUFFENC_AC1_72 + - byte_offset: 1924 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_73 + name: HUFFENC_AC1_73 + - byte_offset: 1928 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_74 + name: HUFFENC_AC1_74 + - byte_offset: 1932 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_75 + name: HUFFENC_AC1_75 + - byte_offset: 1936 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_76 + name: HUFFENC_AC1_76 + - byte_offset: 1940 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_77 + name: HUFFENC_AC1_77 + - byte_offset: 1944 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_78 + name: HUFFENC_AC1_78 + - byte_offset: 1948 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_79 + name: HUFFENC_AC1_79 + - byte_offset: 1952 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_80 + name: HUFFENC_AC1_80 + - byte_offset: 1956 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_81 + name: HUFFENC_AC1_81 + - byte_offset: 1960 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_82 + name: HUFFENC_AC1_82 + - byte_offset: 1964 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_83 + name: HUFFENC_AC1_83 + - byte_offset: 1968 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_84 + name: HUFFENC_AC1_84 + - byte_offset: 1972 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_85 + name: HUFFENC_AC1_85 + - byte_offset: 1976 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_86 + name: HUFFENC_AC1_86 + - byte_offset: 1980 + description: JPEG encoder, AC Huffman table 1 + fieldset: HUFFENC_AC1_87 + name: HUFFENC_AC1_87 + - byte_offset: 1984 + description: JPEG encoder, DC Huffman table 0 + fieldset: HUFFENC_DC0_0 + name: HUFFENC_DC0_0 + - byte_offset: 1988 + description: JPEG encoder, DC Huffman table 0 + fieldset: HUFFENC_DC0_1 + name: HUFFENC_DC0_1 + - byte_offset: 1992 + description: JPEG encoder, DC Huffman table 0 + fieldset: HUFFENC_DC0_2 + name: HUFFENC_DC0_2 + - byte_offset: 1996 + description: JPEG encoder, DC Huffman table 0 + fieldset: HUFFENC_DC0_3 + name: HUFFENC_DC0_3 + - byte_offset: 2000 + description: JPEG encoder, DC Huffman table 0 + fieldset: HUFFENC_DC0_4 + name: HUFFENC_DC0_4 + - byte_offset: 2004 + description: JPEG encoder, DC Huffman table 0 + fieldset: HUFFENC_DC0_5 + name: HUFFENC_DC0_5 + - byte_offset: 2008 + description: JPEG encoder, DC Huffman table 0 + fieldset: HUFFENC_DC0_6 + name: HUFFENC_DC0_6 + - byte_offset: 2012 + description: JPEG encoder, DC Huffman table 0 + fieldset: HUFFENC_DC0_7 + name: HUFFENC_DC0_7 + - byte_offset: 2016 + description: JPEG encoder, DC Huffman table 1 + fieldset: HUFFENC_DC1_0 + name: HUFFENC_DC1_0 + - byte_offset: 2020 + description: JPEG encoder, DC Huffman table 1 + fieldset: HUFFENC_DC1_1 + name: HUFFENC_DC1_1 + - byte_offset: 2024 + description: JPEG encoder, DC Huffman table 1 + fieldset: HUFFENC_DC1_2 + name: HUFFENC_DC1_2 + - byte_offset: 2028 + description: JPEG encoder, DC Huffman table 1 + fieldset: HUFFENC_DC1_3 + name: HUFFENC_DC1_3 + - byte_offset: 2032 + description: JPEG encoder, DC Huffman table 1 + fieldset: HUFFENC_DC1_4 + name: HUFFENC_DC1_4 + - byte_offset: 2036 + description: JPEG encoder, DC Huffman table 1 + fieldset: HUFFENC_DC1_5 + name: HUFFENC_DC1_5 + - byte_offset: 2040 + description: JPEG encoder, DC Huffman table 1 + fieldset: HUFFENC_DC1_6 + name: HUFFENC_DC1_6 + - byte_offset: 2044 + description: JPEG encoder, DC Huffman table 1 + fieldset: HUFFENC_DC1_7 + name: HUFFENC_DC1_7 +fieldset/DHTMEM0: + description: JPEG DHTMem tables + fields: + - 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bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE18: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE19: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE2: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE20: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE21: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE22: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE23: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE24: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE25: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE26: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE27: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE28: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE29: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE3: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE30: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE31: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE4: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE5: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE6: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE7: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE8: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFBASE9: + description: JPEG HuffSymb tables + fields: + - bit_offset: 0 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_0 + - bit_offset: 16 + bit_size: 9 + description: HuffBase RAM + name: HuffBase_RAM_1 +fieldset/HUFFENC_AC0_0: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_1: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_10: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_11: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_12: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_13: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_14: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_15: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_16: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_17: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_18: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_19: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_2: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_20: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_21: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_22: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_23: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_24: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_25: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_26: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_27: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_28: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_29: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_3: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_30: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_31: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_32: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_33: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_34: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_35: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_36: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_37: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_38: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_39: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_4: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_40: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_41: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_42: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_43: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_44: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_45: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_46: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_47: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_48: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_49: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_5: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_50: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_51: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_52: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_53: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_54: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_55: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_56: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_57: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_58: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_59: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_6: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_60: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_61: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_62: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_63: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_64: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_65: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_66: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_67: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_68: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_69: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_7: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_70: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_71: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_72: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_73: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_74: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_75: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_76: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_77: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_78: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_79: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_8: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_80: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_81: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_82: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_83: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_84: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_85: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_86: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_87: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC0_9: + description: JPEG encoder, AC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_0: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_1: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_10: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_11: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_12: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_13: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_14: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_15: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_16: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_17: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_18: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_19: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_2: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_20: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_21: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_22: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_23: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_24: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_25: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_26: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_27: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_28: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_29: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_3: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_30: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_31: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_32: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_33: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_34: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_35: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_36: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_37: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_38: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_39: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_4: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_40: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_41: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_42: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_43: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_44: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_45: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_46: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_47: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_48: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_49: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_5: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_50: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_51: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_52: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_53: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_54: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_55: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_56: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_57: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_58: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_59: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_6: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_60: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_61: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_62: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_63: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_64: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_65: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_66: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_67: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_68: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_69: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_7: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_70: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_71: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_72: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_73: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_74: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_75: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_76: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_77: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_78: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_79: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_8: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_80: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_81: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_82: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_83: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_84: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_85: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_86: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_87: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_AC1_9: + description: JPEG encoder, AC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC0_0: + description: JPEG encoder, DC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC0_1: + description: JPEG encoder, DC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC0_2: + description: JPEG encoder, DC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC0_3: + description: JPEG encoder, DC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC0_4: + description: JPEG encoder, DC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC0_5: + description: JPEG encoder, DC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC0_6: + description: JPEG encoder, DC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC0_7: + description: JPEG encoder, DC Huffman table 0 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC1_0: + description: JPEG encoder, DC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC1_1: + description: JPEG encoder, DC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC1_2: + description: JPEG encoder, DC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC1_3: + description: JPEG encoder, DC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC1_4: + description: JPEG encoder, DC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC1_5: + description: JPEG encoder, DC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC1_6: + description: JPEG encoder, DC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFENC_DC1_7: + description: JPEG encoder, DC Huffman table 1 + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTMem RAM + name: DHTMem_RAM +fieldset/HUFFMIN_0: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_1: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_10: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_11: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_12: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_13: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_14: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_15: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_2: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_3: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_4: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_5: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_6: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_7: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_8: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFMIN_9: + description: JPEG HuffMin tables + fields: + - bit_offset: 0 + bit_size: 32 + description: HuffMin RAM + name: HuffMin_RAM +fieldset/HUFFSYMB0: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB1: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB10: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB11: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB12: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB13: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB14: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB15: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB16: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB17: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB18: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB19: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB2: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB20: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB21: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB22: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB23: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB24: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB25: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB26: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB27: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB28: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB29: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB3: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB30: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB31: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB32: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB33: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB34: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB35: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB36: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB37: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB38: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB39: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB4: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB40: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB41: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB42: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB43: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB44: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB45: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB46: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB47: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB48: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB49: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB5: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB50: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB51: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB52: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB53: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB54: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB55: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB56: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB57: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB58: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB59: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB6: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB60: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB61: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB62: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB63: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB64: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB65: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB66: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB67: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB68: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB69: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB7: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB70: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB71: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB72: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB73: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB74: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB75: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB76: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB77: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB78: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB79: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB8: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB80: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB81: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB82: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB83: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/HUFFSYMB9: + description: JPEG HUFFSYMB tables + fields: + - bit_offset: 0 + bit_size: 32 + description: DHTSymb RAM + name: HuffSymb_RAM +fieldset/JPEG_CFR: + description: JPEG clear flag register + fields: + - bit_offset: 5 + bit_size: 1 + description: Clear End of Conversion Flag + name: CEOCF + - bit_offset: 6 + bit_size: 1 + description: Clear Header Parsing Done Flag + name: CHPDF +fieldset/JPEG_CONFR0: + description: JPEG codec configuration register 0 + fields: + - bit_offset: 0 + bit_size: 1 + description: Start + name: START +fieldset/JPEG_CONFR1: + description: JPEG codec configuration register 1 + fields: + - bit_offset: 0 + bit_size: 2 + description: Number of color components + name: NF + - bit_offset: 3 + bit_size: 1 + description: Decoding Enable + name: DE + - bit_offset: 4 + bit_size: 2 + description: Color Space + name: COLORSPACE + - bit_offset: 6 + bit_size: 2 + description: Number of components for Scan + name: NS + - bit_offset: 8 + bit_size: 1 + description: Header Processing + name: HDR + - bit_offset: 16 + bit_size: 16 + description: Y Size + name: YSIZE +fieldset/JPEG_CONFR2: + description: JPEG codec configuration register 2 + fields: + - bit_offset: 0 + bit_size: 26 + description: Number of MCU + name: NMCU +fieldset/JPEG_CONFR3: + description: JPEG codec configuration register 3 + fields: + - bit_offset: 16 + bit_size: 16 + description: X size + name: XSIZE +fieldset/JPEG_CONFR4: + description: JPEG codec configuration register 4 + fields: + - bit_offset: 0 + bit_size: 1 + description: Huffman DC + name: HD + - bit_offset: 1 + bit_size: 1 + description: Huffman AC + name: HA + - bit_offset: 2 + bit_size: 2 + description: Quantization Table + name: QT + - bit_offset: 4 + bit_size: 4 + description: Number of Block + name: NB + - bit_offset: 8 + bit_size: 4 + description: Vertical Sampling Factor + name: VSF + - bit_offset: 12 + bit_size: 4 + description: Horizontal Sampling Factor + name: HSF +fieldset/JPEG_CONFR5: + description: JPEG codec configuration register 5 + fields: + - bit_offset: 0 + bit_size: 1 + description: Huffman DC + name: HD + - bit_offset: 1 + bit_size: 1 + description: Huffman AC + name: HA + - bit_offset: 2 + bit_size: 2 + description: Quantization Table + name: QT + - bit_offset: 4 + bit_size: 4 + description: Number of Block + name: NB + - bit_offset: 8 + bit_size: 4 + description: Vertical Sampling Factor + name: VSF + - bit_offset: 12 + bit_size: 4 + description: Horizontal Sampling Factor + name: HSF +fieldset/JPEG_CONFR6: + description: JPEG codec configuration register 6 + fields: + - bit_offset: 0 + bit_size: 1 + description: Huffman DC + name: HD + - bit_offset: 1 + bit_size: 1 + description: Huffman AC + name: HA + - bit_offset: 2 + bit_size: 2 + description: Quantization Table + name: QT + - bit_offset: 4 + bit_size: 4 + description: Number of Block + name: NB + - bit_offset: 8 + bit_size: 4 + description: Vertical Sampling Factor + name: VSF + - bit_offset: 12 + bit_size: 4 + description: Horizontal Sampling Factor + name: HSF +fieldset/JPEG_CONFR7: + description: JPEG codec configuration register 7 + fields: + - bit_offset: 0 + bit_size: 1 + description: Huffman DC + name: HD + - bit_offset: 1 + bit_size: 1 + description: Huffman AC + name: HA + - bit_offset: 2 + bit_size: 2 + description: Quantization Table + name: QT + - bit_offset: 4 + bit_size: 4 + description: Number of Block + name: NB + - bit_offset: 8 + bit_size: 4 + description: Vertical Sampling Factor + name: VSF + - bit_offset: 12 + bit_size: 4 + description: Horizontal Sampling Factor + name: HSF +fieldset/JPEG_CR: + description: JPEG control register + fields: + - bit_offset: 0 + bit_size: 1 + description: JPEG Core Enable + name: JCEN + - bit_offset: 1 + bit_size: 1 + description: Input FIFO Threshold Interrupt Enable + name: IFTIE + - bit_offset: 2 + bit_size: 1 + description: Input FIFO Not Full Interrupt Enable + name: IFNFIE + - bit_offset: 3 + bit_size: 1 + description: Output FIFO Threshold Interrupt Enable + name: OFTIE + - bit_offset: 4 + bit_size: 1 + description: Output FIFO Not Empty Interrupt Enable + name: OFNEIE + - bit_offset: 5 + bit_size: 1 + description: End of Conversion Interrupt Enable + name: EOCIE + - bit_offset: 6 + bit_size: 1 + description: Header Parsing Done Interrupt Enable + name: HPDIE + - bit_offset: 11 + bit_size: 1 + description: Input DMA Enable + name: IDMAEN + - bit_offset: 12 + bit_size: 1 + description: Output DMA Enable + name: ODMAEN + - bit_offset: 13 + bit_size: 1 + description: Input FIFO Flush + name: IFF + - bit_offset: 14 + bit_size: 1 + description: Output FIFO Flush + name: 'OFF' +fieldset/JPEG_DIR: + description: JPEG data input register + fields: + - bit_offset: 0 + bit_size: 32 + description: Data Input FIFO + name: DATAIN +fieldset/JPEG_DOR: + description: JPEG data output register + fields: + - bit_offset: 0 + bit_size: 32 + description: Data Output FIFO + name: DATAOUT +fieldset/JPEG_SR: + description: JPEG status register + fields: + - bit_offset: 1 + bit_size: 1 + description: Input FIFO Threshold Flag + name: IFTF + - bit_offset: 2 + bit_size: 1 + description: Input FIFO Not Full Flag + name: IFNFF + - bit_offset: 3 + bit_size: 1 + description: Output FIFO Threshold Flag + name: OFTF + - bit_offset: 4 + bit_size: 1 + description: Output FIFO Not Empty Flag + name: OFNEF + - bit_offset: 5 + bit_size: 1 + description: End of Conversion Flag + name: EOCF + - bit_offset: 6 + bit_size: 1 + description: Header Parsing Done Flag + name: HPDF + - bit_offset: 7 + bit_size: 1 + description: Codec Operation Flag + name: COF +fieldset/QMEM0_0: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_1: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_10: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_11: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_12: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_13: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_14: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_15: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_2: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_3: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_4: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_5: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_6: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_7: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_8: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM0_9: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_0: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_1: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_10: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_11: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_12: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_13: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_14: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_15: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_2: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_3: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_4: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_5: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_6: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_7: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_8: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM1_9: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_0: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_1: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_10: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_11: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_12: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_13: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_14: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_15: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_2: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_3: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_4: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_5: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_6: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_7: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_8: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM2_9: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_0: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_1: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_10: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_11: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_12: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_13: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_14: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_15: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_2: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_3: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_4: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_5: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_6: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_7: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_8: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM +fieldset/QMEM3_9: + description: JPEG quantization tables + fields: + - bit_offset: 0 + bit_size: 32 + description: QMem RAM + name: QMem_RAM diff --git a/data/registers/lptim_v1.yaml b/data/registers/lptim_v1.yaml new file mode 100644 index 0000000..e72e219 --- /dev/null +++ b/data/registers/lptim_v1.yaml @@ -0,0 +1,223 @@ +--- +block/LPTIM: + description: Low power timer + items: + - access: Read + byte_offset: 0 + description: Interrupt and Status Register + fieldset: ISR + name: ISR + - access: Write + byte_offset: 4 + description: Interrupt Clear Register + fieldset: ICR + name: ICR + - byte_offset: 8 + description: Interrupt Enable Register + fieldset: IER + name: IER + - byte_offset: 12 + description: Configuration Register + fieldset: CFGR + name: CFGR + - byte_offset: 16 + description: Control Register + fieldset: CR + name: CR + - byte_offset: 20 + description: Compare Register + fieldset: CMP + name: CMP + - byte_offset: 24 + description: Autoreload Register + fieldset: ARR + name: ARR + - access: Read + byte_offset: 28 + description: Counter Register + fieldset: CNT + name: CNT +fieldset/ARR: + description: Autoreload Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Auto reload value + name: ARR +fieldset/CFGR: + description: Configuration Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Clock selector + name: CKSEL + - bit_offset: 1 + bit_size: 2 + description: Clock Polarity + name: CKPOL + - bit_offset: 3 + bit_size: 2 + description: Configurable digital filter for external clock + name: CKFLT + - bit_offset: 6 + bit_size: 2 + description: Configurable digital filter for trigger + name: TRGFLT + - bit_offset: 9 + bit_size: 3 + description: Clock prescaler + name: PRESC + - bit_offset: 13 + bit_size: 3 + description: Trigger selector + name: TRIGSEL + - bit_offset: 17 + bit_size: 2 + description: Trigger enable and polarity + name: TRIGEN + - bit_offset: 19 + bit_size: 1 + description: Timeout enable + name: TIMOUT + - bit_offset: 20 + bit_size: 1 + description: Waveform shape + name: WAVE + - bit_offset: 21 + bit_size: 1 + description: Waveform shape polarity + name: WAVPOL + - bit_offset: 22 + bit_size: 1 + description: Registers update mode + name: PRELOAD + - bit_offset: 23 + bit_size: 1 + description: counter mode enabled + name: COUNTMODE + - bit_offset: 24 + bit_size: 1 + description: Encoder mode enable + name: ENC +fieldset/CMP: + description: Compare Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Compare value + name: CMP +fieldset/CNT: + description: Counter Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Counter value + name: CNT +fieldset/CR: + description: Control Register + fields: + - bit_offset: 0 + bit_size: 1 + description: LPTIM Enable + name: ENABLE + - bit_offset: 1 + bit_size: 1 + description: LPTIM start in single mode + name: SNGSTRT + - bit_offset: 2 + bit_size: 1 + description: Timer start in continuous mode + name: CNTSTRT +fieldset/ICR: + description: Interrupt Clear Register + fields: + - bit_offset: 0 + bit_size: 1 + description: compare match Clear Flag + name: CMPMCF + - bit_offset: 1 + bit_size: 1 + description: Autoreload match Clear Flag + name: ARRMCF + - bit_offset: 2 + bit_size: 1 + description: External trigger valid edge Clear Flag + name: EXTTRIGCF + - bit_offset: 3 + bit_size: 1 + description: Compare register update OK Clear Flag + name: CMPOKCF + - bit_offset: 4 + bit_size: 1 + description: Autoreload register update OK Clear Flag + name: ARROKCF + - bit_offset: 5 + bit_size: 1 + description: Direction change to UP Clear Flag + name: UPCF + - bit_offset: 6 + bit_size: 1 + description: Direction change to down Clear Flag + name: DOWNCF +fieldset/IER: + description: Interrupt Enable Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Compare match Interrupt Enable + name: CMPMIE + - bit_offset: 1 + bit_size: 1 + description: Autoreload match Interrupt Enable + name: ARRMIE + - bit_offset: 2 + bit_size: 1 + description: External trigger valid edge Interrupt Enable + name: EXTTRIGIE + - bit_offset: 3 + bit_size: 1 + description: Compare register update OK Interrupt Enable + name: CMPOKIE + - bit_offset: 4 + bit_size: 1 + description: Autoreload register update OK Interrupt Enable + name: ARROKIE + - bit_offset: 5 + bit_size: 1 + description: Direction change to UP Interrupt Enable + name: UPIE + - bit_offset: 6 + bit_size: 1 + description: Direction change to down Interrupt Enable + name: DOWNIE +fieldset/ISR: + description: Interrupt and Status Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Compare match + name: CMPM + - bit_offset: 1 + bit_size: 1 + description: Autoreload match + name: ARRM + - bit_offset: 2 + bit_size: 1 + description: External trigger edge event + name: EXTTRIG + - bit_offset: 3 + bit_size: 1 + description: Compare register update OK + name: CMPOK + - bit_offset: 4 + bit_size: 1 + description: Autoreload register update OK + name: ARROK + - bit_offset: 5 + bit_size: 1 + description: Counter direction change down to up + name: UP + - bit_offset: 6 + bit_size: 1 + description: Counter direction change up to down + name: DOWN diff --git a/data/registers/ltdc_v1.yaml b/data/registers/ltdc_v1.yaml new file mode 100644 index 0000000..db13233 --- /dev/null +++ b/data/registers/ltdc_v1.yaml @@ -0,0 +1,774 @@ +--- +block/LAYER: + description: Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, + L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + items: + - byte_offset: 0 + description: Layerx Control Register + fieldset: CR + name: CR + - byte_offset: 4 + description: Layerx Window Horizontal Position Configuration Register + fieldset: WHPCR + name: WHPCR + - byte_offset: 8 + description: Layerx Window Vertical Position Configuration Register + fieldset: WVPCR + name: WVPCR + - byte_offset: 12 + description: Layerx Color Keying Configuration Register + fieldset: CKCR + name: CKCR + - byte_offset: 16 + description: Layerx Pixel Format Configuration Register + fieldset: PFCR + name: PFCR + - byte_offset: 20 + description: Layerx Constant Alpha Configuration Register + fieldset: CACR + name: CACR + - byte_offset: 24 + description: Layerx Default Color Configuration Register + fieldset: DCCR + name: DCCR + - byte_offset: 28 + description: Layerx Blending Factors Configuration Register + fieldset: BFCR + name: BFCR + - byte_offset: 40 + description: Layerx Color Frame Buffer Address Register + fieldset: CFBAR + name: CFBAR + - byte_offset: 44 + description: Layerx Color Frame Buffer Length Register + fieldset: CFBLR + name: CFBLR + - byte_offset: 48 + description: Layerx ColorFrame Buffer Line Number Register + fieldset: CFBLNR + name: CFBLNR + - access: Write + byte_offset: 64 + description: Layerx CLUT Write Register + fieldset: CLUTWR + name: CLUTWR +block/LTDC: + description: LCD-TFT Controller + items: + - byte_offset: 8 + description: Synchronization Size Configuration Register + fieldset: SSCR + name: SSCR + - byte_offset: 12 + description: Back Porch Configuration Register + fieldset: BPCR + name: BPCR + - byte_offset: 16 + description: Active Width Configuration Register + fieldset: AWCR + name: AWCR + - byte_offset: 20 + description: Total Width Configuration Register + fieldset: TWCR + name: TWCR + - byte_offset: 24 + description: Global Control Register + fieldset: GCR + name: GCR + - byte_offset: 36 + description: Shadow Reload Configuration Register + fieldset: SRCR + name: SRCR + - byte_offset: 44 + description: Background Color Configuration Register + fieldset: BCCR + name: BCCR + - byte_offset: 52 + description: Interrupt Enable Register + fieldset: IER + name: IER + - access: Read + byte_offset: 56 + description: Interrupt Status Register + fieldset: ISR + name: ISR + - access: Write + byte_offset: 60 + description: Interrupt Clear Register + fieldset: ICR + name: ICR + - byte_offset: 64 + description: Line Interrupt Position Configuration Register + fieldset: LIPCR + name: LIPCR + - access: Read + byte_offset: 68 + description: Current Position Status Register + fieldset: CPSR + name: CPSR + - access: Read + byte_offset: 72 + description: Current Display Status Register + fieldset: CDSR + name: CDSR + - array: + len: 2 + stride: 128 + block: LAYER + byte_offset: 132 + description: Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, + L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR + name: LAYER +enum/BF1: + bit_size: 3 + variants: + - description: BF1 = constant alpha + name: Constant + value: 4 + - description: BF1 = pixel alpha * constant alpha + name: Pixel + value: 6 +enum/BF2: + bit_size: 3 + variants: + - description: BF2 = 1 - constant alpha + name: Constant + value: 5 + - description: BF2 = 1 - pixel alpha * constant alpha + name: Pixel + value: 7 +enum/CFUIF: + bit_size: 1 + variants: + - description: Clears the FUIF flag in the ISR register + name: Clear + value: 1 +enum/CLIF: + bit_size: 1 + variants: + - description: Clears the LIF flag in the ISR register + name: Clear + value: 1 +enum/CLUTEN: + bit_size: 1 + variants: + - description: Color look-up table disabled + name: Disabled + value: 0 + - description: Color look-up table enabled + name: Enabled + value: 1 +enum/COLKEN: + bit_size: 1 + variants: + - description: Color keying disabled + name: Disabled + value: 0 + - description: Color keying enabled + name: Enabled + value: 1 +enum/CRRIF: + bit_size: 1 + variants: + - description: Clears the RRIF flag in the ISR register + name: Clear + value: 1 +enum/CTERRIF: + bit_size: 1 + variants: + - description: Clears the TERRIF flag in the ISR register + name: Clear + value: 1 +enum/DEN: + bit_size: 1 + variants: + - description: Dither disabled + name: Disabled + value: 0 + - description: Dither enabled + name: Enabled + value: 1 +enum/DEPOL: + bit_size: 1 + variants: + - description: Data enable polarity is active low + name: ActiveLow + value: 0 + - description: Data enable polarity is active high + name: ActiveHigh + value: 1 +enum/FUIE: + bit_size: 1 + variants: + - description: FIFO underrun interrupt disabled + name: Disabled + value: 0 + - description: FIFO underrun interrupt enabled + name: Enabled + value: 1 +enum/FUIF: + bit_size: 1 + variants: + - description: No FIFO underrun + name: NoUnderrun + value: 0 + - description: FIFO underrun interrupt generated, if one of the layer FIFOs is empty + and pixel data is read from the FIFO + name: Underrun + value: 1 +enum/HDES: + bit_size: 1 + variants: + - description: Currently not in horizontal Data Enable phase + name: NotActive + value: 0 + - description: Currently in horizontal Data Enable phase + name: Active + value: 1 +enum/HSPOL: + bit_size: 1 + variants: + - description: Horizontal synchronization polarity is active low + name: ActiveLow + value: 0 + - description: Horizontal synchronization polarity is active high + name: ActiveHigh + value: 1 +enum/HSYNCS: + bit_size: 1 + variants: + - description: Currently not in HSYNC phase + name: NotActive + value: 0 + - description: Currently in HSYNC phase + name: Active + value: 1 +enum/IMR: + bit_size: 1 + variants: + - description: This bit is set by software and cleared only by hardware after reload + (it cannot be cleared through register write once it is set) + name: NoEffect + value: 0 + - description: The shadow registers are reloaded immediately. This bit is set by + software and cleared only by hardware after reload + name: Reload + value: 1 +enum/LEN: + bit_size: 1 + variants: + - description: Layer disabled + name: Disabled + value: 0 + - description: Layer enabled + name: Enabled + value: 1 +enum/LIE: + bit_size: 1 + variants: + - description: Line interrupt disabled + name: Disabled + value: 0 + - description: Line interrupt enabled + name: Enabled + value: 1 +enum/LIF: + bit_size: 1 + variants: + - description: Programmed line not reached + name: NotReached + value: 0 + - description: Line interrupt generated when a programmed line is reached + name: Reached + value: 1 +enum/LTDCEN: + bit_size: 1 + variants: + - description: LCD-TFT controller disabled + name: Disabled + value: 0 + - description: LCD-TFT controller enabled + name: Enabled + value: 1 +enum/PCPOL: + bit_size: 1 + variants: + - description: Pixel clock on rising edge + name: RisingEdge + value: 0 + - description: Pixel clock on falling edge + name: FallingEdge + value: 1 +enum/PF: + bit_size: 3 + variants: + - description: ARGB8888 + name: ARGB8888 + value: 0 + - description: RGB888 + name: RGB888 + value: 1 + - description: RGB565 + name: RGB565 + value: 2 + - description: ARGB1555 + name: ARGB1555 + value: 3 + - description: ARGB4444 + name: ARGB4444 + value: 4 + - description: L8 (8-bit luminance) + name: L8 + value: 5 + - description: AL44 (4-bit alpha, 4-bit luminance) + name: AL44 + value: 6 + - description: AL88 (8-bit alpha, 8-bit luminance) + name: AL88 + value: 7 +enum/RRIE: + bit_size: 1 + variants: + - description: Register reload interrupt disabled + name: Disabled + value: 0 + - description: Register reload interrupt enabled + name: Enabled + value: 1 +enum/RRIF: + bit_size: 1 + variants: + - description: No register reload + name: NoReload + value: 0 + - description: Register reload interrupt generated when a vertical blanking reload + occurs (and the first line after the active area is reached) + name: Reload + value: 1 +enum/TERRIE: + bit_size: 1 + variants: + - description: Transfer error interrupt disabled + name: Disabled + value: 0 + - description: Transfer error interrupt enabled + name: Enabled + value: 1 +enum/TERRIF: + bit_size: 1 + variants: + - description: No transfer error + name: NoError + value: 0 + - description: Transfer error interrupt generated when a bus error occurs + name: Error + value: 1 +enum/VBR: + bit_size: 1 + variants: + - description: This bit is set by software and cleared only by hardware after reload + (it cannot be cleared through register write once it is set) + name: NoEffect + value: 0 + - description: The shadow registers are reloaded during the vertical blanking period + (at the beginning of the first line after the active display area). + name: Reload + value: 1 +enum/VDES: + bit_size: 1 + variants: + - description: Currently not in vertical Data Enable phase + name: NotActive + value: 0 + - description: Currently in vertical Data Enable phase + name: Active + value: 1 +enum/VSPOL: + bit_size: 1 + variants: + - description: Vertical synchronization polarity is active low + name: ActiveLow + value: 0 + - description: Vertical synchronization polarity is active high + name: ActiveHigh + value: 1 +enum/VSYNCS: + bit_size: 1 + variants: + - description: Currently not in VSYNC phase + name: NotActive + value: 0 + - description: Currently in VSYNC phase + name: Active + value: 1 +fieldset/AWCR: + description: Active Width Configuration Register + fields: + - bit_offset: 0 + bit_size: 11 + description: Accumulated Active Height (in units of horizontal scan line) + name: AAH + - bit_offset: 16 + bit_size: 12 + description: Accumulated Active Width (in units of pixel clock period) + name: AAW +fieldset/BCCR: + description: Background Color Configuration Register + fields: + - bit_offset: 0 + bit_size: 8 + description: Background color blue value + name: BCBLUE + - bit_offset: 8 + bit_size: 8 + description: Background color green value + name: BCGREEN + - bit_offset: 16 + bit_size: 8 + description: Background color red value + name: BCRED +fieldset/BFCR: + description: Layerx Blending Factors Configuration Register + fields: + - array: + len: 2 + stride: 8 + bit_offset: 0 + bit_size: 3 + description: Blending Factor 2 + enum: BF2 + name: BF +fieldset/BPCR: + description: Back Porch Configuration Register + fields: + - bit_offset: 0 + bit_size: 11 + description: Accumulated Vertical back porch (in units of horizontal scan line) + name: AVBP + - bit_offset: 16 + bit_size: 12 + description: Accumulated Horizontal back porch (in units of pixel clock period) + name: AHBP +fieldset/CACR: + description: Layerx Constant Alpha Configuration Register + fields: + - bit_offset: 0 + bit_size: 8 + description: Constant Alpha + name: CONSTA +fieldset/CDSR: + description: Current Display Status Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Vertical Data Enable display Status + enum: VDES + name: VDES + - bit_offset: 1 + bit_size: 1 + description: Horizontal Data Enable display Status + enum: HDES + name: HDES + - bit_offset: 2 + bit_size: 1 + description: Vertical Synchronization display Status + enum: VSYNCS + name: VSYNCS + - bit_offset: 3 + bit_size: 1 + description: Horizontal Synchronization display Status + enum: HSYNCS + name: HSYNCS +fieldset/CFBAR: + description: Layerx Color Frame Buffer Address Register + fields: + - bit_offset: 0 + bit_size: 32 + description: Color Frame Buffer Start Address + name: CFBADD +fieldset/CFBLNR: + description: Layerx ColorFrame Buffer Line Number Register + fields: + - bit_offset: 0 + bit_size: 11 + description: Frame Buffer Line Number + name: CFBLNBR +fieldset/CFBLR: + description: Layerx Color Frame Buffer Length Register + fields: + - bit_offset: 0 + bit_size: 13 + description: Color Frame Buffer Line Length + name: CFBLL + - bit_offset: 16 + bit_size: 13 + description: Color Frame Buffer Pitch in bytes + name: CFBP +fieldset/CKCR: + description: Layerx Color Keying Configuration Register + fields: + - bit_offset: 0 + bit_size: 8 + description: Color Key Blue value + name: CKBLUE + - bit_offset: 8 + bit_size: 8 + description: Color Key Green value + name: CKGREEN + - bit_offset: 16 + bit_size: 8 + description: Color Key Red value + name: CKRED +fieldset/CLUTWR: + description: Layerx CLUT Write Register + fields: + - bit_offset: 0 + bit_size: 8 + description: Blue value + name: BLUE + - bit_offset: 8 + bit_size: 8 + description: Green value + name: GREEN + - bit_offset: 16 + bit_size: 8 + description: Red value + name: RED + - bit_offset: 24 + bit_size: 8 + description: CLUT Address + name: CLUTADD +fieldset/CPSR: + description: Current Position Status Register + fields: + - bit_offset: 0 + bit_size: 16 + description: Current Y Position + name: CYPOS + - bit_offset: 16 + bit_size: 16 + description: Current X Position + name: CXPOS +fieldset/CR: + description: Layerx Control Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Layer Enable + enum: LEN + name: LEN + - bit_offset: 1 + bit_size: 1 + description: Color Keying Enable + enum: COLKEN + name: COLKEN + - bit_offset: 4 + bit_size: 1 + description: Color Look-Up Table Enable + enum: CLUTEN + name: CLUTEN +fieldset/DCCR: + description: Layerx Default Color Configuration Register + fields: + - bit_offset: 0 + bit_size: 8 + description: Default Color Blue + name: DCBLUE + - bit_offset: 8 + bit_size: 8 + description: Default Color Green + name: DCGREEN + - bit_offset: 16 + bit_size: 8 + description: Default Color Red + name: DCRED + - bit_offset: 24 + bit_size: 8 + description: Default Color Alpha + name: DCALPHA +fieldset/GCR: + description: Global Control Register + fields: + - bit_offset: 0 + bit_size: 1 + description: LCD-TFT controller enable bit + enum: LTDCEN + name: LTDCEN + - bit_offset: 4 + bit_size: 3 + description: Dither Blue Width + name: DBW + - bit_offset: 8 + bit_size: 3 + description: Dither Green Width + name: DGW + - bit_offset: 12 + bit_size: 3 + description: Dither Red Width + name: DRW + - bit_offset: 16 + bit_size: 1 + description: Dither Enable + enum: DEN + name: DEN + - bit_offset: 28 + bit_size: 1 + description: Pixel Clock Polarity + enum: PCPOL + name: PCPOL + - bit_offset: 29 + bit_size: 1 + description: Data Enable Polarity + enum: DEPOL + name: DEPOL + - bit_offset: 30 + bit_size: 1 + description: Vertical Synchronization Polarity + enum: VSPOL + name: VSPOL + - bit_offset: 31 + bit_size: 1 + description: Horizontal Synchronization Polarity + enum: HSPOL + name: HSPOL +fieldset/ICR: + description: Interrupt Clear Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Clears the Line Interrupt Flag + enum: CLIF + name: CLIF + - bit_offset: 1 + bit_size: 1 + description: Clears the FIFO Underrun Interrupt flag + enum: CFUIF + name: CFUIF + - bit_offset: 2 + bit_size: 1 + description: Clears the Transfer Error Interrupt Flag + enum: CTERRIF + name: CTERRIF + - bit_offset: 3 + bit_size: 1 + description: Clears Register Reload Interrupt Flag + enum: CRRIF + name: CRRIF +fieldset/IER: + description: Interrupt Enable Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Line Interrupt Enable + enum: LIE + name: LIE + - bit_offset: 1 + bit_size: 1 + description: FIFO Underrun Interrupt Enable + enum: FUIE + name: FUIE + - bit_offset: 2 + bit_size: 1 + description: Transfer Error Interrupt Enable + enum: TERRIE + name: TERRIE + - bit_offset: 3 + bit_size: 1 + description: Register Reload interrupt enable + enum: RRIE + name: RRIE +fieldset/ISR: + description: Interrupt Status Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Line Interrupt flag + enum: LIF + name: LIF + - bit_offset: 1 + bit_size: 1 + description: FIFO Underrun Interrupt flag + enum: FUIF + name: FUIF + - bit_offset: 2 + bit_size: 1 + description: Transfer Error interrupt flag + enum: TERRIF + name: TERRIF + - bit_offset: 3 + bit_size: 1 + description: Register Reload Interrupt Flag + enum: RRIF + name: RRIF +fieldset/LIPCR: + description: Line Interrupt Position Configuration Register + fields: + - bit_offset: 0 + bit_size: 11 + description: Line Interrupt Position + name: LIPOS +fieldset/PFCR: + description: Layerx Pixel Format Configuration Register + fields: + - bit_offset: 0 + bit_size: 3 + description: Pixel Format + enum: PF + name: PF +fieldset/SRCR: + description: Shadow Reload Configuration Register + fields: + - bit_offset: 0 + bit_size: 1 + description: Immediate Reload + enum: IMR + name: IMR + - bit_offset: 1 + bit_size: 1 + description: Vertical Blanking Reload + enum: VBR + name: VBR +fieldset/SSCR: + description: Synchronization Size Configuration Register + fields: + - bit_offset: 0 + bit_size: 11 + description: Vertical Synchronization Height (in units of horizontal scan line) + name: VSH + - bit_offset: 16 + bit_size: 12 + description: Horizontal Synchronization Width (in units of pixel clock period) + name: HSW +fieldset/TWCR: + description: Total Width Configuration Register + fields: + - bit_offset: 0 + bit_size: 11 + description: Total Height (in units of horizontal scan line) + name: TOTALH + - bit_offset: 16 + bit_size: 12 + description: Total Width (in units of pixel clock period) + name: TOTALW +fieldset/WHPCR: + description: Layerx Window Horizontal Position Configuration Register + fields: + - bit_offset: 0 + bit_size: 12 + description: Window Horizontal Start Position + name: WHSTPOS + - bit_offset: 16 + bit_size: 12 + description: Window Horizontal Stop Position + name: WHSPPOS +fieldset/WVPCR: + description: Layerx Window Vertical Position Configuration Register + fields: + - bit_offset: 0 + bit_size: 11 + description: Window Vertical Start Position + name: WVSTPOS + - bit_offset: 16 + bit_size: 11 + description: Window Vertical Stop Position + name: WVSPPOS diff --git a/data/registers/mdios_v1.yaml b/data/registers/mdios_v1.yaml new file mode 100644 index 0000000..f456733 --- /dev/null +++ b/data/registers/mdios_v1.yaml @@ -0,0 +1,1193 @@ +--- +block/MDIOS: + description: Management data input/output slave + items: + - byte_offset: 0 + description: MDIOS configuration register + fieldset: MDIOS_CR + name: MDIOS_CR + - byte_offset: 0 + description: MDIOS configuration register + fieldset: CR + name: CR + - access: Read + byte_offset: 4 + description: MDIOS write flag register + fieldset: MDIOS_WRFR + name: MDIOS_WRFR + - access: Read + byte_offset: 4 + description: MDIOS write flag register + fieldset: WRFR + name: WRFR + - byte_offset: 8 + description: MDIOS clear write flag register + fieldset: MDIOS_CWRFR + name: MDIOS_CWRFR + - byte_offset: 8 + description: MDIOS clear write flag register + fieldset: CWRFR + name: CWRFR + - access: Read + byte_offset: 12 + description: MDIOS read flag register + fieldset: MDIOS_RDFR + name: MDIOS_RDFR + - access: Read + byte_offset: 12 + description: MDIOS read flag register + fieldset: RDFR + name: RDFR + - byte_offset: 16 + description: MDIOS clear read flag register + fieldset: MDIOS_CRDFR + name: MDIOS_CRDFR + - byte_offset: 16 + description: MDIOS clear read flag register + fieldset: CRDFR + name: CRDFR + - access: Read + byte_offset: 20 + description: MDIOS status register + fieldset: MDIOS_SR + name: MDIOS_SR + - access: Read + byte_offset: 20 + description: MDIOS status register + fieldset: SR + name: SR + - byte_offset: 24 + description: MDIOS clear flag register + fieldset: MDIOS_CLRFR + name: MDIOS_CLRFR + - byte_offset: 24 + description: MDIOS clear flag register + fieldset: CLRFR + name: CLRFR + - access: Read + byte_offset: 28 + description: MDIOS input data register 0 + fieldset: MDIOS_DINR0 + name: MDIOS_DINR0 + - access: Read + array: + len: 32 + stride: 4 + byte_offset: 28 + description: MDIOS input data register %s + fieldset: DINR + name: DINR + - access: Read + byte_offset: 32 + description: MDIOS input data register 1 + fieldset: MDIOS_DINR1 + name: MDIOS_DINR1 + - access: Read + byte_offset: 36 + description: MDIOS input data register 2 + fieldset: MDIOS_DINR2 + name: MDIOS_DINR2 + - access: Read + byte_offset: 40 + description: MDIOS input data register 3 + fieldset: MDIOS_DINR3 + name: MDIOS_DINR3 + - access: Read + byte_offset: 44 + description: MDIOS input data register 4 + fieldset: MDIOS_DINR4 + name: MDIOS_DINR4 + - access: Read + byte_offset: 48 + description: MDIOS input data register 5 + fieldset: MDIOS_DINR5 + name: MDIOS_DINR5 + - access: Read + byte_offset: 52 + description: MDIOS input data register 6 + fieldset: MDIOS_DINR6 + name: MDIOS_DINR6 + - access: Read + byte_offset: 56 + description: MDIOS input data register 7 + fieldset: MDIOS_DINR7 + name: MDIOS_DINR7 + - access: Read + byte_offset: 60 + description: MDIOS input data register 8 + fieldset: MDIOS_DINR8 + name: MDIOS_DINR8 + - access: Read + byte_offset: 64 + description: MDIOS input data register 9 + fieldset: MDIOS_DINR9 + name: MDIOS_DINR9 + - access: Read + byte_offset: 68 + description: MDIOS input data register 10 + fieldset: MDIOS_DINR10 + name: MDIOS_DINR10 + - access: Read + byte_offset: 72 + description: MDIOS input data register 11 + fieldset: MDIOS_DINR11 + name: MDIOS_DINR11 + - access: Read + byte_offset: 76 + description: MDIOS input data register 12 + fieldset: MDIOS_DINR12 + name: MDIOS_DINR12 + - access: Read + byte_offset: 80 + description: MDIOS input data register 13 + fieldset: MDIOS_DINR13 + name: MDIOS_DINR13 + - access: Read + byte_offset: 84 + description: MDIOS input data register 14 + fieldset: MDIOS_DINR14 + name: MDIOS_DINR14 + - access: Read + byte_offset: 88 + description: MDIOS input data register 15 + fieldset: MDIOS_DINR15 + name: MDIOS_DINR15 + - access: Read + byte_offset: 92 + description: MDIOS input data register 16 + fieldset: MDIOS_DINR16 + name: MDIOS_DINR16 + - access: Read + byte_offset: 96 + description: MDIOS input data register 17 + fieldset: MDIOS_DINR17 + name: MDIOS_DINR17 + - access: Read + byte_offset: 100 + description: MDIOS input data register 18 + fieldset: MDIOS_DINR18 + name: MDIOS_DINR18 + - access: Read + byte_offset: 104 + description: MDIOS input data register 19 + fieldset: MDIOS_DINR19 + name: MDIOS_DINR19 + - access: Read + byte_offset: 108 + description: MDIOS input data register 20 + fieldset: MDIOS_DINR20 + name: MDIOS_DINR20 + - access: Read + byte_offset: 112 + description: MDIOS input data register 21 + fieldset: MDIOS_DINR21 + name: MDIOS_DINR21 + - access: Read + byte_offset: 116 + description: MDIOS input data register 22 + fieldset: MDIOS_DINR22 + name: MDIOS_DINR22 + - access: Read + byte_offset: 120 + description: MDIOS input data register 23 + fieldset: MDIOS_DINR23 + name: MDIOS_DINR23 + - access: Read + byte_offset: 124 + description: MDIOS input data register 24 + fieldset: MDIOS_DINR24 + name: MDIOS_DINR24 + - access: Read + byte_offset: 128 + description: MDIOS input data register 25 + fieldset: MDIOS_DINR25 + name: MDIOS_DINR25 + - access: Read + byte_offset: 132 + description: MDIOS input data register 26 + fieldset: MDIOS_DINR26 + name: MDIOS_DINR26 + - access: Read + byte_offset: 136 + description: MDIOS input data register 27 + fieldset: MDIOS_DINR27 + name: MDIOS_DINR27 + - access: Read + byte_offset: 140 + description: MDIOS input data register 28 + fieldset: MDIOS_DINR28 + name: MDIOS_DINR28 + - access: Read + byte_offset: 144 + description: MDIOS input data register 29 + fieldset: MDIOS_DINR29 + name: MDIOS_DINR29 + - access: Read + byte_offset: 148 + description: MDIOS input data register 30 + fieldset: MDIOS_DINR30 + name: MDIOS_DINR30 + - access: Read + byte_offset: 152 + description: MDIOS input data register 31 + fieldset: MDIOS_DINR31 + name: MDIOS_DINR31 + - byte_offset: 156 + description: MDIOS output data register 0 + fieldset: MDIOS_DOUTR0 + name: MDIOS_DOUTR0 + - array: + len: 32 + stride: 4 + byte_offset: 156 + description: MDIOS output data register %s + fieldset: DOUTR + name: DOUTR + - byte_offset: 160 + description: MDIOS output data register 1 + fieldset: MDIOS_DOUTR1 + name: MDIOS_DOUTR1 + - byte_offset: 164 + description: MDIOS output data register 2 + fieldset: MDIOS_DOUTR2 + name: MDIOS_DOUTR2 + - byte_offset: 168 + description: MDIOS output data register 3 + fieldset: MDIOS_DOUTR3 + name: MDIOS_DOUTR3 + - byte_offset: 172 + description: MDIOS output data register 4 + fieldset: MDIOS_DOUTR4 + name: MDIOS_DOUTR4 + - byte_offset: 176 + description: MDIOS output data register 5 + fieldset: MDIOS_DOUTR5 + name: MDIOS_DOUTR5 + - byte_offset: 180 + description: MDIOS output data register 6 + fieldset: MDIOS_DOUTR6 + name: MDIOS_DOUTR6 + - byte_offset: 184 + description: MDIOS output data register 7 + fieldset: MDIOS_DOUTR7 + name: MDIOS_DOUTR7 + - byte_offset: 188 + description: MDIOS output data register 8 + fieldset: MDIOS_DOUTR8 + name: MDIOS_DOUTR8 + - byte_offset: 192 + description: MDIOS output data register 9 + fieldset: MDIOS_DOUTR9 + name: MDIOS_DOUTR9 + - byte_offset: 196 + description: MDIOS output data register 10 + fieldset: MDIOS_DOUTR10 + name: MDIOS_DOUTR10 + - byte_offset: 200 + description: MDIOS output data register 11 + fieldset: MDIOS_DOUTR11 + name: MDIOS_DOUTR11 + - byte_offset: 204 + description: MDIOS output data register 12 + fieldset: MDIOS_DOUTR12 + name: MDIOS_DOUTR12 + - byte_offset: 208 + description: MDIOS output data register 13 + fieldset: MDIOS_DOUTR13 + name: MDIOS_DOUTR13 + - byte_offset: 212 + description: MDIOS output data register 14 + fieldset: MDIOS_DOUTR14 + name: MDIOS_DOUTR14 + - byte_offset: 216 + description: MDIOS output data register 15 + fieldset: MDIOS_DOUTR15 + name: MDIOS_DOUTR15 + - byte_offset: 220 + description: MDIOS output data register 16 + fieldset: MDIOS_DOUTR16 + name: MDIOS_DOUTR16 + - byte_offset: 224 + description: MDIOS output data register 17 + fieldset: MDIOS_DOUTR17 + name: MDIOS_DOUTR17 + - byte_offset: 228 + description: MDIOS output data register 18 + fieldset: MDIOS_DOUTR18 + name: MDIOS_DOUTR18 + - byte_offset: 232 + description: MDIOS output data register 19 + fieldset: MDIOS_DOUTR19 + name: MDIOS_DOUTR19 + - byte_offset: 236 + description: MDIOS output data register 20 + fieldset: MDIOS_DOUTR20 + name: MDIOS_DOUTR20 + - byte_offset: 240 + description: MDIOS output data register 21 + fieldset: MDIOS_DOUTR21 + name: MDIOS_DOUTR21 + - byte_offset: 244 + description: MDIOS output data register 22 + fieldset: MDIOS_DOUTR22 + name: MDIOS_DOUTR22 + - byte_offset: 248 + description: MDIOS output data register 23 + fieldset: MDIOS_DOUTR23 + name: MDIOS_DOUTR23 + - byte_offset: 252 + description: MDIOS output data register 24 + fieldset: MDIOS_DOUTR24 + name: MDIOS_DOUTR24 + - byte_offset: 256 + description: MDIOS output data register 25 + fieldset: MDIOS_DOUTR25 + name: MDIOS_DOUTR25 + - byte_offset: 260 + description: MDIOS output data register 26 + fieldset: MDIOS_DOUTR26 + name: MDIOS_DOUTR26 + - byte_offset: 264 + description: MDIOS output data register 27 + fieldset: MDIOS_DOUTR27 + name: MDIOS_DOUTR27 + - byte_offset: 268 + description: MDIOS output data register 28 + fieldset: MDIOS_DOUTR28 + name: MDIOS_DOUTR28 + - byte_offset: 272 + description: MDIOS output data register 29 + fieldset: MDIOS_DOUTR29 + name: MDIOS_DOUTR29 + - byte_offset: 276 + description: MDIOS output data register 30 + fieldset: MDIOS_DOUTR30 + name: MDIOS_DOUTR30 + - byte_offset: 280 + description: MDIOS output data register 31 + fieldset: MDIOS_DOUTR31 + name: MDIOS_DOUTR31 +fieldset/CLRFR: + description: MDIOS clear flag register + fields: + - bit_offset: 0 + bit_size: 1 + description: Clear the preamble error flag + name: CPERF + - bit_offset: 1 + bit_size: 1 + description: Clear the start error flag + name: CSERF + - bit_offset: 2 + bit_size: 1 + description: Clear the turnaround error flag + name: CTERF +fieldset/CR: + description: MDIOS configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Peripheral enable + name: EN + - bit_offset: 1 + bit_size: 1 + description: Register write interrupt enable + name: WRIE + - bit_offset: 2 + bit_size: 1 + description: Register Read Interrupt Enable + name: RDIE + - bit_offset: 3 + bit_size: 1 + description: Error interrupt enable + name: EIE + - bit_offset: 7 + bit_size: 1 + description: Disable Preamble Check + name: DPC + - bit_offset: 8 + bit_size: 5 + description: Slaves's address + name: PORT_ADDRESS +fieldset/CRDFR: + description: MDIOS clear read flag register + fields: + - bit_offset: 0 + bit_size: 32 + description: Clear the read flag + name: CRDF +fieldset/CWRFR: + description: MDIOS clear write flag register + fields: + - bit_offset: 0 + bit_size: 32 + description: Clear the write flag + name: CWRF +fieldset/DINR: + description: MDIOS input data register %s + fields: + - bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/DOUTR: + description: MDIOS output data register %s + fields: + - bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_CLRFR: + description: MDIOS clear flag register + fields: + - bit_offset: 0 + bit_size: 1 + description: Clear the preamble error flag + name: CPERF + - bit_offset: 1 + bit_size: 1 + description: Clear the start error flag + name: CSERF + - bit_offset: 2 + bit_size: 1 + description: Clear the turnaround error flag + name: CTERF +fieldset/MDIOS_CR: + description: MDIOS configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Peripheral enable + name: EN + - bit_offset: 1 + bit_size: 1 + description: Register write interrupt enable + name: WRIE + - bit_offset: 2 + bit_size: 1 + description: Register Read Interrupt Enable + name: RDIE + - bit_offset: 3 + bit_size: 1 + description: Error interrupt enable + name: EIE + - bit_offset: 7 + bit_size: 1 + description: Disable Preamble Check + name: DPC + - bit_offset: 8 + bit_size: 5 + description: Slaves's address + name: PORT_ADDRESS +fieldset/MDIOS_CRDFR: + description: MDIOS clear read flag register + fields: + - bit_offset: 0 + bit_size: 32 + description: Clear the read flag + name: CRDF +fieldset/MDIOS_CWRFR: + description: MDIOS clear write flag register + fields: + - bit_offset: 0 + bit_size: 32 + description: Clear the write flag + name: CWRF +fieldset/MDIOS_DINR0: + description: MDIOS input data register 0 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR1: + description: MDIOS input data register 1 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR10: + description: MDIOS input data register 10 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR11: + description: MDIOS input data register 11 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR12: + description: MDIOS input data register 12 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR13: + description: MDIOS input data register 13 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR14: + description: MDIOS input data register 14 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR15: + description: MDIOS input data register 15 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR16: + description: MDIOS input data register 16 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR17: + description: MDIOS input data register 17 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR18: + description: MDIOS input data register 18 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR19: + description: MDIOS input data register 19 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR2: + description: MDIOS input data register 2 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR20: + description: MDIOS input data register 20 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR21: + description: MDIOS input data register 21 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR22: + description: MDIOS input data register 22 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR23: + description: MDIOS input data register 23 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR24: + description: MDIOS input data register 24 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR25: + description: MDIOS input data register 25 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR26: + description: MDIOS input data register 26 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR27: + description: MDIOS input data register 27 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR28: + description: MDIOS input data register 28 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR29: + description: MDIOS input data register 29 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR3: + description: MDIOS input data register 3 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR30: + description: MDIOS input data register 30 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR31: + description: MDIOS input data register 31 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR4: + description: MDIOS input data register 4 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR5: + description: MDIOS input data register 5 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR6: + description: MDIOS input data register 6 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR7: + description: MDIOS input data register 7 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR8: + description: MDIOS input data register 8 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DINR9: + description: MDIOS input data register 9 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Input data received from MDIO Master during write frames + name: DIN +fieldset/MDIOS_DOUTR0: + description: MDIOS output data register 0 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR1: + description: MDIOS output data register 1 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR10: + description: MDIOS output data register 10 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR11: + description: MDIOS output data register 11 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR12: + description: MDIOS output data register 12 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR13: + description: MDIOS output data register 13 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR14: + description: MDIOS output data register 14 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR15: + description: MDIOS output data register 15 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR16: + description: MDIOS output data register 16 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR17: + description: MDIOS output data register 17 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR18: + description: MDIOS output data register 18 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR19: + description: MDIOS output data register 19 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR2: + description: MDIOS output data register 2 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR20: + description: MDIOS output data register 20 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR21: + description: MDIOS output data register 21 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR22: + description: MDIOS output data register 22 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR23: + description: MDIOS output data register 23 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR24: + description: MDIOS output data register 24 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR25: + description: MDIOS output data register 25 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR26: + description: MDIOS output data register 26 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR27: + description: MDIOS output data register 27 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR28: + description: MDIOS output data register 28 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR29: + description: MDIOS output data register 29 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR3: + description: MDIOS output data register 3 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR30: + description: MDIOS output data register 30 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR31: + description: MDIOS output data register 31 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR4: + description: MDIOS output data register 4 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR5: + description: MDIOS output data register 5 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR6: + description: MDIOS output data register 6 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR7: + description: MDIOS output data register 7 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR8: + description: MDIOS output data register 8 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_DOUTR9: + description: MDIOS output data register 9 + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 16 + description: Output data sent to MDIO Master during read frames + name: DOUT +fieldset/MDIOS_RDFR: + description: MDIOS read flag register + fields: + - bit_offset: 0 + bit_size: 32 + description: Read flags for MDIO registers 0 to 31 + name: RDF +fieldset/MDIOS_SR: + description: MDIOS status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Preamble error flag + name: PERF + - bit_offset: 1 + bit_size: 1 + description: Start error flag + name: SERF + - bit_offset: 2 + bit_size: 1 + description: Turnaround error flag + name: TERF +fieldset/MDIOS_WRFR: + description: MDIOS write flag register + fields: + - bit_offset: 0 + bit_size: 32 + description: Write flags for MDIO registers 0 to 31 + name: WRF +fieldset/RDFR: + description: MDIOS read flag register + fields: + - bit_offset: 0 + bit_size: 32 + description: Read flags for MDIO registers 0 to 31 + name: RDF +fieldset/SR: + description: MDIOS status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Preamble error flag + name: PERF + - bit_offset: 1 + bit_size: 1 + description: Start error flag + name: SERF + - bit_offset: 2 + bit_size: 1 + description: Turnaround error flag + name: TERF +fieldset/WRFR: + description: MDIOS write flag register + fields: + - bit_offset: 0 + bit_size: 32 + description: Write flags for MDIO registers 0 to 31 + name: WRF diff --git a/data/registers/otgfs_v1.yaml b/data/registers/otgfs_v1.yaml new file mode 100644 index 0000000..08fd267 --- /dev/null +++ b/data/registers/otgfs_v1.yaml @@ -0,0 +1,936 @@ +--- +block/OTG_FS: + description: USB on the go full speed + items: + - byte_offset: 0 + description: OTG_FS control and status register (OTG_FS_GOTGCTL) + fieldset: OTG_FS_GOTGCTL + name: OTG_FS_GOTGCTL + - byte_offset: 4 + description: OTG_FS interrupt register (OTG_FS_GOTGINT) + fieldset: OTG_FS_GOTGINT + name: OTG_FS_GOTGINT + - byte_offset: 8 + description: OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + fieldset: OTG_FS_GAHBCFG + name: OTG_FS_GAHBCFG + - byte_offset: 12 + description: OTG_FS USB configuration register (OTG_FS_GUSBCFG) + fieldset: OTG_FS_GUSBCFG + name: OTG_FS_GUSBCFG + - byte_offset: 16 + description: OTG_FS reset register (OTG_FS_GRSTCTL) + fieldset: OTG_FS_GRSTCTL + name: OTG_FS_GRSTCTL + - byte_offset: 20 + description: OTG_FS core interrupt register (OTG_FS_GINTSTS) + fieldset: OTG_FS_GINTSTS + name: OTG_FS_GINTSTS + - byte_offset: 24 + description: OTG_FS interrupt mask register (OTG_FS_GINTMSK) + fieldset: OTG_FS_GINTMSK + name: OTG_FS_GINTMSK + - access: Read + byte_offset: 28 + description: OTG_FS Receive status debug read(Device mode) + fieldset: OTG_FS_GRXSTSR_Device + name: OTG_FS_GRXSTSR_Device + - access: Read + byte_offset: 28 + description: OTG_FS Receive status debug read(Host mode) + fieldset: OTG_FS_GRXSTSR_Host + name: OTG_FS_GRXSTSR_Host + - access: Read + byte_offset: 32 + description: OTG status read and pop register (Device mode) + fieldset: OTG_FS_GRXSTSP_Device + name: OTG_FS_GRXSTSP_Device + - access: Read + byte_offset: 32 + description: OTG status read and pop register (Host mode) + fieldset: OTG_FS_GRXSTSP_Host + name: OTG_FS_GRXSTSP_Host + - byte_offset: 36 + description: OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + fieldset: OTG_FS_GRXFSIZ + name: OTG_FS_GRXFSIZ + - byte_offset: 40 + description: OTG_FS Endpoint 0 Transmit FIFO size + fieldset: OTG_FS_DIEPTXF0_Device + name: OTG_FS_DIEPTXF0_Device + - byte_offset: 40 + description: OTG_FS Host non-periodic transmit FIFO size register + fieldset: OTG_FS_HNPTXFSIZ_Host + name: OTG_FS_HNPTXFSIZ_Host + - access: Read + byte_offset: 44 + description: OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + fieldset: OTG_FS_HNPTXSTS + name: OTG_FS_HNPTXSTS + - byte_offset: 48 + description: OTG I2C access register + fieldset: OTG_FS_GI2CCTL + name: OTG_FS_GI2CCTL + - byte_offset: 56 + description: OTG_FS general core configuration register (OTG_FS_GCCFG) + fieldset: OTG_FS_GCCFG + name: OTG_FS_GCCFG + - byte_offset: 60 + description: core ID register + fieldset: OTG_FS_CID + name: OTG_FS_CID + - byte_offset: 84 + description: OTG core LPM configuration register + fieldset: OTG_FS_GLPMCFG + name: OTG_FS_GLPMCFG + - byte_offset: 88 + description: OTG power down register + fieldset: OTG_FS_GPWRDN + name: OTG_FS_GPWRDN + - byte_offset: 96 + description: OTG ADP timer, control and status register + fieldset: OTG_FS_GADPCTL + name: OTG_FS_GADPCTL + - byte_offset: 256 + description: OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + fieldset: OTG_FS_HPTXFSIZ + name: OTG_FS_HPTXFSIZ + - byte_offset: 260 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF1) + fieldset: OTG_FS_DIEPTXF1 + name: OTG_FS_DIEPTXF1 + - byte_offset: 264 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + fieldset: OTG_FS_DIEPTXF2 + name: OTG_FS_DIEPTXF2 + - byte_offset: 268 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) + fieldset: OTG_FS_DIEPTXF3 + name: OTG_FS_DIEPTXF3 + - byte_offset: 272 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) + fieldset: OTG_FS_DIEPTXF4 + name: OTG_FS_DIEPTXF4 + - byte_offset: 276 + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF5) + fieldset: OTG_FS_DIEPTXF5 + name: OTG_FS_DIEPTXF5 +fieldset/OTG_FS_CID: + description: core ID register + fields: + - bit_offset: 0 + bit_size: 32 + description: Product ID field + name: PRODUCT_ID +fieldset/OTG_FS_DIEPTXF0_Device: + description: OTG_FS Endpoint 0 Transmit FIFO size + fields: + - bit_offset: 0 + bit_size: 16 + description: Endpoint 0 transmit RAM start address + name: TX0FSA + - bit_offset: 16 + bit_size: 16 + description: Endpoint 0 TxFIFO depth + name: TX0FD +fieldset/OTG_FS_DIEPTXF1: + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF1) + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFO2 transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_FS_DIEPTXF2: + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFO3 transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_FS_DIEPTXF3: + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFO4 transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_FS_DIEPTXF4: + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint Tx FIFO depth + name: INEPTXFD +fieldset/OTG_FS_DIEPTXF5: + description: OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF5) + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint Tx FIFO depth + name: INEPTXFD +fieldset/OTG_FS_GADPCTL: + description: OTG ADP timer, control and status register + fields: + - bit_offset: 0 + bit_size: 2 + description: Probe discharge + name: PRBDSCHG + - bit_offset: 2 + bit_size: 2 + description: Probe delta + name: PRBDELTA + - bit_offset: 4 + bit_size: 2 + description: Probe period + name: PRBPER + - bit_offset: 6 + bit_size: 11 + description: Ramp time + name: RTIM + - bit_offset: 17 + bit_size: 1 + description: Enable probe + name: ENAPRB + - bit_offset: 18 + bit_size: 1 + description: Enable sense + name: ENASNS + - bit_offset: 19 + bit_size: 1 + description: ADP reset + name: ADPRST + - bit_offset: 20 + bit_size: 1 + description: ADP enable + name: ADPEN + - bit_offset: 21 + bit_size: 1 + description: ADP probe interrupt flag + name: ADPPRBIF + - bit_offset: 22 + bit_size: 1 + description: ADP sense interrupt flag + name: ADPSNSIF + - bit_offset: 23 + bit_size: 1 + description: ADP timeout interrupt flag + name: ADPTOIF + - bit_offset: 24 + bit_size: 1 + description: ADP probe interrupt mask + name: ADPPRBIM + - bit_offset: 25 + bit_size: 1 + description: ADP sense interrupt mask + name: ADPSNSIM + - bit_offset: 26 + bit_size: 1 + description: ADP timeout interrupt mask + name: ADPTOIM + - bit_offset: 27 + bit_size: 2 + description: Access request + name: AR +fieldset/OTG_FS_GAHBCFG: + description: OTG_FS AHB configuration register (OTG_FS_GAHBCFG) + fields: + - bit_offset: 0 + bit_size: 1 + description: Global interrupt mask + name: GINT + - bit_offset: 7 + bit_size: 1 + description: TxFIFO empty level + name: TXFELVL + - bit_offset: 8 + bit_size: 1 + description: Periodic TxFIFO empty level + name: PTXFELVL +fieldset/OTG_FS_GCCFG: + description: OTG_FS general core configuration register (OTG_FS_GCCFG) + fields: + - bit_offset: 0 + bit_size: 1 + description: Data contact detection (DCD) status + name: DCDET + - bit_offset: 1 + bit_size: 1 + description: Primary detection (PD) status + name: PDET + - bit_offset: 2 + bit_size: 1 + description: Secondary detection (SD) status + name: SDET + - bit_offset: 3 + bit_size: 1 + description: DM pull-up detection status + name: PS2DET + - bit_offset: 16 + bit_size: 1 + description: Power down + name: PWRDWN + - bit_offset: 17 + bit_size: 1 + description: Battery charging detector (BCD) enable + name: BCDEN + - bit_offset: 18 + bit_size: 1 + description: Data contact detection (DCD) mode enable + name: DCDEN + - bit_offset: 19 + bit_size: 1 + description: Primary detection (PD) mode enable + name: PDEN + - bit_offset: 20 + bit_size: 1 + description: Secondary detection (SD) mode enable + name: SDEN + - bit_offset: 21 + bit_size: 1 + description: USB VBUS detection enable + name: VBDEN +fieldset/OTG_FS_GI2CCTL: + description: OTG I2C access register + fields: + - bit_offset: 0 + bit_size: 8 + description: I2C Read/Write Data + name: RWDATA + - bit_offset: 8 + bit_size: 8 + description: I2C Register Address + name: REGADDR + - bit_offset: 16 + bit_size: 7 + description: I2C Address + name: ADDR + - bit_offset: 23 + bit_size: 1 + description: I2C Enable + name: I2CEN + - bit_offset: 24 + bit_size: 1 + description: I2C ACK + name: ACK + - bit_offset: 26 + bit_size: 2 + description: I2C Device Address + name: I2CDEVADR + - bit_offset: 28 + bit_size: 1 + description: I2C DatSe0 USB mode + name: I2CDATSE0 + - bit_offset: 30 + bit_size: 1 + description: Read/Write Indicator + name: RW + - bit_offset: 31 + bit_size: 1 + description: I2C Busy/Done + name: BSYDNE +fieldset/OTG_FS_GINTMSK: + description: OTG_FS interrupt mask register (OTG_FS_GINTMSK) + fields: + - bit_offset: 1 + bit_size: 1 + description: Mode mismatch interrupt mask + name: MMISM + - bit_offset: 2 + bit_size: 1 + description: OTG interrupt mask + name: OTGINT + - bit_offset: 3 + bit_size: 1 + description: Start of frame mask + name: SOFM + - bit_offset: 4 + bit_size: 1 + description: Receive FIFO non-empty mask + name: RXFLVLM + - bit_offset: 5 + bit_size: 1 + description: Non-periodic TxFIFO empty mask + name: NPTXFEM + - bit_offset: 6 + bit_size: 1 + description: Global non-periodic IN NAK effective mask + name: GINAKEFFM + - bit_offset: 7 + bit_size: 1 + description: Global OUT NAK effective mask + name: GONAKEFFM + - bit_offset: 10 + bit_size: 1 + description: Early suspend mask + name: ESUSPM + - bit_offset: 11 + bit_size: 1 + description: USB suspend mask + name: USBSUSPM + - bit_offset: 12 + bit_size: 1 + description: USB reset mask + name: USBRST + - bit_offset: 13 + bit_size: 1 + description: Enumeration done mask + name: ENUMDNEM + - bit_offset: 14 + bit_size: 1 + description: Isochronous OUT packet dropped interrupt mask + name: ISOODRPM + - bit_offset: 15 + bit_size: 1 + description: End of periodic frame interrupt mask + name: EOPFM + - bit_offset: 18 + bit_size: 1 + description: IN endpoints interrupt mask + name: IEPINT + - bit_offset: 19 + bit_size: 1 + description: OUT endpoints interrupt mask + name: OEPINT + - bit_offset: 20 + bit_size: 1 + description: Incomplete isochronous IN transfer mask + name: IISOIXFRM + - bit_offset: 21 + bit_size: 1 + description: Incomplete periodic transfer mask(Host mode)/Incomplete isochronous + OUT transfer mask(Device mode) + name: IPXFRM_IISOOXFRM + - bit_offset: 23 + bit_size: 1 + description: Reset detected interrupt mask + name: RSTDETM + - bit_offset: 24 + bit_size: 1 + description: Host port interrupt mask + name: PRTIM + - bit_offset: 25 + bit_size: 1 + description: Host channels interrupt mask + name: HCIM + - bit_offset: 26 + bit_size: 1 + description: Periodic TxFIFO empty mask + name: PTXFEM + - bit_offset: 27 + bit_size: 1 + description: LPM interrupt mask + name: LPMIN + - bit_offset: 28 + bit_size: 1 + description: Connector ID status change mask + name: CIDSCHGM + - bit_offset: 29 + bit_size: 1 + description: Disconnect detected interrupt mask + name: DISCINT + - bit_offset: 30 + bit_size: 1 + description: Session request/new session detected interrupt mask + name: SRQIM + - bit_offset: 31 + bit_size: 1 + description: Resume/remote wakeup detected interrupt mask + name: WUIM +fieldset/OTG_FS_GINTSTS: + description: OTG_FS core interrupt register (OTG_FS_GINTSTS) + fields: + - bit_offset: 0 + bit_size: 1 + description: Current mode of operation + name: CMOD + - bit_offset: 1 + bit_size: 1 + description: Mode mismatch interrupt + name: MMIS + - bit_offset: 2 + bit_size: 1 + description: OTG interrupt + name: OTGINT + - bit_offset: 3 + bit_size: 1 + description: Start of frame + name: SOF + - bit_offset: 4 + bit_size: 1 + description: RxFIFO non-empty + name: RXFLVL + - bit_offset: 5 + bit_size: 1 + description: Non-periodic TxFIFO empty + name: NPTXFE + - bit_offset: 6 + bit_size: 1 + description: Global IN non-periodic NAK effective + name: GINAKEFF + - bit_offset: 7 + bit_size: 1 + description: Global OUT NAK effective + name: GOUTNAKEFF + - bit_offset: 10 + bit_size: 1 + description: Early suspend + name: ESUSP + - bit_offset: 11 + bit_size: 1 + description: USB suspend + name: USBSUSP + - bit_offset: 12 + bit_size: 1 + description: USB reset + name: USBRST + - bit_offset: 13 + bit_size: 1 + description: Enumeration done + name: ENUMDNE + - bit_offset: 14 + bit_size: 1 + description: Isochronous OUT packet dropped interrupt + name: ISOODRP + - bit_offset: 15 + bit_size: 1 + description: End of periodic frame interrupt + name: EOPF + - bit_offset: 18 + bit_size: 1 + description: IN endpoint interrupt + name: IEPINT + - bit_offset: 19 + bit_size: 1 + description: OUT endpoint interrupt + name: OEPINT + - bit_offset: 20 + bit_size: 1 + description: Incomplete isochronous IN transfer + name: IISOIXFR + - bit_offset: 21 + bit_size: 1 + description: Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT + transfer(Device mode) + name: IPXFR_INCOMPISOOUT + - bit_offset: 23 + bit_size: 1 + description: Reset detected interrupt + name: RSTDET + - bit_offset: 24 + bit_size: 1 + description: Host port interrupt + name: HPRTINT + - bit_offset: 25 + bit_size: 1 + description: Host channels interrupt + name: HCINT + - bit_offset: 26 + bit_size: 1 + description: Periodic TxFIFO empty + name: PTXFE + - bit_offset: 28 + bit_size: 1 + description: Connector ID status change + name: CIDSCHG + - bit_offset: 29 + bit_size: 1 + description: Disconnect detected interrupt + name: DISCINT + - bit_offset: 30 + bit_size: 1 + description: Session request/new session detected interrupt + name: SRQINT + - bit_offset: 31 + bit_size: 1 + description: Resume/remote wakeup detected interrupt + name: WKUPINT +fieldset/OTG_FS_GLPMCFG: + description: OTG core LPM configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: LPM support enable + name: LPMEN + - bit_offset: 1 + bit_size: 1 + description: LPM token acknowledge enable + name: LPMACK + - bit_offset: 2 + bit_size: 4 + description: Best effort service latency + name: BESL + - bit_offset: 6 + bit_size: 1 + description: bRemoteWake value + name: REMWAKE + - bit_offset: 7 + bit_size: 1 + description: L1 Shallow Sleep enable + name: L1SSEN + - bit_offset: 8 + bit_size: 4 + description: BESL threshold + name: BESLTHRS + - bit_offset: 12 + bit_size: 1 + description: L1 deep sleep enable + name: L1DSEN + - bit_offset: 13 + bit_size: 2 + description: LPM response + name: LPMRST + - bit_offset: 15 + bit_size: 1 + description: Port sleep status + name: SLPSTS + - bit_offset: 16 + bit_size: 1 + description: Sleep State Resume OK + name: L1RSMOK + - bit_offset: 17 + bit_size: 4 + description: LPM Channel Index + name: LPMCHIDX + - bit_offset: 21 + bit_size: 3 + description: LPM retry count + name: LPMRCNT + - bit_offset: 24 + bit_size: 1 + description: Send LPM transaction + name: SNDLPM + - bit_offset: 25 + bit_size: 3 + description: LPM retry count status + name: LPMRCNTSTS + - bit_offset: 28 + bit_size: 1 + description: Enable best effort service latency + name: ENBESL +fieldset/OTG_FS_GOTGCTL: + description: OTG_FS control and status register (OTG_FS_GOTGCTL) + fields: + - bit_offset: 0 + bit_size: 1 + description: Session request success + name: SRQSCS + - bit_offset: 1 + bit_size: 1 + description: Session request + name: SRQ + - bit_offset: 2 + bit_size: 1 + description: VBUS valid override enable + name: VBVALOEN + - bit_offset: 3 + bit_size: 1 + description: VBUS valid override value + name: VBVALOVAL + - bit_offset: 4 + bit_size: 1 + description: A-peripheral session valid override enable + name: AVALOEN + - bit_offset: 5 + bit_size: 1 + description: A-peripheral session valid override value + name: AVALOVAL + - bit_offset: 6 + bit_size: 1 + description: B-peripheral session valid override enable + name: BVALOEN + - bit_offset: 7 + bit_size: 1 + description: B-peripheral session valid override value + name: BVALOVAL + - bit_offset: 8 + bit_size: 1 + description: Host negotiation success + name: HNGSCS + - bit_offset: 9 + bit_size: 1 + description: HNP request + name: HNPRQ + - bit_offset: 10 + bit_size: 1 + description: Host set HNP enable + name: HSHNPEN + - bit_offset: 11 + bit_size: 1 + description: Device HNP enabled + name: DHNPEN + - bit_offset: 12 + bit_size: 1 + description: Embedded host enable + name: EHEN + - bit_offset: 16 + bit_size: 1 + description: Connector ID status + name: CIDSTS + - bit_offset: 17 + bit_size: 1 + description: Long/short debounce time + name: DBCT + - bit_offset: 18 + bit_size: 1 + description: A-session valid + name: ASVLD + - bit_offset: 19 + bit_size: 1 + description: B-session valid + name: BSVLD + - bit_offset: 20 + bit_size: 1 + description: OTG version + name: OTGVER +fieldset/OTG_FS_GOTGINT: + description: OTG_FS interrupt register (OTG_FS_GOTGINT) + fields: + - bit_offset: 2 + bit_size: 1 + description: Session end detected + name: SEDET + - bit_offset: 8 + bit_size: 1 + description: Session request success status change + name: SRSSCHG + - bit_offset: 9 + bit_size: 1 + description: Host negotiation success status change + name: HNSSCHG + - bit_offset: 17 + bit_size: 1 + description: Host negotiation detected + name: HNGDET + - bit_offset: 18 + bit_size: 1 + description: A-device timeout change + name: ADTOCHG + - bit_offset: 19 + bit_size: 1 + description: Debounce done + name: DBCDNE + - bit_offset: 20 + bit_size: 1 + description: ID input pin changed + name: IDCHNG +fieldset/OTG_FS_GPWRDN: + description: OTG power down register + fields: + - bit_offset: 0 + bit_size: 1 + description: ADP module enable + name: ADPMEN + - bit_offset: 23 + bit_size: 1 + description: ADP interrupt flag + name: ADPIF +fieldset/OTG_FS_GRSTCTL: + description: OTG_FS reset register (OTG_FS_GRSTCTL) + fields: + - bit_offset: 0 + bit_size: 1 + description: Core soft reset + name: CSRST + - bit_offset: 1 + bit_size: 1 + description: HCLK soft reset + name: HSRST + - bit_offset: 2 + bit_size: 1 + description: Host frame counter reset + name: FCRST + - bit_offset: 4 + bit_size: 1 + description: RxFIFO flush + name: RXFFLSH + - bit_offset: 5 + bit_size: 1 + description: TxFIFO flush + name: TXFFLSH + - bit_offset: 6 + bit_size: 5 + description: TxFIFO number + name: TXFNUM + - bit_offset: 31 + bit_size: 1 + description: AHB master idle + name: AHBIDL +fieldset/OTG_FS_GRXFSIZ: + description: OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) + fields: + - bit_offset: 0 + bit_size: 16 + description: RxFIFO depth + name: RXFD +fieldset/OTG_FS_GRXSTSP_Device: + description: OTG status read and pop register (Device mode) + fields: + - bit_offset: 0 + bit_size: 4 + description: Endpoint number + name: EPNUM + - bit_offset: 4 + bit_size: 11 + description: Byte count + name: BCNT + - bit_offset: 15 + bit_size: 2 + description: Data PID + name: DPID + - bit_offset: 17 + bit_size: 4 + description: Packet status + name: PKTSTS + - bit_offset: 21 + bit_size: 4 + description: Frame number + name: FRMNUM +fieldset/OTG_FS_GRXSTSP_Host: + description: OTG status read and pop register (Host mode) + fields: + - bit_offset: 0 + bit_size: 4 + description: Channel number + name: CHNUM + - bit_offset: 4 + bit_size: 11 + description: Byte count + name: BCNT + - bit_offset: 15 + bit_size: 2 + description: Data PID + name: DPID + - bit_offset: 17 + bit_size: 4 + description: Packet status + name: PKTSTS +fieldset/OTG_FS_GRXSTSR_Device: + description: OTG_FS Receive status debug read(Device mode) + fields: + - bit_offset: 0 + bit_size: 4 + description: Endpoint number + name: EPNUM + - bit_offset: 4 + bit_size: 11 + description: Byte count + name: BCNT + - bit_offset: 15 + bit_size: 2 + description: Data PID + name: DPID + - bit_offset: 17 + bit_size: 4 + description: Packet status + name: PKTSTS + - bit_offset: 21 + bit_size: 4 + description: Frame number + name: FRMNUM +fieldset/OTG_FS_GRXSTSR_Host: + description: OTG_FS Receive status debug read(Host mode) + fields: + - bit_offset: 0 + bit_size: 4 + description: Endpoint number + name: CHNUM + - bit_offset: 4 + bit_size: 11 + description: Byte count + name: BCNT + - bit_offset: 15 + bit_size: 2 + description: Data PID + name: DPID + - bit_offset: 17 + bit_size: 4 + description: Packet status + name: PKTSTS +fieldset/OTG_FS_GUSBCFG: + description: OTG_FS USB configuration register (OTG_FS_GUSBCFG) + fields: + - bit_offset: 0 + bit_size: 3 + description: FS timeout calibration + name: TOCAL + - bit_offset: 6 + bit_size: 1 + description: Full Speed serial transceiver select + name: PHYSEL + - bit_offset: 8 + bit_size: 1 + description: SRP-capable + name: SRPCAP + - bit_offset: 9 + bit_size: 1 + description: HNP-capable + name: HNPCAP + - bit_offset: 10 + bit_size: 4 + description: USB turnaround time + name: TRDT + - bit_offset: 29 + bit_size: 1 + description: Force host mode + name: FHMOD + - bit_offset: 30 + bit_size: 1 + description: Force device mode + name: FDMOD +fieldset/OTG_FS_HNPTXFSIZ_Host: + description: OTG_FS Host non-periodic transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: Non-periodic transmit RAM start address + name: NPTXFSA + - bit_offset: 16 + bit_size: 16 + description: Non-periodic TxFIFO depth + name: NPTXFD +fieldset/OTG_FS_HNPTXSTS: + description: OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) + fields: + - bit_offset: 0 + bit_size: 16 + description: Non-periodic TxFIFO space available + name: NPTXFSAV + - bit_offset: 16 + bit_size: 8 + description: Non-periodic transmit request queue space available + name: NPTQXSAV + - bit_offset: 24 + bit_size: 7 + description: Top of the non-periodic transmit request queue + name: NPTXQTOP +fieldset/OTG_FS_HPTXFSIZ: + description: OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) + fields: + - bit_offset: 0 + bit_size: 16 + description: Host periodic TxFIFO start address + name: PTXSA + - bit_offset: 16 + bit_size: 16 + description: Host periodic TxFIFO depth + name: PTXFSIZ diff --git a/data/registers/otghs_v1.yaml b/data/registers/otghs_v1.yaml new file mode 100644 index 0000000..23d8fd9 --- /dev/null +++ b/data/registers/otghs_v1.yaml @@ -0,0 +1,931 @@ +--- +block/OTG_HS: + description: USB on the go high speed + items: + - byte_offset: 0 + description: OTG_HS control and status register + fieldset: OTG_HS_GOTGCTL + name: OTG_HS_GOTGCTL + - byte_offset: 4 + description: OTG_HS interrupt register + fieldset: OTG_HS_GOTGINT + name: OTG_HS_GOTGINT + - byte_offset: 8 + description: OTG_HS AHB configuration register + fieldset: OTG_HS_GAHBCFG + name: OTG_HS_GAHBCFG + - byte_offset: 12 + description: OTG_HS USB configuration register + fieldset: OTG_HS_GUSBCFG + name: OTG_HS_GUSBCFG + - byte_offset: 16 + description: OTG_HS reset register + fieldset: OTG_HS_GRSTCTL + name: OTG_HS_GRSTCTL + - byte_offset: 20 + description: OTG_HS core interrupt register + fieldset: OTG_HS_GINTSTS + name: OTG_HS_GINTSTS + - byte_offset: 24 + description: OTG_HS interrupt mask register + fieldset: OTG_HS_GINTMSK + name: OTG_HS_GINTMSK + - access: Read + byte_offset: 28 + description: OTG_HS Receive status debug read register (peripheral mode mode) + fieldset: OTG_HS_GRXSTSR_Device + name: OTG_HS_GRXSTSR_Device + - access: Read + byte_offset: 28 + description: OTG_HS Receive status debug read register (host mode) + fieldset: OTG_HS_GRXSTSR_Host + name: OTG_HS_GRXSTSR_Host + - access: Read + byte_offset: 32 + description: OTG_HS status read and pop register (peripheral mode) + fieldset: OTG_HS_GRXSTSP_Device + name: OTG_HS_GRXSTSP_Device + - access: Read + byte_offset: 32 + description: OTG_HS status read and pop register (host mode) + fieldset: OTG_HS_GRXSTSP_Host + name: OTG_HS_GRXSTSP_Host + - byte_offset: 36 + description: OTG_HS Receive FIFO size register + fieldset: OTG_HS_GRXFSIZ + name: OTG_HS_GRXFSIZ + - byte_offset: 40 + description: Endpoint 0 transmit FIFO size (peripheral mode) + fieldset: OTG_HS_DIEPTXF0_Device + name: OTG_HS_DIEPTXF0_Device + - byte_offset: 40 + description: OTG_HS nonperiodic transmit FIFO size register (host mode) + fieldset: OTG_HS_HNPTXFSIZ_Host + name: OTG_HS_HNPTXFSIZ_Host + - access: Read + byte_offset: 44 + description: OTG_HS nonperiodic transmit FIFO/queue status register + fieldset: OTG_HS_HNPTXSTS + name: OTG_HS_HNPTXSTS + - access: Read + byte_offset: 44 + description: OTG_HS nonperiodic transmit FIFO/queue status register + fieldset: OTG_HS_GNPTXSTS + name: OTG_HS_GNPTXSTS + - byte_offset: 48 + description: OTG I2C access register + fieldset: OTG_HS_GI2CCTL + name: OTG_HS_GI2CCTL + - byte_offset: 56 + description: OTG_HS general core configuration register + fieldset: OTG_HS_GCCFG + name: OTG_HS_GCCFG + - byte_offset: 60 + description: OTG_HS core ID register + fieldset: OTG_HS_CID + name: OTG_HS_CID + - byte_offset: 84 + description: OTG core LPM configuration register + fieldset: OTG_HS_GLPMCFG + name: OTG_HS_GLPMCFG + - byte_offset: 256 + description: OTG_HS Host periodic transmit FIFO size register + fieldset: OTG_HS_HPTXFSIZ + name: OTG_HS_HPTXFSIZ + - byte_offset: 260 + description: OTG_HS device IN endpoint transmit FIFO size register + fieldset: OTG_HS_DIEPTXF1 + name: OTG_HS_DIEPTXF1 + - byte_offset: 264 + description: OTG_HS device IN endpoint transmit FIFO size register + fieldset: OTG_HS_DIEPTXF2 + name: OTG_HS_DIEPTXF2 + - byte_offset: 268 + description: OTG_HS device IN endpoint transmit FIFO size register + fieldset: OTG_HS_DIEPTXF3 + name: OTG_HS_DIEPTXF3 + - byte_offset: 272 + description: OTG_HS device IN endpoint transmit FIFO size register + fieldset: OTG_HS_DIEPTXF4 + name: OTG_HS_DIEPTXF4 + - byte_offset: 276 + description: OTG_HS device IN endpoint transmit FIFO size register + fieldset: OTG_HS_DIEPTXF5 + name: OTG_HS_DIEPTXF5 + - byte_offset: 280 + description: OTG_HS device IN endpoint transmit FIFO size register + fieldset: OTG_HS_DIEPTXF6 + name: OTG_HS_DIEPTXF6 + - byte_offset: 284 + description: OTG_HS device IN endpoint transmit FIFO size register + fieldset: OTG_HS_DIEPTXF7 + name: OTG_HS_DIEPTXF7 +fieldset/OTG_HS_CID: + description: OTG_HS core ID register + fields: + - bit_offset: 0 + bit_size: 32 + description: Product ID field + name: PRODUCT_ID +fieldset/OTG_HS_DIEPTXF0_Device: + description: Endpoint 0 transmit FIFO size (peripheral mode) + fields: + - bit_offset: 0 + bit_size: 16 + description: Endpoint 0 transmit RAM start address + name: TX0FSA + - bit_offset: 16 + bit_size: 16 + description: Endpoint 0 TxFIFO depth + name: TX0FD +fieldset/OTG_HS_DIEPTXF1: + description: OTG_HS device IN endpoint transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_HS_DIEPTXF2: + description: OTG_HS device IN endpoint transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_HS_DIEPTXF3: + description: OTG_HS device IN endpoint transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_HS_DIEPTXF4: + description: OTG_HS device IN endpoint transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_HS_DIEPTXF5: + description: OTG_HS device IN endpoint transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_HS_DIEPTXF6: + description: OTG_HS device IN endpoint transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_HS_DIEPTXF7: + description: OTG_HS device IN endpoint transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: IN endpoint FIFOx transmit RAM start address + name: INEPTXSA + - bit_offset: 16 + bit_size: 16 + description: IN endpoint TxFIFO depth + name: INEPTXFD +fieldset/OTG_HS_GAHBCFG: + description: OTG_HS AHB configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Global interrupt mask + name: GINT + - bit_offset: 1 + bit_size: 4 + description: Burst length/type + name: HBSTLEN + - bit_offset: 5 + bit_size: 1 + description: DMA enable + name: DMAEN + - bit_offset: 7 + bit_size: 1 + description: TxFIFO empty level + name: TXFELVL + - bit_offset: 8 + bit_size: 1 + description: Periodic TxFIFO empty level + name: PTXFELVL +fieldset/OTG_HS_GCCFG: + description: OTG_HS general core configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Data contact detection (DCD) status + name: DCDET + - bit_offset: 1 + bit_size: 1 + description: Primary detection (PD) status + name: PDET + - bit_offset: 2 + bit_size: 1 + description: Secondary detection (SD) status + name: SDET + - bit_offset: 3 + bit_size: 1 + description: DM pull-up detection status + name: PS2DET + - bit_offset: 16 + bit_size: 1 + description: Power down + name: PWRDWN + - bit_offset: 17 + bit_size: 1 + description: Battery charging detector (BCD) enable + name: BCDEN + - bit_offset: 18 + bit_size: 1 + description: Data contact detection (DCD) mode enable + name: DCDEN + - bit_offset: 19 + bit_size: 1 + description: Primary detection (PD) mode enable + name: PDEN + - bit_offset: 20 + bit_size: 1 + description: Secondary detection (SD) mode enable + name: SDEN + - bit_offset: 21 + bit_size: 1 + description: USB VBUS detection enable + name: VBDEN +fieldset/OTG_HS_GI2CCTL: + description: OTG I2C access register + fields: + - bit_offset: 0 + bit_size: 8 + description: I2C Read/Write Data + name: RWDATA + - bit_offset: 8 + bit_size: 8 + description: I2C Register Address + name: REGADDR + - bit_offset: 16 + bit_size: 7 + description: I2C Address + name: ADDR + - bit_offset: 23 + bit_size: 1 + description: I2C Enable + name: I2CEN + - bit_offset: 24 + bit_size: 1 + description: I2C ACK + name: ACK + - bit_offset: 26 + bit_size: 2 + description: I2C Device Address + name: I2CDEVADR + - bit_offset: 28 + bit_size: 1 + description: I2C DatSe0 USB mode + name: I2CDATSE0 + - bit_offset: 30 + bit_size: 1 + description: Read/Write Indicator + name: RW + - bit_offset: 31 + bit_size: 1 + description: I2C Busy/Done + name: BSYDNE +fieldset/OTG_HS_GINTMSK: + description: OTG_HS interrupt mask register + fields: + - bit_offset: 1 + bit_size: 1 + description: Mode mismatch interrupt mask + name: MMISM + - bit_offset: 2 + bit_size: 1 + description: OTG interrupt mask + name: OTGINT + - bit_offset: 3 + bit_size: 1 + description: Start of frame mask + name: SOFM + - bit_offset: 4 + bit_size: 1 + description: Receive FIFO nonempty mask + name: RXFLVLM + - bit_offset: 5 + bit_size: 1 + description: Nonperiodic TxFIFO empty mask + name: NPTXFEM + - bit_offset: 6 + bit_size: 1 + description: Global nonperiodic IN NAK effective mask + name: GINAKEFFM + - bit_offset: 7 + bit_size: 1 + description: Global OUT NAK effective mask + name: GONAKEFFM + - bit_offset: 10 + bit_size: 1 + description: Early suspend mask + name: ESUSPM + - bit_offset: 11 + bit_size: 1 + description: USB suspend mask + name: USBSUSPM + - bit_offset: 12 + bit_size: 1 + description: USB reset mask + name: USBRST + - bit_offset: 13 + bit_size: 1 + description: Enumeration done mask + name: ENUMDNEM + - bit_offset: 14 + bit_size: 1 + description: Isochronous OUT packet dropped interrupt mask + name: ISOODRPM + - bit_offset: 15 + bit_size: 1 + description: End of periodic frame interrupt mask + name: EOPFM + - bit_offset: 18 + bit_size: 1 + description: IN endpoints interrupt mask + name: IEPINT + - bit_offset: 19 + bit_size: 1 + description: OUT endpoints interrupt mask + name: OEPINT + - bit_offset: 20 + bit_size: 1 + description: Incomplete isochronous IN transfer mask + name: IISOIXFRM + - bit_offset: 21 + bit_size: 1 + description: Incomplete periodic transfer mask + name: PXFRM_IISOOXFRM + - bit_offset: 22 + bit_size: 1 + description: Data fetch suspended mask + name: FSUSPM + - bit_offset: 23 + bit_size: 1 + description: Reset detected interrupt mask + name: RSTDE + - bit_offset: 24 + bit_size: 1 + description: Host port interrupt mask + name: PRTIM + - bit_offset: 25 + bit_size: 1 + description: Host channels interrupt mask + name: HCIM + - bit_offset: 26 + bit_size: 1 + description: Periodic TxFIFO empty mask + name: PTXFEM + - bit_offset: 27 + bit_size: 1 + description: LPM interrupt mask + name: LPMINTM + - bit_offset: 28 + bit_size: 1 + description: Connector ID status change mask + name: CIDSCHGM + - bit_offset: 29 + bit_size: 1 + description: Disconnect detected interrupt mask + name: DISCINT + - bit_offset: 30 + bit_size: 1 + description: Session request/new session detected interrupt mask + name: SRQIM + - bit_offset: 31 + bit_size: 1 + description: Resume/remote wakeup detected interrupt mask + name: WUIM +fieldset/OTG_HS_GINTSTS: + description: OTG_HS core interrupt register + fields: + - bit_offset: 0 + bit_size: 1 + description: Current mode of operation + name: CMOD + - bit_offset: 1 + bit_size: 1 + description: Mode mismatch interrupt + name: MMIS + - bit_offset: 2 + bit_size: 1 + description: OTG interrupt + name: OTGINT + - bit_offset: 3 + bit_size: 1 + description: Start of frame + name: SOF + - bit_offset: 4 + bit_size: 1 + description: RxFIFO nonempty + name: RXFLVL + - bit_offset: 5 + bit_size: 1 + description: Nonperiodic TxFIFO empty + name: NPTXFE + - bit_offset: 6 + bit_size: 1 + description: Global IN nonperiodic NAK effective + name: GINAKEFF + - bit_offset: 7 + bit_size: 1 + description: Global OUT NAK effective + name: BOUTNAKEFF + - bit_offset: 10 + bit_size: 1 + description: Early suspend + name: ESUSP + - bit_offset: 11 + bit_size: 1 + description: USB suspend + name: USBSUSP + - bit_offset: 12 + bit_size: 1 + description: USB reset + name: USBRST + - bit_offset: 13 + bit_size: 1 + description: Enumeration done + name: ENUMDNE + - bit_offset: 14 + bit_size: 1 + description: Isochronous OUT packet dropped interrupt + name: ISOODRP + - bit_offset: 15 + bit_size: 1 + description: End of periodic frame interrupt + name: EOPF + - bit_offset: 18 + bit_size: 1 + description: IN endpoint interrupt + name: IEPINT + - bit_offset: 19 + bit_size: 1 + description: OUT endpoint interrupt + name: OEPINT + - bit_offset: 20 + bit_size: 1 + description: Incomplete isochronous IN transfer + name: IISOIXFR + - bit_offset: 21 + bit_size: 1 + description: Incomplete periodic transfer + name: PXFR_INCOMPISOOUT + - bit_offset: 22 + bit_size: 1 + description: Data fetch suspended + name: DATAFSUSP + - bit_offset: 24 + bit_size: 1 + description: Host port interrupt + name: HPRTINT + - bit_offset: 25 + bit_size: 1 + description: Host channels interrupt + name: HCINT + - bit_offset: 26 + bit_size: 1 + description: Periodic TxFIFO empty + name: PTXFE + - bit_offset: 28 + bit_size: 1 + description: Connector ID status change + name: CIDSCHG + - bit_offset: 29 + bit_size: 1 + description: Disconnect detected interrupt + name: DISCINT + - bit_offset: 30 + bit_size: 1 + description: Session request/new session detected interrupt + name: SRQINT + - bit_offset: 31 + bit_size: 1 + description: Resume/remote wakeup detected interrupt + name: WKUINT +fieldset/OTG_HS_GLPMCFG: + description: OTG core LPM configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: LPM support enable + name: LPMEN + - bit_offset: 1 + bit_size: 1 + description: LPM token acknowledge enable + name: LPMACK + - bit_offset: 2 + bit_size: 4 + description: Best effort service latency + name: BESL + - bit_offset: 6 + bit_size: 1 + description: bRemoteWake value + name: REMWAKE + - bit_offset: 7 + bit_size: 1 + description: L1 Shallow Sleep enable + name: L1SSEN + - bit_offset: 8 + bit_size: 4 + description: BESL threshold + name: BESLTHRS + - bit_offset: 12 + bit_size: 1 + description: L1 deep sleep enable + name: L1DSEN + - bit_offset: 13 + bit_size: 2 + description: LPM response + name: LPMRST + - bit_offset: 15 + bit_size: 1 + description: Port sleep status + name: SLPSTS + - bit_offset: 16 + bit_size: 1 + description: Sleep State Resume OK + name: L1RSMOK + - bit_offset: 17 + bit_size: 4 + description: LPM Channel Index + name: LPMCHIDX + - bit_offset: 21 + bit_size: 3 + description: LPM retry count + name: LPMRCNT + - bit_offset: 24 + bit_size: 1 + description: Send LPM transaction + name: SNDLPM + - bit_offset: 25 + bit_size: 3 + description: LPM retry count status + name: LPMRCNTSTS + - bit_offset: 28 + bit_size: 1 + description: Enable best effort service latency + name: ENBESL +fieldset/OTG_HS_GNPTXSTS: + description: OTG_HS nonperiodic transmit FIFO/queue status register + fields: + - bit_offset: 0 + bit_size: 16 + description: Nonperiodic TxFIFO space available + name: NPTXFSAV + - bit_offset: 16 + bit_size: 8 + description: Nonperiodic transmit request queue space available + name: NPTQXSAV + - bit_offset: 24 + bit_size: 7 + description: Top of the nonperiodic transmit request queue + name: NPTXQTOP +fieldset/OTG_HS_GOTGCTL: + description: OTG_HS control and status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Session request success + name: SRQSCS + - bit_offset: 1 + bit_size: 1 + description: Session request + name: SRQ + - bit_offset: 8 + bit_size: 1 + description: Host negotiation success + name: HNGSCS + - bit_offset: 9 + bit_size: 1 + description: HNP request + name: HNPRQ + - bit_offset: 10 + bit_size: 1 + description: Host set HNP enable + name: HSHNPEN + - bit_offset: 11 + bit_size: 1 + description: Device HNP enabled + name: DHNPEN + - bit_offset: 12 + bit_size: 1 + description: Embedded host enable + name: EHEN + - bit_offset: 16 + bit_size: 1 + description: Connector ID status + name: CIDSTS + - bit_offset: 17 + bit_size: 1 + description: Long/short debounce time + name: DBCT + - bit_offset: 18 + bit_size: 1 + description: A-session valid + name: ASVLD + - bit_offset: 19 + bit_size: 1 + description: B-session valid + name: BSVLD +fieldset/OTG_HS_GOTGINT: + description: OTG_HS interrupt register + fields: + - bit_offset: 2 + bit_size: 1 + description: Session end detected + name: SEDET + - bit_offset: 8 + bit_size: 1 + description: Session request success status change + name: SRSSCHG + - bit_offset: 9 + bit_size: 1 + description: Host negotiation success status change + name: HNSSCHG + - bit_offset: 17 + bit_size: 1 + description: Host negotiation detected + name: HNGDET + - bit_offset: 18 + bit_size: 1 + description: A-device timeout change + name: ADTOCHG + - bit_offset: 19 + bit_size: 1 + description: Debounce done + name: DBCDNE + - bit_offset: 20 + bit_size: 1 + description: ID input pin changed + name: IDCHNG +fieldset/OTG_HS_GRSTCTL: + description: OTG_HS reset register + fields: + - bit_offset: 0 + bit_size: 1 + description: Core soft reset + name: CSRST + - bit_offset: 1 + bit_size: 1 + description: HCLK soft reset + name: HSRST + - bit_offset: 2 + bit_size: 1 + description: Host frame counter reset + name: FCRST + - bit_offset: 4 + bit_size: 1 + description: RxFIFO flush + name: RXFFLSH + - bit_offset: 5 + bit_size: 1 + description: TxFIFO flush + name: TXFFLSH + - bit_offset: 6 + bit_size: 5 + description: TxFIFO number + name: TXFNUM + - bit_offset: 30 + bit_size: 1 + description: DMA request signal enabled for USB OTG HS + name: DMAREQ + - bit_offset: 31 + bit_size: 1 + description: AHB master idle + name: AHBIDL +fieldset/OTG_HS_GRXFSIZ: + description: OTG_HS Receive FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: RxFIFO depth + name: RXFD +fieldset/OTG_HS_GRXSTSP_Device: + description: OTG_HS status read and pop register (peripheral mode) + fields: + - bit_offset: 0 + bit_size: 4 + description: Endpoint number + name: EPNUM + - bit_offset: 4 + bit_size: 11 + description: Byte count + name: BCNT + - bit_offset: 15 + bit_size: 2 + description: Data PID + name: DPID + - bit_offset: 17 + bit_size: 4 + description: Packet status + name: PKTSTS + - bit_offset: 21 + bit_size: 4 + description: Frame number + name: FRMNUM +fieldset/OTG_HS_GRXSTSP_Host: + description: OTG_HS status read and pop register (host mode) + fields: + - bit_offset: 0 + bit_size: 4 + description: Channel number + name: CHNUM + - bit_offset: 4 + bit_size: 11 + description: Byte count + name: BCNT + - bit_offset: 15 + bit_size: 2 + description: Data PID + name: DPID + - bit_offset: 17 + bit_size: 4 + description: Packet status + name: PKTSTS +fieldset/OTG_HS_GRXSTSR_Device: + description: OTG_HS Receive status debug read register (peripheral mode mode) + fields: + - bit_offset: 0 + bit_size: 4 + description: Endpoint number + name: EPNUM + - bit_offset: 4 + bit_size: 11 + description: Byte count + name: BCNT + - bit_offset: 15 + bit_size: 2 + description: Data PID + name: DPID + - bit_offset: 17 + bit_size: 4 + description: Packet status + name: PKTSTS + - bit_offset: 21 + bit_size: 4 + description: Frame number + name: FRMNUM +fieldset/OTG_HS_GRXSTSR_Host: + description: OTG_HS Receive status debug read register (host mode) + fields: + - bit_offset: 0 + bit_size: 4 + description: Channel number + name: CHNUM + - bit_offset: 4 + bit_size: 11 + description: Byte count + name: BCNT + - bit_offset: 15 + bit_size: 2 + description: Data PID + name: DPID + - bit_offset: 17 + bit_size: 4 + description: Packet status + name: PKTSTS +fieldset/OTG_HS_GUSBCFG: + description: OTG_HS USB configuration register + fields: + - bit_offset: 0 + bit_size: 3 + description: FS timeout calibration + name: TOCAL + - bit_offset: 6 + bit_size: 1 + description: USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver + select + name: PHYSEL + - bit_offset: 8 + bit_size: 1 + description: SRP-capable + name: SRPCAP + - bit_offset: 9 + bit_size: 1 + description: HNP-capable + name: HNPCAP + - bit_offset: 10 + bit_size: 4 + description: USB turnaround time + name: TRDT + - bit_offset: 15 + bit_size: 1 + description: PHY Low-power clock select + name: PHYLPCS + - bit_offset: 17 + bit_size: 1 + description: ULPI FS/LS select + name: ULPIFSLS + - bit_offset: 18 + bit_size: 1 + description: ULPI Auto-resume + name: ULPIAR + - bit_offset: 19 + bit_size: 1 + description: ULPI Clock SuspendM + name: ULPICSM + - bit_offset: 20 + bit_size: 1 + description: ULPI External VBUS Drive + name: ULPIEVBUSD + - bit_offset: 21 + bit_size: 1 + description: ULPI external VBUS indicator + name: ULPIEVBUSI + - bit_offset: 22 + bit_size: 1 + description: TermSel DLine pulsing selection + name: TSDPS + - bit_offset: 23 + bit_size: 1 + description: Indicator complement + name: PCCI + - bit_offset: 24 + bit_size: 1 + description: Indicator pass through + name: PTCI + - bit_offset: 25 + bit_size: 1 + description: ULPI interface protect disable + name: ULPIIPD + - bit_offset: 29 + bit_size: 1 + description: Forced host mode + name: FHMOD + - bit_offset: 30 + bit_size: 1 + description: Forced peripheral mode + name: FDMOD +fieldset/OTG_HS_HNPTXFSIZ_Host: + description: OTG_HS nonperiodic transmit FIFO size register (host mode) + fields: + - bit_offset: 0 + bit_size: 16 + description: Nonperiodic transmit RAM start address + name: NPTXFSA + - bit_offset: 16 + bit_size: 16 + description: Nonperiodic TxFIFO depth + name: NPTXFD +fieldset/OTG_HS_HNPTXSTS: + description: OTG_HS nonperiodic transmit FIFO/queue status register + fields: + - bit_offset: 0 + bit_size: 16 + description: Nonperiodic TxFIFO space available + name: NPTXFSAV + - bit_offset: 16 + bit_size: 8 + description: Nonperiodic transmit request queue space available + name: NPTQXSAV + - bit_offset: 24 + bit_size: 7 + description: Top of the nonperiodic transmit request queue + name: NPTXQTOP +fieldset/OTG_HS_HPTXFSIZ: + description: OTG_HS Host periodic transmit FIFO size register + fields: + - bit_offset: 0 + bit_size: 16 + description: Host periodic TxFIFO start address + name: PTXSA + - bit_offset: 16 + bit_size: 16 + description: Host periodic TxFIFO depth + name: PTXFD diff --git a/data/registers/pwr_f7.yaml b/data/registers/pwr_f7.yaml new file mode 100644 index 0000000..fc96a97 --- /dev/null +++ b/data/registers/pwr_f7.yaml @@ -0,0 +1,182 @@ +--- +block/PWR: + description: Power control + items: + - byte_offset: 0 + description: power control register + fieldset: CR1 + name: CR1 + - byte_offset: 4 + description: power control/status register + fieldset: CSR1 + name: CSR1 + - byte_offset: 8 + description: power control register + fieldset: CR2 + name: CR2 + - byte_offset: 12 + description: power control/status register + fieldset: CSR2 + name: CSR2 +enum/PDDS: + bit_size: 1 + variants: + - description: Enter Stop mode when the CPU enters deepsleep + name: STOP_MODE + value: 0 + - description: Enter Standby mode when the CPU enters deepsleep + name: STANDBY_MODE + value: 1 +enum/VOS: + bit_size: 2 + variants: + - description: Scale 3 mode + name: SCALE3 + value: 1 + - description: Scale 2 mode + name: SCALE2 + value: 2 + - description: Scale 1 mode (reset value) + name: SCALE1 + value: 3 +fieldset/CR1: + description: power control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Low-power deep sleep + name: LPDS + - bit_offset: 1 + bit_size: 1 + description: Power down deepsleep + enum: PDDS + name: PDDS + - bit_offset: 3 + bit_size: 1 + description: Clear standby flag + name: CSBF + - bit_offset: 4 + bit_size: 1 + description: Power voltage detector enable + name: PVDE + - bit_offset: 5 + bit_size: 3 + description: PVD level selection + name: PLS + - bit_offset: 8 + bit_size: 1 + description: Disable backup domain write protection + name: DBP + - bit_offset: 9 + bit_size: 1 + description: Flash power down in Stop mode + name: FPDS + - bit_offset: 10 + bit_size: 1 + description: Low-power regulator in deepsleep under-drive mode + name: LPUDS + - bit_offset: 11 + bit_size: 1 + description: Main regulator in deepsleep under-drive mode + name: MRUDS + - array: + len: 1 + stride: 0 + bit_offset: 13 + bit_size: 1 + description: ADCDC1 + name: ADCDC + - bit_offset: 14 + bit_size: 2 + description: Regulator voltage scaling output selection + enum: VOS + name: VOS + - bit_offset: 16 + bit_size: 1 + description: Over-drive enable + name: ODEN + - bit_offset: 17 + bit_size: 1 + description: Over-drive switching enabled + name: ODSWEN + - bit_offset: 18 + bit_size: 2 + description: Under-drive enable in stop mode + name: UDEN +fieldset/CR2: + description: power control register + fields: + - array: + len: 6 + stride: 1 + bit_offset: 0 + bit_size: 1 + description: Clear Wakeup Pin flag for PA0 + name: CWUPF + - array: + len: 6 + stride: 1 + bit_offset: 8 + bit_size: 1 + description: Wakeup pin polarity bit for PA0 + name: WUPP +fieldset/CSR1: + description: power control/status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Wakeup internal flag + name: WUIF + - bit_offset: 1 + bit_size: 1 + description: Standby flag + name: SBF + - bit_offset: 2 + bit_size: 1 + description: PVD output + name: PVDO + - bit_offset: 3 + bit_size: 1 + description: Backup regulator ready + name: BRR + - bit_offset: 8 + bit_size: 1 + description: Enable internal wakeup + name: EIWUP + - bit_offset: 9 + bit_size: 1 + description: Backup regulator enable + name: BRE + - bit_offset: 14 + bit_size: 1 + description: Regulator voltage scaling output selection ready bit + name: VOSRDY + - bit_offset: 16 + bit_size: 1 + description: Over-drive mode ready + name: ODRDY + - bit_offset: 17 + bit_size: 1 + description: Over-drive mode switching ready + name: ODSWRDY + - bit_offset: 18 + bit_size: 2 + description: Under-drive ready flag + name: UDRDY +fieldset/CSR2: + description: power control/status register + fields: + - array: + len: 6 + stride: 1 + bit_offset: 0 + bit_size: 1 + description: Wakeup Pin flag for PA0 + name: WUPF + - array: + len: 6 + stride: 1 + bit_offset: 8 + bit_size: 1 + description: Enable Wakeup pin for PA0 + name: EWUP diff --git a/data/registers/quadspi_v1.yaml b/data/registers/quadspi_v1.yaml new file mode 100644 index 0000000..46d8e60 --- /dev/null +++ b/data/registers/quadspi_v1.yaml @@ -0,0 +1,296 @@ +--- +block/QUADSPI: + description: QuadSPI interface + items: + - byte_offset: 0 + description: control register + fieldset: CR + name: CR + - byte_offset: 4 + description: device configuration register + fieldset: DCR + name: DCR + - access: Read + byte_offset: 8 + description: status register + fieldset: SR + name: SR + - byte_offset: 12 + description: flag clear register + fieldset: FCR + name: FCR + - byte_offset: 16 + description: data length register + fieldset: DLR + name: DLR + - byte_offset: 20 + description: communication configuration register + fieldset: CCR + name: CCR + - byte_offset: 24 + description: address register + fieldset: AR + name: AR + - byte_offset: 28 + description: ABR + fieldset: ABR + name: ABR + - byte_offset: 32 + description: data register + fieldset: DR + name: DR + - byte_offset: 36 + description: polling status mask register + fieldset: PSMKR + name: PSMKR + - byte_offset: 40 + description: polling status match register + fieldset: PSMAR + name: PSMAR + - byte_offset: 44 + description: polling interval register + fieldset: PIR + name: PIR + - byte_offset: 48 + description: low-power timeout register + fieldset: LPTR + name: LPTR +fieldset/ABR: + description: ABR + fields: + - bit_offset: 0 + bit_size: 32 + description: ALTERNATE + name: ALTERNATE +fieldset/AR: + description: address register + fields: + - bit_offset: 0 + bit_size: 32 + description: Address + name: ADDRESS +fieldset/CCR: + description: communication configuration register + fields: + - bit_offset: 0 + bit_size: 8 + description: Instruction + name: INSTRUCTION + - bit_offset: 8 + bit_size: 2 + description: Instruction mode + name: IMODE + - bit_offset: 10 + bit_size: 2 + description: Address mode + name: ADMODE + - bit_offset: 12 + bit_size: 2 + description: Address size + name: ADSIZE + - bit_offset: 14 + bit_size: 2 + description: Alternate bytes mode + name: ABMODE + - bit_offset: 16 + bit_size: 2 + description: Alternate bytes size + name: ABSIZE + - bit_offset: 18 + bit_size: 5 + description: Number of dummy cycles + name: DCYC + - bit_offset: 24 + bit_size: 2 + description: Data mode + name: DMODE + - bit_offset: 26 + bit_size: 2 + description: Functional mode + name: FMODE + - bit_offset: 28 + bit_size: 1 + description: Send instruction only once mode + name: SIOO + - bit_offset: 30 + bit_size: 1 + description: DDR hold half cycle + name: DHHC + - bit_offset: 31 + bit_size: 1 + description: Double data rate mode + name: DDRM +fieldset/CR: + description: control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Enable + name: EN + - bit_offset: 1 + bit_size: 1 + description: Abort request + name: ABORT + - bit_offset: 2 + bit_size: 1 + description: DMA enable + name: DMAEN + - bit_offset: 3 + bit_size: 1 + description: Timeout counter enable + name: TCEN + - bit_offset: 4 + bit_size: 1 + description: Sample shift + name: SSHIFT + - bit_offset: 6 + bit_size: 1 + description: Dual-flash mode + name: DFM + - bit_offset: 7 + bit_size: 1 + description: FLASH memory selection + name: FSEL + - bit_offset: 8 + bit_size: 5 + description: IFO threshold level + name: FTHRES + - bit_offset: 16 + bit_size: 1 + description: Transfer error interrupt enable + name: TEIE + - bit_offset: 17 + bit_size: 1 + description: Transfer complete interrupt enable + name: TCIE + - bit_offset: 18 + bit_size: 1 + description: FIFO threshold interrupt enable + name: FTIE + - bit_offset: 19 + bit_size: 1 + description: Status match interrupt enable + name: SMIE + - bit_offset: 20 + bit_size: 1 + description: TimeOut interrupt enable + name: TOIE + - bit_offset: 22 + bit_size: 1 + description: Automatic poll mode stop + name: APMS + - bit_offset: 23 + bit_size: 1 + description: Polling match mode + name: PMM + - bit_offset: 24 + bit_size: 8 + description: Clock prescaler + name: PRESCALER +fieldset/DCR: + description: device configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Mode 0 / mode 3 + name: CKMODE + - bit_offset: 8 + bit_size: 3 + description: Chip select high time + name: CSHT + - bit_offset: 16 + bit_size: 5 + description: FLASH memory size + name: FSIZE +fieldset/DLR: + description: data length register + fields: + - bit_offset: 0 + bit_size: 32 + description: Data length + name: DL +fieldset/DR: + description: data register + fields: + - bit_offset: 0 + bit_size: 32 + description: Data + name: DATA +fieldset/FCR: + description: flag clear register + fields: + - bit_offset: 0 + bit_size: 1 + description: Clear transfer error flag + name: CTEF + - bit_offset: 1 + bit_size: 1 + description: Clear transfer complete flag + name: CTCF + - bit_offset: 3 + bit_size: 1 + description: Clear status match flag + name: CSMF + - bit_offset: 4 + bit_size: 1 + description: Clear timeout flag + name: CTOF +fieldset/LPTR: + description: low-power timeout register + fields: + - bit_offset: 0 + bit_size: 16 + description: Timeout period + name: TIMEOUT +fieldset/PIR: + description: polling interval register + fields: + - bit_offset: 0 + bit_size: 16 + description: Polling interval + name: INTERVAL +fieldset/PSMAR: + description: polling status match register + fields: + - bit_offset: 0 + bit_size: 32 + description: Status match + name: MATCH +fieldset/PSMKR: + description: polling status mask register + fields: + - bit_offset: 0 + bit_size: 32 + description: Status mask + name: MASK +fieldset/SR: + description: status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Transfer error flag + name: TEF + - bit_offset: 1 + bit_size: 1 + description: Transfer complete flag + name: TCF + - bit_offset: 2 + bit_size: 1 + description: FIFO threshold flag + name: FTF + - bit_offset: 3 + bit_size: 1 + description: Status match flag + name: SMF + - bit_offset: 4 + bit_size: 1 + description: Timeout flag + name: TOF + - bit_offset: 5 + bit_size: 1 + description: Busy + name: BUSY + - bit_offset: 8 + bit_size: 7 + description: FIFO level + name: FLEVEL diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index 4639c96..2d5cc7a 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -1,3 +1,4 @@ +--- block/RCC: description: Reset and clock control items: @@ -114,6 +115,15 @@ enum/ADFSDMSEL: - description: SAI2 clock selected as DFSDM1 Audio clock source name: SAI2 value: 1 +enum/BORRSTFR: + bit_size: 1 + variants: + - description: No reset has occured + name: NoReset + value: 0 + - description: A reset has occured + name: Reset + value: 1 enum/CECSEL: bit_size: 1 variants: @@ -205,6 +215,15 @@ enum/HSEBYP: - description: HSE crystal oscillator bypassed with external clock name: Bypassed value: 1 +enum/HSIRDYR: + bit_size: 1 + variants: + - description: Clock not ready + name: NotReady + value: 0 + - description: Clock ready + name: Ready + value: 1 enum/ICSEL: bit_size: 2 variants: @@ -241,15 +260,6 @@ enum/LPTIMSEL: - description: LSE clock is selected as LPTILM1 clock name: LSE value: 3 -enum/LPWRRSTFR: - bit_size: 1 - variants: - - description: No reset has occured - name: NoReset - value: 0 - - description: A reset has occured - name: Reset - value: 1 enum/LSEBYP: bit_size: 1 variants: @@ -283,6 +293,30 @@ enum/LSERDYR: - description: LSE oscillator ready name: Ready value: 1 +enum/LSIRDYCW: + bit_size: 1 + variants: + - description: Clear interrupt flag + name: Clear + value: 1 +enum/LSIRDYFR: + bit_size: 1 + variants: + - description: No clock ready interrupt + name: NotInterrupted + value: 0 + - description: Clock ready interrupt + name: Interrupted + value: 1 +enum/LSIRDYIE: + bit_size: 1 + variants: + - description: Interrupt disabled + name: Disabled + value: 0 + - description: Interrupt enabled + name: Enabled + value: 1 enum/LSIRDYR: bit_size: 1 variants: @@ -454,15 +488,6 @@ enum/PLLISP: - description: PLL*P=8 name: Div8 value: 3 -enum/PLLISRDYR: - bit_size: 1 - variants: - - description: Clock not ready - name: NotReady - value: 0 - - description: Clock ready - name: Ready - value: 1 enum/PLLP: bit_size: 2 variants: @@ -607,30 +632,6 @@ enum/PLLSAIP: - description: PLL*P=8 name: Div8 value: 3 -enum/PLLSAIRDYCW: - bit_size: 1 - variants: - - description: Clear interrupt flag - name: Clear - value: 1 -enum/PLLSAIRDYFR: - bit_size: 1 - variants: - - description: No clock ready interrupt - name: NotInterrupted - value: 0 - - description: Clock ready interrupt - name: Interrupted - value: 1 -enum/PLLSAIRDYIE: - bit_size: 1 - variants: - - description: Interrupt disabled - name: Disabled - value: 0 - - description: Interrupt enabled - name: Enabled - value: 1 enum/PLLSRC: bit_size: 1 variants: @@ -836,10 +837,6 @@ fieldset/AHB1ENR: bit_size: 1 description: CCM data RAM clock enable name: DTCMRAMEN - - bit_offset: 20 - bit_size: 1 - description: CCM data RAM clock enable - name: CCMDATARAMEN - bit_offset: 21 bit_size: 1 description: DMA1 clock enable @@ -855,27 +852,27 @@ fieldset/AHB1ENR: - bit_offset: 25 bit_size: 1 description: Ethernet MAC clock enable - name: ETHMACEN + name: ETHEN - bit_offset: 26 bit_size: 1 description: Ethernet Transmission clock enable - name: ETHMACTXEN + name: ETHTXEN - bit_offset: 27 bit_size: 1 description: Ethernet Reception clock enable - name: ETHMACRXEN + name: ETHRXEN - bit_offset: 28 bit_size: 1 description: Ethernet PTP clock enable - name: ETHMACPTPEN + name: ETHPTPEN - bit_offset: 29 bit_size: 1 description: USB OTG HS clock enable - name: OTGHSEN + name: USB_OTG_HSEN - bit_offset: 30 bit_size: 1 description: USB OTG HSULPI clock enable - name: OTGHSULPIEN + name: USB_OTG_HSULPIEN fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: @@ -970,27 +967,27 @@ fieldset/AHB1LPENR: - bit_offset: 25 bit_size: 1 description: Ethernet MAC clock enable during Sleep mode - name: ETHMACLPEN + name: ETHLPEN - bit_offset: 26 bit_size: 1 description: Ethernet transmission clock enable during Sleep mode - name: ETHMACTXLPEN + name: ETHTXLPEN - bit_offset: 27 bit_size: 1 description: Ethernet reception clock enable during Sleep mode - name: ETHMACRXLPEN + name: ETHRXLPEN - bit_offset: 28 bit_size: 1 description: Ethernet PTP clock enable during Sleep mode - name: ETHMACPTPLPEN + name: ETHPTPLPEN - bit_offset: 29 bit_size: 1 description: USB OTG HS clock enable during Sleep mode - name: OTGHSLPEN + name: USB_OTG_HSLPEN - bit_offset: 30 bit_size: 1 description: USB OTG HS ULPI clock enable during Sleep mode - name: OTGHSULPILPEN + name: USB_OTG_HSULPILPEN fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: @@ -1057,11 +1054,11 @@ fieldset/AHB1RSTR: - bit_offset: 25 bit_size: 1 description: Ethernet MAC reset - name: ETHMACRST + name: ETHRST - bit_offset: 29 bit_size: 1 description: USB OTG HS module reset - name: OTGHSRST + name: USB_OTG_HSRST fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: @@ -1069,6 +1066,10 @@ fieldset/AHB2ENR: bit_size: 1 description: Camera interface enable name: DCMIEN + - bit_offset: 1 + bit_size: 1 + description: JPEG enable + name: JPEGEN - bit_offset: 4 bit_size: 1 description: AES module clock enable @@ -1088,7 +1089,7 @@ fieldset/AHB2ENR: - bit_offset: 7 bit_size: 1 description: USB OTG FS clock enable - name: OTGFSEN + name: USB_OTG_FSEN fieldset/AHB2LPENR: description: AHB2 peripheral clock enable in low power mode register fields: @@ -1096,6 +1097,10 @@ fieldset/AHB2LPENR: bit_size: 1 description: Camera interface enable during Sleep mode name: DCMILPEN + - bit_offset: 1 + bit_size: 1 + description: JPEG module enabled during Sleep mode + name: JPEGLPEN - bit_offset: 4 bit_size: 1 description: AES module clock enable during Sleep mode @@ -1115,7 +1120,7 @@ fieldset/AHB2LPENR: - bit_offset: 7 bit_size: 1 description: USB OTG FS clock enable during Sleep mode - name: OTGFSLPEN + name: USB_OTG_FSLPEN fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: @@ -1142,7 +1147,7 @@ fieldset/AHB2RSTR: - bit_offset: 7 bit_size: 1 description: USB OTG FS module reset - name: OTGFSRST + name: USB_OTG_FSRST fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: @@ -1153,7 +1158,7 @@ fieldset/AHB3ENR: - bit_offset: 1 bit_size: 1 description: Quad SPI memory controller clock enable - name: QSPIEN + name: QUADSPIEN fieldset/AHB3LPENR: description: AHB3 peripheral clock enable in low power mode register fields: @@ -1164,7 +1169,7 @@ fieldset/AHB3LPENR: - bit_offset: 1 bit_size: 1 description: Quand SPI memory controller clock enable during Sleep mode - name: QSPILPEN + name: QUADSPILPEN fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: @@ -1175,7 +1180,7 @@ fieldset/AHB3RSTR: - bit_offset: 1 bit_size: 1 description: Quad SPI memory controller reset - name: QSPIRST + name: QUADSPIRST fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: @@ -1219,18 +1224,18 @@ fieldset/APB1ENR: bit_size: 1 description: Low power timer 1 clock enable name: LPTIM1EN - - bit_offset: 9 - bit_size: 1 - description: Low power timer 1 clock enable - name: LPTMI1EN - bit_offset: 10 bit_size: 1 description: RTCAPB clock enable - name: RTCAPBEN + name: RTCEN - bit_offset: 11 bit_size: 1 description: Window watchdog clock enable name: WWDGEN + - bit_offset: 13 + bit_size: 1 + description: CAN 3 enable + name: CAN3EN - bit_offset: 14 bit_size: 1 description: SPI2 clock enable @@ -1346,10 +1351,18 @@ fieldset/APB1LPENR: bit_size: 1 description: low power timer 1 clock enable during Sleep mode name: LPTIM1LPEN + - bit_offset: 10 + bit_size: 1 + description: RTCAPB clock enable during Sleep mode + name: RTCLPEN - bit_offset: 11 bit_size: 1 description: Window watchdog clock enable during Sleep mode name: WWDGLPEN + - bit_offset: 13 + bit_size: 1 + description: CAN 3 clock enable during Sleep mode + name: CAN3LPEN - bit_offset: 14 bit_size: 1 description: SPI2 clock enable during Sleep mode @@ -1469,6 +1482,10 @@ fieldset/APB1RSTR: bit_size: 1 description: Window watchdog reset name: WWDGRST + - bit_offset: 13 + bit_size: 1 + description: CAN 3 reset + name: CAN3RST - bit_offset: 14 bit_size: 1 description: SPI 2 reset @@ -1484,11 +1501,11 @@ fieldset/APB1RSTR: - bit_offset: 17 bit_size: 1 description: USART 2 reset - name: UART2RST + name: USART2RST - bit_offset: 18 bit_size: 1 description: USART 3 reset - name: UART3RST + name: USART3RST - bit_offset: 19 bit_size: 1 description: USART 4 reset @@ -1624,10 +1641,18 @@ fieldset/APB2ENR: bit_size: 1 description: LTDC clock enable name: LTDCEN + - bit_offset: 27 + bit_size: 1 + description: DSI clock enable + name: DSIEN + - bit_offset: 29 + bit_size: 1 + description: DFSDM1 clock enable + name: DFSDM1EN - bit_offset: 30 bit_size: 1 description: MDIO clock enable - name: MDIOEN + name: MDIOSEN - bit_offset: 31 bit_size: 1 description: USB OTG HS PHY controller clock enable @@ -1715,6 +1740,18 @@ fieldset/APB2LPENR: bit_size: 1 description: LTDC clock enable during sleep mode name: LTDCLPEN + - bit_offset: 27 + bit_size: 1 + description: DSI clock enable during Sleep mode + name: DSILPEN + - bit_offset: 29 + bit_size: 1 + description: DFSDM1 clock enable during Sleep mode + name: DFSDM1LPEN + - bit_offset: 30 + bit_size: 1 + description: MDIO clock enable during Sleep mode + name: MDIOSLPEN fieldset/APB2RSTR: description: APB2 peripheral reset register fields: @@ -1790,6 +1827,18 @@ fieldset/APB2RSTR: bit_size: 1 description: LTDC reset name: LTDCRST + - bit_offset: 27 + bit_size: 1 + description: DSI reset + name: DSIRST + - bit_offset: 29 + bit_size: 1 + description: DFSDM 1 reset + name: DFSDM1RST + - bit_offset: 30 + bit_size: 1 + description: MDIOS reset + name: MDIOSRST - bit_offset: 31 bit_size: 1 description: USB OTG HS PHY controller reset @@ -1892,37 +1941,37 @@ fieldset/CIR: - bit_offset: 0 bit_size: 1 description: LSI ready interrupt flag - enum_read: PLLSAIRDYFR + enum_read: LSIRDYFR name: LSIRDYF - bit_offset: 1 bit_size: 1 description: LSE ready interrupt flag - enum_read: PLLSAIRDYFR + enum_read: LSIRDYFR name: LSERDYF - bit_offset: 2 bit_size: 1 description: HSI ready interrupt flag - enum_read: PLLSAIRDYFR + enum_read: LSIRDYFR name: HSIRDYF - bit_offset: 3 bit_size: 1 description: HSE ready interrupt flag - enum_read: PLLSAIRDYFR + enum_read: LSIRDYFR name: HSERDYF - bit_offset: 4 bit_size: 1 description: Main PLL (PLL) ready interrupt flag - enum_read: PLLSAIRDYFR + enum_read: LSIRDYFR name: PLLRDYF - bit_offset: 5 bit_size: 1 description: PLLI2S ready interrupt flag - enum_read: PLLSAIRDYFR + enum_read: LSIRDYFR name: PLLI2SRDYF - bit_offset: 6 bit_size: 1 description: PLLSAI ready interrupt flag - enum_read: PLLSAIRDYFR + enum_read: LSIRDYFR name: PLLSAIRDYF - bit_offset: 7 bit_size: 1 @@ -1932,72 +1981,72 @@ fieldset/CIR: - bit_offset: 8 bit_size: 1 description: LSI ready interrupt enable - enum: PLLSAIRDYIE + enum: LSIRDYIE name: LSIRDYIE - bit_offset: 9 bit_size: 1 description: LSE ready interrupt enable - enum: PLLSAIRDYIE + enum: LSIRDYIE name: LSERDYIE - bit_offset: 10 bit_size: 1 description: HSI ready interrupt enable - enum: PLLSAIRDYIE + enum: LSIRDYIE name: HSIRDYIE - bit_offset: 11 bit_size: 1 description: HSE ready interrupt enable - enum: PLLSAIRDYIE + enum: LSIRDYIE name: HSERDYIE - bit_offset: 12 bit_size: 1 description: Main PLL (PLL) ready interrupt enable - enum: PLLSAIRDYIE + enum: LSIRDYIE name: PLLRDYIE - bit_offset: 13 bit_size: 1 description: PLLI2S ready interrupt enable - enum: PLLSAIRDYIE + enum: LSIRDYIE name: PLLI2SRDYIE - bit_offset: 14 bit_size: 1 description: PLLSAI Ready Interrupt Enable - enum: PLLSAIRDYIE + enum: LSIRDYIE name: PLLSAIRDYIE - bit_offset: 16 bit_size: 1 description: LSI ready interrupt clear - enum_write: PLLSAIRDYCW + enum_write: LSIRDYCW name: LSIRDYC - bit_offset: 17 bit_size: 1 description: LSE ready interrupt clear - enum_write: PLLSAIRDYCW + enum_write: LSIRDYCW name: LSERDYC - bit_offset: 18 bit_size: 1 description: HSI ready interrupt clear - enum_write: PLLSAIRDYCW + enum_write: LSIRDYCW name: HSIRDYC - bit_offset: 19 bit_size: 1 description: HSE ready interrupt clear - enum_write: PLLSAIRDYCW + enum_write: LSIRDYCW name: HSERDYC - bit_offset: 20 bit_size: 1 description: Main PLL(PLL) ready interrupt clear - enum_write: PLLSAIRDYCW + enum_write: LSIRDYCW name: PLLRDYC - bit_offset: 21 bit_size: 1 description: PLLI2S ready interrupt clear - enum_write: PLLSAIRDYCW + enum_write: LSIRDYCW name: PLLI2SRDYC - bit_offset: 22 bit_size: 1 description: PLLSAI Ready Interrupt Clear - enum_write: PLLSAIRDYCW + enum_write: LSIRDYCW name: PLLSAIRDYC - bit_offset: 23 bit_size: 1 @@ -2014,7 +2063,7 @@ fieldset/CR: - bit_offset: 1 bit_size: 1 description: Internal high-speed clock ready flag - enum_read: PLLISRDYR + enum_read: HSIRDYR name: HSIRDY - bit_offset: 3 bit_size: 5 @@ -2031,7 +2080,7 @@ fieldset/CR: - bit_offset: 17 bit_size: 1 description: HSE clock ready flag - enum_read: PLLISRDYR + enum_read: HSIRDYR name: HSERDY - bit_offset: 18 bit_size: 1 @@ -2049,7 +2098,7 @@ fieldset/CR: - bit_offset: 25 bit_size: 1 description: Main PLL (PLL) clock ready flag - enum_read: PLLISRDYR + enum_read: HSIRDYR name: PLLRDY - bit_offset: 26 bit_size: 1 @@ -2058,7 +2107,7 @@ fieldset/CR: - bit_offset: 27 bit_size: 1 description: PLLI2S clock ready flag - enum_read: PLLISRDYR + enum_read: HSIRDYR name: PLLI2SRDY - bit_offset: 28 bit_size: 1 @@ -2067,7 +2116,7 @@ fieldset/CR: - bit_offset: 29 bit_size: 1 description: PLLSAI clock ready flag - enum_read: PLLISRDYR + enum_read: HSIRDYR name: PLLSAIRDY fieldset/CSR: description: clock control & status register @@ -2089,37 +2138,37 @@ fieldset/CSR: - bit_offset: 25 bit_size: 1 description: BOR reset flag - enum_read: LPWRRSTFR + enum_read: BORRSTFR name: BORRSTF - bit_offset: 26 bit_size: 1 description: PIN reset flag - enum_read: LPWRRSTFR + enum_read: BORRSTFR name: PADRSTF - bit_offset: 27 bit_size: 1 description: POR/PDR reset flag - enum_read: LPWRRSTFR + enum_read: BORRSTFR name: PORRSTF - bit_offset: 28 bit_size: 1 description: Software reset flag - enum_read: LPWRRSTFR + enum_read: BORRSTFR name: SFTRSTF - bit_offset: 29 bit_size: 1 description: Independent watchdog reset flag - enum_read: LPWRRSTFR + enum_read: BORRSTFR name: WDGRSTF - bit_offset: 30 bit_size: 1 description: Window watchdog reset flag - enum_read: LPWRRSTFR + enum_read: BORRSTFR name: WWDGRSTF - bit_offset: 31 bit_size: 1 description: Low-power reset flag - enum_read: LPWRRSTFR + enum_read: BORRSTFR name: LPWRRSTF fieldset/DCKCFGR1: description: dedicated clocks configuration register diff --git a/data/registers/rtc_v2.yaml b/data/registers/rtc_v2.yaml new file mode 100644 index 0000000..708ef41 --- /dev/null +++ b/data/registers/rtc_v2.yaml @@ -0,0 +1,1173 @@ +--- +block/RTC: + description: Real-time clock + items: + - byte_offset: 0 + description: time register + fieldset: TR + name: TR + - byte_offset: 4 + description: date register + fieldset: DR + name: DR + - byte_offset: 8 + description: control register + fieldset: CR + name: CR + - byte_offset: 12 + description: initialization and status register + fieldset: ISR + name: ISR + - byte_offset: 16 + description: prescaler register + fieldset: PRER + name: PRER + - byte_offset: 20 + description: wakeup timer register + fieldset: WUTR + name: WUTR + - byte_offset: 28 + description: alarm A register + fieldset: ALRMAR + name: ALRMAR + - byte_offset: 32 + description: alarm B register + fieldset: ALRMBR + name: ALRMBR + - access: Write + byte_offset: 36 + description: write protection register + fieldset: WPR + name: WPR + - access: Read + byte_offset: 40 + description: sub second register + fieldset: SSR + name: SSR + - access: Write + byte_offset: 44 + description: shift control register + fieldset: SHIFTR + name: SHIFTR + - access: Read + byte_offset: 48 + description: time stamp time register + fieldset: TSTR + name: TSTR + - access: Read + byte_offset: 52 + description: time stamp date register + fieldset: TSDR + name: TSDR + - access: Read + byte_offset: 56 + description: timestamp sub second register + fieldset: TSSSR + name: TSSSR + - byte_offset: 60 + description: calibration register + fieldset: CALR + name: CALR + - byte_offset: 64 + description: tamper configuration register + fieldset: TAMPCR + name: TAMPCR + - byte_offset: 68 + description: alarm A sub second register + fieldset: ALRMASSR + name: ALRMASSR + - byte_offset: 72 + description: alarm B sub second register + fieldset: ALRMBSSR + name: ALRMBSSR + - byte_offset: 76 + description: option register + fieldset: OR + name: OR + - array: + len: 32 + stride: 4 + byte_offset: 80 + description: backup register + fieldset: BKPR + name: BKPR +enum/ADDHW: + bit_size: 1 + variants: + - description: Adds 1 hour to the current time. This can be used for summer time + change outside initialization mode + name: Add1 + value: 1 +enum/ADDSW: + bit_size: 1 + variants: + - description: Add one second to the clock/calendar + name: Add1 + value: 1 +enum/ALRAE: + bit_size: 1 + variants: + - description: Alarm A disabled + name: Disabled + value: 0 + - description: Alarm A enabled + name: Enabled + value: 1 +enum/ALRAFR: + bit_size: 1 + variants: + - description: This flag is set by hardware when the time/date registers (RTC_TR + and RTC_DR) match the Alarm A register (RTC_ALRMAR) + name: Match + value: 1 +enum/ALRAFW: + bit_size: 1 + variants: + - description: This flag is cleared by software by writing 0 + name: Clear + value: 0 +enum/ALRAIE: + bit_size: 1 + variants: + - description: Alarm A interrupt disabled + name: Disabled + value: 0 + - description: Alarm A interrupt enabled + name: Enabled + value: 1 +enum/ALRAWFR: + bit_size: 1 + variants: + - description: Alarm update not allowed + name: UpdateNotAllowed + value: 0 + - description: Alarm update allowed + name: UpdateAllowed + value: 1 +enum/ALRBE: + bit_size: 1 + variants: + - description: Alarm B disabled + name: Disabled + value: 0 + - description: Alarm B enabled + name: Enabled + value: 1 +enum/ALRBFR: + bit_size: 1 + variants: + - description: This flag is set by hardware when the time/date registers (RTC_TR + and RTC_DR) match the Alarm B register (RTC_ALRMBR) + name: Match + value: 1 +enum/ALRBFW: + bit_size: 1 + variants: + - description: This flag is cleared by software by writing 0 + name: Clear + value: 0 +enum/ALRBIE: + bit_size: 1 + variants: + - description: Alarm B Interrupt disabled + name: Disabled + value: 0 + - description: Alarm B Interrupt enabled + name: Enabled + value: 1 +enum/ALRMAR_MSK: + bit_size: 1 + variants: + - description: Alarm set if the date/day match + name: Mask + value: 0 + - description: "Date/day don\u2019t care in Alarm comparison" + name: NotMask + value: 1 +enum/ALRMAR_PM: + bit_size: 1 + variants: + - description: AM or 24-hour format + name: AM + value: 0 + - description: PM + name: PM + value: 1 +enum/ALRMAR_WDSEL: + bit_size: 1 + variants: + - description: DU[3:0] represents the date units + name: DateUnits + value: 0 + - description: "DU[3:0] represents the week day. DT[1:0] is don\u2019t care." + name: WeekDay + value: 1 +enum/ALRMBR_MSK: + bit_size: 1 + variants: + - description: Alarm set if the date/day match + name: Mask + value: 0 + - description: "Date/day don\u2019t care in Alarm comparison" + name: NotMask + value: 1 +enum/ALRMBR_PM: + bit_size: 1 + variants: + - description: AM or 24-hour format + name: AM + value: 0 + - description: PM + name: PM + value: 1 +enum/ALRMBR_WDSEL: + bit_size: 1 + variants: + - description: DU[3:0] represents the date units + name: DateUnits + value: 0 + - description: "DU[3:0] represents the week day. DT[1:0] is don\u2019t care." + name: WeekDay + value: 1 +enum/BKP: + bit_size: 1 + variants: + - description: Daylight Saving Time change has not been performed + name: DST_Not_Changed + value: 0 + - description: Daylight Saving Time change has been performed + name: DST_Changed + value: 1 +enum/BYPSHAD: + bit_size: 1 + variants: + - description: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are + taken from the shadow registers, which are updated once every two RTCCLK cycles + name: ShadowReg + value: 0 + - description: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are + taken directly from the calendar counters + name: BypassShadowReg + value: 1 +enum/CALP: + bit_size: 1 + variants: + - description: No RTCCLK pulses are added + name: NoChange + value: 0 + - description: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency + increased by 488.5 ppm) + name: IncreaseFreq + value: 1 +enum/CALW16: + bit_size: 1 + variants: + - description: "When CALW16 is set to \u20181\u2019, the 16-second calibration cycle\ + \ period is selected.This bit must not be set to \u20181\u2019 if CALW8=1" + name: Sixteen_Second + value: 1 +enum/CALW8: + bit_size: 1 + variants: + - description: "When CALW8 is set to \u20181\u2019, the 8-second calibration cycle\ + \ period is selected" + name: Eight_Second + value: 1 +enum/COE: + bit_size: 1 + variants: + - description: Calibration output disabled + name: Disabled + value: 0 + - description: Calibration output enabled + name: Enabled + value: 1 +enum/COSEL: + bit_size: 1 + variants: + - description: Calibration output is 512 Hz (with default prescaler setting) + name: CalFreq_512Hz + value: 0 + - description: Calibration output is 1 Hz (with default prescaler setting) + name: CalFreq_1Hz + value: 1 +enum/FMT: + bit_size: 1 + variants: + - description: 24 hour/day format + name: Twenty_Four_Hour + value: 0 + - description: AM/PM hour format + name: AM_PM + value: 1 +enum/INIT: + bit_size: 1 + variants: + - description: Free running mode + name: FreeRunningMode + value: 0 + - description: Initialization mode used to program time and date register (RTC_TR + and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start + counting from the new value when INIT is reset. + name: InitMode + value: 1 +enum/INITFR: + bit_size: 1 + variants: + - description: Calendar registers update is not allowed + name: NotAllowed + value: 0 + - description: Calendar registers update is allowed + name: Allowed + value: 1 +enum/INITSR: + bit_size: 1 + variants: + - description: Calendar has not been initialized + name: NotInitalized + value: 0 + - description: Calendar has been initialized + name: Initalized + value: 1 +enum/OSEL: + bit_size: 2 + variants: + - description: Output disabled + name: Disabled + value: 0 + - description: Alarm A output enabled + name: AlarmA + value: 1 + - description: Alarm B output enabled + name: AlarmB + value: 2 + - description: Wakeup output enabled + name: Wakeup + value: 3 +enum/POL: + bit_size: 1 + variants: + - description: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + name: High + value: 0 + - description: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]) + name: Low + value: 1 +enum/RECALPFR: + bit_size: 1 + variants: + - description: The RECALPF status flag is automatically set to 1 when software writes + to the RTC_CALR register, indicating that the RTC_CALR register is blocked. + When the new calibration settings are taken into account, this bit returns to + 0 + name: Pending + value: 1 +enum/REFCKON: + bit_size: 1 + variants: + - description: RTC_REFIN detection disabled + name: Disabled + value: 0 + - description: RTC_REFIN detection enabled + name: Enabled + value: 1 +enum/RSFR: + bit_size: 1 + variants: + - description: Calendar shadow registers not yet synchronized + name: NotSynced + value: 0 + - description: Calendar shadow registers synchronized + name: Synced + value: 1 +enum/RSFW: + bit_size: 1 + variants: + - description: This flag is cleared by software by writing 0 + name: Clear + value: 0 +enum/SHPFR: + bit_size: 1 + variants: + - description: No shift operation is pending + name: NoShiftPending + value: 0 + - description: A shift operation is pending + name: ShiftPending + value: 1 +enum/SUBHW: + bit_size: 1 + variants: + - description: Subtracts 1 hour to the current time. This can be used for winter + time change outside initialization mode + name: Sub1 + value: 1 +enum/TAMPFR: + bit_size: 1 + variants: + - description: This flag is set by hardware when a tamper detection event is detected + on the RTC_TAMPx input + name: Tampered + value: 1 +enum/TAMPFW: + bit_size: 1 + variants: + - description: Flag cleared by software writing 0 + name: Clear + value: 0 +enum/TR_PM: + bit_size: 1 + variants: + - description: AM or 24-hour format + name: AM + value: 0 + - description: PM + name: PM + value: 1 +enum/TSE: + bit_size: 1 + variants: + - description: Timestamp disabled + name: Disabled + value: 0 + - description: Timestamp enabled + name: Enabled + value: 1 +enum/TSEDGE: + bit_size: 1 + variants: + - description: RTC_TS input rising edge generates a time-stamp event + name: RisingEdge + value: 0 + - description: RTC_TS input falling edge generates a time-stamp event + name: FallingEdge + value: 1 +enum/TSFR: + bit_size: 1 + variants: + - description: This flag is set by hardware when a time-stamp event occurs + name: TimestampEvent + value: 1 +enum/TSFW: + bit_size: 1 + variants: + - description: This flag is cleared by software by writing 0 + name: Clear + value: 0 +enum/TSIE: + bit_size: 1 + variants: + - description: Time-stamp Interrupt disabled + name: Disabled + value: 0 + - description: Time-stamp Interrupt enabled + name: Enabled + value: 1 +enum/TSOVFR: + bit_size: 1 + variants: + - description: This flag is set by hardware when a time-stamp event occurs while + TSF is already set + name: Overflow + value: 1 +enum/TSOVFW: + bit_size: 1 + variants: + - description: This flag is cleared by software by writing 0 + name: Clear + value: 0 +enum/WUCKSEL: + bit_size: 3 + variants: + - description: RTC/16 clock is selected + name: Div16 + value: 0 + - description: RTC/8 clock is selected + name: Div8 + value: 1 + - description: RTC/4 clock is selected + name: Div4 + value: 2 + - description: RTC/2 clock is selected + name: Div2 + value: 3 + - description: ck_spre (usually 1 Hz) clock is selected + name: ClockSpare + value: 4 + - description: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the + WUT counter value + name: ClockSpareWithOffset + value: 6 +enum/WUTE: + bit_size: 1 + variants: + - description: Wakeup timer disabled + name: Disabled + value: 0 + - description: Wakeup timer enabled + name: Enabled + value: 1 +enum/WUTFR: + bit_size: 1 + variants: + - description: This flag is set by hardware when the wakeup auto-reload counter + reaches 0 + name: Zero + value: 1 +enum/WUTFW: + bit_size: 1 + variants: + - description: This flag is cleared by software by writing 0 + name: Clear + value: 0 +enum/WUTIE: + bit_size: 1 + variants: + - description: Wakeup timer interrupt disabled + name: Disabled + value: 0 + - description: Wakeup timer interrupt enabled + name: Enabled + value: 1 +enum/WUTWFR: + bit_size: 1 + variants: + - description: Wakeup timer configuration update not allowed + name: UpdateNotAllowed + value: 0 + - description: Wakeup timer configuration update allowed + name: UpdateAllowed + value: 1 +fieldset/ALRMAR: + description: alarm A register + fields: + - bit_offset: 0 + bit_size: 4 + description: Second units in BCD format + name: SU + - bit_offset: 4 + bit_size: 3 + description: Second tens in BCD format + name: ST + - array: + len: 4 + stride: 8 + bit_offset: 7 + bit_size: 1 + description: Alarm A seconds mask + enum: ALRMAR_MSK + name: MSK + - bit_offset: 8 + bit_size: 4 + description: Minute units in BCD format + name: MNU + - bit_offset: 12 + bit_size: 3 + description: Minute tens in BCD format + name: MNT + - bit_offset: 16 + bit_size: 4 + description: Hour units in BCD format + name: HU + - bit_offset: 20 + bit_size: 2 + description: Hour tens in BCD format + name: HT + - bit_offset: 22 + bit_size: 1 + description: AM/PM notation + enum: ALRMAR_PM + name: PM + - bit_offset: 24 + bit_size: 4 + description: Date units or day in BCD format + name: DU + - bit_offset: 28 + bit_size: 2 + description: Date tens in BCD format + name: DT + - bit_offset: 30 + bit_size: 1 + description: Week day selection + enum: ALRMAR_WDSEL + name: WDSEL +fieldset/ALRMASSR: + description: alarm A sub second register + fields: + - bit_offset: 0 + bit_size: 15 + description: Sub seconds value + name: SS + - bit_offset: 24 + bit_size: 4 + description: Mask the most-significant bits starting at this bit + name: MASKSS +fieldset/ALRMBR: + description: alarm B register + fields: + - bit_offset: 0 + bit_size: 4 + description: Second units in BCD format + name: SU + - bit_offset: 4 + bit_size: 3 + description: Second tens in BCD format + name: ST + - array: + len: 4 + stride: 8 + bit_offset: 7 + bit_size: 1 + description: Alarm B seconds mask + enum: ALRMBR_MSK + name: MSK + - bit_offset: 8 + bit_size: 4 + description: Minute units in BCD format + name: MNU + - bit_offset: 12 + bit_size: 3 + description: Minute tens in BCD format + name: MNT + - bit_offset: 16 + bit_size: 4 + description: Hour units in BCD format + name: HU + - bit_offset: 20 + bit_size: 2 + description: Hour tens in BCD format + name: HT + - bit_offset: 22 + bit_size: 1 + description: AM/PM notation + enum: ALRMBR_PM + name: PM + - bit_offset: 24 + bit_size: 4 + description: Date units or day in BCD format + name: DU + - bit_offset: 28 + bit_size: 2 + description: Date tens in BCD format + name: DT + - bit_offset: 30 + bit_size: 1 + description: Week day selection + enum: ALRMBR_WDSEL + name: WDSEL +fieldset/ALRMBSSR: + description: alarm B sub second register + fields: + - bit_offset: 0 + bit_size: 15 + description: Sub seconds value + name: SS + - bit_offset: 24 + bit_size: 4 + description: Mask the most-significant bits starting at this bit + name: MASKSS +fieldset/BKPR: + description: backup register + fields: + - bit_offset: 0 + bit_size: 32 + description: BKP + name: BKP +fieldset/CALR: + description: calibration register + fields: + - bit_offset: 0 + bit_size: 9 + description: Calibration minus + name: CALM + - array: + len: 2 + stride: 1 + bit_offset: 13 + bit_size: 1 + description: Use a 16-second calibration cycle period + enum: CALW16 + name: CALW + - bit_offset: 15 + bit_size: 1 + description: Increase frequency of RTC by 488.5 ppm + enum: CALP + name: CALP +fieldset/CR: + description: control register + fields: + - bit_offset: 0 + bit_size: 3 + description: Wakeup clock selection + enum: WUCKSEL + name: WUCKSEL + - bit_offset: 3 + bit_size: 1 + description: Time-stamp event active edge + enum: TSEDGE + name: TSEDGE + - bit_offset: 4 + bit_size: 1 + description: Reference clock detection enable (50 or 60 Hz) + enum: REFCKON + name: REFCKON + - bit_offset: 5 + bit_size: 1 + description: Bypass the shadow registers + enum: BYPSHAD + name: BYPSHAD + - bit_offset: 6 + bit_size: 1 + description: Hour format + enum: FMT + name: FMT + - bit_offset: 8 + bit_size: 1 + description: Alarm A enable + enum: ALRAE + name: ALRAE + - bit_offset: 9 + bit_size: 1 + description: Alarm B enable + enum: ALRBE + name: ALRBE + - bit_offset: 10 + bit_size: 1 + description: Wakeup timer enable + enum: WUTE + name: WUTE + - bit_offset: 11 + bit_size: 1 + description: Time stamp enable + enum: TSE + name: TSE + - bit_offset: 12 + bit_size: 1 + description: Alarm A interrupt enable + enum: ALRAIE + name: ALRAIE + - bit_offset: 13 + bit_size: 1 + description: Alarm B interrupt enable + enum: ALRBIE + name: ALRBIE + - bit_offset: 14 + bit_size: 1 + description: Wakeup timer interrupt enable + enum: WUTIE + name: WUTIE + - bit_offset: 15 + bit_size: 1 + description: Time-stamp interrupt enable + enum: TSIE + name: TSIE + - bit_offset: 16 + bit_size: 1 + description: Add 1 hour (summer time change) + enum_write: ADDHW + name: ADD1H + - bit_offset: 17 + bit_size: 1 + description: Subtract 1 hour (winter time change) + enum_write: SUBHW + name: SUB1H + - bit_offset: 18 + bit_size: 1 + description: Backup + enum: BKP + name: BKP + - bit_offset: 19 + bit_size: 1 + description: Calibration output selection + enum: COSEL + name: COSEL + - bit_offset: 20 + bit_size: 1 + description: Output polarity + enum: POL + name: POL + - bit_offset: 21 + bit_size: 2 + description: Output selection + enum: OSEL + name: OSEL + - bit_offset: 23 + bit_size: 1 + description: Calibration output enable + enum: COE + name: COE + - bit_offset: 24 + bit_size: 1 + description: timestamp on internal event enable + name: ITSE +fieldset/DR: + description: date register + fields: + - bit_offset: 0 + bit_size: 4 + description: Date units in BCD format + name: DU + - bit_offset: 4 + bit_size: 2 + description: Date tens in BCD format + name: DT + - bit_offset: 8 + bit_size: 4 + description: Month units in BCD format + name: MU + - bit_offset: 12 + bit_size: 1 + description: Month tens in BCD format + name: MT + - bit_offset: 13 + bit_size: 3 + description: Week day units + name: WDU + - bit_offset: 16 + bit_size: 4 + description: Year units in BCD format + name: YU + - bit_offset: 20 + bit_size: 4 + description: Year tens in BCD format + name: YT +fieldset/ISR: + description: initialization and status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Alarm A write flag + enum_read: ALRAWFR + name: ALRAWF + - bit_offset: 1 + bit_size: 1 + description: Alarm B write flag + enum_read: ALRAWFR + name: ALRBWF + - bit_offset: 2 + bit_size: 1 + description: Wakeup timer write flag + enum_read: WUTWFR + name: WUTWF + - bit_offset: 3 + bit_size: 1 + description: Shift operation pending + enum_read: SHPFR + name: SHPF + - bit_offset: 4 + bit_size: 1 + description: Initialization status flag + enum_read: INITSR + name: INITS + - bit_offset: 5 + bit_size: 1 + description: Registers synchronization flag + enum_read: RSFR + enum_write: RSFW + name: RSF + - bit_offset: 6 + bit_size: 1 + description: Initialization flag + enum_read: INITFR + name: INITF + - bit_offset: 7 + bit_size: 1 + description: Initialization mode + enum: INIT + name: INIT + - bit_offset: 8 + bit_size: 1 + description: Alarm A flag + enum_read: ALRAFR + enum_write: ALRAFW + name: ALRAF + - bit_offset: 9 + bit_size: 1 + description: Alarm B flag + enum_read: ALRBFR + enum_write: ALRBFW + name: ALRBF + - bit_offset: 10 + bit_size: 1 + description: Wakeup timer flag + enum_read: WUTFR + enum_write: WUTFW + name: WUTF + - bit_offset: 11 + bit_size: 1 + description: Time-stamp flag + enum_read: TSFR + enum_write: TSFW + name: TSF + - bit_offset: 12 + bit_size: 1 + description: Time-stamp overflow flag + enum_read: TSOVFR + enum_write: TSOVFW + name: TSOVF + - bit_offset: 13 + bit_size: 1 + description: Tamper detection flag + enum_read: TAMPFR + enum_write: TAMPFW + name: TAMP1F + - bit_offset: 14 + bit_size: 1 + description: RTC_TAMP2 detection flag + enum_read: TAMPFR + enum_write: TAMPFW + name: TAMP2F + - bit_offset: 15 + bit_size: 1 + description: RTC_TAMP3 detection flag + enum_read: TAMPFR + enum_write: TAMPFW + name: TAMP3F + - bit_offset: 16 + bit_size: 1 + description: Recalibration pending Flag + enum_read: RECALPFR + name: RECALPF + - bit_offset: 17 + bit_size: 1 + description: Internal tTime-stamp flag + name: ITSF +fieldset/OR: + description: option register + fields: + - bit_offset: 1 + bit_size: 1 + description: TIMESTAMP mapping + name: TSINSEL + - bit_offset: 1 + bit_size: 1 + description: RTC_OUT remap + name: RTC_OUT_RMP + - bit_offset: 3 + bit_size: 1 + description: RTC_ALARM on PC13 output type + name: RTC_ALARM_TYPE +fieldset/PRER: + description: prescaler register + fields: + - bit_offset: 0 + bit_size: 15 + description: Synchronous prescaler factor + name: PREDIV_S + - bit_offset: 16 + bit_size: 7 + description: Asynchronous prescaler factor + name: PREDIV_A +fieldset/SHIFTR: + description: shift control register + fields: + - bit_offset: 0 + bit_size: 15 + description: Subtract a fraction of a second + name: SUBFS + - bit_offset: 31 + bit_size: 1 + description: Add one second + enum_write: ADDSW + name: ADD1S +fieldset/SSR: + description: sub second register + fields: + - bit_offset: 0 + bit_size: 16 + description: Sub second value + name: SS +fieldset/TAMPCR: + description: tamper configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Tamper 1 detection enable + name: TAMP1E + - bit_offset: 1 + bit_size: 1 + description: Active level for tamper 1 + name: TAMP1TRG + - bit_offset: 2 + bit_size: 1 + description: Tamper interrupt enable + name: TAMPIE + - bit_offset: 3 + bit_size: 1 + description: Tamper 2 detection enable + name: TAMP2E + - bit_offset: 4 + bit_size: 1 + description: Active level for tamper 2 + name: TAMP2TRG + - bit_offset: 5 + bit_size: 1 + description: Tamper 3 detection enable + name: TAMP3E + - bit_offset: 6 + bit_size: 1 + description: Active level for tamper 3 + name: TAMP3TRG + - bit_offset: 7 + bit_size: 1 + description: Activate timestamp on tamper detection event + name: TAMPTS + - bit_offset: 8 + bit_size: 3 + description: Tamper sampling frequency + name: TAMPFREQ + - bit_offset: 11 + bit_size: 2 + description: Tamper filter count + name: TAMPFLT + - bit_offset: 13 + bit_size: 2 + description: Tamper precharge duration + name: TAMPPRCH + - bit_offset: 15 + bit_size: 1 + description: TAMPER pull-up disable + name: TAMPPUDIS + - bit_offset: 16 + bit_size: 1 + description: Tamper 1 interrupt enable + name: TAMP1IE + - bit_offset: 17 + bit_size: 1 + description: Tamper 1 no erase + name: TAMP1NOERASE + - bit_offset: 18 + bit_size: 1 + description: Tamper 1 mask flag + name: TAMP1MF + - bit_offset: 19 + bit_size: 1 + description: Tamper 2 interrupt enable + name: TAMP2IE + - bit_offset: 20 + bit_size: 1 + description: Tamper 2 no erase + name: TAMP2NOERASE + - bit_offset: 21 + bit_size: 1 + description: Tamper 2 mask flag + name: TAMP2MF + - bit_offset: 22 + bit_size: 1 + description: Tamper 3 interrupt enable + name: TAMP3IE + - bit_offset: 23 + bit_size: 1 + description: Tamper 3 no erase + name: TAMP3NOERASE + - bit_offset: 24 + bit_size: 1 + description: Tamper 3 mask flag + name: TAMP3MF +fieldset/TR: + description: time register + fields: + - bit_offset: 0 + bit_size: 4 + description: Second units in BCD format + name: SU + - bit_offset: 4 + bit_size: 3 + description: Second tens in BCD format + name: ST + - bit_offset: 8 + bit_size: 4 + description: Minute units in BCD format + name: MNU + - bit_offset: 12 + bit_size: 3 + description: Minute tens in BCD format + name: MNT + - bit_offset: 16 + bit_size: 4 + description: Hour units in BCD format + name: HU + - bit_offset: 20 + bit_size: 2 + description: Hour tens in BCD format + name: HT + - bit_offset: 22 + bit_size: 1 + description: AM/PM notation + enum: TR_PM + name: PM +fieldset/TSDR: + description: time stamp date register + fields: + - bit_offset: 0 + bit_size: 4 + description: Date units in BCD format + name: DU + - bit_offset: 4 + bit_size: 2 + description: Date tens in BCD format + name: DT + - bit_offset: 8 + bit_size: 4 + description: Month units in BCD format + name: MU + - bit_offset: 12 + bit_size: 1 + description: Month tens in BCD format + name: MT + - bit_offset: 13 + bit_size: 3 + description: Week day units + name: WDU +fieldset/TSSSR: + description: timestamp sub second register + fields: + - bit_offset: 0 + bit_size: 16 + description: Sub second value + name: SS +fieldset/TSTR: + description: time stamp time register + fields: + - bit_offset: 0 + bit_size: 4 + description: Second units in BCD format + name: SU + - bit_offset: 4 + bit_size: 3 + description: Second tens in BCD format + name: ST + - bit_offset: 8 + bit_size: 4 + description: Minute units in BCD format + name: MNU + - bit_offset: 12 + bit_size: 3 + description: Minute tens in BCD format + name: MNT + - bit_offset: 16 + bit_size: 4 + description: Hour units in BCD format + name: HU + - bit_offset: 20 + bit_size: 2 + description: Hour tens in BCD format + name: HT + - bit_offset: 22 + bit_size: 1 + description: AM/PM notation + name: PM +fieldset/WPR: + description: write protection register + fields: + - bit_offset: 0 + bit_size: 8 + description: Write protection key + name: KEY +fieldset/WUTR: + description: wakeup timer register + fields: + - bit_offset: 0 + bit_size: 16 + description: Wakeup auto-reload value bits + name: WUT diff --git a/data/registers/sai_v1.yaml b/data/registers/sai_v1.yaml new file mode 100644 index 0000000..fda1c7f --- /dev/null +++ b/data/registers/sai_v1.yaml @@ -0,0 +1,755 @@ +--- +block/CH: + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, + ?DR + items: + - byte_offset: 0 + description: AConfiguration register 1 + fieldset: CR1 + name: CR1 + - byte_offset: 4 + description: AConfiguration register 2 + fieldset: CR2 + name: CR2 + - byte_offset: 8 + description: AFRCR + fieldset: FRCR + name: FRCR + - byte_offset: 12 + description: ASlot register + fieldset: SLOTR + name: SLOTR + - byte_offset: 16 + description: AInterrupt mask register2 + fieldset: IM + name: IM + - access: Read + byte_offset: 20 + description: AStatus register + fieldset: SR + name: SR + - access: Write + byte_offset: 24 + description: AClear flag register + fieldset: CLRFR + name: CLRFR + - byte_offset: 28 + description: AData register + fieldset: DR + name: DR +block/SAI: + description: Serial audio interface + items: + - byte_offset: 0 + description: Global configuration register + fieldset: GCR + name: GCR + - array: + len: 2 + stride: 32 + block: CH + byte_offset: 4 + description: Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, + ?DR + name: CH +enum/AFSDETIE: + bit_size: 1 + variants: + - description: Interrupt is disabled + name: Disabled + value: 0 + - description: Interrupt is enabled + name: Enabled + value: 1 +enum/AFSDETR: + bit_size: 1 + variants: + - description: No error + name: NoError + value: 0 + - description: Frame synchronization signal is detected earlier than expected + name: EarlySync + value: 1 +enum/CAFSDETW: + bit_size: 1 + variants: + - description: Clears the AFSDET flag + name: Clear + value: 1 +enum/CCNRDYW: + bit_size: 1 + variants: + - description: Clears the CNRDY flag + name: Clear + value: 1 +enum/CKSTR: + bit_size: 1 + variants: + - description: Data strobing edge is falling edge of SCK + name: FallingEdge + value: 0 + - description: Data strobing edge is rising edge of SCK + name: RisingEdge + value: 1 +enum/CLFSDETW: + bit_size: 1 + variants: + - description: Clears the LFSDET flag + name: Clear + value: 1 +enum/CMUTEDETW: + bit_size: 1 + variants: + - description: Clears the MUTEDET flag + name: Clear + value: 1 +enum/CNRDYIE: + bit_size: 1 + variants: + - description: Interrupt is disabled + name: Disabled + value: 0 + - description: Interrupt is enabled + name: Enabled + value: 1 +enum/CNRDYR: + bit_size: 1 + variants: + - description: "External AC\u201997 Codec is ready" + name: Ready + value: 0 + - description: "External AC\u201997 Codec is not ready" + name: NotReady + value: 1 +enum/COMP: + bit_size: 2 + variants: + - description: No companding algorithm + name: NoCompanding + value: 0 + - description: "\u03BC-Law algorithm" + name: MuLaw + value: 2 + - description: A-Law algorithm + name: ALaw + value: 3 +enum/COVRUDRW: + bit_size: 1 + variants: + - description: Clears the OVRUDR flag + name: Clear + value: 1 +enum/CPL: + bit_size: 1 + variants: + - description: "1\u2019s complement representation" + name: OnesComplement + value: 0 + - description: "2\u2019s complement representation" + name: TwosComplement + value: 1 +enum/CWCKCFGW: + bit_size: 1 + variants: + - description: Clears the WCKCFG flag + name: Clear + value: 1 +enum/DMAEN: + bit_size: 1 + variants: + - description: DMA disabled + name: Disabled + value: 0 + - description: DMA enabled + name: Enabled + value: 1 +enum/DS: + bit_size: 3 + variants: + - description: 8 bits + name: Bit8 + value: 2 + - description: 10 bits + name: Bit10 + value: 3 + - description: 16 bits + name: Bit16 + value: 4 + - description: 20 bits + name: Bit20 + value: 5 + - description: 24 bits + name: Bit24 + value: 6 + - description: 32 bits + name: Bit32 + value: 7 +enum/FFLUSH: + bit_size: 1 + variants: + - description: No FIFO flush + name: NoFlush + value: 0 + - description: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All + the internal FIFO pointers (read and write) are cleared + name: Flush + value: 1 +enum/FLVLR: + bit_size: 3 + variants: + - description: FIFO empty + name: Empty + value: 0 + - description: "FIFO <= 1\u20444 but not empty" + name: Quarter1 + value: 1 + - description: "1\u20444 < FIFO <= 1\u20442" + name: Quarter2 + value: 2 + - description: "1\u20442 < FIFO <= 3\u20444" + name: Quarter3 + value: 3 + - description: "3\u20444 < FIFO but not full" + name: Quarter4 + value: 4 + - description: FIFO full + name: Full + value: 5 +enum/FREQIE: + bit_size: 1 + variants: + - description: Interrupt is disabled + name: Disabled + value: 0 + - description: Interrupt is enabled + name: Enabled + value: 1 +enum/FREQR: + bit_size: 1 + variants: + - description: No FIFO request + name: NoRequest + value: 0 + - description: FIFO request to read or to write the SAI_xDR + name: Request + value: 1 +enum/FSOFF: + bit_size: 1 + variants: + - description: FS is asserted on the first bit of the slot 0 + name: OnFirst + value: 0 + - description: FS is asserted one bit before the first bit of the slot 0 + name: BeforeFirst + value: 1 +enum/FSPOL: + bit_size: 1 + variants: + - description: FS is active low (falling edge) + name: FallingEdge + value: 0 + - description: FS is active high (rising edge) + name: RisingEdge + value: 1 +enum/FTH: + bit_size: 3 + variants: + - description: FIFO empty + name: Empty + value: 0 + - description: "1\u20444 FIFO" + name: Quarter1 + value: 1 + - description: "1\u20442 FIFO" + name: Quarter2 + value: 2 + - description: "3\u20444 FIFO" + name: Quarter3 + value: 3 + - description: FIFO full + name: Full + value: 4 +enum/LFSDETIE: + bit_size: 1 + variants: + - description: Interrupt is disabled + name: Disabled + value: 0 + - description: Interrupt is enabled + name: Enabled + value: 1 +enum/LFSDETR: + bit_size: 1 + variants: + - description: No error + name: NoError + value: 0 + - description: Frame synchronization signal is not present at the right time + name: NoSync + value: 1 +enum/LSBFIRST: + bit_size: 1 + variants: + - description: Data are transferred with MSB first + name: MsbFirst + value: 0 + - description: Data are transferred with LSB first + name: LsbFirst + value: 1 +enum/MODE: + bit_size: 2 + variants: + - description: Master transmitter + name: MasterTx + value: 0 + - description: Master receiver + name: MasterRx + value: 1 + - description: Slave transmitter + name: SlaveTx + value: 2 + - description: Slave receiver + name: SlaveRx + value: 3 +enum/MONO: + bit_size: 1 + variants: + - description: Stereo mode + name: Stereo + value: 0 + - description: Mono mode + name: Mono + value: 1 +enum/MUTE: + bit_size: 1 + variants: + - description: No mute mode + name: Disabled + value: 0 + - description: Mute mode enabled + name: Enabled + value: 1 +enum/MUTEDETIE: + bit_size: 1 + variants: + - description: Interrupt is disabled + name: Disabled + value: 0 + - description: Interrupt is enabled + name: Enabled + value: 1 +enum/MUTEDETR: + bit_size: 1 + variants: + - description: No MUTE detection on the SD input line + name: NoMute + value: 0 + - description: MUTE value detected on the SD input line (0 value) for a specified + number of consecutive audio frame + name: Mute + value: 1 +enum/MUTEVAL: + bit_size: 1 + variants: + - description: Bit value 0 is sent during the mute mode + name: SendZero + value: 0 + - description: Last values are sent during the mute mode + name: SendLast + value: 1 +enum/NODIV: + bit_size: 1 + variants: + - description: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 + or 512 according to the OSR value + name: MasterClock + value: 0 + - description: MCLK output enable set by the MCKEN bit (where present, else 0). + Ratio between FS and MCLK depends on FRL. + name: NoDiv + value: 1 +enum/OUTDRIV: + bit_size: 1 + variants: + - description: Audio block output driven when SAIEN is set + name: OnStart + value: 0 + - description: Audio block output driven immediately after the setting of this bit + name: Immediately + value: 1 +enum/OVRUDRIE: + bit_size: 1 + variants: + - description: Interrupt is disabled + name: Disabled + value: 0 + - description: Interrupt is enabled + name: Enabled + value: 1 +enum/OVRUDRR: + bit_size: 1 + variants: + - description: No overrun/underrun error + name: NoError + value: 0 + - description: Overrun/underrun error detection + name: Overrun + value: 1 +enum/PRTCFG: + bit_size: 2 + variants: + - description: Free protocol. Free protocol allows to use the powerful configuration + of the audio block to address a specific audio protocol + name: Free + value: 0 + - description: SPDIF protocol + name: Spdif + value: 1 + - description: "AC\u201997 protocol" + name: Ac97 + value: 2 +enum/SAIEN: + bit_size: 1 + variants: + - description: SAI audio block disabled + name: Disabled + value: 0 + - description: SAI audio block enabled + name: Enabled + value: 1 +enum/SLOTEN: + bit_size: 16 + variants: + - description: Inactive slot + name: Inactive + value: 0 + - description: Active slot + name: Active + value: 1 +enum/SLOTSZ: + bit_size: 2 + variants: + - description: The slot size is equivalent to the data size (specified in DS[3:0] + in the SAI_xCR1 register) + name: DataSize + value: 0 + - description: 16-bit + name: Bit16 + value: 1 + - description: 32-bit + name: Bit32 + value: 2 +enum/SYNCEN: + bit_size: 2 + variants: + - description: audio sub-block in asynchronous mode + name: Asynchronous + value: 0 + - description: audio sub-block is synchronous with the other internal audio sub-block. + In this case, the audio sub-block must be configured in slave mode + name: Internal + value: 1 + - description: audio sub-block is synchronous with an external SAI embedded peripheral. + In this case the audio sub-block should be configured in Slave mode + name: External + value: 2 +enum/WCKCFGIE: + bit_size: 1 + variants: + - description: Interrupt is disabled + name: Disabled + value: 0 + - description: Interrupt is enabled + name: Enabled + value: 1 +enum/WCKCFGR: + bit_size: 1 + variants: + - description: Clock configuration is correct + name: Correct + value: 0 + - description: Clock configuration does not respect the rule concerning the frame + length specification + name: Wrong + value: 1 +fieldset/CLRFR: + description: AClear flag register + fields: + - bit_offset: 0 + bit_size: 1 + description: Clear overrun / underrun + enum_write: COVRUDRW + name: COVRUDR + - bit_offset: 1 + bit_size: 1 + description: Mute detection flag + enum_write: CMUTEDETW + name: CMUTEDET + - bit_offset: 2 + bit_size: 1 + description: Clear wrong clock configuration flag + enum_write: CWCKCFGW + name: CWCKCFG + - bit_offset: 4 + bit_size: 1 + description: Clear codec not ready flag + enum_write: CCNRDYW + name: CCNRDY + - bit_offset: 5 + bit_size: 1 + description: Clear anticipated frame synchronization detection flag. + enum_write: CAFSDETW + name: CAFSDET + - bit_offset: 6 + bit_size: 1 + description: Clear late frame synchronization detection flag + enum_write: CLFSDETW + name: CLFSDET +fieldset/CR1: + description: AConfiguration register 1 + fields: + - bit_offset: 0 + bit_size: 2 + description: Audio block mode + enum: MODE + name: MODE + - bit_offset: 2 + bit_size: 2 + description: Protocol configuration + enum: PRTCFG + name: PRTCFG + - bit_offset: 5 + bit_size: 3 + description: Data size + enum: DS + name: DS + - bit_offset: 8 + bit_size: 1 + description: Least significant bit first + enum: LSBFIRST + name: LSBFIRST + - bit_offset: 9 + bit_size: 1 + description: Clock strobing edge + enum: CKSTR + name: CKSTR + - bit_offset: 10 + bit_size: 2 + description: Synchronization enable + enum: SYNCEN + name: SYNCEN + - bit_offset: 12 + bit_size: 1 + description: Mono mode + enum: MONO + name: MONO + - bit_offset: 13 + bit_size: 1 + description: Output drive + enum: OUTDRIV + name: OUTDRIV + - bit_offset: 16 + bit_size: 1 + description: Audio block A enable + enum: SAIEN + name: SAIEN + - bit_offset: 17 + bit_size: 1 + description: DMA enable + enum: DMAEN + name: DMAEN + - bit_offset: 19 + bit_size: 1 + description: No divider + enum: NODIV + name: NODIV + - bit_offset: 20 + bit_size: 4 + description: Master clock divider + name: MCKDIV +fieldset/CR2: + description: AConfiguration register 2 + fields: + - bit_offset: 0 + bit_size: 3 + description: FIFO threshold + enum: FTH + name: FTH + - bit_offset: 3 + bit_size: 1 + description: FIFO flush + enum: FFLUSH + name: FFLUSH + - bit_offset: 4 + bit_size: 1 + description: Tristate management on data line + name: TRIS + - bit_offset: 5 + bit_size: 1 + description: Mute + enum: MUTE + name: MUTE + - bit_offset: 6 + bit_size: 1 + description: Mute value + enum: MUTEVAL + name: MUTEVAL + - bit_offset: 7 + bit_size: 6 + description: Mute counter + name: MUTECN + - bit_offset: 13 + bit_size: 1 + description: Complement bit + enum: CPL + name: CPL + - bit_offset: 14 + bit_size: 2 + description: Companding mode + enum: COMP + name: COMP +fieldset/DR: + description: AData register + fields: + - bit_offset: 0 + bit_size: 32 + description: Data + name: DATA +fieldset/FRCR: + description: AFRCR + fields: + - bit_offset: 0 + bit_size: 8 + description: Frame length + name: FRL + - bit_offset: 8 + bit_size: 7 + description: Frame synchronization active level length + name: FSALL + - bit_offset: 16 + bit_size: 1 + description: Frame synchronization definition + name: FSDEF + - bit_offset: 17 + bit_size: 1 + description: Frame synchronization polarity + enum: FSPOL + name: FSPOL + - bit_offset: 18 + bit_size: 1 + description: Frame synchronization offset + enum: FSOFF + name: FSOFF +fieldset/GCR: + description: Global configuration register + fields: + - bit_offset: 0 + bit_size: 2 + description: Synchronization inputs + name: SYNCIN + - bit_offset: 4 + bit_size: 2 + description: Synchronization outputs + name: SYNCOUT +fieldset/IM: + description: AInterrupt mask register2 + fields: + - bit_offset: 0 + bit_size: 1 + description: Overrun/underrun interrupt enable + enum: OVRUDRIE + name: OVRUDRIE + - bit_offset: 1 + bit_size: 1 + description: Mute detection interrupt enable + enum: MUTEDETIE + name: MUTEDETIE + - bit_offset: 2 + bit_size: 1 + description: Wrong clock configuration interrupt enable + enum: WCKCFGIE + name: WCKCFGIE + - bit_offset: 3 + bit_size: 1 + description: FIFO request interrupt enable + enum: FREQIE + name: FREQIE + - bit_offset: 4 + bit_size: 1 + description: Codec not ready interrupt enable + enum: CNRDYIE + name: CNRDYIE + - bit_offset: 5 + bit_size: 1 + description: Anticipated frame synchronization detection interrupt enable + enum: AFSDETIE + name: AFSDETIE + - bit_offset: 6 + bit_size: 1 + description: Late frame synchronization detection interrupt enable + enum: LFSDETIE + name: LFSDETIE +fieldset/SLOTR: + description: ASlot register + fields: + - bit_offset: 0 + bit_size: 5 + description: First bit offset + name: FBOFF + - bit_offset: 6 + bit_size: 2 + description: Slot size + enum: SLOTSZ + name: SLOTSZ + - bit_offset: 8 + bit_size: 4 + description: Number of slots in an audio frame + name: NBSLOT + - bit_offset: 16 + bit_size: 16 + description: Slot enable + enum: SLOTEN + name: SLOTEN +fieldset/SR: + description: AStatus register + fields: + - bit_offset: 0 + bit_size: 1 + description: Overrun / underrun + enum_read: OVRUDRR + name: OVRUDR + - bit_offset: 1 + bit_size: 1 + description: Mute detection + enum_read: MUTEDETR + name: MUTEDET + - bit_offset: 2 + bit_size: 1 + description: Wrong clock configuration flag. This bit is read only. + enum_read: WCKCFGR + name: WCKCFG + - bit_offset: 3 + bit_size: 1 + description: FIFO request + enum_read: FREQR + name: FREQ + - bit_offset: 4 + bit_size: 1 + description: Codec not ready + enum_read: CNRDYR + name: CNRDY + - bit_offset: 5 + bit_size: 1 + description: Anticipated frame synchronization detection + enum_read: AFSDETR + name: AFSDET + - bit_offset: 6 + bit_size: 1 + description: Late frame synchronization detection + enum_read: LFSDETR + name: LFSDET + - bit_offset: 16 + bit_size: 3 + description: FIFO level threshold + enum_read: FLVLR + name: FLVL diff --git a/data/registers/sdmmc_v1.yaml b/data/registers/sdmmc_v1.yaml new file mode 100644 index 0000000..81c7d32 --- /dev/null +++ b/data/registers/sdmmc_v1.yaml @@ -0,0 +1,507 @@ +--- +block/SDMMC: + description: Secure digital input/output interface + items: + - byte_offset: 0 + description: power control register + fieldset: POWER + name: POWER + - byte_offset: 4 + description: SDI clock control register + fieldset: CLKCR + name: CLKCR + - byte_offset: 8 + description: argument register + fieldset: ARG + name: ARG + - byte_offset: 12 + description: command register + fieldset: CMD + name: CMD + - access: Read + byte_offset: 16 + description: command response register + fieldset: RESPCMD + name: RESPCMD + - access: Read + byte_offset: 20 + description: response 1..4 register + fieldset: RESP1 + name: RESP1 + - access: Read + byte_offset: 24 + description: response 1..4 register + fieldset: RESP2 + name: RESP2 + - access: Read + byte_offset: 28 + description: response 1..4 register + fieldset: RESP3 + name: RESP3 + - access: Read + byte_offset: 32 + description: response 1..4 register + fieldset: RESP4 + name: RESP4 + - byte_offset: 36 + description: data timer register + fieldset: DTIMER + name: DTIMER + - byte_offset: 40 + description: data length register + fieldset: DLEN + name: DLEN + - byte_offset: 44 + description: data control register + fieldset: DCTRL + name: DCTRL + - access: Read + byte_offset: 48 + description: data counter register + fieldset: DCOUNT + name: DCOUNT + - access: Read + byte_offset: 52 + description: status register + fieldset: STA + name: STA + - byte_offset: 56 + description: interrupt clear register + fieldset: ICR + name: ICR + - byte_offset: 60 + description: mask register + fieldset: MASK + name: MASK + - access: Read + byte_offset: 72 + description: FIFO counter register + fieldset: FIFOCNT + name: FIFOCNT + - byte_offset: 128 + description: data FIFO register + fieldset: FIFO + name: FIFO +fieldset/ARG: + description: argument register + fields: + - bit_offset: 0 + bit_size: 32 + description: Command argument + name: CMDARG +fieldset/CLKCR: + description: SDI clock control register + fields: + - bit_offset: 0 + bit_size: 8 + description: Clock divide factor + name: CLKDIV + - bit_offset: 8 + bit_size: 1 + description: Clock enable bit + name: CLKEN + - bit_offset: 9 + bit_size: 1 + description: Power saving configuration bit + name: PWRSAV + - bit_offset: 10 + bit_size: 1 + description: Clock divider bypass enable bit + name: BYPASS + - bit_offset: 11 + bit_size: 2 + description: Wide bus mode enable bit + name: WIDBUS + - bit_offset: 13 + bit_size: 1 + description: SDIO_CK dephasing selection bit + name: NEGEDGE + - bit_offset: 14 + bit_size: 1 + description: HW Flow Control enable + name: HWFC_EN +fieldset/CMD: + description: command register + fields: + - bit_offset: 0 + bit_size: 6 + description: Command index + name: CMDINDEX + - bit_offset: 6 + bit_size: 2 + description: Wait for response bits + name: WAITRESP + - bit_offset: 8 + bit_size: 1 + description: CPSM waits for interrupt request + name: WAITINT + - bit_offset: 9 + bit_size: 1 + description: CPSM Waits for ends of data transfer (CmdPend internal signal) + name: WAITPEND + - bit_offset: 10 + bit_size: 1 + description: Command path state machine (CPSM) Enable bit + name: CPSMEN + - bit_offset: 11 + bit_size: 1 + description: SD I/O suspend command + name: SDIOSuspend +fieldset/DCOUNT: + description: data counter register + fields: + - bit_offset: 0 + bit_size: 25 + description: Data count value + name: DATACOUNT +fieldset/DCTRL: + description: data control register + fields: + - bit_offset: 0 + bit_size: 1 + description: DTEN + name: DTEN + - bit_offset: 1 + bit_size: 1 + description: Data transfer direction selection + name: DTDIR + - bit_offset: 2 + bit_size: 1 + description: 'Data transfer mode selection 1: Stream or SDIO multibyte data transfer' + name: DTMODE + - bit_offset: 3 + bit_size: 1 + description: DMA enable bit + name: DMAEN + - bit_offset: 4 + bit_size: 4 + description: Data block size + name: DBLOCKSIZE + - bit_offset: 8 + bit_size: 1 + description: Read wait start + name: RWSTART + - bit_offset: 9 + bit_size: 1 + description: Read wait stop + name: RWSTOP + - bit_offset: 10 + bit_size: 1 + description: Read wait mode + name: RWMOD + - bit_offset: 11 + bit_size: 1 + description: SD I/O enable functions + name: SDIOEN +fieldset/DLEN: + description: data length register + fields: + - bit_offset: 0 + bit_size: 25 + description: Data length value + name: DATALENGTH +fieldset/DTIMER: + description: data timer register + fields: + - bit_offset: 0 + bit_size: 32 + description: Data timeout period + name: DATATIME +fieldset/FIFO: + description: data FIFO register + fields: + - bit_offset: 0 + bit_size: 32 + description: Receive and transmit FIFO data + name: FIFOData +fieldset/FIFOCNT: + description: FIFO counter register + fields: + - bit_offset: 0 + bit_size: 24 + description: Remaining number of words to be written to or read from the FIFO + name: FIFOCOUNT +fieldset/ICR: + description: interrupt clear register + fields: + - bit_offset: 0 + bit_size: 1 + description: CCRCFAIL flag clear bit + name: CCRCFAILC + - bit_offset: 1 + bit_size: 1 + description: DCRCFAIL flag clear bit + name: DCRCFAILC + - bit_offset: 2 + bit_size: 1 + description: CTIMEOUT flag clear bit + name: CTIMEOUTC + - bit_offset: 3 + bit_size: 1 + description: DTIMEOUT flag clear bit + name: DTIMEOUTC + - bit_offset: 4 + bit_size: 1 + description: TXUNDERR flag clear bit + name: TXUNDERRC + - bit_offset: 5 + bit_size: 1 + description: RXOVERR flag clear bit + name: RXOVERRC + - bit_offset: 6 + bit_size: 1 + description: CMDREND flag clear bit + name: CMDRENDC + - bit_offset: 7 + bit_size: 1 + description: CMDSENT flag clear bit + name: CMDSENTC + - bit_offset: 8 + bit_size: 1 + description: DATAEND flag clear bit + name: DATAENDC + - bit_offset: 10 + bit_size: 1 + description: DBCKEND flag clear bit + name: DBCKENDC + - bit_offset: 22 + bit_size: 1 + description: SDIOIT flag clear bit + name: SDIOITC +fieldset/MASK: + description: mask register + fields: + - bit_offset: 0 + bit_size: 1 + description: Command CRC fail interrupt enable + name: CCRCFAILIE + - bit_offset: 1 + bit_size: 1 + description: Data CRC fail interrupt enable + name: DCRCFAILIE + - bit_offset: 2 + bit_size: 1 + description: Command timeout interrupt enable + name: CTIMEOUTIE + - bit_offset: 3 + bit_size: 1 + description: Data timeout interrupt enable + name: DTIMEOUTIE + - bit_offset: 4 + bit_size: 1 + description: Tx FIFO underrun error interrupt enable + name: TXUNDERRIE + - bit_offset: 5 + bit_size: 1 + description: Rx FIFO overrun error interrupt enable + name: RXOVERRIE + - bit_offset: 6 + bit_size: 1 + description: Command response received interrupt enable + name: CMDRENDIE + - bit_offset: 7 + bit_size: 1 + description: Command sent interrupt enable + name: CMDSENTIE + - bit_offset: 8 + bit_size: 1 + description: Data end interrupt enable + name: DATAENDIE + - bit_offset: 10 + bit_size: 1 + description: Data block end interrupt enable + name: DBCKENDIE + - bit_offset: 11 + bit_size: 1 + description: Command acting interrupt enable + name: CMDACTIE + - bit_offset: 12 + bit_size: 1 + description: Data transmit acting interrupt enable + name: TXACTIE + - bit_offset: 13 + bit_size: 1 + description: Data receive acting interrupt enable + name: RXACTIE + - bit_offset: 14 + bit_size: 1 + description: Tx FIFO half empty interrupt enable + name: TXFIFOHEIE + - bit_offset: 15 + bit_size: 1 + description: Rx FIFO half full interrupt enable + name: RXFIFOHFIE + - bit_offset: 16 + bit_size: 1 + description: Tx FIFO full interrupt enable + name: TXFIFOFIE + - bit_offset: 17 + bit_size: 1 + description: Rx FIFO full interrupt enable + name: RXFIFOFIE + - bit_offset: 18 + bit_size: 1 + description: Tx FIFO empty interrupt enable + name: TXFIFOEIE + - bit_offset: 19 + bit_size: 1 + description: Rx FIFO empty interrupt enable + name: RXFIFOEIE + - bit_offset: 20 + bit_size: 1 + description: Data available in Tx FIFO interrupt enable + name: TXDAVLIE + - bit_offset: 21 + bit_size: 1 + description: Data available in Rx FIFO interrupt enable + name: RXDAVLIE + - bit_offset: 22 + bit_size: 1 + description: SDIO mode interrupt received interrupt enable + name: SDIOITIE +fieldset/POWER: + description: power control register + fields: + - bit_offset: 0 + bit_size: 2 + description: PWRCTRL + name: PWRCTRL +fieldset/RESP1: + description: response 1..4 register + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 32 + description: see Table 132 + name: CARDSTATUS +fieldset/RESP2: + description: response 1..4 register + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 32 + description: see Table 132 + name: CARDSTATUS +fieldset/RESP3: + description: response 1..4 register + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 32 + description: see Table 132 + name: CARDSTATUS +fieldset/RESP4: + description: response 1..4 register + fields: + - array: + len: 1 + stride: 0 + bit_offset: 0 + bit_size: 32 + description: see Table 132 + name: CARDSTATUS +fieldset/RESPCMD: + description: command response register + fields: + - bit_offset: 0 + bit_size: 6 + description: Response command index + name: RESPCMD +fieldset/STA: + description: status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Command response received (CRC check failed) + name: CCRCFAIL + - bit_offset: 1 + bit_size: 1 + description: Data block sent/received (CRC check failed) + name: DCRCFAIL + - bit_offset: 2 + bit_size: 1 + description: Command response timeout + name: CTIMEOUT + - bit_offset: 3 + bit_size: 1 + description: Data timeout + name: DTIMEOUT + - bit_offset: 4 + bit_size: 1 + description: Transmit FIFO underrun error + name: TXUNDERR + - bit_offset: 5 + bit_size: 1 + description: Received FIFO overrun error + name: RXOVERR + - bit_offset: 6 + bit_size: 1 + description: Command response received (CRC check passed) + name: CMDREND + - bit_offset: 7 + bit_size: 1 + description: Command sent (no response required) + name: CMDSENT + - bit_offset: 8 + bit_size: 1 + description: Data end (data counter, SDIDCOUNT, is zero) + name: DATAEND + - bit_offset: 10 + bit_size: 1 + description: Data block sent/received (CRC check passed) + name: DBCKEND + - bit_offset: 11 + bit_size: 1 + description: Command transfer in progress + name: CMDACT + - bit_offset: 12 + bit_size: 1 + description: Data transmit in progress + name: TXACT + - bit_offset: 13 + bit_size: 1 + description: Data receive in progress + name: RXACT + - bit_offset: 14 + bit_size: 1 + description: 'Transmit FIFO half empty: at least 8 words can be written into the + FIFO' + name: TXFIFOHE + - bit_offset: 15 + bit_size: 1 + description: 'Receive FIFO half full: there are at least 8 words in the FIFO' + name: RXFIFOHF + - bit_offset: 16 + bit_size: 1 + description: Transmit FIFO full + name: TXFIFOF + - bit_offset: 17 + bit_size: 1 + description: Receive FIFO full + name: RXFIFOF + - bit_offset: 18 + bit_size: 1 + description: Transmit FIFO empty + name: TXFIFOE + - bit_offset: 19 + bit_size: 1 + description: Receive FIFO empty + name: RXFIFOE + - bit_offset: 20 + bit_size: 1 + description: Data available in transmit FIFO + name: TXDAVL + - bit_offset: 21 + bit_size: 1 + description: Data available in receive FIFO + name: RXDAVL + - bit_offset: 22 + bit_size: 1 + description: SDIO interrupt received + name: SDIOIT diff --git a/data/registers/spdifrx_v1.yaml b/data/registers/spdifrx_v1.yaml new file mode 100644 index 0000000..5e9c30d --- /dev/null +++ b/data/registers/spdifrx_v1.yaml @@ -0,0 +1,241 @@ +--- +block/SPDIFRX: + description: Receiver Interface + items: + - byte_offset: 0 + description: Control register + fieldset: CR + name: CR + - byte_offset: 4 + description: Interrupt mask register + fieldset: IMR + name: IMR + - access: Read + byte_offset: 8 + description: Status register + fieldset: SR + name: SR + - access: Write + byte_offset: 12 + description: Interrupt Flag Clear register + fieldset: IFCR + name: IFCR + - access: Read + byte_offset: 16 + description: Data input register + fieldset: DR + name: DR + - access: Read + byte_offset: 20 + description: Channel Status register + fieldset: CSR + name: CSR + - access: Read + byte_offset: 24 + description: Debug Information register + fieldset: DIR + name: DIR +fieldset/CR: + description: Control register + fields: + - bit_offset: 0 + bit_size: 2 + description: Peripheral Block Enable + name: SPDIFEN + - bit_offset: 2 + bit_size: 1 + description: Receiver DMA ENable for data flow + name: RXDMAEN + - bit_offset: 3 + bit_size: 1 + description: STerEO Mode + name: RXSTEO + - bit_offset: 4 + bit_size: 2 + description: RX Data format + name: DRFMT + - bit_offset: 6 + bit_size: 1 + description: Mask Parity error bit + name: PMSK + - bit_offset: 7 + bit_size: 1 + description: Mask of Validity bit + name: VMSK + - bit_offset: 8 + bit_size: 1 + description: Mask of channel status and user bits + name: CUMSK + - bit_offset: 9 + bit_size: 1 + description: Mask of Preamble Type bits + name: PTMSK + - bit_offset: 10 + bit_size: 1 + description: Control Buffer DMA ENable for control flow + name: CBDMAEN + - bit_offset: 11 + bit_size: 1 + description: Channel Selection + name: CHSEL + - bit_offset: 12 + bit_size: 2 + description: Maximum allowed re-tries during synchronization phase + name: NBTR + - bit_offset: 14 + bit_size: 1 + description: Wait For Activity + name: WFA + - bit_offset: 16 + bit_size: 3 + description: input selection + name: INSEL +fieldset/CSR: + description: Channel Status register + fields: + - bit_offset: 0 + bit_size: 16 + description: User data information + name: USR + - bit_offset: 16 + bit_size: 8 + description: Channel A status information + name: CS + - bit_offset: 24 + bit_size: 1 + description: Start Of Block + name: SOB +fieldset/DIR: + description: Debug Information register + fields: + - bit_offset: 0 + bit_size: 13 + description: Threshold HIGH + name: THI + - bit_offset: 16 + bit_size: 13 + description: Threshold LOW + name: TLO +fieldset/DR: + description: Data input register + fields: + - bit_offset: 0 + bit_size: 24 + description: Parity Error bit + name: DR + - bit_offset: 24 + bit_size: 1 + description: Parity Error bit + name: PE + - bit_offset: 25 + bit_size: 1 + description: Validity bit + name: V + - bit_offset: 26 + bit_size: 1 + description: User bit + name: U + - bit_offset: 27 + bit_size: 1 + description: Channel Status bit + name: C + - bit_offset: 28 + bit_size: 2 + description: Preamble Type + name: PT +fieldset/IFCR: + description: Interrupt Flag Clear register + fields: + - bit_offset: 2 + bit_size: 1 + description: Clears the Parity error flag + name: PERRCF + - bit_offset: 3 + bit_size: 1 + description: Clears the Overrun error flag + name: OVRCF + - bit_offset: 4 + bit_size: 1 + description: Clears the Synchronization Block Detected flag + name: SBDCF + - bit_offset: 5 + bit_size: 1 + description: Clears the Synchronization Done flag + name: SYNCDCF +fieldset/IMR: + description: Interrupt mask register + fields: + - bit_offset: 0 + bit_size: 1 + description: RXNE interrupt enable + name: RXNEIE + - bit_offset: 1 + bit_size: 1 + description: Control Buffer Ready Interrupt Enable + name: CSRNEIE + - bit_offset: 2 + bit_size: 1 + description: Parity error interrupt enable + name: PERRIE + - bit_offset: 3 + bit_size: 1 + description: Overrun error Interrupt Enable + name: OVRIE + - bit_offset: 4 + bit_size: 1 + description: Synchronization Block Detected Interrupt Enable + name: SBLKIE + - bit_offset: 5 + bit_size: 1 + description: Synchronization Done + name: SYNCDIE + - bit_offset: 6 + bit_size: 1 + description: Serial Interface Error Interrupt Enable + name: IFEIE +fieldset/SR: + description: Status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Read data register not empty + name: RXNE + - bit_offset: 1 + bit_size: 1 + description: Control Buffer register is not empty + name: CSRNE + - bit_offset: 2 + bit_size: 1 + description: Parity error + name: PERR + - bit_offset: 3 + bit_size: 1 + description: Overrun error + name: OVR + - bit_offset: 4 + bit_size: 1 + description: Synchronization Block Detected + name: SBD + - bit_offset: 5 + bit_size: 1 + description: Synchronization Done + name: SYNCD + - bit_offset: 6 + bit_size: 1 + description: Framing error + name: FERR + - bit_offset: 7 + bit_size: 1 + description: Synchronization error + name: SERR + - bit_offset: 8 + bit_size: 1 + description: Time-out error + name: TERR + - array: + len: 1 + stride: 0 + bit_offset: 16 + bit_size: 15 + description: Duration of 5 symbols counted with SPDIF_CLK + name: WIDTH diff --git a/data/registers/spi_v2.yaml b/data/registers/spi_v2.yaml index 3fcd92c..29beb35 100644 --- a/data/registers/spi_v2.yaml +++ b/data/registers/spi_v2.yaml @@ -2,453 +2,669 @@ block/SPI: description: Serial peripheral interface items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2 - - name: SR - description: status register - byte_offset: 8 - fieldset: SR - - name: DR - description: data register - byte_offset: 12 - fieldset: DR - - name: CRCPR - description: CRC polynomial register - byte_offset: 16 - fieldset: CRCPR - - name: RXCRCR - description: RX CRC register - byte_offset: 20 - access: Read - fieldset: RXCRCR - - name: TXCRCR - description: TX CRC register - byte_offset: 24 - access: Read - fieldset: TXCRCR + - byte_offset: 0 + description: control register 1 + fieldset: CR1 + name: CR1 + - byte_offset: 4 + description: control register 2 + fieldset: CR2 + name: CR2 + - byte_offset: 8 + description: status register + fieldset: SR + name: SR + - byte_offset: 12 + description: data register + fieldset: DR + name: DR + - byte_offset: 16 + description: CRC polynomial register + fieldset: CRCPR + name: CRCPR + - access: Read + byte_offset: 20 + description: RX CRC register + fieldset: RXCRCR + name: RXCRCR + - access: Read + byte_offset: 24 + description: TX CRC register + fieldset: TXCRCR + name: TXCRCR + - byte_offset: 28 + description: I2S configuration register + fieldset: I2SCFGR + name: I2SCFGR + - byte_offset: 32 + description: I2S prescaler register + fieldset: I2SPR + name: I2SPR fieldset/CR1: description: control register 1 fields: - - name: CPHA - description: Clock phase - bit_offset: 0 - bit_size: 1 - enum: CPHA - - name: CPOL - description: Clock polarity - bit_offset: 1 - bit_size: 1 - enum: CPOL - - name: MSTR - description: Master selection - bit_offset: 2 - bit_size: 1 - enum: MSTR - - name: BR - description: Baud rate control - bit_offset: 3 - bit_size: 3 - enum: BR - - name: SPE - description: SPI enable - bit_offset: 6 - bit_size: 1 - - name: LSBFIRST - description: Frame format - bit_offset: 7 - bit_size: 1 - enum: LSBFIRST - - name: SSI - description: Internal slave select - bit_offset: 8 - bit_size: 1 - - name: SSM - description: Software slave management - bit_offset: 9 - bit_size: 1 - - name: RXONLY - description: Receive only - bit_offset: 10 - bit_size: 1 - enum: RXONLY - - name: CRCL - description: CRC length - bit_offset: 11 - bit_size: 1 - enum: CRCL - - name: CRCNEXT - description: CRC transfer next - bit_offset: 12 - bit_size: 1 - enum: CRCNEXT - - name: CRCEN - description: Hardware CRC calculation enable - bit_offset: 13 - bit_size: 1 - - name: BIDIOE - description: Output enable in bidirectional mode - bit_offset: 14 - bit_size: 1 - enum: BIDIOE - - name: BIDIMODE - description: Bidirectional data mode enable - bit_offset: 15 - bit_size: 1 - enum: BIDIMODE + - bit_offset: 0 + bit_size: 1 + description: Clock phase + enum: CPHA + name: CPHA + - bit_offset: 1 + bit_size: 1 + description: Clock polarity + enum: CPOL + name: CPOL + - bit_offset: 2 + bit_size: 1 + description: Master selection + enum: MSTR + name: MSTR + - bit_offset: 3 + bit_size: 3 + description: Baud rate control + enum: BR + name: BR + - bit_offset: 6 + bit_size: 1 + description: SPI enable + name: SPE + - bit_offset: 7 + bit_size: 1 + description: Frame format + enum: LSBFIRST + name: LSBFIRST + - bit_offset: 8 + bit_size: 1 + description: Internal slave select + name: SSI + - bit_offset: 9 + bit_size: 1 + description: Software slave management + name: SSM + - bit_offset: 10 + bit_size: 1 + description: Receive only + enum: RXONLY + name: RXONLY + - bit_offset: 11 + bit_size: 1 + description: CRC length + enum: CRCL + name: CRCL + - bit_offset: 12 + bit_size: 1 + description: CRC transfer next + enum: CRCNEXT + name: CRCNEXT + - bit_offset: 13 + bit_size: 1 + description: Hardware CRC calculation enable + name: CRCEN + - bit_offset: 14 + bit_size: 1 + description: Output enable in bidirectional mode + enum: BIDIOE + name: BIDIOE + - bit_offset: 15 + bit_size: 1 + description: Bidirectional data mode enable + enum: BIDIMODE + name: BIDIMODE fieldset/CR2: description: control register 2 fields: - - name: RXDMAEN - description: Rx buffer DMA enable - bit_offset: 0 - bit_size: 1 - - name: TXDMAEN - description: Tx buffer DMA enable - bit_offset: 1 - bit_size: 1 - - name: SSOE - description: SS output enable - bit_offset: 2 - bit_size: 1 - - name: NSSP - description: NSS pulse management - bit_offset: 3 - bit_size: 1 - - name: FRF - description: Frame format - bit_offset: 4 - bit_size: 1 - enum: FRF - - name: ERRIE - description: Error interrupt enable - bit_offset: 5 - bit_size: 1 - - name: RXNEIE - description: RX buffer not empty interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: Tx buffer empty interrupt enable - bit_offset: 7 - bit_size: 1 - - name: DS - description: Data size - bit_offset: 8 - bit_size: 4 - enum: DS - - name: FRXTH - description: FIFO reception threshold - bit_offset: 12 - bit_size: 1 - enum: FRXTH - - name: LDMA_RX - description: Last DMA transfer for reception - bit_offset: 13 - bit_size: 1 - enum: LDMA_RX - - name: LDMA_TX - description: Last DMA transfer for transmission - bit_offset: 14 - bit_size: 1 - enum: LDMA_TX + - bit_offset: 0 + bit_size: 1 + description: Rx buffer DMA enable + name: RXDMAEN + - bit_offset: 1 + bit_size: 1 + description: Tx buffer DMA enable + name: TXDMAEN + - bit_offset: 2 + bit_size: 1 + description: SS output enable + name: SSOE + - bit_offset: 3 + bit_size: 1 + description: NSS pulse management + name: NSSP + - bit_offset: 4 + bit_size: 1 + description: Frame format + enum: FRF + name: FRF + - bit_offset: 5 + bit_size: 1 + description: Error interrupt enable + name: ERRIE + - bit_offset: 6 + bit_size: 1 + description: RX buffer not empty interrupt enable + name: RXNEIE + - bit_offset: 7 + bit_size: 1 + description: Tx buffer empty interrupt enable + name: TXEIE + - bit_offset: 8 + bit_size: 4 + description: Data size + enum: DS + name: DS + - bit_offset: 12 + bit_size: 1 + description: FIFO reception threshold + enum: FRXTH + name: FRXTH + - bit_offset: 13 + bit_size: 1 + description: Last DMA transfer for reception + enum: LDMA_RX + name: LDMA_RX + - bit_offset: 14 + bit_size: 1 + description: Last DMA transfer for transmission + enum: LDMA_TX + name: LDMA_TX fieldset/CRCPR: description: CRC polynomial register fields: - - name: CRCPOLY - description: CRC polynomial register - bit_offset: 0 - bit_size: 16 + - bit_offset: 0 + bit_size: 16 + description: CRC polynomial register + name: CRCPOLY fieldset/DR: description: data register fields: - - name: DR - description: Data register - bit_offset: 0 - bit_size: 16 + - bit_offset: 0 + bit_size: 16 + description: Data register + name: DR fieldset/RXCRCR: description: RX CRC register fields: - - name: RxCRC - description: Rx CRC register - bit_offset: 0 + - bit_offset: 0 bit_size: 16 + description: Rx CRC register + name: RxCRC fieldset/SR: description: status register fields: - - name: RXNE + - bit_offset: 0 + bit_size: 1 description: Receive buffer not empty - bit_offset: 0 + name: RXNE + - bit_offset: 1 bit_size: 1 - - name: TXE description: Transmit buffer empty - bit_offset: 1 + name: TXE + - bit_offset: 2 + bit_size: 1 + description: Channel side + enum: CHSIDE + name: CHSIDE + - bit_offset: 3 + bit_size: 1 + description: Underrun flag + enum_read: UDRR + name: UDR + - bit_offset: 4 bit_size: 1 - - name: CRCERR description: CRC error flag - bit_offset: 4 + name: CRCERR + - bit_offset: 5 bit_size: 1 - - name: MODF description: Mode fault - bit_offset: 5 + name: MODF + - bit_offset: 6 bit_size: 1 - - name: OVR description: Overrun flag - bit_offset: 6 + name: OVR + - bit_offset: 7 bit_size: 1 - - name: BSY description: Busy flag - bit_offset: 7 - bit_size: 1 - - name: FRE - description: Frame format error - bit_offset: 8 + name: BSY + - bit_offset: 8 bit_size: 1 + description: frame format error enum_read: FRER - - name: FRLVL + name: FRE + - bit_offset: 9 + bit_size: 2 description: FIFO reception level - bit_offset: 9 - bit_size: 2 enum_read: FRLVLR - - name: FTLVL - description: FIFO Transmission Level - bit_offset: 11 + name: FRLVL + - bit_offset: 11 bit_size: 2 + description: FIFO Transmission Level enum_read: FTLVLR + name: FTLVL fieldset/TXCRCR: description: TX CRC register fields: - - name: TxCRC - description: Tx CRC register - bit_offset: 0 + - bit_offset: 0 bit_size: 16 + description: Tx CRC register + name: TxCRC +fieldset/I2SCFGR: + description: I2S configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: Channel length (number of bits per audio channel) + enum: CHLEN + name: CHLEN + - bit_offset: 1 + bit_size: 2 + description: Data length to be transferred + enum: DATLEN + name: DATLEN + - bit_offset: 3 + bit_size: 1 + description: Steady state clock polarity + enum: CKPOL + name: CKPOL + - bit_offset: 4 + bit_size: 2 + description: I2S standard selection + enum: ISSTD + name: I2SSTD + - bit_offset: 7 + bit_size: 1 + description: PCM frame synchronization + enum: PCMSYNC + name: PCMSYNC + - bit_offset: 8 + bit_size: 2 + description: I2S configuration mode + enum: ISCFG + name: I2SCFG + - bit_offset: 10 + bit_size: 1 + description: I2S Enable + enum: ISE + name: I2SE + - bit_offset: 11 + bit_size: 1 + description: I2S mode selection + enum: ISMOD + name: I2SMOD + - bit_offset: 12 + bit_size: 1 + description: Asynchronous start enable + name: ASTRTEN +fieldset/I2SPR: + description: I2S prescaler register + fields: + - bit_offset: 0 + bit_size: 8 + description: I2S Linear prescaler + name: I2SDIV + - bit_offset: 8 + bit_size: 1 + description: Odd factor for the prescaler + enum: ODD + name: ODD + - bit_offset: 9 + bit_size: 1 + description: Master clock output enable + enum: MCKOE + name: MCKOE enum/BIDIMODE: bit_size: 1 variants: - - name: Unidirectional - description: 2-line unidirectional data mode selected + - description: 2-line unidirectional data mode selected + name: Unidirectional value: 0 - - name: Bidirectional - description: 1-line bidirectional data mode selected + - description: 1-line bidirectional data mode selected + name: Bidirectional value: 1 enum/BIDIOE: bit_size: 1 variants: - - name: OutputDisabled - description: Output disabled (receive-only mode) + - description: Output disabled (receive-only mode) + name: OutputDisabled value: 0 - - name: OutputEnabled - description: Output enabled (transmit-only mode) + - description: Output enabled (transmit-only mode) + name: OutputEnabled value: 1 enum/BR: bit_size: 3 variants: - - name: Div2 - description: f_PCLK / 2 + - description: f_PCLK / 2 + name: Div2 value: 0 - - name: Div4 - description: f_PCLK / 4 + - description: f_PCLK / 4 + name: Div4 value: 1 - - name: Div8 - description: f_PCLK / 8 + - description: f_PCLK / 8 + name: Div8 value: 2 - - name: Div16 - description: f_PCLK / 16 + - description: f_PCLK / 16 + name: Div16 value: 3 - - name: Div32 - description: f_PCLK / 32 + - description: f_PCLK / 32 + name: Div32 value: 4 - - name: Div64 - description: f_PCLK / 64 + - description: f_PCLK / 64 + name: Div64 value: 5 - - name: Div128 - description: f_PCLK / 128 + - description: f_PCLK / 128 + name: Div128 value: 6 - - name: Div256 - description: f_PCLK / 256 + - description: f_PCLK / 256 + name: Div256 value: 7 +enum/CHLEN: + bit_size: 1 + variants: + - description: 16-bit wide + name: SixteenBit + value: 0 + - description: 32-bit wide + name: ThirtyTwoBit + value: 1 +enum/CHSIDE: + bit_size: 1 + variants: + - description: Channel left has to be transmitted or has been received + name: Left + value: 0 + - description: Channel right has to be transmitted or has been received + name: Right + value: 1 +enum/CKPOL: + bit_size: 1 + variants: + - description: I2S clock inactive state is low level + name: IdleLow + value: 0 + - description: I2S clock inactive state is high level + name: IdleHigh + value: 1 enum/CPHA: bit_size: 1 variants: - - name: FirstEdge - description: The first clock transition is the first data capture edge + - description: The first clock transition is the first data capture edge + name: FirstEdge value: 0 - - name: SecondEdge - description: The second clock transition is the first data capture edge + - description: The second clock transition is the first data capture edge + name: SecondEdge value: 1 enum/CPOL: bit_size: 1 variants: - - name: IdleLow - description: CK to 0 when idle + - description: CK to 0 when idle + name: IdleLow value: 0 - - name: IdleHigh - description: CK to 1 when idle + - description: CK to 1 when idle + name: IdleHigh value: 1 enum/CRCL: bit_size: 1 variants: - - name: EightBit - description: 8-bit CRC length + - description: 8-bit CRC length + name: EightBit value: 0 - - name: SixteenBit - description: 16-bit CRC length + - description: 16-bit CRC length + name: SixteenBit value: 1 enum/CRCNEXT: bit_size: 1 variants: - - name: TxBuffer - description: Next transmit value is from Tx buffer + - description: Next transmit value is from Tx buffer + name: TxBuffer value: 0 - - name: CRC - description: Next transmit value is from Tx CRC register + - description: Next transmit value is from Tx CRC register + name: CRC value: 1 +enum/DATLEN: + bit_size: 2 + variants: + - description: 16-bit data length + name: SixteenBit + value: 0 + - description: 24-bit data length + name: TwentyFourBit + value: 1 + - description: 32-bit data length + name: ThirtyTwoBit + value: 2 enum/DS: bit_size: 4 variants: - - name: FourBit - description: 4-bit + - description: 4-bit + name: FourBit value: 3 - - name: FiveBit - description: 5-bit + - description: 5-bit + name: FiveBit value: 4 - - name: SixBit - description: 6-bit + - description: 6-bit + name: SixBit value: 5 - - name: SevenBit - description: 7-bit + - description: 7-bit + name: SevenBit value: 6 - - name: EightBit - description: 8-bit + - description: 8-bit + name: EightBit value: 7 - - name: NineBit - description: 9-bit + - description: 9-bit + name: NineBit value: 8 - - name: TenBit - description: 10-bit + - description: 10-bit + name: TenBit value: 9 - - name: ElevenBit - description: 11-bit + - description: 11-bit + name: ElevenBit value: 10 - - name: TwelveBit - description: 12-bit + - description: 12-bit + name: TwelveBit value: 11 - - name: ThirteenBit - description: 13-bit + - description: 13-bit + name: ThirteenBit value: 12 - - name: FourteenBit - description: 14-bit + - description: 14-bit + name: FourteenBit value: 13 - - name: FifteenBit - description: 15-bit + - description: 15-bit + name: FifteenBit value: 14 - - name: SixteenBit - description: 16-bit + - description: 16-bit + name: SixteenBit value: 15 enum/FRER: bit_size: 1 variants: - - name: NoError - description: No frame format error + - description: No frame format error + name: NoError value: 0 - - name: Error - description: A frame format error occurred + - description: A frame format error occurred + name: Error value: 1 enum/FRF: bit_size: 1 variants: - - name: Motorola - description: SPI Motorola mode + - description: SPI Motorola mode + name: Motorola value: 0 - - name: TI - description: SPI TI mode + - description: SPI TI mode + name: TI value: 1 enum/FRLVLR: bit_size: 2 variants: - - name: Empty - description: Rx FIFO Empty + - description: Rx FIFO Empty + name: Empty value: 0 - - name: Quarter - description: Rx 1/4 FIFO + - description: Rx 1/4 FIFO + name: Quarter value: 1 - - name: Half - description: Rx 1/2 FIFO + - description: Rx 1/2 FIFO + name: Half value: 2 - - name: Full - description: Rx FIFO full + - description: Rx FIFO full + name: Full value: 3 enum/FRXTH: bit_size: 1 variants: - - name: Half - description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit) + - description: RXNE event is generated if the FIFO level is greater than or equal + to 1/2 (16-bit) + name: Half value: 0 - - name: Quarter - description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit) + - description: RXNE event is generated if the FIFO level is greater than or equal + to 1/4 (8-bit) + name: Quarter value: 1 enum/FTLVLR: bit_size: 2 variants: - - name: Empty - description: Tx FIFO Empty + - description: Tx FIFO Empty + name: Empty value: 0 - - name: Quarter - description: Tx 1/4 FIFO + - description: Tx 1/4 FIFO + name: Quarter value: 1 - - name: Half - description: Tx 1/2 FIFO + - description: Tx 1/2 FIFO + name: Half value: 2 - - name: Full - description: Tx FIFO full + - description: Tx FIFO full + name: Full + value: 3 +enum/ISCFG: + bit_size: 2 + variants: + - description: Slave - transmit + name: SlaveTx + value: 0 + - description: Slave - receive + name: SlaveRx + value: 1 + - description: Master - transmit + name: MasterTx + value: 2 + - description: Master - receive + name: MasterRx + value: 3 +enum/ISE: + bit_size: 1 + variants: + - description: I2S peripheral is disabled + name: Disabled + value: 0 + - description: I2S peripheral is enabled + name: Enabled + value: 1 +enum/ISMOD: + bit_size: 1 + variants: + - description: SPI mode is selected + name: SPIMode + value: 0 + - description: I2S mode is selected + name: I2SMode + value: 1 +enum/ISSTD: + bit_size: 2 + variants: + - description: I2S Philips standard + name: Philips + value: 0 + - description: MSB justified standard + name: MSB + value: 1 + - description: LSB justified standard + name: LSB + value: 2 + - description: PCM standard + name: PCM value: 3 enum/LDMA_RX: bit_size: 1 variants: - - name: Even - description: Number of data to transfer for receive is even + - description: Number of data to transfer for receive is even + name: Even value: 0 - - name: Odd - description: Number of data to transfer for receive is odd + - description: Number of data to transfer for receive is odd + name: Odd value: 1 enum/LDMA_TX: bit_size: 1 variants: - - name: Even - description: Number of data to transfer for transmit is even + - description: Number of data to transfer for transmit is even + name: Even value: 0 - - name: Odd - description: Number of data to transfer for transmit is odd + - description: Number of data to transfer for transmit is odd + name: Odd value: 1 enum/LSBFIRST: bit_size: 1 variants: - - name: MSBFirst - description: Data is transmitted/received with the MSB first + - description: Data is transmitted/received with the MSB first + name: MSBFirst value: 0 - - name: LSBFirst - description: Data is transmitted/received with the LSB first + - description: Data is transmitted/received with the LSB first + name: LSBFirst + value: 1 +enum/MCKOE: + bit_size: 1 + variants: + - description: Master clock output is disabled + name: Disabled + value: 0 + - description: Master clock output is enabled + name: Enabled value: 1 enum/MSTR: bit_size: 1 variants: - - name: Slave - description: Slave configuration + - description: Slave configuration + name: Slave value: 0 - - name: Master - description: Master configuration + - description: Master configuration + name: Master + value: 1 +enum/ODD: + bit_size: 1 + variants: + - description: Real divider value is I2SDIV * 2 + name: Even + value: 0 + - description: Real divider value is (I2SDIV * 2) + 1 + name: Odd + value: 1 +enum/OVRR: + bit_size: 1 + variants: + - description: No overrun occurred + name: NoOverrun + value: 0 + - description: Overrun occurred + name: Overrun + value: 1 +enum/PCMSYNC: + bit_size: 1 + variants: + - description: Short frame synchronisation + name: Short + value: 0 + - description: Long frame synchronisation + name: Long value: 1 enum/RXONLY: bit_size: 1 variants: - - name: FullDuplex - description: Full duplex (Transmit and receive) + - description: Full duplex (Transmit and receive) + name: FullDuplex value: 0 - - name: OutputDisabled - description: Output disabled (Receive-only mode) + - description: Output disabled (Receive-only mode) + name: OutputDisabled + value: 1 +enum/UDRR: + bit_size: 1 + variants: + - description: No underrun occurred + name: NoUnderrun + value: 0 + - description: Underrun occurred + name: Underrun value: 1 diff --git a/data/registers/syscfg_f7.yaml b/data/registers/syscfg_f7.yaml new file mode 100644 index 0000000..50d0f6f --- /dev/null +++ b/data/registers/syscfg_f7.yaml @@ -0,0 +1,111 @@ +--- +block/SYSCFG: + description: System configuration controller + items: + - byte_offset: 0 + description: memory remap register + fieldset: MEMRMP + name: MEMRMP + - byte_offset: 4 + description: peripheral mode configuration register + fieldset: PMC + name: PMC + - array: + len: 4 + stride: 4 + byte_offset: 8 + description: external interrupt configuration register 1 + fieldset: EXTICR + name: EXTICR + - access: Read + byte_offset: 32 + description: Compensation cell control register + fieldset: CMPCR + name: CMPCR +fieldset/CMPCR: + description: Compensation cell control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Compensation cell power-down + name: CMP_PD + - bit_offset: 8 + bit_size: 1 + description: READY + name: READY +fieldset/EXTICR: + description: external interrupt configuration register 1 + fields: + - array: + len: 4 + stride: 4 + bit_offset: 0 + bit_size: 4 + description: EXTI x configuration (x = 0 to 3) + name: EXTI +fieldset/MEMRMP: + description: memory remap register + fields: + - bit_offset: 0 + bit_size: 1 + description: Memory boot mapping + name: MEM_BOOT + - bit_offset: 8 + bit_size: 1 + description: Flash bank mode selection + name: FB_MODE + - bit_offset: 10 + bit_size: 2 + description: FMC memory mapping swap + name: SWP_FMC +fieldset/PMC: + description: peripheral mode configuration register + fields: + - bit_offset: 0 + bit_size: 1 + description: I2C1_FMP I2C1 Fast Mode + Enable + name: I2C1_FMP + - bit_offset: 1 + bit_size: 1 + description: I2C2_FMP I2C2 Fast Mode + Enable + name: I2C2_FMP + - bit_offset: 2 + bit_size: 1 + description: I2C3_FMP I2C3 Fast Mode + Enable + name: I2C3_FMP + - bit_offset: 3 + bit_size: 1 + description: I2C4 Fast Mode + Enable + name: I2C4_FMP + - bit_offset: 4 + bit_size: 1 + description: PB6_FMP Fast Mode + name: PB6_FMP + - bit_offset: 5 + bit_size: 1 + description: PB7_FMP Fast Mode + Enable + name: PB7_FMP + - bit_offset: 6 + bit_size: 1 + description: PB8_FMP Fast Mode + Enable + name: PB8_FMP + - bit_offset: 7 + bit_size: 1 + description: Fast Mode + Enable + name: PB9_FMP + - bit_offset: 16 + bit_size: 1 + description: ADC3DC2 + name: ADC1DC2 + - bit_offset: 17 + bit_size: 1 + description: ADC2DC2 + name: ADC2DC2 + - bit_offset: 18 + bit_size: 1 + description: ADC3DC2 + name: ADC3DC2 + - bit_offset: 23 + bit_size: 1 + description: Ethernet PHY interface selection + name: MII_RMII_SEL diff --git a/data/registers/wwdg_v1.yaml b/data/registers/wwdg_v1.yaml new file mode 100644 index 0000000..65a11e7 --- /dev/null +++ b/data/registers/wwdg_v1.yaml @@ -0,0 +1,99 @@ +--- +block/WWDG: + description: Window watchdog + items: + - byte_offset: 0 + description: Control register + fieldset: CR + name: CR + - byte_offset: 4 + description: Configuration register + fieldset: CFR + name: CFR + - byte_offset: 8 + description: Status register + fieldset: SR + name: SR +enum/EWIFR: + bit_size: 1 + variants: + - description: The EWI Interrupt Service Routine has been serviced + name: Finished + value: 0 + - description: The EWI Interrupt Service Routine has been triggered + name: Pending + value: 1 +enum/EWIFW: + bit_size: 1 + variants: + - description: The EWI Interrupt Service Routine has been serviced + name: Finished + value: 0 +enum/EWIW: + bit_size: 1 + variants: + - description: interrupt occurs whenever the counter reaches the value 0x40 + name: Enable + value: 1 +enum/WDGA: + bit_size: 1 + variants: + - description: Watchdog disabled + name: Disabled + value: 0 + - description: Watchdog enabled + name: Enabled + value: 1 +enum/WDGTB: + bit_size: 2 + variants: + - description: Counter clock (PCLK1 div 4096) div 1 + name: Div1 + value: 0 + - description: Counter clock (PCLK1 div 4096) div 2 + name: Div2 + value: 1 + - description: Counter clock (PCLK1 div 4096) div 4 + name: Div4 + value: 2 + - description: Counter clock (PCLK1 div 4096) div 8 + name: Div8 + value: 3 +fieldset/CFR: + description: Configuration register + fields: + - bit_offset: 0 + bit_size: 7 + description: 7-bit window value + name: W + - bit_offset: 7 + bit_size: 2 + description: Timer base + enum: WDGTB + name: WDGTB + - bit_offset: 9 + bit_size: 1 + description: Early wakeup interrupt + enum_write: EWIW + name: EWI +fieldset/CR: + description: Control register + fields: + - bit_offset: 0 + bit_size: 7 + description: 7-bit counter (MSB to LSB) + name: T + - bit_offset: 7 + bit_size: 1 + description: Activation bit + enum: WDGA + name: WDGA +fieldset/SR: + description: Status register + fields: + - bit_offset: 0 + bit_size: 1 + description: Early wakeup interrupt flag + enum_read: EWIFR + enum_write: EWIFW + name: EWIF diff --git a/parse.py b/parse.py index aa0071f..3d208d9 100755 --- a/parse.py +++ b/parse.py @@ -329,6 +329,7 @@ perimap = [ ('.*:RNG:rng1_v3_1', 'rng_v1/RNG'), ('.*:SPI:spi2_v1_4', 'spi_f1/SPI'), ('.*:SPI:spi2s1_v2_2', 'spi_v1/SPI'), + ('.*:SPI:spi2s1_v3_2', 'spi_v2/SPI'), ('.*:SPI:spi2s1_v3_3', 'spi_v2/SPI'), ('.*:SPI:spi2s1_v3_5', 'spi_v2/SPI'), ('.*:SUBGHZSPI:.*', 'spi_v2/SPI'), @@ -338,15 +339,20 @@ perimap = [ ('.*:I2C:i2c1_v1_5', 'i2c_v1/I2C'), ('.*:I2C:i2c2_v1_1', 'i2c_v2/I2C'), ('.*:I2C:i2c2_v1_1F7', 'i2c_v2/I2C'), + ('.*:DAC:dacif_v1_1', 'dac_v1/DAC'), ('.*:DAC:dacif_v2_0', 'dac_v2/DAC'), ('.*:DAC:dacif_v3_0', 'dac_v2/DAC'), + ('.*:ADC:aditf2_v1_1', 'adc_v2/ADC'), ('.*:ADC:aditf5_v2_0', 'adc_v3/ADC'), ('STM32G0.*:ADC:.*', 'adc_g0/ADC'), ('STM32G0.*:ADC_COMMON:.*', 'adccommon_v3/ADC_COMMON'), + ('.*:ADC_COMMON:aditf2_v1_1', 'adccommon_v2/ADC_COMMON'), ('.*:ADC_COMMON:aditf5_v2_0', 'adccommon_v3/ADC_COMMON'), ('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'), + ('.*:DCMI:cci_v2_0', 'dcmi_v1/DCMI'), ('STM32F0.*:SYS:.*', 'syscfg_f0/SYSCFG'), ('STM32F4.*:SYS:.*', 'syscfg_f4/SYSCFG'), + ('STM32F7.*:SYS:.*', 'syscfg_f7/SYSCFG'), ('STM32L4.*:SYS:.*', 'syscfg_l4/SYSCFG'), ('STM32L0.*:SYS:.*', 'syscfg_l0/SYSCFG'), ('STM32L1.*:SYS:.*', 'syscfg_l1/SYSCFG'), @@ -356,6 +362,20 @@ perimap = [ ('STM32WL5.*:SYS:.*', 'syscfg_wl5/SYSCFG'), ('STM32WLE.*:SYS:.*', 'syscfg_wle/SYSCFG'), + ('.*:IWDG:iwdg1_v2_0', 'iwdg_v2/IWDG'), + ('.*:WWDG:wwdg1_v1_0', 'wwdg_v1/WWDG'), + ('.*:JPEG:jpeg1_v1_0', 'jpeg_v1/JPEG'), + ('.*:LPTIM:F7_lptimer1_v1_1', 'lptim_v1/LPTIM'), + ('.*:LTDC:lcdtft1_v1_1', 'ltdc_v1/LTDC'), + ('.*:MDIOS:mdios1_v1_0', 'mdios_v1/MDIOS'), + ('.*:QUADSPI:quadspi1_v1_0', 'quadspi_v1/QUADSPI'), + ('.*:RTC:rtc2_v2_6', 'rtc_v2/RTC'), + ('.*:SAI:sai1_v1_1', 'sai_v1/SAI'), + ('.*:SDMMC:sdmmc_v1_3', 'sdmmc_v1/SDMMC'), + ('.*:SPDIFRX:spdifrx1_v1_0', 'spdifrx_v1/SPDIFRX'), + ('.*:USB_OTG_FS:otgfs1_v1_2', 'otgfs_v1/OTG_FS'), + ('.*:USB_OTG_HS:otghs1_v1_1', 'otghs_v1/OTG_HS'), + ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'), ('STM32F0.*:RCC:.*', 'rcc_f0/RCC'), ('STM32F1.*:RCC:.*', 'rcc_f1/RCC'), @@ -392,16 +412,22 @@ perimap = [ ('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'), ('.*:STM32H7_pwr_v1_0', 'pwr_h7smps/PWR'), ('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'), + ('.*:STM32F7_pwr_v1_0', 'pwr_f7/PWR'), ('.*:STM32L1_pwr_v1_0', 'pwr_l1/PWR'), ('.*:STM32WL_pwr_v1_0', 'pwr_wl5/PWR'), ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'), ('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'), ('.*:STM32F1_flash_v1_0', 'flash_f1/FLASH'), ('.*:STM32F4_flash_v1_0', 'flash_f4/FLASH'), + ('.*:STM32F7_flash_v1_0', 'flash_f7/FLASH'), ('.*:STM32L4_flash_v1_0', 'flash_l4/FLASH'), - ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'), + ('STM32F7.*:ETH:ETH:ethermac110_v2_0', 'eth_v1c/ETH'), ('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'), + ('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'), + ('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'), + ('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'), + ('.*:STM32F0_dbgmcu_v1_0', 'dbgmcu_f0/DBGMCU'), ('.*:STM32F1_dbgmcu_v1_0', 'dbgmcu_f1/DBGMCU'), ('.*:STM32F2_dbgmcu_v1_0', 'dbgmcu_f2/DBGMCU'), @@ -421,6 +447,8 @@ perimap = [ ('.*:DMAMUX:v1', 'dmamux_v1/DMAMUX'), ('.*:BDMA:DMA', 'bdma_v1/DMA'), + ('STM32H7.*:DMA2D:DMA2D:dma2d1_v1_0', 'dma2d_v2/DMA2D'), + ('.*:DMA2D:dma2d1_v1_0', 'dma2d_v1/DMA2D'), ('STM32L4[PQRS].*:.*:DMA', 'bdma_v1/DMA'), # L4+ ('STM32L[04].*:.*:DMA', 'bdma_v2/DMA'), # L0, L4 non-plus (since plus is handled above) ('STM32F030.C.*:.*:DMA', 'bdma_v2/DMA'), # Weird F0