Support STM32G4 ADC peripheral

data/registers/rcc_g4.yaml

@@ -1027,9 +1027,11 @@ fieldset/CCIPR:
       description: ADCs clock source selection
       bit_offset: 28
       bit_size: 2
+      enum: ADCSEL
     - name: ADC345SEL
       description: ADC3/4/5 clock source selection
       bit_offset: 30
+      enum: ADCSEL
       bit_size: 2
 fieldset/CCIPR2:
   description: Peripherals independent clock configuration register
@@ -1333,6 +1335,18 @@ fieldset/PLLCFGR:
       description: Main PLL division factor for PLLSAI2CLK
       bit_offset: 27
       bit_size: 5
+enum/ADCSEL:
+  bit_size: 2
+  variants:
+    - name: NOCLK
+      description: No clock selected
+      value: 0
+    - name: PLLP
+      description: PLL 'P' clock selected as ADC clock
+      value: 1
+    - name: SYSCLK
+      description: System clock selected as ADC clock
+      value: 2
 enum/CLK48SEL:
   bit_size: 2
   variants: