diff --git a/data/registers/can_fdcan_v1.yaml b/data/registers/can_fdcan_v1.yaml
index 15ff8d3..1cf3931 100644
--- a/data/registers/can_fdcan_v1.yaml
+++ b/data/registers/can_fdcan_v1.yaml
@@ -1032,6 +1032,15 @@ enum/PDIV:
   - name: DIV_30
     description: Divide by 30
     value: 15
+enum/TFQM:
+  bit_size: 1
+  variants:
+  - name: FIFO
+    description: Tx FIFO operation
+    value: 0
+  - name: QUEUE
+    description: Tx queue operation
+    value: 1
 enum/TOS:
   bit_size: 2
   variants:
@@ -1074,12 +1083,3 @@ enum/TX:
   - name: RECESSIVE
     description: Recessive (1) at pin FDCANx_TX
     value: 3
-enum/TFQM:
-  bit_size: 1
-  variants:
-  - name: FIFO
-    description: Tx FIFO operation
-    value: 0
-  - name: QUEUE
-    description: Tx queue operation
-    value: 1
diff --git a/data/registers/comp_h5.yaml b/data/registers/comp_h5.yaml
index 0d47a05..afbf7c5 100644
--- a/data/registers/comp_h5.yaml
+++ b/data/registers/comp_h5.yaml
@@ -96,16 +96,16 @@ fieldset/ICFR:
 fieldset/SR:
   description: Comparator status register.
   fields:
-  - name: CIF
-    description: COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register.
-    bit_offset: 16
+  - name: CVAL
+    description: COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect.
+    bit_offset: 0
     bit_size: 1
     array:
       len: 1
       stride: 0
-  - name: CVAL
-    description: COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect.
-    bit_offset: 0
+  - name: CIF
+    description: COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register.
+    bit_offset: 16
     bit_size: 1
     array:
       len: 1
diff --git a/data/registers/cryp_v3.yaml b/data/registers/cryp_v3.yaml
index 543ceba..9f125da 100644
--- a/data/registers/cryp_v3.yaml
+++ b/data/registers/cryp_v3.yaml
@@ -1,189 +1,189 @@
 block/CRYP:
   description: Cryptographic processor.
   items:
-    - name: CR
-      description: control register.
-      byte_offset: 0
-      fieldset: CR
-    - name: SR
-      description: status register.
-      byte_offset: 4
-      access: Read
-      fieldset: SR
-    - name: DIN
-      description: data input register.
-      byte_offset: 8
-    - name: DOUT
-      description: data output register.
-      byte_offset: 12
-      access: Read
-    - name: DMACR
-      description: DMA control register.
-      byte_offset: 16
-      fieldset: DMACR
-    - name: IMSCR
-      description: interrupt mask set/clear register.
-      byte_offset: 20
-      fieldset: IMSCR
-    - name: RISR
-      description: raw interrupt status register.
-      byte_offset: 24
-      access: Read
-      fieldset: RISR
-    - name: MISR
-      description: masked interrupt status register.
-      byte_offset: 28
-      access: Read
-      fieldset: MISR
-    - name: KEY
-      description: Cluster KEY%s, containing K?LR, K?RR.
-      array:
-        len: 4
-        stride: 8
-      byte_offset: 32
-      block: KEY
-    - name: INIT
-      description: Cluster INIT%s, containing IV?LR, IV?RR.
-      array:
-        len: 2
-        stride: 8
-      byte_offset: 64
-      block: INIT
-    - name: CSGCMCCMR
-      description: context swap register.
-      array:
-        len: 8
-        stride: 4
-      byte_offset: 80
-    - name: CSGCMR
-      description: context swap register.
-      array:
-        len: 8
-        stride: 4
-      byte_offset: 112
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: status register.
+    byte_offset: 4
+    access: Read
+    fieldset: SR
+  - name: DIN
+    description: data input register.
+    byte_offset: 8
+  - name: DOUT
+    description: data output register.
+    byte_offset: 12
+    access: Read
+  - name: DMACR
+    description: DMA control register.
+    byte_offset: 16
+    fieldset: DMACR
+  - name: IMSCR
+    description: interrupt mask set/clear register.
+    byte_offset: 20
+    fieldset: IMSCR
+  - name: RISR
+    description: raw interrupt status register.
+    byte_offset: 24
+    access: Read
+    fieldset: RISR
+  - name: MISR
+    description: masked interrupt status register.
+    byte_offset: 28
+    access: Read
+    fieldset: MISR
+  - name: KEY
+    description: Cluster KEY%s, containing K?LR, K?RR.
+    array:
+      len: 4
+      stride: 8
+    byte_offset: 32
+    block: KEY
+  - name: INIT
+    description: Cluster INIT%s, containing IV?LR, IV?RR.
+    array:
+      len: 2
+      stride: 8
+    byte_offset: 64
+    block: INIT
+  - name: CSGCMCCMR
+    description: context swap register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 80
+  - name: CSGCMR
+    description: context swap register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 112
 block/INIT:
   description: Cluster INIT%s, containing IV?LR, IV?RR.
   items:
-    - name: IVLR
-      description: initialization vector registers.
-      byte_offset: 0
-    - name: IVRR
-      description: initialization vector registers.
-      byte_offset: 4
+  - name: IVLR
+    description: initialization vector registers.
+    byte_offset: 0
+  - name: IVRR
+    description: initialization vector registers.
+    byte_offset: 4
 block/KEY:
   description: Cluster KEY%s, containing K?LR, K?RR.
   items:
-    - name: KLR
-      description: key registers.
-      byte_offset: 0
-      access: Write
-    - name: KRR
-      description: key registers.
-      byte_offset: 4
-      access: Write
+  - name: KLR
+    description: key registers.
+    byte_offset: 0
+    access: Write
+  - name: KRR
+    description: key registers.
+    byte_offset: 4
+    access: Write
 fieldset/CR:
   description: control register.
   fields:
-    - name: ALGODIR
-      description: Algorithm direction.
-      bit_offset: 2
-      bit_size: 1
-    - name: ALGOMODE0
-      description: Algorithm mode.
-      bit_offset: 3
-      bit_size: 3
-    - name: DATATYPE
-      description: Data type selection.
-      bit_offset: 6
-      bit_size: 2
-    - name: KEYSIZE
-      description: Key size selection (AES mode only).
-      bit_offset: 8
-      bit_size: 2
-    - name: FFLUSH
-      description: FIFO flush.
-      bit_offset: 14
-      bit_size: 1
-    - name: CRYPEN
-      description: Cryptographic processor enable.
-      bit_offset: 15
-      bit_size: 1
-    - name: GCM_CCMPH
-      description: GCM_CCMPH.
-      bit_offset: 16
-      bit_size: 2
-    - name: ALGOMODE3
-      description: ALGOMODE.
-      bit_offset: 19
-      bit_size: 1
-    - name: NPBLB
-      description: Number of Padding Bytes in Last Block of payload.
-      bit_offset: 20
-      bit_size: 4
+  - name: ALGODIR
+    description: Algorithm direction.
+    bit_offset: 2
+    bit_size: 1
+  - name: ALGOMODE0
+    description: Algorithm mode.
+    bit_offset: 3
+    bit_size: 3
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 6
+    bit_size: 2
+  - name: KEYSIZE
+    description: Key size selection (AES mode only).
+    bit_offset: 8
+    bit_size: 2
+  - name: FFLUSH
+    description: FIFO flush.
+    bit_offset: 14
+    bit_size: 1
+  - name: CRYPEN
+    description: Cryptographic processor enable.
+    bit_offset: 15
+    bit_size: 1
+  - name: GCM_CCMPH
+    description: GCM_CCMPH.
+    bit_offset: 16
+    bit_size: 2
+  - name: ALGOMODE3
+    description: ALGOMODE.
+    bit_offset: 19
+    bit_size: 1
+  - name: NPBLB
+    description: Number of Padding Bytes in Last Block of payload.
+    bit_offset: 20
+    bit_size: 4
 fieldset/DMACR:
   description: DMA control register.
   fields:
-    - name: DIEN
-      description: DMA input enable.
-      bit_offset: 0
-      bit_size: 1
-    - name: DOEN
-      description: DMA output enable.
-      bit_offset: 1
-      bit_size: 1
+  - name: DIEN
+    description: DMA input enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DOEN
+    description: DMA output enable.
+    bit_offset: 1
+    bit_size: 1
 fieldset/IMSCR:
   description: interrupt mask set/clear register.
   fields:
-    - name: INIM
-      description: Input FIFO service interrupt mask.
-      bit_offset: 0
-      bit_size: 1
-    - name: OUTIM
-      description: Output FIFO service interrupt mask.
-      bit_offset: 1
-      bit_size: 1
+  - name: INIM
+    description: Input FIFO service interrupt mask.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTIM
+    description: Output FIFO service interrupt mask.
+    bit_offset: 1
+    bit_size: 1
 fieldset/MISR:
   description: masked interrupt status register.
   fields:
-    - name: INMIS
-      description: Input FIFO service masked interrupt status.
-      bit_offset: 0
-      bit_size: 1
-    - name: OUTMIS
-      description: Output FIFO service masked interrupt status.
-      bit_offset: 1
-      bit_size: 1
+  - name: INMIS
+    description: Input FIFO service masked interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTMIS
+    description: Output FIFO service masked interrupt status.
+    bit_offset: 1
+    bit_size: 1
 fieldset/RISR:
   description: raw interrupt status register.
   fields:
-    - name: INRIS
-      description: Input FIFO service raw interrupt status.
-      bit_offset: 0
-      bit_size: 1
-    - name: OUTRIS
-      description: Output FIFO service raw interrupt status.
-      bit_offset: 1
-      bit_size: 1
+  - name: INRIS
+    description: Input FIFO service raw interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: OUTRIS
+    description: Output FIFO service raw interrupt status.
+    bit_offset: 1
+    bit_size: 1
 fieldset/SR:
   description: status register.
   fields:
-    - name: IFEM
-      description: Input FIFO empty.
-      bit_offset: 0
-      bit_size: 1
-    - name: IFNF
-      description: Input FIFO not full.
-      bit_offset: 1
-      bit_size: 1
-    - name: OFNE
-      description: Output FIFO not empty.
-      bit_offset: 2
-      bit_size: 1
-    - name: OFFU
-      description: Output FIFO full.
-      bit_offset: 3
-      bit_size: 1
-    - name: BUSY
-      description: Busy bit.
-      bit_offset: 4
-      bit_size: 1
+  - name: IFEM
+    description: Input FIFO empty.
+    bit_offset: 0
+    bit_size: 1
+  - name: IFNF
+    description: Input FIFO not full.
+    bit_offset: 1
+    bit_size: 1
+  - name: OFNE
+    description: Output FIFO not empty.
+    bit_offset: 2
+    bit_size: 1
+  - name: OFFU
+    description: Output FIFO full.
+    bit_offset: 3
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 4
+    bit_size: 1
diff --git a/data/registers/opamp_h_v1.yaml b/data/registers/opamp_h_v1.yaml
index 29d0d77..fd2ef7c 100644
--- a/data/registers/opamp_h_v1.yaml
+++ b/data/registers/opamp_h_v1.yaml
@@ -142,39 +142,6 @@ enum/OPAHSM:
   - name: HighSpeed
     description: operational amplifier in high-speed mode
     value: 1
-enum/USERTRIM:
-  bit_size: 1
-  variants:
-  - name: Factory
-    description: \'factory\' trim code used
-    value: 0
-  - name: User
-    description: \'user\' trim code used
-    value: 1
-enum/VM_SEL:
-  bit_size: 2
-  variants:
-  - name: Inm0
-    description: INM0 connected to OPAMP_VINM input
-    value: 0
-  - name: Inm1
-    description: INM1 connected to OPAMP_VINM input
-    value: 1
-  - name: Pga
-    description: Feedback resistor is connected to the OPAMP_VINM input (PGA mode), Inverting input selection depends on the PGA_GAIN setting
-    value: 2
-  - name: Follower
-    description: opamp_out connected to OPAMP_VINM input (Follower mode)
-    value: 3
-enum/VP_SEL:
-  bit_size: 2
-  variants:
-  - name: Gpio
-    description: GPIO connected to OPAMPx_VINP
-    value: 0
-  - name: DacOut
-    description: dac_outx connected to OPAMPx_VINP
-    value: 1
 enum/PGA_GAIN:
   bit_size: 4
   variants:
@@ -226,3 +193,36 @@ enum/PGA_GAIN:
   - name: Gain16InvGainNeg15_InputVINM0FilteringVINM1
     description: Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias, INM1 node for filtering
     value: 15
+enum/USERTRIM:
+  bit_size: 1
+  variants:
+  - name: Factory
+    description: \'factory\' trim code used
+    value: 0
+  - name: User
+    description: \'user\' trim code used
+    value: 1
+enum/VM_SEL:
+  bit_size: 2
+  variants:
+  - name: Inm0
+    description: INM0 connected to OPAMP_VINM input
+    value: 0
+  - name: Inm1
+    description: INM1 connected to OPAMP_VINM input
+    value: 1
+  - name: Pga
+    description: Feedback resistor is connected to the OPAMP_VINM input (PGA mode), Inverting input selection depends on the PGA_GAIN setting
+    value: 2
+  - name: Follower
+    description: opamp_out connected to OPAMP_VINM input (Follower mode)
+    value: 3
+enum/VP_SEL:
+  bit_size: 2
+  variants:
+  - name: Gpio
+    description: GPIO connected to OPAMPx_VINP
+    value: 0
+  - name: DacOut
+    description: dac_outx connected to OPAMPx_VINP
+    value: 1
diff --git a/data/registers/opamp_h_v2.yaml b/data/registers/opamp_h_v2.yaml
index cef2365..18d824f 100644
--- a/data/registers/opamp_h_v2.yaml
+++ b/data/registers/opamp_h_v2.yaml
@@ -142,42 +142,6 @@ enum/OPAHSM:
   - name: HighSpeed
     description: operational amplifier in high-speed mode
     value: 1
-enum/USERTRIM:
-  bit_size: 1
-  variants:
-  - name: Factory
-    description: \'factory\' trim code used
-    value: 0
-  - name: User
-    description: \'user\' trim code used
-    value: 1
-enum/VM_SEL:
-  bit_size: 2
-  variants:
-  - name: Inm0
-    description: INM0 connected to OPAMP_VINM input
-    value: 0
-  - name: Inm1
-    description: INM1 connected to OPAMP_VINM input
-    value: 1
-  - name: Pga
-    description: Feedback resistor is connected to the OPAMP_VINM input (PGA mode), Inverting input selection depends on the PGA_GAIN setting
-    value: 2
-  - name: Follower
-    description: opamp_out connected to OPAMP_VINM input (Follower mode)
-    value: 3
-enum/VP_SEL:
-  bit_size: 2
-  variants:
-  - name: GpioInp0
-    description: GPIO INP0 connected to OPAMP_VINP
-    value: 0
-  - name: DacOut
-    description: dac_outx connected to OPAMPx_VINP
-    value: 1
-  - name: GpioInp2
-    description: GPIO INP2 is connected to OPAMP_VINP
-    value: 2
 enum/PGA_GAIN:
   bit_size: 4
   variants:
@@ -229,3 +193,39 @@ enum/PGA_GAIN:
   - name: Gain16InvGainNeg15_InputVINM0FilteringVINM1
     description: Inverting gain=-15/ Non-inverting gain =16 with INM0 node for input or bias, INM1 node for filtering
     value: 15
+enum/USERTRIM:
+  bit_size: 1
+  variants:
+  - name: Factory
+    description: \'factory\' trim code used
+    value: 0
+  - name: User
+    description: \'user\' trim code used
+    value: 1
+enum/VM_SEL:
+  bit_size: 2
+  variants:
+  - name: Inm0
+    description: INM0 connected to OPAMP_VINM input
+    value: 0
+  - name: Inm1
+    description: INM1 connected to OPAMP_VINM input
+    value: 1
+  - name: Pga
+    description: Feedback resistor is connected to the OPAMP_VINM input (PGA mode), Inverting input selection depends on the PGA_GAIN setting
+    value: 2
+  - name: Follower
+    description: opamp_out connected to OPAMP_VINM input (Follower mode)
+    value: 3
+enum/VP_SEL:
+  bit_size: 2
+  variants:
+  - name: GpioInp0
+    description: GPIO INP0 connected to OPAMP_VINP
+    value: 0
+  - name: DacOut
+    description: dac_outx connected to OPAMPx_VINP
+    value: 1
+  - name: GpioInp2
+    description: GPIO INP2 is connected to OPAMP_VINP
+    value: 2