Merge pull request #69 from embassy-rs/f4-pwr

Add F4 PWR

data/registers/pwr_f4.yaml

@@ -0,0 +1,130 @@
+---
+block/PWR:
+  description: Power control
+  items:
+    - name: CR
+      description: power control register
+      byte_offset: 0
+      fieldset: CR
+    - name: CSR
+      description: power control/status register
+      byte_offset: 4
+      fieldset: CSR
+fieldset/CR:
+  description: power control register
+  fields:
+    - name: LPDS
+      description: Low-power deep sleep
+      bit_offset: 0
+      bit_size: 1
+    - name: PDDS
+      description: Power down deepsleep
+      bit_offset: 1
+      bit_size: 1
+    - name: CWUF
+      description: Clear wakeup flag
+      bit_offset: 2
+      bit_size: 1
+    - name: CSBF
+      description: Clear standby flag
+      bit_offset: 3
+      bit_size: 1
+    - name: PVDE
+      description: Power voltage detector enable
+      bit_offset: 4
+      bit_size: 1
+    - name: PLS
+      description: PVD level selection
+      bit_offset: 5
+      bit_size: 3
+    - name: DBP
+      description: Disable backup domain write protection
+      bit_offset: 8
+      bit_size: 1
+    - name: FPDS
+      description: Flash power down in Stop mode
+      bit_offset: 9
+      bit_size: 1
+    - name: LPLVDS
+      description: Low-Power Regulator Low Voltage in deepsleep
+      bit_offset: 10
+      bit_size: 1
+    - name: MRLVDS
+      description: Main regulator low voltage in deepsleep mode
+      bit_offset: 11
+      bit_size: 1
+    - name: ADCDC1
+      description: ADCDC1
+      bit_offset: 13
+      bit_size: 1
+    - name: VOS
+      description: Regulator voltage scaling output selection
+      bit_offset: 14
+      bit_size: 2
+    - name: ODEN
+      description: Over-drive enable
+      bit_offset: 16
+      bit_size: 1
+    - name: ODSWEN
+      description: Over-drive switching enabled
+      bit_offset: 17
+      bit_size: 1
+    - name: UDEN
+      description: Under-drive enable in stop mode
+      bit_offset: 18
+      bit_size: 2
+    - name: FMSSR
+      description: Flash Memory Stop while System Run
+      bit_offset: 20
+      bit_size: 1
+    - name: FISSR
+      description: Flash Interface Stop while System Run
+      bit_offset: 21
+      bit_size: 1
+fieldset/CSR:
+  description: power control/status register
+  fields:
+    - name: WUF
+      description: Wakeup flag
+      bit_offset: 0
+      bit_size: 1
+    - name: SBF
+      description: Standby flag
+      bit_offset: 1
+      bit_size: 1
+    - name: PVDO
+      description: PVD output
+      bit_offset: 2
+      bit_size: 1
+    - name: BRR
+      description: Backup regulator ready
+      bit_offset: 3
+      bit_size: 1
+    - name: EWUP2
+      description: Enable WKUP2 pin
+      bit_offset: 7
+      bit_size: 1
+    - name: EWUP
+      description: Enable WKUP pin
+      bit_offset: 8
+      bit_size: 1
+    - name: BRE
+      description: Backup regulator enable
+      bit_offset: 9
+      bit_size: 1
+    - name: VOSRDY
+      description: Regulator voltage scaling output selection ready bit
+      bit_offset: 14
+      bit_size: 1
+    - name: ODRDY
+      description: Over-drive mode ready
+      bit_offset: 16
+      bit_size: 1
+    - name: ODSWRDY
+      description: Over-drive mode switching ready
+      bit_offset: 17
+      bit_size: 1
+    - name: UDRDY
+      description: Under-drive ready flag
+      bit_offset: 18
+      bit_size: 2

parse.py

@@ -331,6 +331,7 @@ perimap = [
     ('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
     ('STM32H7(42|43|53|50).*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
     ('.*:STM32H7_pwr_v1_0', 'pwr_h7smps/PWR'),
+    ('.*:STM32F4_pwr_v1_0', 'pwr_f4/PWR'),
     ('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
     ('.*:STM32F0_flash_v1_0', 'flash_f0/FLASH'),
     ('.*:STM32F4_flash_v1_0', 'flash_f4/FLASH'),
@@ -789,6 +790,18 @@ def parse_chips():
                     crs_peri['block'] = block
                 peris['CRS'] = crs_peri
 
+            # PWR is not in some XMLs
+            if 'PWR' not in peris:
+                if addr := defines.get('PWR_BASE'):
+                    kind = 'PWR:' + chip_name[:7] + '_pwr_v1_0'
+                    pwr_peri = OrderedDict({
+                        'address': addr,
+                        'kind': kind,
+                    })
+                    if block := match_peri(kind):
+                        pwr_peri['block'] = block
+                    peris['PWR'] = pwr_peri
+
             core['peripherals'] = peris
 
             if 'block' in core['peripherals']['RCC']: