From 2cd7632fc9cc523e6ea6a1218c4c688f383effe6 Mon Sep 17 00:00:00 2001 From: Nicolas Viennot Date: Mon, 14 Mar 2022 21:46:02 -0400 Subject: [PATCH] Add SPI modules for F1 family --- stm32data/__main__.py | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index d2b3ab2..bedb622 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -178,6 +178,7 @@ perimap = [ ('STM32WL5.*:RCC:.*', ('rcc', 'wl5', 'RCC')), ('STM32WLE.*:RCC:.*', ('rcc', 'wle', 'RCC')), + ('STM32F1.*:SPI[1234]:.*', ('spi', 'f1', 'SPI')), ('STM32F3.*:SPI[1234]:.*', ('spi', 'v2', 'SPI')), ('STM32F1.*:AFIO:.*', ('afio', 'f1', 'AFIO')),