add comparators to G0 and G4

This commit is contained in:
Adin Ackerman 2024-01-30 15:57:55 -08:00
parent 82bbb78206
commit 675a67c3af
3 changed files with 192 additions and 0 deletions

103
data/registers/comp_v1.yaml Normal file
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@ -0,0 +1,103 @@
block/COMP:
description: Comparator v1. (RM0444 18)
items:
- name: CSR
description: Comparator control and status register.
byte_offset: 0
fieldset: CSR
fieldset/CSR:
description: Comparator control and status register.
fields:
- name: EN
description: COMP enable bit.
bit_offset: 0
bit_size: 1
- name: INMSEL
description: Comparator signal selector for inverting input INM.
bit_offset: 4
bit_size: 4
- name: INPSEL
description: Comparator signal selector for non-inverting input INP.
bit_offset: 8
bit_size: 2
- name: WINMODE
description: Comparator non-inverting input selector for window mode.
bit_offset: 11
bit_size: 1
- name: WINOUT
description: Comparator output selector.
bit_offset: 14
bit_size: 1
- name: POLARITY
description: Comparator polarity selector.
bit_offset: 15
bit_size: 1
enum: POLARITY
- name: HYST
description: Comparator hysteresis selector.
bit_offset: 16
bit_size: 2
enum: HYST
- name: PWRMODE
description: Comparator power mode selector.
bit_offset: 18
bit_size: 2
enum: PWRMODE
- name: BLANKSEL
description: Comparator blanking source selector.
bit_offset: 20
bit_size: 5
enum: BLANKSEL
- name: VALUE_DO_NOT_SET
description: Comparator output status. (READ ONLY)
bit_offset: 30
bit_size: 1
- name: LOCK
description: CSR register lock.
bit_offset: 31
bit_size: 1
enum/POLARITY:
bit_size: 1
variants:
- name: NonInverted
value: 0
- name: Inverted
value: 1
enum/HYST:
bit_size: 2
variants:
- name: None
value: 0
- name: Low
value: 1
- name: Medium
value: 2
- name: High
value: 3
enum/PWRMODE:
bit_size: 2
variants:
- name: HighSpeed
value: 0
- name: MediumSpeed
value: 1
enum/BLANKSEL:
bit_size: 5
variants:
- name: None
value: 0
- name: Tim1Oc4
description: TIM1 OC4
value: 1
- name: Tim1Oc5
description: TIM1 OC5
value: 2
- name: Tim2Oc3
description: TIM2 OC3
value: 4
- name: Tim3Oc3
description: TIM3 OC3
value: 8
- name: Tim15Oc2
description: TIM15 OC2
value: 16

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@ -0,0 +1,87 @@
block/COMP:
description: Comparator v2. (RM0440 24)
items:
- name: CSR
description: Comparator control and status register.
byte_offset: 0
fieldset: CSR
fieldset/CSR:
description: Comparator control and status register.
fields:
- name: EN
description: COMP enable bit.
bit_offset: 0
bit_size: 1
- name: INMSEL
description: Comparator signal selector for inverting input INM. (RM0440 24.3.2 Table 197)
bit_offset: 4
bit_size: 3
- name: INPSEL
description: Comparator signal selector for non-inverting input INP. (RM0440 24.3.2 Table 196)
bit_offset: 8
bit_size: 1
- name: POLARITY
description: Comparator polarity selector.
bit_offset: 15
bit_size: 1
enum: POLARITY
- name: HYST
description: Comparator hysteresis selector.
bit_offset: 16
bit_size: 3
enum: HYST
- name: BLANKSEL
description: Comparator blanking source selector. (RM0440 24.3.6 Table 198)
bit_offset: 19
bit_size: 3
- name: BRGEN
description: Vrefint resistor bridge enable. (RM0440 24.6)
bit_offset: 22
bit_size: 1
- name: SCALEN
description: Vrefint scaled input enable. (RM0440 24.6)
bit_offset: 23
bit_size: 1
- name: VALUE_DO_NOT_SET
description: Comparator output status. (READ ONLY)
bit_offset: 30
bit_size: 1
- name: LOCK
description: CSR register lock.
bit_offset: 31
bit_size: 1
enum/POLARITY:
bit_size: 1
variants:
- name: NonInverted
description: Non-inverted polarity
value: 0
- name: Inverted
description: Inverted polarity
value: 1
enum/HYST:
bit_size: 3
variants:
- name: None
value: 0
- name: Hyst10m
description: 10mV hysteresis
value: 1
- name: Hyst20m
description: 20mV hysteresis
value: 2
- name: Hyst30m
description: 30mV hysteresis
value: 3
- name: Hyst40m
description: 40mV hysteresis
value: 4
- name: Hyst50m
description: 50mV hysteresis
value: 5
- name: Hyst60m
description: 60mV hysteresis
value: 6
- name: Hyst70m
description: 70mV hysteresis
value: 7

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@ -523,6 +523,8 @@ impl PeriMatcher {
("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")), ("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")),
("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")), ("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")),
("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")), ("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")),
("STM32G0.*1.*:.*:COMP:.*", ("comp", "v1", "COMP")),
("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")),
]; ];
Self { Self {