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rcc: unify rcc_f0, rcc_f0x0

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Dario Nieuwenhuis 2022-02-14 00:24:53 +01:00
parent 3d6895a77f
commit 66ecaf8b98
3 changed files with 3 additions and 1157 deletions
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6
data/registers/rcc_f0.yaml
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@ -1086,13 +1086,13 @@ enum/PLLSRC:
description: HSI divided by 2 selected as PLL input clock
value: 0
- name: HSI_Div_PREDIV
description: HSI divided by PREDIV selected as PLL input clock
description: NOT ALLOWED IN F0x0 - HSI divided by PREDIV selected as PLL input clock
value: 1
- name: HSE_Div_PREDIV
description: HSE divided by PREDIV selected as PLL input clock
value: 2
- name: HSI48_Div_PREDIV
description: HSI48 divided by PREDIV selected as PLL input clock
description: NOT ALLOWED IN F0x0 - HSI48 divided by PREDIV selected as PLL input clock
value: 3
enum/PLLXTPRE:
bit_size: 1
@ -1242,7 +1242,7 @@ enum/USBSW:
bit_size: 1
variants:
- name: HSI48
description: HSI48 selected as USB clock source
description: NOT ALLOWED IN F0x0 - HSI48 selected as USB clock source
value: 0
- name: PLLCLK
description: PLL clock selected as USB clock source

1153
data/registers/rcc_f0x0.yaml
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File diff suppressed because it is too large Load Diff

1
stm32data/__main__.py
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@ -157,7 +157,6 @@ perimap = [
('.*:USB_OTG_FS:otgfs1_v1_2', ('otgfs', 'v1', 'OTG_FS')),
('.*:USB_OTG_HS:otghs1_v1_1', ('otghs', 'v1', 'OTG_HS')),
('STM32F0.0.*:RCC:.*', ('rcc', 'f0x0', 'RCC')),
('STM32F0.*:RCC:.*', ('rcc', 'f0', 'RCC')),
('STM32F1.*:RCC:.*', ('rcc', 'f1', 'RCC')),
('STM32F2.*:RCC:.*', ('rcc', 'f2', 'RCC')),