rcc: unify rcc_f0, rcc_f0x0

data/registers/rcc_f0.yaml

@@ -1086,13 +1086,13 @@ enum/PLLSRC:
       description: HSI divided by 2 selected as PLL input clock
       value: 0
     - name: HSI_Div_PREDIV
-      description: HSI divided by PREDIV selected as PLL input clock
+      description: NOT ALLOWED IN F0x0 - HSI divided by PREDIV selected as PLL input clock
       value: 1
     - name: HSE_Div_PREDIV
       description: HSE divided by PREDIV selected as PLL input clock
       value: 2
     - name: HSI48_Div_PREDIV
-      description: HSI48 divided by PREDIV selected as PLL input clock
+      description: NOT ALLOWED IN F0x0 - HSI48 divided by PREDIV selected as PLL input clock
       value: 3
 enum/PLLXTPRE:
   bit_size: 1
@@ -1242,7 +1242,7 @@ enum/USBSW:
   bit_size: 1
   variants:
     - name: HSI48
-      description: HSI48 selected as USB clock source
+      description: NOT ALLOWED IN F0x0 - HSI48 selected as USB clock source
       value: 0
     - name: PLLCLK
       description: PLL clock selected as USB clock source