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usart: merge lpuart, add over8, add presc.

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This commit is contained in:
Dario Nieuwenhuis 2023-05-02 02:43:43 +02:00
parent e19240e3d3
commit 64846c91ba
6 changed files with 1249 additions and 976 deletions
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454
data/registers/lpuart_v1.yaml
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@ -1,454 +0,0 @@
---
block/LPUART:
description: Lower power Universal asynchronous receiver transmitter
items:
- name: CR1
description: Control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: Control register 2
byte_offset: 4
fieldset: CR2
- name: CR3
description: Control register 3
byte_offset: 8
fieldset: CR3
- name: BRR
description: Baud rate register
byte_offset: 12
fieldset: BRR
- name: RQR
description: Request register
byte_offset: 24
access: Write
fieldset: RQR
- name: ISR
description: Interrupt & status register
byte_offset: 28
access: Read
fieldset: ISR
- name: ICR
description: Interrupt flag clear register
byte_offset: 32
access: Write
fieldset: ICR
- name: RDR
description: Receive data register
byte_offset: 36
access: Read
fieldset: RDR
- name: TDR
description: Transmit data register
byte_offset: 40
fieldset: TDR
fieldset/BRR:
description: Baud rate register
fields:
- name: BRR
description: BRR
bit_offset: 0
bit_size: 20
fieldset/CR1:
description: Control register 1
fields:
- name: UE
description: USART enable
bit_offset: 0
bit_size: 1
- name: UESM
description: USART enable in Stop mode
bit_offset: 1
bit_size: 1
- name: RE
description: Receiver enable
bit_offset: 2
bit_size: 1
- name: TE
description: Transmitter enable
bit_offset: 3
bit_size: 1
- name: IDLEIE
description: IDLE interrupt enable
bit_offset: 4
bit_size: 1
- name: RXNEIE
description: RXNE interrupt enable
bit_offset: 5
bit_size: 1
- name: TCIE
description: Transmission complete interrupt enable
bit_offset: 6
bit_size: 1
- name: TXEIE
description: interrupt enable
bit_offset: 7
bit_size: 1
- name: PEIE
description: PE interrupt enable
bit_offset: 8
bit_size: 1
- name: PS
description: Parity selection
bit_offset: 9
bit_size: 1
enum: PS
- name: PCE
description: Parity control enable
bit_offset: 10
bit_size: 1
- name: WAKE
description: Receiver wakeup method
bit_offset: 11
bit_size: 1
enum: WAKE
- name: M0
description: Word length
bit_offset: 12
bit_size: 1
enum: M0
- name: MME
description: Mute mode enable
bit_offset: 13
bit_size: 1
- name: CMIE
description: Character match interrupt enable
bit_offset: 14
bit_size: 1
- name: DEDT
description: Driver Enable de-assertion time
bit_offset: 16
bit_size: 5
- name: DEAT
description: Driver Enable assertion time
bit_offset: 21
bit_size: 5
- name: M1
description: Word length
bit_offset: 28
bit_size: 1
enum: M1
fieldset/CR2:
description: Control register 2
fields:
- name: ADDM7
description: 7-bit Address Detection/4-bit Address Detection
bit_offset: 4
bit_size: 1
enum: ADDM7
- name: STOP
description: STOP bits
bit_offset: 12
bit_size: 2
enum: STOP
- name: SWAP
description: Swap TX/RX pins
bit_offset: 15
bit_size: 1
- name: RXINV
description: RX pin active level inversion
bit_offset: 16
bit_size: 1
- name: TXINV
description: TX pin active level inversion
bit_offset: 17
bit_size: 1
- name: DATAINV
description: Binary data inversion
bit_offset: 18
bit_size: 1
- name: MSBFIRST
description: Most significant bit first
bit_offset: 19
bit_size: 1
enum: MSBFIRST
- name: ADD
description: Address of the USART node
bit_offset: 24
bit_size: 8
fieldset/CR3:
description: Control register 3
fields:
- name: EIE
description: Error interrupt enable
bit_offset: 0
bit_size: 1
- name: HDSEL
description: Half-duplex selection
bit_offset: 3
bit_size: 1
- name: DMAR
description: DMA enable receiver
bit_offset: 6
bit_size: 1
- name: DMAT
description: DMA enable transmitter
bit_offset: 7
bit_size: 1
- name: RTSE
description: RTS enable
bit_offset: 8
bit_size: 1
- name: CTSE
description: CTS enable
bit_offset: 9
bit_size: 1
- name: CTSIE
description: CTS interrupt enable
bit_offset: 10
bit_size: 1
- name: OVRDIS
description: Overrun Disable
bit_offset: 12
bit_size: 1
- name: DDRE
description: DMA Disable on Reception Error
bit_offset: 13
bit_size: 1
- name: DEM
description: Driver enable mode
bit_offset: 14
bit_size: 1
- name: DEP
description: Driver enable polarity selection
bit_offset: 15
bit_size: 1
enum: DEP
- name: WUS
description: Wakeup from Stop mode interrupt flag selection
bit_offset: 20
bit_size: 2
enum: WUS
- name: WUFIE
description: Wakeup from Stop mode interrupt enable
bit_offset: 22
bit_size: 1
fieldset/ICR:
description: Interrupt flag clear register
fields:
- name: PECF
description: Parity error clear flag
bit_offset: 0
bit_size: 1
- name: FECF
description: Framing error clear flag
bit_offset: 1
bit_size: 1
- name: NCF
description: Noise detected clear flag
bit_offset: 2
bit_size: 1
- name: ORECF
description: Overrun error clear flag
bit_offset: 3
bit_size: 1
- name: IDLECF
description: Idle line detected clear flag
bit_offset: 4
bit_size: 1
- name: TCCF
description: Transmission complete clear flag
bit_offset: 6
bit_size: 1
- name: CTSCF
description: CTS clear flag
bit_offset: 9
bit_size: 1
- name: CMCF
description: Character match clear flag
bit_offset: 17
bit_size: 1
- name: WUCF
description: Wakeup from Stop mode clear flag
bit_offset: 20
bit_size: 1
fieldset/ISR:
description: Interrupt & status register
fields:
- name: PE
description: PE
bit_offset: 0
bit_size: 1
- name: FE
description: FE
bit_offset: 1
bit_size: 1
- name: NE
description: NE
bit_offset: 2
bit_size: 1
- name: ORE
description: ORE
bit_offset: 3
bit_size: 1
- name: IDLE
description: IDLE
bit_offset: 4
bit_size: 1
- name: RXNE
description: RXNE
bit_offset: 5
bit_size: 1
- name: TC
description: TC
bit_offset: 6
bit_size: 1
- name: TXE
description: TXE
bit_offset: 7
bit_size: 1
- name: CTSIF
description: CTSIF
bit_offset: 9
bit_size: 1
- name: CTS
description: CTS
bit_offset: 10
bit_size: 1
- name: BUSY
description: BUSY
bit_offset: 16
bit_size: 1
- name: CMF
description: CMF
bit_offset: 17
bit_size: 1
- name: SBKF
description: SBKF
bit_offset: 18
bit_size: 1
- name: RWU
description: RWU
bit_offset: 19
bit_size: 1
- name: WUF
description: WUF
bit_offset: 20
bit_size: 1
- name: TEACK
description: TEACK
bit_offset: 21
bit_size: 1
- name: REACK
description: REACK
bit_offset: 22
bit_size: 1
fieldset/RDR:
description: Receive data register
fields:
- name: RDR
description: Receive data value
bit_offset: 0
bit_size: 9
fieldset/RQR:
description: Request register
fields:
- name: SBKRQ
description: Send break request
bit_offset: 1
bit_size: 1
- name: MMRQ
description: Mute mode request
bit_offset: 2
bit_size: 1
- name: RXFRQ
description: Receive data flush request
bit_offset: 3
bit_size: 1
fieldset/TDR:
description: Transmit data register
fields:
- name: TDR
description: Transmit data value
bit_offset: 0
bit_size: 9
enum/ADDM7:
bit_size: 1
variants:
- name: Bit4
description: 4-bit address detection
value: 0
- name: Bit7
description: 7-bit address detection
value: 1
enum/DEP:
bit_size: 1
variants:
- name: High
description: DE signal is active high
value: 0
- name: Low
description: DE signal is active low
value: 1
enum/M0:
bit_size: 1
variants:
- name: Bit8
description: "1 start bit, 8 data bits, n stop bits"
value: 0
- name: Bit9
description: "1 start bit, 9 data bits, n stop bits"
value: 1
enum/M1:
bit_size: 1
variants:
- name: M0
description: Use M0 to set the data bits
value: 0
- name: Bit7
description: "1 start bit, 7 data bits, n stop bits"
value: 1
enum/MSBFIRST:
bit_size: 1
variants:
- name: LSB
description: "data is transmitted/received with data bit 0 first, following the start bit"
value: 0
- name: MSB
description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"
value: 1
enum/PS:
bit_size: 1
variants:
- name: Even
description: Even parity
value: 0
- name: Odd
description: Odd parity
value: 1
enum/STOP:
bit_size: 2
variants:
- name: Stop1
description: 1 stop bit
value: 0
- name: Stop0p5
description: 0.5 stop bit
value: 1
- name: Stop2
description: 2 stop bit
value: 2
- name: Stop1p5
description: 1.5 stop bit
value: 3
enum/WAKE:
bit_size: 1
variants:
- name: Idle
description: Idle line
value: 0
- name: Address
description: Address mask
value: 1
enum/WUS:
bit_size: 2
variants:
- name: Address
description: WUF active on address match
value: 0
- name: Start
description: WuF active on Start bit detection
value: 2
- name: RXNE
description: WUF active on RXNE
value: 3

10
data/registers/usart_v1.yaml
View File

@ -45,14 +45,10 @@ block/USART:
fieldset/BRR:
description: Baud rate register
fields:
- name: DIV_Fraction
description: fraction of USARTDIV
- name: BRR
description: USARTDIV
bit_offset: 0
bit_size: 4
- name: DIV_Mantissa
description: mantissa of USARTDIV
bit_offset: 4
bit_size: 12
bit_size: 16
fieldset/CR1:
description: Control register 1
fields:

463
data/registers/usart_v2.yaml
View File

@ -1,74 +1,66 @@
---
block/USART:
description: Universal synchronous asynchronous receiver transmitter
block/UART:
description: Universal asynchronous receiver transmitter
items:
- name: SR
description: Status register
byte_offset: 0
fieldset: SR
- name: DR
description: Data register
byte_offset: 4
fieldset: DR
- name: BRR
description: Baud rate register
byte_offset: 8
fieldset: BRR
- name: CR1
description: Control register 1
byte_offset: 0
byte_offset: 12
fieldset: CR1
- name: CR2
description: Control register 2
byte_offset: 4
byte_offset: 16
fieldset: CR2
- name: CR3
description: Control register 3
byte_offset: 8
byte_offset: 20
fieldset: CR3
- name: BRR
description: Baud rate register
byte_offset: 12
fieldset: BRR
block/USART:
extends: UART
description: Universal synchronous asynchronous receiver transmitter
items:
- name: CR2
description: Control register 2
byte_offset: 16
fieldset: CR2_USART
- name: CR3
description: Control register 3
byte_offset: 20
fieldset: CR3_USART
- name: GTPR
description: Guard time and prescaler register
byte_offset: 16
fieldset: GTPR
- name: RTOR
description: Receiver timeout register
byte_offset: 20
fieldset: RTOR
- name: RQR
description: Request register
byte_offset: 24
access: Write
fieldset: RQR
- name: ISR
description: Interrupt & status register
byte_offset: 28
access: Read
fieldset: ISR
- name: ICR
description: Interrupt flag clear register
byte_offset: 32
access: Write
fieldset: ICR
- name: RDR
description: Receive data register
byte_offset: 36
access: Read
fieldset: DR
- name: TDR
description: Transmit data register
byte_offset: 40
access: Write
fieldset: DR
fieldset: GTPR
fieldset/BRR:
description: Baud rate register
fields:
- name: BRR
description: mantissa of USARTDIV
description: USARTDIV
bit_offset: 0
bit_size: 16
fieldset/CR1:
description: Control register 1
fields:
- name: UE
description: USART enable
- name: SBK
description: Send break
bit_offset: 0
bit_size: 1
- name: UESM
description: USART enable in Stop mode
- name: RWU
description: Receiver wakeup
bit_offset: 1
bit_size: 1
enum: RWU
- name: RE
description: Receiver enable
bit_offset: 2
@ -116,54 +108,22 @@ fieldset/CR1:
bit_offset: 12
bit_size: 1
enum: M0
- name: MME
description: Mute mode enable
- name: UE
description: USART enable
bit_offset: 13
bit_size: 1
- name: CMIE
description: Character match interrupt enable
bit_offset: 14
bit_size: 1
- name: OVER
- name: OVER8
description: Oversampling mode
bit_offset: 15
bit_size: 1
array:
len: 1
stride: 0
enum: OVER
- name: DEDT
description: Driver Enable deassertion time
bit_offset: 16
bit_size: 5
- name: DEAT
description: Driver Enable assertion time
bit_offset: 21
bit_size: 5
- name: RTOIE
description: Receiver timeout interrupt enable
bit_offset: 26
bit_size: 1
- name: EOBIE
description: End of Block interrupt enable
bit_offset: 27
bit_size: 1
- name: M1
description: Word length
bit_offset: 28
bit_size: 1
enum: M1
enum: OVER8
fieldset/CR2:
description: Control register 2
fields:
- name: ADDM
description: 7-bit Address Detection/4-bit Address Detection
bit_offset: 4
bit_size: 1
array:
len: 1
stride: 0
enum: ADDM
- name: ADD
description: Address of the USART node
bit_offset: 0
bit_size: 4
- name: LBDL
description: Line break detection length
bit_offset: 5
@ -173,6 +133,19 @@ fieldset/CR2:
description: LIN break detection interrupt enable
bit_offset: 6
bit_size: 1
- name: STOP
description: STOP bits
bit_offset: 12
bit_size: 2
enum: STOP
- name: LINEN
description: LIN mode enable
bit_offset: 14
bit_size: 1
fieldset/CR2_USART:
extends: CR2
description: Control register 2
fields:
- name: LBCL
description: Last bit clock pulse
bit_offset: 8
@ -191,53 +164,6 @@ fieldset/CR2:
description: Clock enable
bit_offset: 11
bit_size: 1
- name: STOP
description: STOP bits
bit_offset: 12
bit_size: 2
enum: STOP
- name: LINEN
description: LIN mode enable
bit_offset: 14
bit_size: 1
- name: SWAP
description: Swap TX/RX pins
bit_offset: 15
bit_size: 1
- name: RXINV
description: RX pin active level inversion
bit_offset: 16
bit_size: 1
- name: TXINV
description: TX pin active level inversion
bit_offset: 17
bit_size: 1
- name: DATAINV
description: Binary data inversion
bit_offset: 18
bit_size: 1
- name: MSBFIRST
description: Most significant bit first
bit_offset: 19
bit_size: 1
enum: MSBFIRST
- name: ABREN
description: Auto baud rate enable
bit_offset: 20
bit_size: 1
- name: ABRMOD
description: Auto baud rate mode
bit_offset: 21
bit_size: 2
enum: ABRMOD
- name: RTOEN
description: Receiver timeout enable
bit_offset: 23
bit_size: 1
- name: ADD
description: Address of the USART node
bit_offset: 24
bit_size: 8
fieldset/CR3:
description: Control register 3
fields:
@ -258,14 +184,6 @@ fieldset/CR3:
description: Half-duplex selection
bit_offset: 3
bit_size: 1
- name: NACK
description: Smartcard NACK enable
bit_offset: 4
bit_size: 1
- name: SCEN
description: Smartcard mode enable
bit_offset: 5
bit_size: 1
- name: DMAR
description: DMA enable receiver
bit_offset: 6
@ -274,6 +192,18 @@ fieldset/CR3:
description: DMA enable transmitter
bit_offset: 7
bit_size: 1
fieldset/CR3_USART:
extends: CR3
description: Control register 3
fields:
- name: NACK
description: Smartcard NACK enable
bit_offset: 4
bit_size: 1
- name: SCEN
description: Smartcard mode enable
bit_offset: 5
bit_size: 1
- name: RTSE
description: RTS enable
bit_offset: 8
@ -290,37 +220,6 @@ fieldset/CR3:
description: One sample bit method enable
bit_offset: 11
bit_size: 1
enum: ONEBIT
- name: OVRDIS
description: Overrun Disable
bit_offset: 12
bit_size: 1
- name: DDRE
description: DMA Disable on Reception Error
bit_offset: 13
bit_size: 1
- name: DEM
description: Driver enable mode
bit_offset: 14
bit_size: 1
- name: DEP
description: Driver enable polarity selection
bit_offset: 15
bit_size: 1
enum: DEP
- name: SCARCNT
description: Smartcard auto-retry count
bit_offset: 17
bit_size: 3
- name: WUS
description: Wakeup from Stop mode interrupt flag selection
bit_offset: 20
bit_size: 2
enum: WUS
- name: WUFIE
description: Wakeup from Stop mode interrupt enable
bit_offset: 22
bit_size: 1
fieldset/DR:
description: Data register
fields:
@ -339,59 +238,8 @@ fieldset/GTPR:
description: Guard time value
bit_offset: 8
bit_size: 8
fieldset/ICR:
description: Interrupt flag clear register
fields:
- name: PE
description: Parity error clear flag
bit_offset: 0
bit_size: 1
- name: FE
description: Framing error clear flag
bit_offset: 1
bit_size: 1
- name: NE
description: Noise error clear flag
bit_offset: 2
bit_size: 1
- name: ORE
description: Overrun error clear flag
bit_offset: 3
bit_size: 1
- name: IDLE
description: Idle line detected clear flag
bit_offset: 4
bit_size: 1
- name: TC
description: Transmission complete clear flag
bit_offset: 6
bit_size: 1
- name: LBD
description: LIN break detection clear flag
bit_offset: 8
bit_size: 1
- name: CTS
description: CTS clear flag
bit_offset: 9
bit_size: 1
- name: RTOF
description: Receiver timeout clear flag
bit_offset: 11
bit_size: 1
- name: EOBF
description: End of block clear flag
bit_offset: 12
bit_size: 1
- name: CMF
description: Character match clear flag
bit_offset: 17
bit_size: 1
- name: WUF
description: Wakeup from Stop mode clear flag
bit_offset: 20
bit_size: 1
fieldset/ISR:
description: Interrupt & status register
fieldset/SR:
description: Status register
fields:
- name: PE
description: Parity error
@ -429,117 +277,14 @@ fieldset/ISR:
description: LIN break detection flag
bit_offset: 8
bit_size: 1
- name: CTSIF
description: CTS interrupt flag
bit_offset: 9
bit_size: 1
fieldset/SR_USART:
extends: SR
description: Status register
fields:
- name: CTS
description: CTS flag
bit_offset: 10
bit_offset: 9
bit_size: 1
- name: RTOF
description: Receiver timeout
bit_offset: 11
bit_size: 1
- name: EOBF
description: End of block flag
bit_offset: 12
bit_size: 1
- name: ABRE
description: Auto baud rate error
bit_offset: 14
bit_size: 1
- name: ABRF
description: Auto baud rate flag
bit_offset: 15
bit_size: 1
- name: BUSY
description: Busy flag
bit_offset: 16
bit_size: 1
- name: CMF
description: character match flag
bit_offset: 17
bit_size: 1
- name: SBKF
description: Send break flag
bit_offset: 18
bit_size: 1
- name: RWU
description: Receiver wakeup from Mute mode
bit_offset: 19
bit_size: 1
enum: RWU
- name: WUF
description: Wakeup from Stop mode flag
bit_offset: 20
bit_size: 1
- name: TEACK
description: Transmit enable acknowledge flag
bit_offset: 21
bit_size: 1
- name: REACK
description: Receive enable acknowledge flag
bit_offset: 22
bit_size: 1
fieldset/RQR:
description: Request register
fields:
- name: ABRRQ
description: Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame.
bit_offset: 0
bit_size: 1
- name: SBKRQ
description: "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"
bit_offset: 1
bit_size: 1
- name: MMRQ
description: Mute mode request. Puts the USART in mute mode and sets the RWU flag.
bit_offset: 2
bit_size: 1
- name: RXFRQ
description: "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"
bit_offset: 3
bit_size: 1
- name: TXFRQ
description: Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data.
bit_offset: 4
bit_size: 1
fieldset/RTOR:
description: Receiver timeout register
fields:
- name: RTO
description: Receiver timeout value
bit_offset: 0
bit_size: 24
- name: BLEN
description: Block Length
bit_offset: 24
bit_size: 8
enum/ABRMOD:
bit_size: 2
variants:
- name: Start
description: Measurement of the start bit is used to detect the baud rate
value: 0
- name: Edge
description: Falling edge to falling edge measurement
value: 1
- name: Frame7F
description: "0x7F frame detection"
value: 2
- name: Frame55
description: "0x55 frame detection"
value: 3
enum/ADDM:
bit_size: 1
variants:
- name: Bit4
description: 4-bit address detection
value: 0
- name: Bit7
description: 7-bit address detection
value: 1
enum/CPHA:
bit_size: 1
variants:
@ -558,15 +303,6 @@ enum/CPOL:
- name: High
description: Steady high value on CK pin outside transmission window
value: 1
enum/DEP:
bit_size: 1
variants:
- name: High
description: DE signal is active high
value: 0
- name: Low
description: DE signal is active low
value: 1
enum/IRLP:
bit_size: 1
variants:
@ -594,34 +330,7 @@ enum/M0:
- name: Bit9
description: "1 start bit, 9 data bits, n stop bits"
value: 1
enum/M1:
bit_size: 1
variants:
- name: M0
description: Use M0 to set the data bits
value: 0
- name: Bit7
description: "1 start bit, 7 data bits, n stop bits"
value: 1
enum/MSBFIRST:
bit_size: 1
variants:
- name: LSB
description: "data is transmitted/received with data bit 0 first, following the start bit"
value: 0
- name: MSB
description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"
value: 1
enum/ONEBIT:
bit_size: 1
variants:
- name: Sample3
description: Three sample bit method
value: 0
- name: Sample1
description: One sample bit method
value: 1
enum/OVER:
enum/OVER8:
bit_size: 1
variants:
- name: Oversampling16
@ -655,13 +364,13 @@ enum/STOP:
description: 1 stop bit
value: 0
- name: Stop0p5
description: 0.5 stop bit
description: 0.5 stop bits
value: 1
- name: Stop2
description: 2 stop bit
description: 2 stop bits
value: 2
- name: Stop1p5
description: 1.5 stop bit
description: 1.5 stop bits
value: 3
enum/WAKE:
bit_size: 1
@ -672,15 +381,3 @@ enum/WAKE:
- name: AddressMark
description: USART wakeup on address mark
value: 1
enum/WUS:
bit_size: 2
variants:
- name: Address
description: WUF active on address match
value: 0
- name: Start
description: WuF active on Start bit detection
value: 2
- name: RXNE
description: WUF active on RXNE
value: 3

441
data/registers/lpuart_v2.yaml → data/registers/usart_v3.yaml
View File

@ -1,6 +1,58 @@
---
block/USART:
description: Universal synchronous asynchronous receiver transmitter
items:
- name: CR1
description: Control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: Control register 2
byte_offset: 4
fieldset: CR2
- name: CR3
description: Control register 3
byte_offset: 8
fieldset: CR3
- name: BRR
description: Baud rate register
byte_offset: 12
fieldset: BRR
- name: GTPR
description: Guard time and prescaler register
byte_offset: 16
fieldset: GTPR
- name: RTOR
description: Receiver timeout register
byte_offset: 20
fieldset: RTOR
- name: RQR
description: Request register
byte_offset: 24
access: Write
fieldset: RQR
- name: ISR
description: Interrupt & status register
byte_offset: 28
access: Read
fieldset: ISR
- name: ICR
description: Interrupt flag clear register
byte_offset: 32
access: Write
fieldset: ICR
- name: RDR
description: Receive data register
byte_offset: 36
access: Read
fieldset: DR
- name: TDR
description: Transmit data register
byte_offset: 40
access: Write
fieldset: DR
block/LPUART:
description: Lower power Universal asynchronous receiver transmitter
description: Low-power Universal synchronous asynchronous receiver transmitter
items:
- name: CR1
description: Control register 1
@ -37,22 +89,19 @@ block/LPUART:
description: Receive data register
byte_offset: 36
access: Read
fieldset: RDR
fieldset: DR
- name: TDR
description: Transmit data register
byte_offset: 40
fieldset: TDR
- name: PRESC
description: Prescaler register
byte_offset: 44
fieldset: PRESC
access: Write
fieldset: DR
fieldset/BRR:
description: Baud rate register
fields:
- name: BRR
description: BRR
description: USARTDIV
bit_offset: 0
bit_size: 20
bit_size: 16
fieldset/CR1:
description: Control register 1
fields:
@ -85,7 +134,7 @@ fieldset/CR1:
bit_offset: 6
bit_size: 1
- name: TXEIE
description: interrupt enable
description: TXE interrupt enable
bit_offset: 7
bit_size: 1
- name: PEIE
@ -119,44 +168,76 @@ fieldset/CR1:
description: Character match interrupt enable
bit_offset: 14
bit_size: 1
- name: OVER8
description: Oversampling mode
bit_offset: 15
bit_size: 1
enum: OVER8
- name: DEDT
description: Driver Enable de-assertion time
description: Driver Enable deassertion time
bit_offset: 16
bit_size: 5
- name: DEAT
description: Driver Enable assertion time
bit_offset: 21
bit_size: 5
- name: RTOIE
description: Receiver timeout interrupt enable
bit_offset: 26
bit_size: 1
- name: EOBIE
description: End of Block interrupt enable
bit_offset: 27
bit_size: 1
- name: M1
description: Word length
bit_offset: 28
bit_size: 1
enum: M1
- name: FIFOEN
description: FIFO mode enable
bit_offset: 29
bit_size: 1
- name: TXFEIE
description: TXFIFO empty interrupt enable
bit_offset: 30
bit_size: 1
- name: RXFFIE
description: RXFIFO Full interrupt enable
bit_offset: 31
bit_size: 1
fieldset/CR2:
description: Control register 2
fields:
- name: ADDM7
- name: ADDM
description: 7-bit Address Detection/4-bit Address Detection
bit_offset: 4
bit_size: 1
enum: ADDM7
enum: ADDM
- name: LBDL
description: Line break detection length
bit_offset: 5
bit_size: 1
enum: LBDL
- name: LBDIE
description: LIN break detection interrupt enable
bit_offset: 6
bit_size: 1
- name: LBCL
description: Last bit clock pulse
bit_offset: 8
bit_size: 1
- name: CPHA
description: Clock phase
bit_offset: 9
bit_size: 1
enum: CPHA
- name: CPOL
description: Clock polarity
bit_offset: 10
bit_size: 1
enum: CPOL
- name: CLKEN
description: Clock enable
bit_offset: 11
bit_size: 1
- name: STOP
description: STOP bits
bit_offset: 12
bit_size: 2
enum: STOP
- name: LINEN
description: LIN mode enable
bit_offset: 14
bit_size: 1
- name: SWAP
description: Swap TX/RX pins
bit_offset: 15
@ -178,6 +259,19 @@ fieldset/CR2:
bit_offset: 19
bit_size: 1
enum: MSBFIRST
- name: ABREN
description: Auto baud rate enable
bit_offset: 20
bit_size: 1
- name: ABRMOD
description: Auto baud rate mode
bit_offset: 21
bit_size: 2
enum: ABRMOD
- name: RTOEN
description: Receiver timeout enable
bit_offset: 23
bit_size: 1
- name: ADD
description: Address of the USART node
bit_offset: 24
@ -189,10 +283,27 @@ fieldset/CR3:
description: Error interrupt enable
bit_offset: 0
bit_size: 1
- name: IREN
description: IrDA mode enable
bit_offset: 1
bit_size: 1
- name: IRLP
description: IrDA low-power
bit_offset: 2
bit_size: 1
enum: IRLP
- name: HDSEL
description: Half-duplex selection
bit_offset: 3
bit_size: 1
- name: NACK
description: Smartcard NACK enable
bit_offset: 4
bit_size: 1
- name: SCEN
description: Smartcard mode enable
bit_offset: 5
bit_size: 1
- name: DMAR
description: DMA enable receiver
bit_offset: 6
@ -213,6 +324,11 @@ fieldset/CR3:
description: CTS interrupt enable
bit_offset: 10
bit_size: 1
- name: ONEBIT
description: One sample bit method enable
bit_offset: 11
bit_size: 1
enum: ONEBIT
- name: OVRDIS
description: Overrun Disable
bit_offset: 12
@ -230,6 +346,10 @@ fieldset/CR3:
bit_offset: 15
bit_size: 1
enum: DEP
- name: SCARCNT
description: Smartcard auto-retry count
bit_offset: 17
bit_size: 3
- name: WUS
description: Wakeup from Stop mode interrupt flag selection
bit_offset: 20
@ -239,58 +359,72 @@ fieldset/CR3:
description: Wakeup from Stop mode interrupt enable
bit_offset: 22
bit_size: 1
- name: TXFTIE
description: TXFIFO threshold interrupt enable
bit_offset: 23
bit_size: 1
- name: RXFTCFG
description: Receive FIFO threshold configuration
bit_offset: 25
bit_size: 3
- name: RXFTIE
description: RXFIFO threshold interrupt enable
bit_offset: 28
bit_size: 1
- name: TXFTCFG
description: TXFIFO threshold configuration
bit_offset: 29
bit_size: 3
fieldset/DR:
description: Data register
fields:
- name: DR
description: Data value
bit_offset: 0
bit_size: 9
fieldset/GTPR:
description: Guard time and prescaler register
fields:
- name: PSC
description: Prescaler value
bit_offset: 0
bit_size: 8
- name: GT
description: Guard time value
bit_offset: 8
bit_size: 8
fieldset/ICR:
description: Interrupt flag clear register
fields:
- name: PECF
- name: PE
description: Parity error clear flag
bit_offset: 0
bit_size: 1
- name: FECF
- name: FE
description: Framing error clear flag
bit_offset: 1
bit_size: 1
- name: NCF
description: Noise detected clear flag
- name: NE
description: Noise error clear flag
bit_offset: 2
bit_size: 1
- name: ORECF
- name: ORE
description: Overrun error clear flag
bit_offset: 3
bit_size: 1
- name: IDLECF
- name: IDLE
description: Idle line detected clear flag
bit_offset: 4
bit_size: 1
- name: TCCF
- name: TC
description: Transmission complete clear flag
bit_offset: 6
bit_size: 1
- name: CTSCF
- name: LBD
description: LIN break detection clear flag
bit_offset: 8
bit_size: 1
- name: CTS
description: CTS clear flag
bit_offset: 9
bit_size: 1
- name: CMCF
- name: RTOF
description: Receiver timeout clear flag
bit_offset: 11
bit_size: 1
- name: EOBF
description: End of block clear flag
bit_offset: 12
bit_size: 1
- name: CMF
description: Character match clear flag
bit_offset: 17
bit_size: 1
- name: WUCF
- name: WUF
description: Wakeup from Stop mode clear flag
bit_offset: 20
bit_size: 1
@ -298,130 +432,144 @@ fieldset/ISR:
description: Interrupt & status register
fields:
- name: PE
description: PE
description: Parity error
bit_offset: 0
bit_size: 1
- name: FE
description: FE
description: Framing error
bit_offset: 1
bit_size: 1
- name: NE
description: NE
description: Noise error flag
bit_offset: 2
bit_size: 1
- name: ORE
description: ORE
description: Overrun error
bit_offset: 3
bit_size: 1
- name: IDLE
description: IDLE
description: Idle line detected
bit_offset: 4
bit_size: 1
- name: RXNE
description: RXNE
description: Read data register not empty
bit_offset: 5
bit_size: 1
- name: TC
description: TC
description: Transmission complete
bit_offset: 6
bit_size: 1
- name: TXE
description: TXE
description: Transmit data register empty
bit_offset: 7
bit_size: 1
- name: LBD
description: LIN break detection flag
bit_offset: 8
bit_size: 1
- name: CTSIF
description: CTSIF
description: CTS interrupt flag
bit_offset: 9
bit_size: 1
- name: CTS
description: CTS
description: CTS flag
bit_offset: 10
bit_size: 1
- name: RTOF
description: Receiver timeout
bit_offset: 11
bit_size: 1
- name: EOBF
description: End of block flag
bit_offset: 12
bit_size: 1
- name: ABRE
description: Auto baud rate error
bit_offset: 14
bit_size: 1
- name: ABRF
description: Auto baud rate flag
bit_offset: 15
bit_size: 1
- name: BUSY
description: BUSY
description: Busy flag
bit_offset: 16
bit_size: 1
- name: CMF
description: CMF
description: character match flag
bit_offset: 17
bit_size: 1
- name: SBKF
description: SBKF
description: Send break flag
bit_offset: 18
bit_size: 1
- name: RWU
description: RWU
description: Receiver wakeup from Mute mode
bit_offset: 19
bit_size: 1
enum: RWU
- name: WUF
description: WUF
description: Wakeup from Stop mode flag
bit_offset: 20
bit_size: 1
- name: TEACK
description: TEACK
description: Transmit enable acknowledge flag
bit_offset: 21
bit_size: 1
- name: REACK
description: REACK
description: Receive enable acknowledge flag
bit_offset: 22
bit_size: 1
- name: TXFE
description: TXFIFO Empty
bit_offset: 23
bit_size: 1
- name: RXFF
description: RXFIFO Full
bit_offset: 24
bit_size: 1
- name: RXFT
description: RXFIFO threshold flag
bit_offset: 26
bit_size: 1
- name: TXFT
description: TXFIFO threshold flag
bit_offset: 27
bit_size: 1
fieldset/PRESC:
description: Prescaler register
fields:
- name: PRESCALER
description: Clock prescaler
bit_offset: 0
bit_size: 4
fieldset/RDR:
description: Receive data register
fields:
- name: RDR
description: Receive data value
bit_offset: 0
bit_size: 9
fieldset/RQR:
description: Request register
fields:
- name: ABRRQ
description: Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame.
bit_offset: 0
bit_size: 1
- name: SBKRQ
description: Send break request
description: "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"
bit_offset: 1
bit_size: 1
- name: MMRQ
description: Mute mode request
description: Mute mode request. Puts the USART in mute mode and sets the RWU flag.
bit_offset: 2
bit_size: 1
- name: RXFRQ
description: Receive data flush request
description: "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"
bit_offset: 3
bit_size: 1
- name: TXFRQ
description: Transmit data flush request
description: Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data.
bit_offset: 4
bit_size: 1
fieldset/TDR:
description: Transmit data register
fieldset/RTOR:
description: Receiver timeout register
fields:
- name: TDR
description: Transmit data value
- name: RTO
description: Receiver timeout value
bit_offset: 0
bit_size: 9
enum/ADDM7:
bit_size: 24
- name: BLEN
description: Block Length
bit_offset: 24
bit_size: 8
enum/ABRMOD:
bit_size: 2
variants:
- name: Start
description: Measurement of the start bit is used to detect the baud rate
value: 0
- name: Edge
description: Falling edge to falling edge measurement
value: 1
- name: Frame7F
description: "0x7F frame detection"
value: 2
- name: Frame55
description: "0x55 frame detection"
value: 3
enum/ADDM:
bit_size: 1
variants:
- name: Bit4
@ -430,6 +578,24 @@ enum/ADDM7:
- name: Bit7
description: 7-bit address detection
value: 1
enum/CPHA:
bit_size: 1
variants:
- name: First
description: The first clock transition is the first data capture edge
value: 0
- name: Second
description: The second clock transition is the first data capture edge
value: 1
enum/CPOL:
bit_size: 1
variants:
- name: Low
description: Steady low value on CK pin outside transmission window
value: 0
- name: High
description: Steady high value on CK pin outside transmission window
value: 1
enum/DEP:
bit_size: 1
variants:
@ -439,6 +605,24 @@ enum/DEP:
- name: Low
description: DE signal is active low
value: 1
enum/IRLP:
bit_size: 1
variants:
- name: Normal
description: Normal mode
value: 0
- name: LowPower
description: Low-power mode
value: 1
enum/LBDL:
bit_size: 1
variants:
- name: Bit10
description: 10-bit break detection
value: 0
- name: Bit11
description: 11-bit break detection
value: 1
enum/M0:
bit_size: 1
variants:
@ -466,6 +650,24 @@ enum/MSBFIRST:
- name: MSB
description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"
value: 1
enum/ONEBIT:
bit_size: 1
variants:
- name: Sample3
description: Three sample bit method
value: 0
- name: Sample1
description: One sample bit method
value: 1
enum/OVER8:
bit_size: 1
variants:
- name: Oversampling16
description: Oversampling by 16
value: 0
- name: Oversampling8
description: Oversampling by 8
value: 1
enum/PS:
bit_size: 1
variants:
@ -475,6 +677,15 @@ enum/PS:
- name: Odd
description: Odd parity
value: 1
enum/RWU:
bit_size: 1
variants:
- name: Active
description: Receiver in active mode
value: 0
- name: Mute
description: Receiver in mute mode
value: 1
enum/STOP:
bit_size: 2
variants:
@ -482,22 +693,22 @@ enum/STOP:
description: 1 stop bit
value: 0
- name: Stop0p5
description: 0.5 stop bit
description: 0.5 stop bits
value: 1
- name: Stop2
description: 2 stop bit
description: 2 stop bits
value: 2
- name: Stop1p5
description: 1.5 stop bit
description: 1.5 stop bits
value: 3
enum/WAKE:
bit_size: 1
variants:
- name: Idle
description: Idle line
- name: IdleLine
description: USART wakeup on idle line
value: 0
- name: Address
description: Address mask
- name: AddressMark
description: USART wakeup on address mark
value: 1
enum/WUS:
bit_size: 2

823
data/registers/usart_v4.yaml Normal file
View File

@ -0,0 +1,823 @@
---
block/USART:
description: Universal synchronous asynchronous receiver transmitter
items:
- name: CR1
description: Control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: Control register 2
byte_offset: 4
fieldset: CR2
- name: CR3
description: Control register 3
byte_offset: 8
fieldset: CR3
- name: BRR
description: Baud rate register
byte_offset: 12
fieldset: BRR
- name: GTPR
description: Guard time and prescaler register
byte_offset: 16
fieldset: GTPR
- name: RTOR
description: Receiver timeout register
byte_offset: 20
fieldset: RTOR
- name: RQR
description: Request register
byte_offset: 24
access: Write
fieldset: RQR
- name: ISR
description: Interrupt & status register
byte_offset: 28
access: Read
fieldset: ISR
- name: ICR
description: Interrupt flag clear register
byte_offset: 32
access: Write
fieldset: ICR
- name: RDR
description: Receive data register
byte_offset: 36
access: Read
fieldset: DR
- name: TDR
description: Transmit data register
byte_offset: 40
access: Write
fieldset: DR
- name: PRESC
description: Prescaler register
byte_offset: 44
fieldset: PRESC
block/LPUART:
description: Low-power Universal synchronous asynchronous receiver transmitter
items:
- name: CR1
description: Control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: Control register 2
byte_offset: 4
fieldset: CR2
- name: CR3
description: Control register 3
byte_offset: 8
fieldset: CR3
- name: BRR
description: Baud rate register
byte_offset: 12
fieldset: BRR
- name: RQR
description: Request register
byte_offset: 24
access: Write
fieldset: RQR
- name: ISR
description: Interrupt & status register
byte_offset: 28
access: Read
fieldset: ISR
- name: ICR
description: Interrupt flag clear register
byte_offset: 32
access: Write
fieldset: ICR
- name: RDR
description: Receive data register
byte_offset: 36
access: Read
fieldset: DR
- name: TDR
description: Transmit data register
byte_offset: 40
access: Write
fieldset: DR
- name: PRESC
description: Prescaler register
byte_offset: 44
fieldset: PRESC
fieldset/BRR:
description: Baud rate register
fields:
- name: BRR
description: USARTDIV
bit_offset: 0
bit_size: 16
fieldset/CR1:
description: Control register 1
fields:
- name: UE
description: USART enable
bit_offset: 0
bit_size: 1
- name: UESM
description: USART enable in Stop mode
bit_offset: 1
bit_size: 1
- name: RE
description: Receiver enable
bit_offset: 2
bit_size: 1
- name: TE
description: Transmitter enable
bit_offset: 3
bit_size: 1
- name: IDLEIE
description: IDLE interrupt enable
bit_offset: 4
bit_size: 1
- name: RXNEIE
description: RXNE interrupt enable
bit_offset: 5
bit_size: 1
- name: TCIE
description: Transmission complete interrupt enable
bit_offset: 6
bit_size: 1
- name: TXEIE
description: TXE interrupt enable
bit_offset: 7
bit_size: 1
- name: PEIE
description: PE interrupt enable
bit_offset: 8
bit_size: 1
- name: PS
description: Parity selection
bit_offset: 9
bit_size: 1
enum: PS
- name: PCE
description: Parity control enable
bit_offset: 10
bit_size: 1
- name: WAKE
description: Receiver wakeup method
bit_offset: 11
bit_size: 1
enum: WAKE
- name: M0
description: Word length
bit_offset: 12
bit_size: 1
enum: M0
- name: MME
description: Mute mode enable
bit_offset: 13
bit_size: 1
- name: CMIE
description: Character match interrupt enable
bit_offset: 14
bit_size: 1
- name: OVER8
description: Oversampling mode
bit_offset: 15
bit_size: 1
enum: OVER8
- name: DEDT
description: Driver Enable deassertion time
bit_offset: 16
bit_size: 5
- name: DEAT
description: Driver Enable assertion time
bit_offset: 21
bit_size: 5
- name: RTOIE
description: Receiver timeout interrupt enable
bit_offset: 26
bit_size: 1
- name: EOBIE
description: End of Block interrupt enable
bit_offset: 27
bit_size: 1
- name: M1
description: Word length
bit_offset: 28
bit_size: 1
enum: M1
- name: FIFOEN
description: FIFO mode enable
bit_offset: 29
bit_size: 1
- name: TXFEIE
description: TXFIFO empty interrupt enable
bit_offset: 30
bit_size: 1
- name: RXFFIE
description: RXFIFO Full interrupt enable
bit_offset: 31
bit_size: 1
fieldset/CR2:
description: Control register 2
fields:
- name: ADDM
description: 7-bit Address Detection/4-bit Address Detection
bit_offset: 4
bit_size: 1
enum: ADDM
- name: LBDL
description: Line break detection length
bit_offset: 5
bit_size: 1
enum: LBDL
- name: LBDIE
description: LIN break detection interrupt enable
bit_offset: 6
bit_size: 1
- name: LBCL
description: Last bit clock pulse
bit_offset: 8
bit_size: 1
- name: CPHA
description: Clock phase
bit_offset: 9
bit_size: 1
enum: CPHA
- name: CPOL
description: Clock polarity
bit_offset: 10
bit_size: 1
enum: CPOL
- name: CLKEN
description: Clock enable
bit_offset: 11
bit_size: 1
- name: STOP
description: STOP bits
bit_offset: 12
bit_size: 2
enum: STOP
- name: LINEN
description: LIN mode enable
bit_offset: 14
bit_size: 1
- name: SWAP
description: Swap TX/RX pins
bit_offset: 15
bit_size: 1
- name: RXINV
description: RX pin active level inversion
bit_offset: 16
bit_size: 1
- name: TXINV
description: TX pin active level inversion
bit_offset: 17
bit_size: 1
- name: DATAINV
description: Binary data inversion
bit_offset: 18
bit_size: 1
- name: MSBFIRST
description: Most significant bit first
bit_offset: 19
bit_size: 1
enum: MSBFIRST
- name: ABREN
description: Auto baud rate enable
bit_offset: 20
bit_size: 1
- name: ABRMOD
description: Auto baud rate mode
bit_offset: 21
bit_size: 2
enum: ABRMOD
- name: RTOEN
description: Receiver timeout enable
bit_offset: 23
bit_size: 1
- name: ADD
description: Address of the USART node
bit_offset: 24
bit_size: 8
fieldset/CR3:
description: Control register 3
fields:
- name: EIE
description: Error interrupt enable
bit_offset: 0
bit_size: 1
- name: IREN
description: IrDA mode enable
bit_offset: 1
bit_size: 1
- name: IRLP
description: IrDA low-power
bit_offset: 2
bit_size: 1
enum: IRLP
- name: HDSEL
description: Half-duplex selection
bit_offset: 3
bit_size: 1
- name: NACK
description: Smartcard NACK enable
bit_offset: 4
bit_size: 1
- name: SCEN
description: Smartcard mode enable
bit_offset: 5
bit_size: 1
- name: DMAR
description: DMA enable receiver
bit_offset: 6
bit_size: 1
- name: DMAT
description: DMA enable transmitter
bit_offset: 7
bit_size: 1
- name: RTSE
description: RTS enable
bit_offset: 8
bit_size: 1
- name: CTSE
description: CTS enable
bit_offset: 9
bit_size: 1
- name: CTSIE
description: CTS interrupt enable
bit_offset: 10
bit_size: 1
- name: ONEBIT
description: One sample bit method enable
bit_offset: 11
bit_size: 1
enum: ONEBIT
- name: OVRDIS
description: Overrun Disable
bit_offset: 12
bit_size: 1
- name: DDRE
description: DMA Disable on Reception Error
bit_offset: 13
bit_size: 1
- name: DEM
description: Driver enable mode
bit_offset: 14
bit_size: 1
- name: DEP
description: Driver enable polarity selection
bit_offset: 15
bit_size: 1
enum: DEP
- name: SCARCNT
description: Smartcard auto-retry count
bit_offset: 17
bit_size: 3
- name: WUS
description: Wakeup from Stop mode interrupt flag selection
bit_offset: 20
bit_size: 2
enum: WUS
- name: WUFIE
description: Wakeup from Stop mode interrupt enable
bit_offset: 22
bit_size: 1
- name: TXFTIE
description: TXFIFO threshold interrupt enable
bit_offset: 23
bit_size: 1
- name: RXFTCFG
description: Receive FIFO threshold configuration
bit_offset: 25
bit_size: 3
- name: RXFTIE
description: RXFIFO threshold interrupt enable
bit_offset: 28
bit_size: 1
- name: TXFTCFG
description: TXFIFO threshold configuration
bit_offset: 29
bit_size: 3
fieldset/DR:
description: Data register
fields:
- name: DR
description: Data value
bit_offset: 0
bit_size: 9
fieldset/GTPR:
description: Guard time and prescaler register
fields:
- name: PSC
description: Prescaler value
bit_offset: 0
bit_size: 8
- name: GT
description: Guard time value
bit_offset: 8
bit_size: 8
fieldset/ICR:
description: Interrupt flag clear register
fields:
- name: PE
description: Parity error clear flag
bit_offset: 0
bit_size: 1
- name: FE
description: Framing error clear flag
bit_offset: 1
bit_size: 1
- name: NE
description: Noise error clear flag
bit_offset: 2
bit_size: 1
- name: ORE
description: Overrun error clear flag
bit_offset: 3
bit_size: 1
- name: IDLE
description: Idle line detected clear flag
bit_offset: 4
bit_size: 1
- name: TC
description: Transmission complete clear flag
bit_offset: 6
bit_size: 1
- name: LBD
description: LIN break detection clear flag
bit_offset: 8
bit_size: 1
- name: CTS
description: CTS clear flag
bit_offset: 9
bit_size: 1
- name: RTOF
description: Receiver timeout clear flag
bit_offset: 11
bit_size: 1
- name: EOBF
description: End of block clear flag
bit_offset: 12
bit_size: 1
- name: CMF
description: Character match clear flag
bit_offset: 17
bit_size: 1
- name: WUF
description: Wakeup from Stop mode clear flag
bit_offset: 20
bit_size: 1
fieldset/ISR:
description: Interrupt & status register
fields:
- name: PE
description: Parity error
bit_offset: 0
bit_size: 1
- name: FE
description: Framing error
bit_offset: 1
bit_size: 1
- name: NE
description: Noise error flag
bit_offset: 2
bit_size: 1
- name: ORE
description: Overrun error
bit_offset: 3
bit_size: 1
- name: IDLE
description: Idle line detected
bit_offset: 4
bit_size: 1
- name: RXNE
description: Read data register not empty
bit_offset: 5
bit_size: 1
- name: TC
description: Transmission complete
bit_offset: 6
bit_size: 1
- name: TXE
description: Transmit data register empty
bit_offset: 7
bit_size: 1
- name: LBD
description: LIN break detection flag
bit_offset: 8
bit_size: 1
- name: CTSIF
description: CTS interrupt flag
bit_offset: 9
bit_size: 1
- name: CTS
description: CTS flag
bit_offset: 10
bit_size: 1
- name: RTOF
description: Receiver timeout
bit_offset: 11
bit_size: 1
- name: EOBF
description: End of block flag
bit_offset: 12
bit_size: 1
- name: ABRE
description: Auto baud rate error
bit_offset: 14
bit_size: 1
- name: ABRF
description: Auto baud rate flag
bit_offset: 15
bit_size: 1
- name: BUSY
description: Busy flag
bit_offset: 16
bit_size: 1
- name: CMF
description: character match flag
bit_offset: 17
bit_size: 1
- name: SBKF
description: Send break flag
bit_offset: 18
bit_size: 1
- name: RWU
description: Receiver wakeup from Mute mode
bit_offset: 19
bit_size: 1
enum: RWU
- name: WUF
description: Wakeup from Stop mode flag
bit_offset: 20
bit_size: 1
- name: TEACK
description: Transmit enable acknowledge flag
bit_offset: 21
bit_size: 1
- name: REACK
description: Receive enable acknowledge flag
bit_offset: 22
bit_size: 1
- name: TXFE
description: TXFIFO Empty
bit_offset: 23
bit_size: 1
- name: RXFF
description: RXFIFO Full
bit_offset: 24
bit_size: 1
- name: RXFT
description: RXFIFO threshold flag
bit_offset: 26
bit_size: 1
- name: TXFT
description: TXFIFO threshold flag
bit_offset: 27
bit_size: 1
fieldset/PRESC:
description: Prescaler register
fields:
- name: PRESCALER
description: Clock prescaler
bit_offset: 0
bit_size: 4
enum: PRESC
fieldset/RQR:
description: Request register
fields:
- name: ABRRQ
description: Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame.
bit_offset: 0
bit_size: 1
- name: SBKRQ
description: "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"
bit_offset: 1
bit_size: 1
- name: MMRQ
description: Mute mode request. Puts the USART in mute mode and sets the RWU flag.
bit_offset: 2
bit_size: 1
- name: RXFRQ
description: "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"
bit_offset: 3
bit_size: 1
- name: TXFRQ
description: Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data.
bit_offset: 4
bit_size: 1
fieldset/RTOR:
description: Receiver timeout register
fields:
- name: RTO
description: Receiver timeout value
bit_offset: 0
bit_size: 24
- name: BLEN
description: Block Length
bit_offset: 24
bit_size: 8
enum/ABRMOD:
bit_size: 2
variants:
- name: Start
description: Measurement of the start bit is used to detect the baud rate
value: 0
- name: Edge
description: Falling edge to falling edge measurement
value: 1
- name: Frame7F
description: "0x7F frame detection"
value: 2
- name: Frame55
description: "0x55 frame detection"
value: 3
enum/ADDM:
bit_size: 1
variants:
- name: Bit4
description: 4-bit address detection
value: 0
- name: Bit7
description: 7-bit address detection
value: 1
enum/CPHA:
bit_size: 1
variants:
- name: First
description: The first clock transition is the first data capture edge
value: 0
- name: Second
description: The second clock transition is the first data capture edge
value: 1
enum/CPOL:
bit_size: 1
variants:
- name: Low
description: Steady low value on CK pin outside transmission window
value: 0
- name: High
description: Steady high value on CK pin outside transmission window
value: 1
enum/DEP:
bit_size: 1
variants:
- name: High
description: DE signal is active high
value: 0
- name: Low
description: DE signal is active low
value: 1
enum/IRLP:
bit_size: 1
variants:
- name: Normal
description: Normal mode
value: 0
- name: LowPower
description: Low-power mode
value: 1
enum/LBDL:
bit_size: 1
variants:
- name: Bit10
description: 10-bit break detection
value: 0
- name: Bit11
description: 11-bit break detection
value: 1
enum/M0:
bit_size: 1
variants:
- name: Bit8
description: "1 start bit, 8 data bits, n stop bits"
value: 0
- name: Bit9
description: "1 start bit, 9 data bits, n stop bits"
value: 1
enum/M1:
bit_size: 1
variants:
- name: M0
description: Use M0 to set the data bits
value: 0
- name: Bit7
description: "1 start bit, 7 data bits, n stop bits"
value: 1
enum/MSBFIRST:
bit_size: 1
variants:
- name: LSB
description: "data is transmitted/received with data bit 0 first, following the start bit"
value: 0
- name: MSB
description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"
value: 1
enum/ONEBIT:
bit_size: 1
variants:
- name: Sample3
description: Three sample bit method
value: 0
- name: Sample1
description: One sample bit method
value: 1
enum/OVER8:
bit_size: 1
variants:
- name: Oversampling16
description: Oversampling by 16
value: 0
- name: Oversampling8
description: Oversampling by 8
value: 1
enum/PRESC:
bit_size: 4
variants:
- name: Div1
description: input clock not divided
value: 0
- name: Div2
description: input clock divided by 2
value: 1
- name: Div4
description: input clock divided by 4
value: 2
- name: Div6
description: input clock divided by 6
value: 3
- name: Div8
description: input clock divided by 8
value: 4
- name: Div10
description: input clock divided by 10
value: 5
- name: Div12
description: input clock divided by 12
value: 6
- name: Div16
description: input clock divided by 16
value: 7
- name: Div32
description: input clock divided by 32
value: 8
- name: Div64
description: input clock divided by 64
value: 9
- name: Div128
description: input clock divided by 128
value: 10
- name: Div256
description: input clock divided by 256
value: 11
enum/PS:
bit_size: 1
variants:
- name: Even
description: Even parity
value: 0
- name: Odd
description: Odd parity
value: 1
enum/RWU:
bit_size: 1
variants:
- name: Active
description: Receiver in active mode
value: 0
- name: Mute
description: Receiver in mute mode
value: 1
enum/STOP:
bit_size: 2
variants:
- name: Stop1
description: 1 stop bit
value: 0
- name: Stop0p5
description: 0.5 stop bits
value: 1
- name: Stop2
description: 2 stop bits
value: 2
- name: Stop1p5
description: 1.5 stop bits
value: 3
enum/WAKE:
bit_size: 1
variants:
- name: IdleLine
description: USART wakeup on idle line
value: 0
- name: AddressMark
description: USART wakeup on address mark
value: 1
enum/WUS:
bit_size: 2
variants:
- name: Address
description: WUF active on address match
value: 0
- name: Start
description: WuF active on Start bit detection
value: 2
- name: RXNE
description: WUF active on RXNE
value: 3

34
stm32-data-gen/src/chips.rs
View File

@ -113,23 +113,23 @@ impl PeriMatcher {
const PERIMAP: &[(&str, (&str, &str, &str))] = &[
(".*:USART:sci2_v1_1", ("usart", "v1", "USART")),
(".*:USART:sci2_v1_2_F1", ("usart", "v1", "USART")),
(".*:USART:sci2_v1_2", ("usart", "v1", "USART")),
(".*:USART:sci2_v2_0", ("usart", "v2", "USART")),
(".*:USART:sci2_v2_1", ("usart", "v2", "USART")),
(".*:USART:sci2_v2_2", ("usart", "v2", "USART")),
(".*:USART:sci3_v1_0", ("usart", "v2", "USART")),
(".*:USART:sci3_v1_1", ("usart", "v2", "USART")),
(".*:USART:sci3_v1_2", ("usart", "v2", "USART")),
(".*:USART:sci3_v2_0", ("usart", "v2", "USART")),
(".*:USART:sci3_v2_1", ("usart", "v2", "USART")),
(".*:UART:sci2_v1_2_F4", ("usart", "v1", "USART")),
(".*:UART:sci2_v2_1", ("usart", "v2", "USART")),
(".*:UART:sci2_v3_0", ("usart", "v2", "USART")),
(".*:UART:sci2_v3_1", ("usart", "v2", "USART")),
(".*:LPUART:sci3_v1_1", ("lpuart", "v1", "LPUART")),
(".*:LPUART:sci3_v1_2", ("lpuart", "v2", "LPUART")),
(".*:LPUART:sci3_v1_3", ("lpuart", "v2", "LPUART")),
(".*:LPUART:sci3_v1_4", ("lpuart", "v2", "LPUART")),
(".*:USART:sci2_v1_2", ("usart", "v2", "USART")),
(".*:USART:sci2_v2_0", ("usart", "v3", "USART")),
(".*:USART:sci2_v2_1", ("usart", "v3", "USART")),
(".*:USART:sci2_v2_2", ("usart", "v3", "USART")),
(".*:USART:sci3_v1_0", ("usart", "v3", "USART")),
(".*:USART:sci3_v1_1", ("usart", "v3", "USART")),
(".*:USART:sci3_v1_2", ("usart", "v4", "USART")),
(".*:USART:sci3_v2_0", ("usart", "v4", "USART")),
(".*:USART:sci3_v2_1", ("usart", "v4", "USART")),
(".*:UART:sci2_v1_2_F4", ("usart", "v2", "USART")),
(".*:UART:sci2_v2_1", ("usart", "v3", "USART")),
(".*:UART:sci2_v3_0", ("usart", "v4", "USART")),
(".*:UART:sci2_v3_1", ("usart", "v4", "USART")),
(".*:LPUART:sci3_v1_1", ("usart", "v3", "LPUART")),
(".*:LPUART:sci3_v1_2", ("usart", "v4", "LPUART")),
(".*:LPUART:sci3_v1_3", ("usart", "v4", "LPUART")),
(".*:LPUART:sci3_v1_4", ("usart", "v4", "LPUART")),
("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")),
(".*:RNG:rng1_v1_1", ("rng", "v1", "RNG")),
(".*:RNG:rng1_v2_0", ("rng", "v1", "RNG")),