diff --git a/.github/ci/build.sh b/.github/ci/build.sh
index e2ec747..8b47d09 100755
--- a/.github/ci/build.sh
+++ b/.github/ci/build.sh
@@ -17,7 +17,10 @@ cargo fmt -- --check
 # so the diff will show this PR's effect
 git remote add upstream https://github.com/embassy-rs/stm32-data
 git fetch --depth 15 upstream main
+set +e
 git clone --depth 1 --branch stm32-data-$(git merge-base HEAD upstream/main) https://github.com/embassy-rs/stm32-data-generated/ build -q
+DIFF_OK=$?
+set -e
 
 # move the sources directory out of the cache if it exists
 mv /ci/cache/sources ./sources || true
@@ -27,12 +30,18 @@ mv /ci/cache/sources ./sources || true
 # move the sources directory into the cache
 mv ./sources /ci/cache/sources
 
-# upload diff
-(
-    cd build
-    git add .
-    git diff --staged --color data | aha --black > /ci/artifacts/diff.html
-)
+if [ $DIFF_OK -eq 0 ]; then
+    # upload diff
+    (
+        cd build
+        git add .
+        git diff --staged --color data | aha --black > /ci/artifacts/diff.html
+    )
+
+    cat > /ci/comment.md <<EOF
+diff: https://ci.embassy.dev/jobs/$(jq -r .id < /ci/job.json)/artifacts/diff.html
+EOF
+fi
 
 # upload generated data to a fake git repo at
 # https://ci.embassy.dev/jobs/$ID/artifacts/generated.git
@@ -47,7 +56,3 @@ mv ./sources /ci/cache/sources
     git update-server-info  # generate .git/info/refs
     mv .git /ci/artifacts/generated.git
 )
-
-cat > /ci/comment.md <<EOF
-diff: https://ci.embassy.dev/jobs/$(jq -r .id < /ci/job.json)/artifacts/diff.html
-EOF
diff --git a/data/registers/cordic_v1.yaml b/data/registers/cordic_v1.yaml
new file mode 100644
index 0000000..8887d72
--- /dev/null
+++ b/data/registers/cordic_v1.yaml
@@ -0,0 +1,187 @@
+block/CORDIC:
+  description: CORDIC co-processor.
+  items:
+  - name: CSR
+    description: Control and status register.
+    byte_offset: 0
+    fieldset: CSR
+  - name: WDATA
+    description: Argument register.
+    byte_offset: 4
+    bit_offset: 0
+    bit_size: 32
+  - name: RDATA
+    description: Result register.
+    byte_offset: 8
+    bit_offset: 0
+    bit_size: 32
+fieldset/CSR:
+  description: Control and status register.
+  fields:
+  - name: FUNC
+    description: Function.
+    bit_offset: 0
+    bit_size: 4
+    enum: FUNC
+  - name: PRECISION
+    description: Precision required (number of iterations/cycles), where PRECISION = (number of iterations/4).
+    bit_offset: 4
+    bit_size: 4
+    enum: PRECISION
+  - name: SCALE
+    description: Scaling factor (2^-n for arguments, 2^n for results).
+    bit_offset: 8
+    bit_size: 3
+  - name: IEN
+    description: Enable interrupt.
+    bit_offset: 16
+    bit_size: 1
+  - name: DMAREN
+    description: Enable DMA wread channel.
+    bit_offset: 17
+    bit_size: 1
+  - name: DMAWEN
+    description: Enable DMA write channel.
+    bit_offset: 18
+    bit_size: 1
+  - name: NRES
+    description: Number of results in the RDATA register.
+    bit_offset: 19
+    bit_size: 1
+    enum: NRES
+  - name: NARGS
+    description: Number of arguments expected by the WDATA register.
+    bit_offset: 20
+    bit_size: 1
+    enum: NARGS
+  - name: RESSIZE
+    description: Width of output data.
+    bit_offset: 21
+    bit_size: 1
+    enum: RESSIZE
+  - name: ARGSIZE
+    description: Width of input data.
+    bit_offset: 22
+    bit_size: 1
+    enum: ARGSIZE
+  - name: RRDY
+    description: Result ready flag.
+    bit_offset: 31
+    bit_size: 1
+enum/ARGSIZE:
+  bit_size: 1
+  variants:
+  - name: Bits32
+    description: Use 32 bit input values.
+    value: 0
+  - name: Bits16
+    description: Use 16 bit input values.
+    value: 1
+enum/FUNC:
+  bit_size: 4
+  variants:
+  - name: Cosine
+    description: Cosine function.
+    value: 0
+  - name: Sine
+    description: Sine function.
+    value: 1
+  - name: Phase
+    description: Phase function.
+    value: 2
+  - name: Modulus
+    description: Modulus function.
+    value: 3
+  - name: Arctangent
+    description: Arctangent function.
+    value: 4
+  - name: HyperbolicCosine
+    description: Hyperbolic Cosine function.
+    value: 5
+  - name: HyperbolicSine
+    description: Hyperbolic Sine function.
+    value: 6
+  - name: Arctanh
+    description: Arctanh function.
+    value: 7
+  - name: NaturalLogarithm
+    description: Natural Logarithm function.
+    value: 8
+  - name: SquareRoot
+    description: Square Root function.
+    value: 9
+enum/NARGS:
+  bit_size: 1
+  variants:
+  - name: Num1
+    description: Only single argument write is needed for next calculation.
+    value: 0
+  - name: Num2
+    description: Two argument writes need to be performed for next calculation.
+    value: 1
+enum/NRES:
+  bit_size: 1
+  variants:
+  - name: Num1
+    description: Only single result value will be returned. After a single read RRDY will be automatically cleared.
+    value: 0
+  - name: Num2
+    description: Two return reads need to be performed. After two reads RRDY will be automatically cleared.
+    value: 1
+enum/PRECISION:
+  bit_size: 4
+  variants:
+  - name: Iters4
+    description: 4 iterations.
+    value: 1
+  - name: Iters8
+    description: 8 iterations.
+    value: 2
+  - name: Iters12
+    description: 12 iterations.
+    value: 3
+  - name: Iters16
+    description: 16 iterations.
+    value: 4
+  - name: Iters20
+    description: 20 iterations.
+    value: 5
+  - name: Iters24
+    description: 24 iterations.
+    value: 6
+  - name: Iters28
+    description: 28 iterations.
+    value: 7
+  - name: Iters32
+    description: 32 iterations.
+    value: 8
+  - name: Iters36
+    description: 36 iterations.
+    value: 9
+  - name: Iters40
+    description: 40 iterations.
+    value: 10
+  - name: Iters44
+    description: 44 iterations.
+    value: 11
+  - name: Iters48
+    description: 48 iterations.
+    value: 12
+  - name: Iters52
+    description: 52 iterations.
+    value: 13
+  - name: Iters56
+    description: 56 iterations.
+    value: 14
+  - name: Iters60
+    description: 60 iterations.
+    value: 15
+enum/RESSIZE:
+  bit_size: 1
+  variants:
+  - name: Bits32
+    description: Use 32 bit output values.
+    value: 0
+  - name: Bits16
+    description: Use 16 bit output values.
+    value: 1
\ No newline at end of file
diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs
index caa5887..7e1d238 100644
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@@ -514,6 +514,7 @@ impl PeriMatcher {
             ("STM32L4.*:GFXMMU:.*", ("gfxmmu", "v1", "GFXMMU")),
             ("STM32U5.*:GFXMMU:.*", ("gfxmmu", "v2", "GFXMMU")),
             ("STM32U5.*:ICACHE:.*", ("icache", "v1", "ICACHE")),
+            (".*:CORDIC:.*", ("cordic", "v1", "CORDIC")),
             ("STM32F0x[128].*:TSC:.*", ("tsc", "v1", "TSC")),
             ("STM32F3[07][123].*:TSC:.*", ("tsc", "v1", "TSC")),
             ("STM32WB55.*:TSC:.*", ("tsc", "v2", "TSC")),