Merge pull request #317 from eZioPan/tim-cleanup

remove `OCPE`, `OPM`, `ECE` enum of `TIM`

data/registers/timer_v1.yaml

@@ -289,7 +289,6 @@ fieldset/CCMR_Output:
     array:
       len: 2
       stride: 8
-    enum: OCPE
   - name: OCM
     description: Output compare 3 mode
     bit_offset: 4
@@ -350,10 +349,9 @@ fieldset/CR1_BASIC:
     bit_size: 1
     enum: URS
   - name: OPM
-    description: One-pulse mode
+    description: One-pulse mode enbaled
     bit_offset: 3
     bit_size: 1
-    enum: OPM
   - name: ARPE
     description: Auto-reload preload enable
     bit_offset: 7
@@ -586,10 +584,9 @@ fieldset/SMCR:
     bit_size: 2
     enum: ETPS
   - name: ECE
-    description: External clock enable
+    description: External clock mode 2 enable
     bit_offset: 14
     bit_size: 1
-    enum: ECE
   - name: ETP
     description: External trigger polarity
     bit_offset: 15
@@ -707,15 +704,6 @@ enum/DIR:
   - name: Down
     description: Counter used as downcounter
     value: 1
-enum/ECE:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: External clock mode 2 disabled
-    value: 0
-  - name: Enabled
-    description: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
-    value: 1
 enum/ETF:
   bit_size: 4
   variants:
@@ -905,24 +893,6 @@ enum/OCM:
   - name: PwmMode2
     description: Inversely to PwmMode1
     value: 7
-enum/OCPE:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately
-    value: 0
-  - name: Enabled
-    description: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event
-    value: 1
-enum/OPM:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Counter is not stopped at update event
-    value: 0
-  - name: Enabled
-    description: Counter stops counting at the next update event (clearing the CEN bit)
-    value: 1
 enum/OSSI:
   bit_size: 1
   variants: