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dma_v2: merge ISR and IFCR fieldsets

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This commit is contained in:
Dario Nieuwenhuis 2021-05-16 02:52:59 +02:00
parent 8d8801d432
commit 5e59f22819
1 changed files with 5 additions and 58 deletions
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61
data/registers/dma_v2.yaml
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@ -10,7 +10,7 @@ block/DMA:
byte_offset: 0
reset_value: 0
access: Read
fieldset: ISR
fieldset: IXR
- name: IFCR
description: low interrupt flag clear register
array:
@ -19,7 +19,7 @@ block/DMA:
byte_offset: 8
reset_value: 0
access: Write
fieldset: IFCR
fieldset: IXR
- name: ST
description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"
array:
@ -171,61 +171,8 @@ fieldset/FCR:
description: FIFO error interrupt enable
bit_offset: 7
bit_size: 1
fieldset/IFCR:
description: low interrupt flag clear register
fields:
- name: CFEIF
description: Stream x clear FIFO error interrupt flag (x = 3..0)
bit_offset: 0
bit_size: 1
array:
offsets:
- 0
- 6
- 16
- 22
- name: CDMEIF
description: Stream x clear direct mode error interrupt flag (x = 3..0)
bit_offset: 2
bit_size: 1
array:
offsets:
- 0
- 6
- 16
- 22
- name: CTEIF
description: Stream x clear transfer error interrupt flag (x = 3..0)
bit_offset: 3
bit_size: 1
array:
offsets:
- 0
- 6
- 16
- 22
- name: CHTIF
description: Stream x clear half transfer interrupt flag (x = 3..0)
bit_offset: 4
bit_size: 1
array:
offsets:
- 0
- 6
- 16
- 22
- name: CTCIF
description: Stream x clear transfer complete interrupt flag (x = 3..0)
bit_offset: 5
bit_size: 1
array:
offsets:
- 0
- 6
- 16
- 22
fieldset/ISR:
description: low interrupt status register
fieldset/IXR:
description: interrupt register
fields:
- name: FEIF
description: Stream x FIFO error interrupt flag (x=3..0)