From 5d58d7dddafcc3c4bc1f329362762aa7fa42f398 Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Wed, 1 May 2024 16:11:06 +0200
Subject: [PATCH] chiptool fmt.

---
 data/registers/cryp_v4.yaml  |  2 +-
 data/registers/pwr_h7rs.yaml | 14 ++++-----
 data/registers/rcc_h7rs.yaml | 60 ++++++++++++++++++------------------
 3 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/data/registers/cryp_v4.yaml b/data/registers/cryp_v4.yaml
index 08c5850..3ae1fa3 100644
--- a/data/registers/cryp_v4.yaml
+++ b/data/registers/cryp_v4.yaml
@@ -212,4 +212,4 @@ enum/KMOD:
     value: 0
   - name: Shared
     description: Shared-key mode. If shared-key mode is properly initialized in SAES peripheral, the CRYP peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in CRYP key registers when BUSY bit is cleared and KEYVALID is set in the CRYP_SR register. Key error flag KERF is set otherwise in the CRYP_SR register.
-    value: 2
\ No newline at end of file
+    value: 2
diff --git a/data/registers/pwr_h7rs.yaml b/data/registers/pwr_h7rs.yaml
index a711a61..e8d6276 100644
--- a/data/registers/pwr_h7rs.yaml
+++ b/data/registers/pwr_h7rs.yaml
@@ -249,13 +249,6 @@ fieldset/CSR2:
     description: USB HS regulator enable.
     bit_offset: 27
     bit_size: 1
-enum/SDLEVEL:
-  bit_size: 1
-  variants:
-  - name: Reset
-    value: 0
-  - name: V1_8
-    value: 1
 fieldset/CSR3:
   description: PWR CPU control register 3.
   fields:
@@ -560,6 +553,13 @@ enum/RLPSN:
   - name: Normal
     description: RAM remains in normal mode when system enters to STOP.
     value: 1
+enum/SDLEVEL:
+  bit_size: 1
+  variants:
+  - name: Reset
+    value: 0
+  - name: V1_8
+    value: 1
 enum/SVOS:
   bit_size: 1
   variants:
diff --git a/data/registers/rcc_h7rs.yaml b/data/registers/rcc_h7rs.yaml
index 5b8c94a..dbcf0b2 100644
--- a/data/registers/rcc_h7rs.yaml
+++ b/data/registers/rcc_h7rs.yaml
@@ -2092,15 +2092,6 @@ fieldset/CR:
     array:
       len: 3
       stride: 2
-enum/HSEEXT:
-  bit_size: 1
-  variants:
-  - name: Analog
-    description: HSE in analog mode (default after reset)
-    value: 0
-  - name: Digital
-    description: HSE in digital mode
-    value: 1
 fieldset/CRRCR:
   description: RCC clock recovery RC register.
   fields:
@@ -2352,27 +2343,6 @@ enum/ADFSEL:
   - name: PLL2_P
     description: pll2_p_ck selected as ADF kernel clock.
     value: 1
-enum/HPRE:
-  bit_size: 4
-  variants:
-  - name: Div1
-    value: 0
-  - name: Div2
-    value: 8
-  - name: Div4
-    value: 9
-  - name: Div8
-    value: 10
-  - name: Div16
-    value: 11
-  - name: Div64
-    value: 12
-  - name: Div128
-    value: 13
-  - name: Div256
-    value: 14
-  - name: Div512
-    value: 15
 enum/CECSEL:
   bit_size: 2
   variants:
@@ -2463,6 +2433,36 @@ enum/FMCSWP:
   - name: B_0x5
     description: The switch is in recovery position (hclk5/4).
     value: 5
+enum/HPRE:
+  bit_size: 4
+  variants:
+  - name: Div1
+    value: 0
+  - name: Div2
+    value: 8
+  - name: Div4
+    value: 9
+  - name: Div8
+    value: 10
+  - name: Div16
+    value: 11
+  - name: Div64
+    value: 12
+  - name: Div128
+    value: 13
+  - name: Div256
+    value: 14
+  - name: Div512
+    value: 15
+enum/HSEEXT:
+  bit_size: 1
+  variants:
+  - name: Analog
+    description: HSE in analog mode (default after reset)
+    value: 0
+  - name: Digital
+    description: HSE in digital mode
+    value: 1
 enum/HSIDIV:
   bit_size: 2
   variants: