Merge remote-tracking branch 'upstream/main' into flash-blocks
This commit is contained in:
Rasmus Melchior Jacobsen
commit
5bf71d3d89
6
.vscode/settings.json
vendored
6
.vscode/settings.json
vendored
@ -3,4 +3,10 @@
|
|||||||
"[toml]": {
|
"[toml]": {
|
||||||
"editor.formatOnSave": false
|
"editor.formatOnSave": false
|
||||||
},
|
},
|
||||||
|
"[c]": {
|
||||||
|
"editor.formatOnSave": false
|
||||||
|
},
|
||||||
|
"[cpp]": {
|
||||||
|
"editor.formatOnSave": false
|
||||||
|
},
|
||||||
}
|
}
|
||||||
46
Cargo.lock
generated
46
Cargo.lock
generated
@ -53,7 +53,7 @@ source = "git+https://github.com/embassy-rs/chiptool?rev=1d9e0a39a6acc291e50cabc
|
|||||||
dependencies = [
|
dependencies = [
|
||||||
"anyhow",
|
"anyhow",
|
||||||
"clap",
|
"clap",
|
||||||
"env_logger",
|
"env_logger 0.9.3",
|
||||||
"inflections",
|
"inflections",
|
||||||
"log",
|
"log",
|
||||||
"proc-macro2",
|
"proc-macro2",
|
||||||
@ -71,7 +71,7 @@ source = "git+https://github.com/embassy-rs/chiptool#150ce4a3442001ef73e0c0f2924
|
|||||||
dependencies = [
|
dependencies = [
|
||||||
"anyhow",
|
"anyhow",
|
||||||
"clap",
|
"clap",
|
||||||
"env_logger",
|
"env_logger 0.9.3",
|
||||||
"inflections",
|
"inflections",
|
||||||
"log",
|
"log",
|
||||||
"proc-macro2",
|
"proc-macro2",
|
||||||
@ -170,6 +170,19 @@ version = "1.8.1"
|
|||||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
checksum = "7fcaabb2fef8c910e7f4c7ce9f67a1283a1715879a7c230ca9d6d1ae31f16d91"
|
checksum = "7fcaabb2fef8c910e7f4c7ce9f67a1283a1715879a7c230ca9d6d1ae31f16d91"
|
||||||
|
|
||||||
|
[[package]]
|
||||||
|
name = "env_logger"
|
||||||
|
version = "0.7.1"
|
||||||
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
|
checksum = "44533bbbb3bb3c1fa17d9f2e4e38bbbaf8396ba82193c4cb1b6445d711445d36"
|
||||||
|
dependencies = [
|
||||||
|
"atty",
|
||||||
|
"humantime 1.3.0",
|
||||||
|
"log",
|
||||||
|
"regex",
|
||||||
|
"termcolor",
|
||||||
|
]
|
||||||
|
|
||||||
[[package]]
|
[[package]]
|
||||||
name = "env_logger"
|
name = "env_logger"
|
||||||
version = "0.9.3"
|
version = "0.9.3"
|
||||||
@ -177,7 +190,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
|
|||||||
checksum = "a12e6657c4c97ebab115a42dcee77225f7f482cdd841cf7088c657a42e9e00e7"
|
checksum = "a12e6657c4c97ebab115a42dcee77225f7f482cdd841cf7088c657a42e9e00e7"
|
||||||
dependencies = [
|
dependencies = [
|
||||||
"atty",
|
"atty",
|
||||||
"humantime",
|
"humantime 2.1.0",
|
||||||
"log",
|
"log",
|
||||||
"regex",
|
"regex",
|
||||||
"termcolor",
|
"termcolor",
|
||||||
@ -219,6 +232,15 @@ dependencies = [
|
|||||||
"libc",
|
"libc",
|
||||||
]
|
]
|
||||||
|
|
||||||
|
[[package]]
|
||||||
|
name = "humantime"
|
||||||
|
version = "1.3.0"
|
||||||
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
|
checksum = "df004cfca50ef23c36850aaaa59ad52cc70d0e90243c3c7737a4dd32dc7a3c4f"
|
||||||
|
dependencies = [
|
||||||
|
"quick-error",
|
||||||
|
]
|
||||||
|
|
||||||
[[package]]
|
[[package]]
|
||||||
name = "humantime"
|
name = "humantime"
|
||||||
version = "2.1.0"
|
version = "2.1.0"
|
||||||
@ -390,6 +412,16 @@ version = "6.5.0"
|
|||||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
checksum = "ceedf44fb00f2d1984b0bc98102627ce622e083e49a5bacdb3e514fa4238e267"
|
checksum = "ceedf44fb00f2d1984b0bc98102627ce622e083e49a5bacdb3e514fa4238e267"
|
||||||
|
|
||||||
|
[[package]]
|
||||||
|
name = "pretty_env_logger"
|
||||||
|
version = "0.4.0"
|
||||||
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
|
checksum = "926d36b9553851b8b0005f1275891b392ee4d2d833852c417ed025477350fb9d"
|
||||||
|
dependencies = [
|
||||||
|
"env_logger 0.7.1",
|
||||||
|
"log",
|
||||||
|
]
|
||||||
|
|
||||||
[[package]]
|
[[package]]
|
||||||
name = "proc-macro-error"
|
name = "proc-macro-error"
|
||||||
version = "1.0.4"
|
version = "1.0.4"
|
||||||
@ -423,6 +455,12 @@ dependencies = [
|
|||||||
"unicode-ident",
|
"unicode-ident",
|
||||||
]
|
]
|
||||||
|
|
||||||
|
[[package]]
|
||||||
|
name = "quick-error"
|
||||||
|
version = "1.2.3"
|
||||||
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
|
checksum = "a1d01941d82fa2ab50be1e79e6714289dd7cde78eba4c074bc5a4374f650dfe0"
|
||||||
|
|
||||||
[[package]]
|
[[package]]
|
||||||
name = "quick-xml"
|
name = "quick-xml"
|
||||||
version = "0.26.0"
|
version = "0.26.0"
|
||||||
@ -562,7 +600,9 @@ dependencies = [
|
|||||||
"anyhow",
|
"anyhow",
|
||||||
"chiptool 0.1.0 (git+https://github.com/embassy-rs/chiptool?rev=1d9e0a39a6acc291e50cabc4ed617a87f06d5e89)",
|
"chiptool 0.1.0 (git+https://github.com/embassy-rs/chiptool?rev=1d9e0a39a6acc291e50cabc4ed617a87f06d5e89)",
|
||||||
"glob",
|
"glob",
|
||||||
|
"log",
|
||||||
"num",
|
"num",
|
||||||
|
"pretty_env_logger",
|
||||||
"quick-xml",
|
"quick-xml",
|
||||||
"rayon",
|
"rayon",
|
||||||
"ref_thread_local",
|
"ref_thread_local",
|
||||||
|
|||||||
5
d
5
d
@ -10,9 +10,8 @@ case "$CMD" in
|
|||||||
download-all)
|
download-all)
|
||||||
rm -rf ./sources/
|
rm -rf ./sources/
|
||||||
git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
|
git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
|
||||||
# The following is a temporary workaround until https://github.com/embassy-rs/stm32-data/pull/175 is merged.
|
|
||||||
cd ./sources/
|
cd ./sources/
|
||||||
git checkout 3d60b46
|
git checkout ca89656b
|
||||||
;;
|
;;
|
||||||
install-chiptool)
|
install-chiptool)
|
||||||
cargo install --git https://github.com/embassy-rs/chiptool
|
cargo install --git https://github.com/embassy-rs/chiptool
|
||||||
@ -40,7 +39,7 @@ case "$CMD" in
|
|||||||
;;
|
;;
|
||||||
ci)
|
ci)
|
||||||
[ -d sources ] || ./d download-all
|
[ -d sources ] || ./d download-all
|
||||||
rm -rf build
|
rm -rf build/{data,stm32-metapac}
|
||||||
cargo run --release --bin stm32-data-gen
|
cargo run --release --bin stm32-data-gen
|
||||||
cargo run --release --bin stm32-metapac-gen
|
cargo run --release --bin stm32-metapac-gen
|
||||||
(cd build/stm32-metapac && cargo check --features stm32h755zi-cm7,pac,metadata)
|
(cd build/stm32-metapac && cargo check --features stm32h755zi-cm7,pac,metadata)
|
||||||
|
|||||||
133
data/dmamux/H5_GPDMA.yaml
Normal file
133
data/dmamux/H5_GPDMA.yaml
Normal file
@ -0,0 +1,133 @@
|
|||||||
|
ADC1: 0
|
||||||
|
ADC2: 1
|
||||||
|
DAC1_CH1: 2
|
||||||
|
DAC1_CH2: 3
|
||||||
|
TIM6_UPD: 4
|
||||||
|
TIM7_UPD: 5
|
||||||
|
SPI1_RX: 6
|
||||||
|
SPI1_TX: 7
|
||||||
|
SPI2_RX: 8
|
||||||
|
SPI2_TX: 9
|
||||||
|
SPI3_RX: 10
|
||||||
|
SPI3_TX: 11
|
||||||
|
I2C1_RX: 12
|
||||||
|
I2C1_TX: 13
|
||||||
|
I2C2_RX: 15
|
||||||
|
I2C2_TX: 16
|
||||||
|
I2C3_RX: 18
|
||||||
|
I2C3_TX: 19
|
||||||
|
USART1_RX: 21
|
||||||
|
USART1_TX: 22
|
||||||
|
USART2_RX: 23
|
||||||
|
USART2_TX: 24
|
||||||
|
USART3_RX: 25
|
||||||
|
USART3_TX: 26
|
||||||
|
UART4_RX: 27
|
||||||
|
UART4_TX: 28
|
||||||
|
UART5_RX: 29
|
||||||
|
UART5_TX: 30
|
||||||
|
USART6_RX: 31
|
||||||
|
USART6_TX: 32
|
||||||
|
UART7_RX: 33
|
||||||
|
UART7_TX: 34
|
||||||
|
UART8_RX: 35
|
||||||
|
UART8_TX: 36
|
||||||
|
UART9_RX: 37
|
||||||
|
UART9_TX: 38
|
||||||
|
UART10_RX: 39
|
||||||
|
UART10_TX: 40
|
||||||
|
UART11_RX: 41
|
||||||
|
UART11_TX: 42
|
||||||
|
UART12_RX: 43
|
||||||
|
UART12_TX: 44
|
||||||
|
LPUART1_RX: 45
|
||||||
|
LPUART1_TX: 46
|
||||||
|
SPI4_RX: 47
|
||||||
|
SPI4_TX: 48
|
||||||
|
SPI5_RX: 49
|
||||||
|
SPI5_TX: 50
|
||||||
|
SPI6_RX: 51
|
||||||
|
SPI6_TX: 52
|
||||||
|
SAI1_A: 53
|
||||||
|
SAI1_B: 54
|
||||||
|
SAI2_A: 55
|
||||||
|
SAI2_B: 56
|
||||||
|
OSPI1: 57
|
||||||
|
TIM1_CC1: 58
|
||||||
|
TIM1_CC2: 59
|
||||||
|
TIM1_CC3: 60
|
||||||
|
TIM1_CC4: 61
|
||||||
|
TIM1_UPD: 62
|
||||||
|
TIM1_TRG: 63
|
||||||
|
TIM1_COM: 64
|
||||||
|
TIM8_CC1: 65
|
||||||
|
TIM8_CC2: 66
|
||||||
|
TIM8_CC3: 67
|
||||||
|
TIM8_CC4: 68
|
||||||
|
TIM8_UPD: 69
|
||||||
|
TIM8_TIG: 70
|
||||||
|
TIM8_COM: 71
|
||||||
|
TIM2_CC1: 72
|
||||||
|
TIM2_CC2: 73
|
||||||
|
TIM2_CC3: 74
|
||||||
|
TIM2_CC4: 75
|
||||||
|
TIM2_UPD: 76
|
||||||
|
TIM3_CC1: 77
|
||||||
|
TIM3_CC2: 78
|
||||||
|
TIM3_CC3: 79
|
||||||
|
TIM3_CC4: 80
|
||||||
|
TIM3_UPD: 81
|
||||||
|
TIM3_TRG: 82
|
||||||
|
TIM4_CC1: 83
|
||||||
|
TIM4_CC2: 84
|
||||||
|
TIM4_CC3: 85
|
||||||
|
TIM4_CC4: 86
|
||||||
|
TIM4_UPD: 87
|
||||||
|
TIM5_CC1: 88
|
||||||
|
TIM5_CC2: 89
|
||||||
|
TIM5_CC3: 90
|
||||||
|
TIM5_CC4: 91
|
||||||
|
TIM5_UPD: 92
|
||||||
|
TIM5_TRG: 93
|
||||||
|
TIM15_CC1: 94
|
||||||
|
TIM15_UPD: 95
|
||||||
|
TIM15_TRG: 96
|
||||||
|
TIM15_COM: 97
|
||||||
|
TIM16_CC1: 98
|
||||||
|
TIM16_UPD: 99
|
||||||
|
TIM17_CC1: 100
|
||||||
|
TIM17_UPD: 101
|
||||||
|
LPTIM1_IC1: 102
|
||||||
|
LPTIM1_IC2: 103
|
||||||
|
LPTIM1_UE: 104
|
||||||
|
LPTIM2_IC1: 105
|
||||||
|
LPTIM2_IC2: 106
|
||||||
|
LPTIM2_UE: 107
|
||||||
|
DCMI: 108
|
||||||
|
AES_OUT: 109
|
||||||
|
AES_IN: 110
|
||||||
|
HASH_IN: 111
|
||||||
|
UCPD1_RX: 112
|
||||||
|
UCPD1_TX: 113
|
||||||
|
CORDIC_READ: 114
|
||||||
|
CORDIC_WRITE: 115
|
||||||
|
FMAC_READ: 116
|
||||||
|
FMAC_WRITE: 117
|
||||||
|
SAES_OUT: 118
|
||||||
|
SAES_IN: 119
|
||||||
|
I3C1_RX: 120
|
||||||
|
I3C1_TX: 121
|
||||||
|
I3C1_TC: 122
|
||||||
|
I3C1_RS: 123
|
||||||
|
I2C4_RX: 124
|
||||||
|
I2C4_TX: 125
|
||||||
|
RESE: 126
|
||||||
|
LPTIM3_IC1: 127
|
||||||
|
LPTIM3_IC2: 128
|
||||||
|
LPTIM3_UE: 129
|
||||||
|
LPTIM5_IC1: 130
|
||||||
|
LPTIM5_IC2: 131
|
||||||
|
LPTIM5_UE: 132
|
||||||
|
LPTIM6_IC1: 133
|
||||||
|
LPTIM6_IC2: 134
|
||||||
|
LPTIM6_UE: 135
|
||||||
1280
data/registers/flash_h5.yaml
Normal file
1280
data/registers/flash_h5.yaml
Normal file
File diff suppressed because it is too large
Load Diff
779
data/registers/flash_h50.yaml
Normal file
779
data/registers/flash_h50.yaml
Normal file
@ -0,0 +1,779 @@
|
|||||||
|
---
|
||||||
|
block/FLASH:
|
||||||
|
description: FLASH address block description
|
||||||
|
items:
|
||||||
|
- name: ACR
|
||||||
|
description: "FLASH access control register "
|
||||||
|
byte_offset: 0
|
||||||
|
fieldset: ACR
|
||||||
|
- name: NSKEYR
|
||||||
|
description: "FLASH key register "
|
||||||
|
byte_offset: 4
|
||||||
|
fieldset: NSKEYR
|
||||||
|
- name: OPTKEYR
|
||||||
|
description: "FLASH option key register "
|
||||||
|
byte_offset: 12
|
||||||
|
fieldset: OPTKEYR
|
||||||
|
- name: OPSR
|
||||||
|
description: "FLASH operation status register "
|
||||||
|
byte_offset: 24
|
||||||
|
fieldset: OPSR
|
||||||
|
- name: OPTCR
|
||||||
|
description: "FLASH option control register "
|
||||||
|
byte_offset: 28
|
||||||
|
fieldset: OPTCR
|
||||||
|
- name: NSSR
|
||||||
|
description: "FLASH non-secure status register "
|
||||||
|
byte_offset: 32
|
||||||
|
fieldset: NSSR
|
||||||
|
- name: SECSR
|
||||||
|
description: "FLASH secure status register "
|
||||||
|
byte_offset: 36
|
||||||
|
fieldset: SECSR
|
||||||
|
- name: NSCR
|
||||||
|
description: "FLASH Non Secure control register "
|
||||||
|
byte_offset: 40
|
||||||
|
fieldset: NSCR
|
||||||
|
- name: NSCCR
|
||||||
|
description: "FLASH non-secure clear control register "
|
||||||
|
byte_offset: 48
|
||||||
|
fieldset: NSCCR
|
||||||
|
- name: PRIVCFGR
|
||||||
|
description: "FLASH privilege configuration register "
|
||||||
|
byte_offset: 60
|
||||||
|
fieldset: PRIVCFGR
|
||||||
|
- name: HDPEXTR
|
||||||
|
description: "FLASH HDP extension register "
|
||||||
|
byte_offset: 72
|
||||||
|
fieldset: HDPEXTR
|
||||||
|
- name: OPTSR_CUR
|
||||||
|
description: "FLASH option status register "
|
||||||
|
byte_offset: 80
|
||||||
|
fieldset: OPTSR
|
||||||
|
- name: OPTSR_PRG
|
||||||
|
description: "FLASH option status register "
|
||||||
|
byte_offset: 84
|
||||||
|
fieldset: OPTSR
|
||||||
|
- name: OPTSR2_CUR
|
||||||
|
description: "FLASH option status register 2 "
|
||||||
|
byte_offset: 112
|
||||||
|
fieldset: OPTSR2
|
||||||
|
- name: OPTSR2_PRG
|
||||||
|
description: "FLASH option status register 2 "
|
||||||
|
byte_offset: 116
|
||||||
|
fieldset: OPTSR2
|
||||||
|
- name: NSBOOTR_CUR
|
||||||
|
description: "FLASH non-secure unique boot entry register "
|
||||||
|
byte_offset: 128
|
||||||
|
fieldset: NSBOOTR
|
||||||
|
- name: NSBOOTR_PRG
|
||||||
|
description: "FLASH non-secure unique boot entry address "
|
||||||
|
byte_offset: 132
|
||||||
|
fieldset: NSBOOTR
|
||||||
|
- name: OTPBLR_CUR
|
||||||
|
description: "FLASH non-secure OTP block lock "
|
||||||
|
byte_offset: 144
|
||||||
|
fieldset: OTPBLR
|
||||||
|
- name: OTPBLR_PRG
|
||||||
|
description: "FLASH non-secure OTP block lock "
|
||||||
|
byte_offset: 148
|
||||||
|
fieldset: OTPBLR
|
||||||
|
- name: PRIVBB1R
|
||||||
|
description: "FLASH privilege register for bank 1 "
|
||||||
|
byte_offset: 192
|
||||||
|
fieldset: PRIVBB
|
||||||
|
- name: WRPSGN1R_CUR
|
||||||
|
description: "FLASH write sector protection for Bank1\t"
|
||||||
|
byte_offset: 232
|
||||||
|
fieldset: WRP
|
||||||
|
- name: WRPSGN1R_PRG
|
||||||
|
description: "FLASH write sector protection for Bank1\t"
|
||||||
|
byte_offset: 236
|
||||||
|
fieldset: WRP
|
||||||
|
- name: HDP1R_CUR
|
||||||
|
description: "FLASH HDP Bank1 register "
|
||||||
|
byte_offset: 248
|
||||||
|
fieldset: HDP1R
|
||||||
|
- name: HDP1R_PRG
|
||||||
|
description: "FLASH HDP Bank1 register "
|
||||||
|
byte_offset: 252
|
||||||
|
fieldset: HDP1R
|
||||||
|
- name: ECCCORR
|
||||||
|
description: "FLASH Flash ECC correction register "
|
||||||
|
byte_offset: 256
|
||||||
|
fieldset: ECCCORR
|
||||||
|
- name: ECCDETR
|
||||||
|
description: "FLASH ECC detection register "
|
||||||
|
byte_offset: 260
|
||||||
|
fieldset: ECCDETR
|
||||||
|
- name: ECCDR
|
||||||
|
description: "FLASH ECC data "
|
||||||
|
byte_offset: 264
|
||||||
|
fieldset: ECCDR
|
||||||
|
- name: WRPSGN2R_CUR
|
||||||
|
description: "FLASH write sector protection for Bank2\t"
|
||||||
|
byte_offset: 488
|
||||||
|
fieldset: WRP
|
||||||
|
- name: WRPSGN2R_PRG
|
||||||
|
description: "FLASH write sector protection for Bank2\t"
|
||||||
|
byte_offset: 492
|
||||||
|
fieldset: WRP
|
||||||
|
- name: HDP2R_CUR
|
||||||
|
description: "FLASH HDP Bank2 register "
|
||||||
|
byte_offset: 504
|
||||||
|
fieldset: HDP2R
|
||||||
|
- name: HDP2R_PRG
|
||||||
|
description: "FLASH HDP Bank2 register "
|
||||||
|
byte_offset: 508
|
||||||
|
fieldset: HDP2R
|
||||||
|
fieldset/ACR:
|
||||||
|
description: "FLASH access control register "
|
||||||
|
fields:
|
||||||
|
- name: LATENCY
|
||||||
|
description: "Read latency\r These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions.\r ...\r Note: No check is performed by hardware to verify that the configuration is correct."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: WRHIGHFREQ
|
||||||
|
description: "Flash signal delay\r These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to for details.\r Note: No check is performed to verify that the configuration is correct.\r Two WRHIGHFREQ values can be selected for some frequencies."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
- name: PRFTEN
|
||||||
|
description: "Prefetch enable. When bit value is modified, user must read back ACR register to be sure PRFTEN has been taken into account.\r Bits used to control the prefetch."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: S_PRFTEN
|
||||||
|
description: "Smart prefetch enable. When bit value is modified, user must read back ACR register to be sure S_PRFTEN has been taken into account.\r Bits used to control the prefetch functionality."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/ECCCORR:
|
||||||
|
description: "FLASH Flash ECC correction register "
|
||||||
|
fields:
|
||||||
|
- name: ADDR_ECC
|
||||||
|
description: "ECC error address\r When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
- name: BK_ECC
|
||||||
|
description: "ECC bank flag for corrected ECC error\r It indicates which bank is concerned by ECC error"
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: SYSF_ECC
|
||||||
|
description: "ECC flag for corrected ECC error in system FLASH\r It indicates if system Flash memory is concerned by ECC error."
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
- name: OTP_ECC
|
||||||
|
description: "OTP ECC error bit\r This bit is set to 1 when one single ECC correction occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bitfield."
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: ECCCIE
|
||||||
|
description: "ECC single correction error interrupt enable bit When ECCCIE bit is set to 1, an interrupt is generated when an ECC single correction error occurs during a read operation."
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
- name: ECCC
|
||||||
|
description: "ECC correction set by hardware when single ECC error has been detected and corrected.\r Cleared by writing 1."
|
||||||
|
bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/ECCDETR:
|
||||||
|
description: "FLASH ECC detection register "
|
||||||
|
fields:
|
||||||
|
- name: ADDR_ECC
|
||||||
|
description: "ECC error address\r When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
- name: BK_ECC
|
||||||
|
description: "ECC fail bank for double ECC Error\r It indicates which bank is concerned by ECC error"
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: SYSF_ECC
|
||||||
|
description: "ECC fail for double ECC error in system Flash memory\r It indicates if system Flash memory is concerned by ECC error."
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
- name: OTP_ECC
|
||||||
|
description: "OTP ECC error bit\r This bit is set to 1 when double ECC detection occurred during the last read operation from the read-only/ OTP area. The address of the ECC error is available in ADDR_ECC bit field."
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: ECCD
|
||||||
|
description: "ECC detection set by hardware when two ECC error has been detected.\r When this bit is set, a NMI is generated.\r Cleared by writing 1. Needs to be cleared in order to detect subsequent double ECC errors."
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/ECCDR:
|
||||||
|
description: "FLASH ECC data "
|
||||||
|
fields:
|
||||||
|
- name: DATA_ECC
|
||||||
|
description: "ECC error data\r When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register.\r By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/HDP1R:
|
||||||
|
description: "FLASH HDP Bank1 register "
|
||||||
|
fields:
|
||||||
|
- name: HDP1_STRT
|
||||||
|
description: HDPL barrier start set in number of 8 Kbytes sectors
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: HDP1_END
|
||||||
|
description: HDPL barrier end set in number of 8 Kbytes sectors
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
fieldset/HDP2R:
|
||||||
|
description: "FLASH HDP Bank2 register "
|
||||||
|
fields:
|
||||||
|
- name: HDP2_STRT
|
||||||
|
description: Bank 2 HDPL barrier start set in number of 8 Kbytes sectors
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: HDP2_END
|
||||||
|
description: Bank 2 HDPL barrier end set in number of 8 Kbytes sectors
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
fieldset/HDPEXTR:
|
||||||
|
description: "FLASH HDP extension register "
|
||||||
|
fields:
|
||||||
|
- name: HDP1_EXT
|
||||||
|
description: HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector.
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
- name: HDP2_EXT
|
||||||
|
description: HDP area extension in 8 Kbytes sectors in Bank2. Extension is added after the HDP2_END sector.
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 3
|
||||||
|
fieldset/NSBOOTR:
|
||||||
|
description: "FLASH non-secure unique boot entry register "
|
||||||
|
fields:
|
||||||
|
- name: NSBOOT_LOCK
|
||||||
|
description: "A field locking the values of SWAP_BANK, and NSBOOTADD settings."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: NSBOOTR_NSBOOT_LOCK
|
||||||
|
- name: NSBOOTADD
|
||||||
|
description: "unique boot entry address\r These bits reflect the UBE address"
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 24
|
||||||
|
fieldset/NSCCR:
|
||||||
|
description: "FLASH non-secure clear control register "
|
||||||
|
fields:
|
||||||
|
- name: CLR_EOP
|
||||||
|
description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLR_WRPERR
|
||||||
|
description: "WRPERR flag clear bit\r Setting this bit to 1 resets to 0 WRPERR flag in FLASH_NSSR register."
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLR_PGSERR
|
||||||
|
description: "PGSERR flag clear bit\r Setting this bit to 1 resets to 0 PGSERR flag in FLASH_NSSR register."
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLR_STRBERR
|
||||||
|
description: "STRBERR flag clear bit\r Setting this bit to 1 resets to 0 STRBERR flag in FLASH_NSSR register."
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLR_INCERR
|
||||||
|
description: "INCERR flag clear bit\r Setting this bit to 1 resets to 0 INCERR flag in FLASH_NSSR register."
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: CLR_OPTCHANGEERR
|
||||||
|
description: Clear the flag corresponding flag in FLASH_NSSR by writing this bit.
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/NSCR:
|
||||||
|
description: "FLASH Non Secure control register "
|
||||||
|
fields:
|
||||||
|
- name: LOCK
|
||||||
|
description: "configuration lock bit\r This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset.\r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: PG
|
||||||
|
description: "programming control bit\r PG can be programmed only when LOCK is cleared to 0.\r PG allows programming in Bank1 and Bank2."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: SER
|
||||||
|
description: "sector erase request\r Setting SER bit to 1 requests a sector erase. SER can be programmed only when LOCK is cleared to 0.\r If MER and SER are also set, a PGSERR is raised."
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: BER
|
||||||
|
description: "erase request\r Setting BER bit to 1 requests a bank erase operation (user Flash memory only). BER can be programmed only when LOCK is cleared to 0.\r If MER and SER are also set, a PGSERR is raised.\r Note: Write protection error is triggered when a bank erase is required and some sectors are protected."
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: FW
|
||||||
|
description: "write forcing control bit\r FW forces a write operation even if the write buffer is not full. In this case all bits not written are set to 1 by hardware. FW can be programmed only when LOCK is cleared to 0.\r The embedded Flash memory resets FW when the corresponding operation has been acknowledged.\r Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it leads to permanent ECC error.\r Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively).\r Since there is just one write buffer, FW can force a write in bank1 or bank2."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
- name: STRT
|
||||||
|
description: "erase start control bit\r STRT bit is used to start a sector erase or a bank erase operation. STRT can be programmed only when LOCK is cleared to 0.\r STRT is reset at the end of the operation or when an error occurs. It cannot be reseted by software."
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: SNB
|
||||||
|
description: "sector erase selection number\r These bits are used to select the target sector for an erase operation (they are unused otherwise). SNB can be programmed only when LOCK is cleared to 0.\r ..."
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 3
|
||||||
|
- name: MER
|
||||||
|
description: "Mass erase request\r Setting MER bit to 1 requests a mass erase operation (user Flash memory only). MER can be programmed only when LOCK is cleared to 0.\r If BER or SER are both set, a PGSERR is raised.\r Error is triggered when a mass erase is required and some sectors are protected."
|
||||||
|
bit_offset: 15
|
||||||
|
bit_size: 1
|
||||||
|
- name: EOPIE
|
||||||
|
description: "end of operation interrupt control bit\r Setting EOPIE bit to 1 enables the generation of an interrupt at the end of a program or erase operation. EOPIE can be programmed only when LOCK is cleared to 0."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: WRPERRIE
|
||||||
|
description: "write protection error interrupt enable bit\r When WRPERRIE bit is set to 1, an interrupt is generated when a protection error occurs during a program operation. WRPERRIE can be programmed only when LOCK is cleared to 0."
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: PGSERRIE
|
||||||
|
description: "programming sequence error interrupt enable bit\r When PGSERRIE bit is set to 1, an interrupt is generated when a sequence error occurs during a program operation. PGSERRIE can be programmed only when LOCK is cleared to 0."
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: STRBERRIE
|
||||||
|
description: "strobe error interrupt enable bit\r When STRBERRIE bit is set to 1, an interrupt is generated when a strobe error occurs (the master programs several times the same byte in the write buffer) during a write operation. STRBERRIE can be programmed only when LOCK is cleared to 0."
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: INCERRIE
|
||||||
|
description: "inconsistency error interrupt enable bit\r When INCERRIE bit is set to 1, an interrupt is generated when an inconsistency error occurs during a write operation. INCERRIE can be programmed only when LOCK is cleared to 0."
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: OPTCHANGEERRIE
|
||||||
|
description: "Option byte change error interrupt enable bit\r OPTCHANGEERRIE bit controls if an interrupt has to be generated when an error occurs during an option byte change. This bit can be programmed only when LOCK bit is cleared to 0."
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
- name: BKSEL
|
||||||
|
description: "Bank selector bit\r BKSEL can only be programmed when LOCK is cleared to 0. The bit selects physical bank, SWAP_BANK setting is ignored."
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
enum: BKSEL
|
||||||
|
fieldset/NSKEYR:
|
||||||
|
description: "FLASH key register "
|
||||||
|
fields:
|
||||||
|
- name: NSKEY
|
||||||
|
description: Non-volatile memory configuration access unlock key
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/NSSR:
|
||||||
|
description: "FLASH non-secure status register "
|
||||||
|
fields:
|
||||||
|
- name: BSY
|
||||||
|
description: "busy flag\r BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: WBNE
|
||||||
|
description: "write buffer not empty flag\r WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_NSCR\r the embedded Flash memory detects an error that involves data loss\r This bit cannot be reset by software writing 0 directly. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: DBNE
|
||||||
|
description: "data buffer not empty flag\r DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free."
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: EOP
|
||||||
|
description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to 1. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_NSCCR register."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: WRPERR
|
||||||
|
description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_NSCCR register clears WRPERR."
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: PGSERR
|
||||||
|
description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_NSCCR register clears PGSERR."
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: STRBERR
|
||||||
|
description: "strobe error flag\r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_NSCCR register clears STRBERR."
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: INCERR
|
||||||
|
description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_NSCCR register clears INCERR."
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: OPTCHANGEERR
|
||||||
|
description: "Option byte change error flag\r OPTCHANGEERR flag indicates that an error occurred during an option byte change operation. When OPTCHANGEERR is set to 1, the option byte change operation did not successfully complete. An interrupt is generated when this flag is raised if the OPTCHANGEERRIE bit of FLASH_NSCR register is set to 1.\r Writing 1 to CLR_OPTCHANGEERR of register FLASH_CCR clears OPTCHANGEERR.\r Note: The OPTSTRT bit in FLASH_OPTCR cannot be set while OPTCHANGEERR is set."
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/OPSR:
|
||||||
|
description: "FLASH operation status register "
|
||||||
|
fields:
|
||||||
|
- name: ADDR_OP
|
||||||
|
description: Interrupted operation address.
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 20
|
||||||
|
- name: BK_OP
|
||||||
|
description: "Interrupted operation bank\r It indicates which bank was concerned by operation."
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: SYSF_OP
|
||||||
|
description: "Operation in system Flash memory interrupted\r Indicates that reset interrupted an ongoing operation in System Flash."
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
- name: OTP_OP
|
||||||
|
description: "OTP operation interrupted\r Indicates that reset interrupted an ongoing operation in OTP area."
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: CODE_OP
|
||||||
|
description: Flash memory operation code
|
||||||
|
bit_offset: 29
|
||||||
|
bit_size: 3
|
||||||
|
enum: CODE_OP
|
||||||
|
fieldset/OPTCR:
|
||||||
|
description: "FLASH option control register "
|
||||||
|
fields:
|
||||||
|
- name: OPTLOCK
|
||||||
|
description: "FLASH_OPTCR lock option configuration bit\r The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset.\r It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: OPTSTRT
|
||||||
|
description: "Option byte start change option configuration bit\r OPTSTRT triggers an option byte change operation. The user can set OPTSTRT only when the OPTLOCK bit is cleared to 0. It’s set only by Software and cleared when the option byte change is completed or an error occurs (PGSERR or OPTCHANGEERR). It’s reseted at the same time as BSY bit.\r The user application cannot modify any FLASH_XXX_PRG embedded Flash memory register until the option change operation has been completed.\r Before setting this bit, the user has to write the required values in the FLASH_XXX_PRG registers. The FLASH_XXX_PRG registers are locked until the option byte change operation has been executed in non-volatile memory."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: SWAP_BANK
|
||||||
|
description: "Bank swapping option configuration bit\r SWAP_BANK controls whether Bank1 and Bank2 are swapped or not. This bit is loaded with the SWAP_BANK bit of FLASH_OPTSR_CUR register only after reset or POR."
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTCR_SWAP_BANK
|
||||||
|
fieldset/OPTKEYR:
|
||||||
|
description: "FLASH option key register "
|
||||||
|
fields:
|
||||||
|
- name: OPTKEY
|
||||||
|
description: FLASH option bytes control access unlock key
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/OPTSR:
|
||||||
|
description: "FLASH option status register "
|
||||||
|
fields:
|
||||||
|
- name: BOR_LEV
|
||||||
|
description: "Brownout level option status bit\r These bits reflects the power level that generates a system reset."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 2
|
||||||
|
enum: OPTSR_BOR_LEV
|
||||||
|
- name: BORH_EN
|
||||||
|
description: Brownout high enable status bit
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: IWDG_SW
|
||||||
|
description: IWDG control mode option status bit
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_IWDG_SW
|
||||||
|
- name: WWDG_SW
|
||||||
|
description: WWDG control mode option status bit
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_WWDG_SW
|
||||||
|
- name: NRST_SHDW
|
||||||
|
description: Core domain Shutdown entry reset option status bit
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_NRST_SHDW
|
||||||
|
- name: NRST_STOP
|
||||||
|
description: Core domain Stop entry reset option status bit
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_NRST_STOP
|
||||||
|
- name: NRST_STDBY
|
||||||
|
description: Core domain Standby entry reset option status bit
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_NRST_STDBY
|
||||||
|
- name: PRODUCT_STATE
|
||||||
|
description: "Life state code (based on Hamming 8,4). More information in ."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: IO_VDD_HSLV
|
||||||
|
description: High-speed IO at low VDD voltage status bit. This bit can be set only with VDD below 2.5 V.
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_IO_VDD_HSLV
|
||||||
|
- name: IO_VDDIO2_HSLV
|
||||||
|
description: High-speed IO at low VDDIO2 voltage status bit. This bit can be set only with VDDIO2 below 2.5 V.
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_IO_VDDIO_HSLV
|
||||||
|
- name: IWDG_STOP
|
||||||
|
description: "IWDG Stop mode freeze option status bit\r When set the independent watchdog IWDG is in system Stop mode."
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_IWDG_STOP
|
||||||
|
- name: IWDG_STDBY
|
||||||
|
description: "IWDG Standby mode freeze option status bit\r When set the independent watchdog IWDG is frozen in system Standby mode."
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_IWDG_STDBY
|
||||||
|
- name: SWAP_BANK
|
||||||
|
description: "Bank swapping option status bit\r SWAP_BANK reflects whether Bank1 and Bank2 are swapped or not.\r SWAP_BANK is loaded to SWAP_BANK of FLASH_OPTCR after a reset."
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_SWAP_BANK
|
||||||
|
fieldset/OPTSR2:
|
||||||
|
description: "FLASH option status register 2 "
|
||||||
|
fields:
|
||||||
|
- name: SRAM2_RST
|
||||||
|
description: SRAM2 erase when system reset
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: BKPRAM_ECC
|
||||||
|
description: Backup RAM ECC detection and correction disable
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_BKPRAM_ECC
|
||||||
|
- name: SRAM2_ECC
|
||||||
|
description: SRAM2 ECC detection and correction disable
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_SRAM_ECC
|
||||||
|
- name: SRAM1_RST
|
||||||
|
description: SRAM1 erase upon system reset
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: SRAM1_ECC
|
||||||
|
description: SRAM1 ECC detection and correction disable
|
||||||
|
bit_offset: 10
|
||||||
|
bit_size: 1
|
||||||
|
enum: OPTSR_SRAM_ECC
|
||||||
|
fieldset/OTPBLR:
|
||||||
|
description: "FLASH non-secure OTP block lock "
|
||||||
|
fields:
|
||||||
|
- name: LOCKBL
|
||||||
|
description: "OTP block lock\r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it is not possible to remove the write protection.\r LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 32
|
||||||
|
fieldset/PRIVBB:
|
||||||
|
description: "FLASH privilege register for bank 1 "
|
||||||
|
fields:
|
||||||
|
- name: PRIVBB
|
||||||
|
description: Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7)
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: PRIVBB
|
||||||
|
fieldset/PRIVCFGR:
|
||||||
|
description: "FLASH privilege configuration register "
|
||||||
|
fields:
|
||||||
|
- name: NSPRIV
|
||||||
|
description: privilege attribute for non secure registers
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
enum: NSPRIV
|
||||||
|
fieldset/SECSR:
|
||||||
|
description: "FLASH secure status register "
|
||||||
|
fields:
|
||||||
|
- name: SECBSY
|
||||||
|
description: "busy flag\r BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: SECWBNE
|
||||||
|
description: "write buffer not empty flag\r WBNE flag is set when the embedded Flash memory is waiting for new data to complete the write buffer. In this state, the write buffer is not empty. WBNE is reset by hardware each time the write buffer is complete or the write buffer is emptied following one of the event below:\r the application software forces the write operation using FW bit in FLASH_SECCR\r the embedded Flash memory detects an error that involves data loss\r This bit cannot be reset by writing 0 directly by software. To reset it, clear the write buffer by performing any of the above listed actions, or send the missing data."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: SECDBNE
|
||||||
|
description: "data buffer not empty flag\r DBNE flag is set when the embedded Flash memory interface is processing 6-bits ECC data in dedicated buffer. This bit cannot be set to 0 by software. The hardware resets it once the buffer is free."
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: SECEOP
|
||||||
|
description: "end of operation flag\r EOP flag is set when a operation (program/erase) completes. An interrupt is generated if the EOPIE is set to. It is not necessary to reset EOP before starting a new operation. EOP bit is cleared by writing 1 to CLR_EOP bit in FLASH_SECCCR register."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: SECWRPERR
|
||||||
|
description: "write protection error flag\r WRPERR flag is raised when a protection error occurs during a program operation. An interrupt is also generated if the WRPERRIE is set to 1. Writing 1 to CLR_WRPERR bit in FLASH_SECCCR register clears WRPERR."
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: SECPGSERR
|
||||||
|
description: "programming sequence error flag\r PGSERR flag is raised when a sequence error occurs. An interrupt is generated if the PGSERRIE bit is set to 1. Writing 1 to CLR_PGSERR bit in FLASH_SECCCR register clears PGSERR."
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: SECSTRBERR
|
||||||
|
description: "strobe error flag\r STRBERR flag is raised when a strobe error occurs (when the master attempts to write several times the same byte in the write buffer). An interrupt is generated if the STRBERRIE bit is set to 1. Writing 1 to CLR_STRBERR bit in FLASH_SECCCR register clears STRBERR."
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: SECINCERR
|
||||||
|
description: "inconsistency error flag\r INCERR flag is raised when a inconsistency error occurs. An interrupt is generated if INCERRIE is set to 1. Writing 1 to CLR_INCERR bit in the FLASH_SECCCR register clears INCERR."
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/WRP:
|
||||||
|
description: "FLASH write sector protection for Bank2\t"
|
||||||
|
fields:
|
||||||
|
- name: WRPSG
|
||||||
|
description: "Bank2 sector protection option status byte\r Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected)"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum/BKSEL:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Bank1 is selected for Bank erase / sector erase / interrupt enable
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Bank2 is selected for BER / SER
|
||||||
|
value: 1
|
||||||
|
enum/CODE_OP:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: No Flash operation on going during previous reset
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "Single write operation interrupted "
|
||||||
|
value: 1
|
||||||
|
- name: B_0x3
|
||||||
|
description: Sector erase operation interrupted
|
||||||
|
value: 3
|
||||||
|
- name: B_0x4
|
||||||
|
description: "Bank erase operation interrupted "
|
||||||
|
value: 4
|
||||||
|
- name: B_0x5
|
||||||
|
description: Mass erase operation interrupted
|
||||||
|
value: 5
|
||||||
|
- name: B_0x6
|
||||||
|
description: Option change operation interrupted
|
||||||
|
value: 6
|
||||||
|
enum/NSBOOTR_NSBOOT_LOCK:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0xB4
|
||||||
|
description: The NSBOOTADD and SWAP_BANK are frozen.
|
||||||
|
value: 180
|
||||||
|
- name: B_0xC3
|
||||||
|
description: The SWAP_BANK and NSBOOTADD can still be modified following their individual rules.
|
||||||
|
value: 195
|
||||||
|
enum/NSPRIV:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: access to non secure registers is always granted
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: access to non secure registers is denied in case of non privileged access.
|
||||||
|
value: 1
|
||||||
|
enum/OPTCR_SWAP_BANK:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Bank1 and Bank2 not swapped
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Bank1 and Bank2 swapped
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_BKPRAM_ECC:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "BKPRAM ECC check enabled "
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: BKPRAM ECC check disabled
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_BOR_LEV:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "BOR OFF, POR/PDR reset threshold level is applied"
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "BOR Level 1, the threshold level is low (around 2.1 V)"
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: "BOR Level 2, the threshold level is medium (around 2.4 V)"
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: "BOR Level 3, the threshold level is high (around 2.7 V)"
|
||||||
|
value: 3
|
||||||
|
enum/OPTSR_IO_VDDIO_HSLV:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) "
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) "
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_IO_VDD_HSLV:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) "
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) "
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_IWDG_STDBY:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Independent watchdog frozen in Standby mode
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Independent watchdog keep running in Standby mode.
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_IWDG_STOP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Independent watchdog frozen in system Stop mode
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Independent watchdog keep running in system Stop mode.
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_IWDG_SW:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: IWDG watchdog is controlled by hardware
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: IWDG watchdog is controlled by software
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_NRST_SHDW:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: a reset is generated when entering Shutdown mode on core domain
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "no reset generated when entering Shutdown mode on core domain. "
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_NRST_STDBY:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: a reset is generated when entering Standby mode on core domain
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "no reset generated when entering Standby mode on core domain. "
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_NRST_STOP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: a reset is generated when entering Stop mode on core domain
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: no reset generated when entering Stop mode on core domain.
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_SRAM_ECC:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "SRAM2 ECC check enabled "
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: SRAM2 ECC check disabled
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_SWAP_BANK:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Bank1 and Bank2 not swapped
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Bank1 and Bank2 swapped
|
||||||
|
value: 1
|
||||||
|
enum/OPTSR_WWDG_SW:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: WWDG watchdog is controlled by hardware
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: WWDG watchdog is controlled by software
|
||||||
|
value: 1
|
||||||
|
enum/PRIVBB:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: sectors y in bank 1 is non privileged
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: sector y in bank 1 is privileged
|
||||||
|
value: 1
|
||||||
582
data/registers/pwr_h5.yaml
Normal file
582
data/registers/pwr_h5.yaml
Normal file
@ -0,0 +1,582 @@
|
|||||||
|
---
|
||||||
|
block/PWR:
|
||||||
|
description: Power control
|
||||||
|
items:
|
||||||
|
- name: PMCR
|
||||||
|
description: PWR power mode control register
|
||||||
|
byte_offset: 0
|
||||||
|
fieldset: PMCR
|
||||||
|
- name: PMSR
|
||||||
|
description: PWR status register
|
||||||
|
byte_offset: 4
|
||||||
|
fieldset: PMSR
|
||||||
|
- name: VOSCR
|
||||||
|
description: PWR voltage scaling control register
|
||||||
|
byte_offset: 16
|
||||||
|
fieldset: VOSCR
|
||||||
|
- name: VOSSR
|
||||||
|
description: PWR voltage scaling status register
|
||||||
|
byte_offset: 20
|
||||||
|
fieldset: VOSSR
|
||||||
|
- name: BDCR
|
||||||
|
description: PWR Backup domain control register
|
||||||
|
byte_offset: 32
|
||||||
|
fieldset: BDCR
|
||||||
|
- name: DBPCR
|
||||||
|
description: PWR Backup domain control register
|
||||||
|
byte_offset: 36
|
||||||
|
fieldset: DBPCR
|
||||||
|
- name: BDSR
|
||||||
|
description: PWR Backup domain status register
|
||||||
|
byte_offset: 40
|
||||||
|
fieldset: BDSR
|
||||||
|
- name: UCPDR
|
||||||
|
description: PWR USB Type-C power delivery register
|
||||||
|
byte_offset: 44
|
||||||
|
fieldset: UCPDR
|
||||||
|
- name: SCCR
|
||||||
|
description: PWR supply configuration control register
|
||||||
|
byte_offset: 48
|
||||||
|
fieldset: SCCR
|
||||||
|
- name: VMCR
|
||||||
|
description: PWR voltage monitor control register
|
||||||
|
byte_offset: 52
|
||||||
|
fieldset: VMCR
|
||||||
|
- name: USBSCR
|
||||||
|
description: PWR USB supply control register
|
||||||
|
byte_offset: 56
|
||||||
|
fieldset: USBSCR
|
||||||
|
- name: VMSR
|
||||||
|
description: PWR voltage monitor status register
|
||||||
|
byte_offset: 60
|
||||||
|
fieldset: VMSR
|
||||||
|
- name: WUSCR
|
||||||
|
description: PWR wakeup status clear register
|
||||||
|
byte_offset: 64
|
||||||
|
fieldset: WUSCR
|
||||||
|
- name: WUSR
|
||||||
|
description: PWR wakeup status register
|
||||||
|
byte_offset: 68
|
||||||
|
fieldset: WUSR
|
||||||
|
- name: WUCR
|
||||||
|
description: PWR wakeup configuration register
|
||||||
|
byte_offset: 72
|
||||||
|
fieldset: WUCR
|
||||||
|
- name: IORETR
|
||||||
|
description: PWR I/O retention register
|
||||||
|
byte_offset: 80
|
||||||
|
fieldset: IORETR
|
||||||
|
- name: SECCFGR
|
||||||
|
description: PWR security configuration register
|
||||||
|
byte_offset: 256
|
||||||
|
fieldset: SECCFGR
|
||||||
|
- name: PRIVCFGR
|
||||||
|
description: PWR privilege configuration register
|
||||||
|
byte_offset: 260
|
||||||
|
fieldset: PRIVCFGR
|
||||||
|
fieldset/BDCR:
|
||||||
|
description: PWR Backup domain control register
|
||||||
|
fields:
|
||||||
|
- name: BREN
|
||||||
|
description: "Backup RAM retention in Standby and V<sub>BAT</sub> modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V<sub>BAT</sub> modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and V<sub>BAT</sub> modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V<sub>BAT</sub> modes."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: MONEN
|
||||||
|
description: Backup domain voltage and temperature monitoring enable
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBE
|
||||||
|
description: "V<sub>BAT</sub> charging enable\r Note: Reset only by POR,."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBRS
|
||||||
|
description: V<sub>BAT</sub> charging resistor selection
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
enum: VBRS
|
||||||
|
fieldset/BDSR:
|
||||||
|
description: PWR Backup domain status register
|
||||||
|
fields:
|
||||||
|
- name: BRRDY
|
||||||
|
description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBATL
|
||||||
|
description: V<sub>BAT</sub> level monitoring versus low threshold
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBATH
|
||||||
|
description: V<sub>BAT</sub> level monitoring versus high threshold
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
- name: TEMPL
|
||||||
|
description: temperature level monitoring versus low threshold
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: TEMPH
|
||||||
|
description: temperature level monitoring versus high threshold
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/DBPCR:
|
||||||
|
description: PWR Backup domain control register
|
||||||
|
fields:
|
||||||
|
- name: DBP
|
||||||
|
description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/IORETR:
|
||||||
|
description: PWR I/O retention register
|
||||||
|
fields:
|
||||||
|
- name: IORETEN
|
||||||
|
description: "IO retention enable:\r When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: JTAGIORETEN
|
||||||
|
description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode"
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PMCR:
|
||||||
|
description: PWR power mode control register
|
||||||
|
fields:
|
||||||
|
- name: LPMS
|
||||||
|
description: "low-power mode selection\r This bit defines the Deepsleep mode."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: SVOS
|
||||||
|
description: "system Stop mode voltage scaling selection\r These bits control the V<sub>CORE</sub> voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance."
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 2
|
||||||
|
enum: SVOS
|
||||||
|
- name: CSSF
|
||||||
|
description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware."
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: FLPS
|
||||||
|
description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: BOOSTE
|
||||||
|
description: "analog switch V<sub>BOOST</sub> control\r This bit enables the booster to guarantee the analog switch AC performance when the V<sub>DD</sub> supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V<sub>DD</sub> supply voltage can be monitored through the PVD and the PLS bits."
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 1
|
||||||
|
- name: AVD_READY
|
||||||
|
description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected V<sub>DDA</sub> analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)."
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
- name: ETHERNETSO
|
||||||
|
description: ETHERNET RAM shut-off in Stop mode.
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: SRAM3SO
|
||||||
|
description: AHB SRAM3 shut-off in Stop mode.
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
- name: SRAM2_16SO
|
||||||
|
description: AHB SRAM2 16-Kbyte shut-off in Stop mode.
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: SRAM2_48SO
|
||||||
|
description: AHB SRAM2 48-Kbyte shut-off in Stop mode.
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
- name: SRAM1SO
|
||||||
|
description: AHB SRAM1 shut-off in Stop mode
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PMSR:
|
||||||
|
description: PWR status register
|
||||||
|
fields:
|
||||||
|
- name: STOPF
|
||||||
|
description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit."
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: SBF
|
||||||
|
description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit."
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PRIVCFGR:
|
||||||
|
description: PWR privilege configuration register
|
||||||
|
fields:
|
||||||
|
- name: SPRIV
|
||||||
|
description: "PWR secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
enum: PRIV
|
||||||
|
- name: NSPRIV
|
||||||
|
description: "PWR non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
enum: PRIV
|
||||||
|
fieldset/SCCR:
|
||||||
|
description: PWR supply configuration control register
|
||||||
|
fields:
|
||||||
|
- name: BYPASS
|
||||||
|
description: power management unit bypass
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: LDOEN
|
||||||
|
description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: SMPSEN
|
||||||
|
description: "SMPS enable \r The value is set by hardware when the package uses the SMPS regulator."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/SECCFGR:
|
||||||
|
description: PWR security configuration register
|
||||||
|
fields:
|
||||||
|
- name: WUP1SEC
|
||||||
|
description: WUPx secure protection
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: WUP2SEC
|
||||||
|
description: WUPx secure protection
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: WUP3SEC
|
||||||
|
description: WUPx secure protection
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: WUP4SEC
|
||||||
|
description: WUPx secure protection
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: WUP5SEC
|
||||||
|
description: WUPx secure protection
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: WUP6SEC
|
||||||
|
description: WUPx secure protection
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: WUP7SEC
|
||||||
|
description: WUPx secure protection
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: WUP8SEC
|
||||||
|
description: WUPx secure protection
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: RETSEC
|
||||||
|
description: retention secure protection
|
||||||
|
bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: LPMSEC
|
||||||
|
description: low-power modes secure protection
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: SCMSEC
|
||||||
|
description: supply configuration and monitoring secure protection.
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: VBSEC
|
||||||
|
description: backup domain secure protection
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: VUSBSEC
|
||||||
|
description: voltage USB secure protection
|
||||||
|
bit_offset: 15
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
fieldset/UCPDR:
|
||||||
|
description: PWR USB Type-C power delivery register
|
||||||
|
fields:
|
||||||
|
- name: UCPD_DBDIS
|
||||||
|
description: "USB Type-C and power delivery dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable)."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: UCPD_STBY
|
||||||
|
description: "USB Type-c and Power delivery Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/USBSCR:
|
||||||
|
description: PWR USB supply control register
|
||||||
|
fields:
|
||||||
|
- name: USB33DEN
|
||||||
|
description: V<sub>DDUSB</sub> voltage level detector enable
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
- name: USB33SV
|
||||||
|
description: "independent USB supply valid\r This bit is used to validate the V<sub>DDUSB</sub> supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If V<sub>DDUSB</sub> is not always present in the application, the V<sub>DDUSB</sub> voltage monitor can be used to determine whether this supply is ready or not."
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/VMCR:
|
||||||
|
description: PWR voltage monitor control register
|
||||||
|
fields:
|
||||||
|
- name: PVDE
|
||||||
|
description: PVD enable
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: PLS
|
||||||
|
description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 3
|
||||||
|
enum: PLS
|
||||||
|
- name: AVDEN
|
||||||
|
description: peripheral voltage monitor on V<sub>DDA</sub> enable
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: ALS
|
||||||
|
description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 2
|
||||||
|
enum: ALS
|
||||||
|
fieldset/VMSR:
|
||||||
|
description: PWR voltage monitor status register
|
||||||
|
fields:
|
||||||
|
- name: AVDO
|
||||||
|
description: "analog voltage detector output on V<sub>DDA</sub>\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set."
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
enum: AVDO
|
||||||
|
- name: VDDIO2RDY
|
||||||
|
description: "voltage detector output on V<sub>DDIO2</sub>\r This bit is set and cleared by hardware."
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: PVDO
|
||||||
|
description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set."
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
enum: PVDO
|
||||||
|
- name: USB33RDY
|
||||||
|
description: V<sub>DDUSB</sub> ready
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/VOSCR:
|
||||||
|
description: PWR voltage scaling control register
|
||||||
|
fields:
|
||||||
|
- name: VOS
|
||||||
|
description: "voltage scaling selection according to performance\r These bits control the V<sub>CORE</sub> voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
enum: VOS
|
||||||
|
fieldset/VOSSR:
|
||||||
|
description: PWR voltage scaling status register
|
||||||
|
fields:
|
||||||
|
- name: VOSRDY
|
||||||
|
description: Ready bit for V<sub>CORE</sub> voltage scaling output selection.
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: ACTVOSRDY
|
||||||
|
description: Voltage level ready for currently used VOS
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
- name: ACTVOS
|
||||||
|
description: "voltage output scaling currently applied to V<sub>CORE</sub>\r This field provides the last VOS value."
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 2
|
||||||
|
enum: ACTVOS
|
||||||
|
fieldset/WUCR:
|
||||||
|
description: PWR wakeup configuration register
|
||||||
|
fields:
|
||||||
|
- name: WUPPUPD
|
||||||
|
description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 2
|
||||||
|
array:
|
||||||
|
len: 8
|
||||||
|
stride: 2
|
||||||
|
enum: WUPPUPD
|
||||||
|
- name: WUPEN
|
||||||
|
description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 8
|
||||||
|
stride: 1
|
||||||
|
- name: WUPP
|
||||||
|
description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 8
|
||||||
|
stride: 1
|
||||||
|
enum: WUPP
|
||||||
|
fieldset/WUSCR:
|
||||||
|
description: PWR wakeup status clear register
|
||||||
|
fields:
|
||||||
|
- name: CWUF
|
||||||
|
description: "clear wakeup pin flag for WUFx\r These bits are always read as 0."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 8
|
||||||
|
stride: 1
|
||||||
|
fieldset/WUSR:
|
||||||
|
description: PWR wakeup status register
|
||||||
|
fields:
|
||||||
|
- name: WUF
|
||||||
|
description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 8
|
||||||
|
stride: 1
|
||||||
|
enum/ACTVOS:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: VOS3 (lowest power)
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: VOS2
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: VOS1
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: VOS0 (highest frequency)
|
||||||
|
value: 3
|
||||||
|
enum/ALS:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: 1.7 V
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: 2.1 V
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: 2.5 V
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: 2.8 V
|
||||||
|
value: 3
|
||||||
|
enum/AVDO:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "V<sub>DDA</sub> is equal or higher than the AVD threshold selected with the ALS[2:0] bits."
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "V<sub>DDA</sub> is lower than the AVD threshold selected with the ALS[2:0] bits."
|
||||||
|
value: 1
|
||||||
|
enum/PLS:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: 1.95 V
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: 2.1 V
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: 2.25 V
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: 2.4 V
|
||||||
|
value: 3
|
||||||
|
- name: B_0x4
|
||||||
|
description: 2.55 V
|
||||||
|
value: 4
|
||||||
|
- name: B_0x5
|
||||||
|
description: 2.7 V
|
||||||
|
value: 5
|
||||||
|
- name: B_0x6
|
||||||
|
description: 2.85 V
|
||||||
|
value: 6
|
||||||
|
- name: B_0x7
|
||||||
|
description: PVD_IN pin
|
||||||
|
value: 7
|
||||||
|
enum/PRIV:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Read and write to PWR secure functions can be done by privileged or unprivileged access.
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Read and write to PWR secure functions can be done by privileged access only.
|
||||||
|
value: 1
|
||||||
|
enum/PVDO:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "V<sub>DD</sub> is equal or higher than the PVD threshold selected through the PLS[2:0] bits."
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "V<sub>DD</sub> is lower than the PVD threshold selected through the PLS[2:0] bits."
|
||||||
|
value: 1
|
||||||
|
enum/SEC:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: PWR_SCCR and PWR_VMCR can be read and written with secure or non-secure access.
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: PWR_SCCR and PWR_VMCR can be read and written only with secure access.
|
||||||
|
value: 1
|
||||||
|
enum/SVOS:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: reserved
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: SVOS5 scale 5
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: SVOS4 scale 4
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: SVOS3 scale 3 (default).
|
||||||
|
value: 3
|
||||||
|
enum/VBRS:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Charge V<sub>BAT</sub> through a 5 kΩ resistor.
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Charge V<sub>BAT</sub> through a 1.5 kΩ resistor.
|
||||||
|
value: 1
|
||||||
|
enum/VOS:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: scale 3 (default)
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: scale 2
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: scale 1
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: scale 0
|
||||||
|
value: 3
|
||||||
|
enum/WUPP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: detection on high level (rising edge)
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: detection on low level (falling edge)
|
||||||
|
value: 1
|
||||||
|
enum/WUPPUPD:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: no pull-up
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: pull-up
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: pull-down
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: reserved
|
||||||
|
value: 3
|
||||||
446
data/registers/pwr_h50.yaml
Normal file
446
data/registers/pwr_h50.yaml
Normal file
@ -0,0 +1,446 @@
|
|||||||
|
---
|
||||||
|
block/PWR:
|
||||||
|
description: Power control
|
||||||
|
items:
|
||||||
|
- name: PMCR
|
||||||
|
description: PWR power mode control register
|
||||||
|
byte_offset: 0
|
||||||
|
fieldset: PMCR
|
||||||
|
- name: PMSR
|
||||||
|
description: PWR status register
|
||||||
|
byte_offset: 4
|
||||||
|
fieldset: PMSR
|
||||||
|
- name: VOSCR
|
||||||
|
description: PWR voltage scaling control register
|
||||||
|
byte_offset: 16
|
||||||
|
fieldset: VOSCR
|
||||||
|
- name: VOSSR
|
||||||
|
description: PWR voltage scaling status register
|
||||||
|
byte_offset: 20
|
||||||
|
fieldset: VOSSR
|
||||||
|
- name: BDCR
|
||||||
|
description: PWR Backup domain control register
|
||||||
|
byte_offset: 32
|
||||||
|
fieldset: BDCR
|
||||||
|
- name: DBPCR
|
||||||
|
description: PWR disable backup protection control register
|
||||||
|
byte_offset: 36
|
||||||
|
fieldset: DBPCR
|
||||||
|
- name: BDSR
|
||||||
|
description: PWR Backup domain status register
|
||||||
|
byte_offset: 40
|
||||||
|
fieldset: BDSR
|
||||||
|
- name: SCCR
|
||||||
|
description: PWR supply configuration control register
|
||||||
|
byte_offset: 48
|
||||||
|
fieldset: SCCR
|
||||||
|
- name: VMCR
|
||||||
|
description: PWR voltage monitor control register
|
||||||
|
byte_offset: 52
|
||||||
|
fieldset: VMCR
|
||||||
|
- name: VMSR
|
||||||
|
description: PWR voltage monitor status register
|
||||||
|
byte_offset: 60
|
||||||
|
fieldset: VMSR
|
||||||
|
- name: WUSCR
|
||||||
|
description: PWR wakeup status clear register
|
||||||
|
byte_offset: 64
|
||||||
|
fieldset: WUSCR
|
||||||
|
- name: WUSR
|
||||||
|
description: PWR wakeup status register
|
||||||
|
byte_offset: 68
|
||||||
|
fieldset: WUSR
|
||||||
|
- name: WUCR
|
||||||
|
description: PWR wakeup configuration register
|
||||||
|
byte_offset: 72
|
||||||
|
fieldset: WUCR
|
||||||
|
- name: IORETR
|
||||||
|
description: PWR I/O retention register
|
||||||
|
byte_offset: 80
|
||||||
|
fieldset: IORETR
|
||||||
|
- name: PRIVCFGR
|
||||||
|
description: PWR privilege configuration register
|
||||||
|
byte_offset: 260
|
||||||
|
fieldset: PRIVCFGR
|
||||||
|
fieldset/BDCR:
|
||||||
|
description: PWR Backup domain control register
|
||||||
|
fields:
|
||||||
|
- name: BREN
|
||||||
|
description: "Backup RAM retention in Standby and V<sub>BAT</sub> modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and V<sub>BAT</sub> modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and V<sub>BAT</sub> modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and V<sub>BAT</sub> modes."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: MONEN
|
||||||
|
description: Backup domain voltage and temperature monitoring enable
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBE
|
||||||
|
description: "V<sub>BAT</sub> charging enable\r Note: Reset only by POR,."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBRS
|
||||||
|
description: V<sub>BAT</sub> charging resistor selection
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
enum: VBRS
|
||||||
|
fieldset/BDSR:
|
||||||
|
description: PWR Backup domain status register
|
||||||
|
fields:
|
||||||
|
- name: BRRDY
|
||||||
|
description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBATL
|
||||||
|
description: V<sub>BAT</sub> level monitoring versus low threshold
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: VBATH
|
||||||
|
description: V<sub>BAT</sub> level monitoring versus high threshold
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
- name: TEMPL
|
||||||
|
description: temperature level monitoring versus low threshold
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
- name: TEMPH
|
||||||
|
description: temperature level monitoring versus high threshold
|
||||||
|
bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/DBPCR:
|
||||||
|
description: PWR disable backup protection control register
|
||||||
|
fields:
|
||||||
|
- name: DBP
|
||||||
|
description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/IORETR:
|
||||||
|
description: PWR I/O retention register
|
||||||
|
fields:
|
||||||
|
- name: IORETEN
|
||||||
|
description: "IO retention enable:\r When entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: JTAGIORETEN
|
||||||
|
description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and applied to the output IO during the standby power mode"
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PMCR:
|
||||||
|
description: PWR power mode control register
|
||||||
|
fields:
|
||||||
|
- name: LPMS
|
||||||
|
description: "low-power mode selection\r This bit defines the Deepsleep mode."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: SVOS
|
||||||
|
description: "system Stop mode voltage scaling selection\r These bits control the V<sub>CORE</sub> voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance."
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 2
|
||||||
|
enum: SVOS
|
||||||
|
- name: CSSF
|
||||||
|
description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware."
|
||||||
|
bit_offset: 7
|
||||||
|
bit_size: 1
|
||||||
|
- name: FLPS
|
||||||
|
description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: BOOSTE
|
||||||
|
description: "analog switch V<sub>BOOST</sub> control\r This bit enables the booster to guarantee the analog switch AC performance when the V<sub>DD</sub> supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The V<sub>DD</sub> supply voltage can be monitored through the PVD and the PLS bits."
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 1
|
||||||
|
- name: AVD_READY
|
||||||
|
description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected V<sub>DDA</sub> analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)."
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
- name: SRAM2SO
|
||||||
|
description: AHB SRAM2 shut-off in Stop mode.
|
||||||
|
bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
- name: SRAM1SO
|
||||||
|
description: AHB SRAM1 shut-off in Stop mode
|
||||||
|
bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PMSR:
|
||||||
|
description: PWR status register
|
||||||
|
fields:
|
||||||
|
- name: STOPF
|
||||||
|
description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit."
|
||||||
|
bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
- name: SBF
|
||||||
|
description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit."
|
||||||
|
bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PRIVCFGR:
|
||||||
|
description: PWR privilege configuration register
|
||||||
|
fields:
|
||||||
|
- name: NSPRIV
|
||||||
|
description: "PWR functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
enum: PRIV
|
||||||
|
fieldset/SCCR:
|
||||||
|
description: PWR supply configuration control register
|
||||||
|
fields:
|
||||||
|
- name: BYPASS
|
||||||
|
description: power management unit bypass
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: LDOEN
|
||||||
|
description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/VMCR:
|
||||||
|
description: PWR voltage monitor control register
|
||||||
|
fields:
|
||||||
|
- name: PVDE
|
||||||
|
description: PVD enable
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: PLS
|
||||||
|
description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 3
|
||||||
|
enum: PLS
|
||||||
|
- name: AVDEN
|
||||||
|
description: peripheral voltage monitor on V<sub>DDA</sub> enable
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: ALS
|
||||||
|
description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 2
|
||||||
|
enum: ALS
|
||||||
|
fieldset/VMSR:
|
||||||
|
description: PWR voltage monitor status register
|
||||||
|
fields:
|
||||||
|
- name: AVDO
|
||||||
|
description: "analog voltage detector output on V<sub>DDA</sub>\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set."
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
enum: AVDO
|
||||||
|
- name: VDDIO2RDY
|
||||||
|
description: "voltage detector output on V<sub>DDIO2</sub>\r This bit is set and cleared by hardware."
|
||||||
|
bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
- name: PVDO
|
||||||
|
description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set."
|
||||||
|
bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
enum: PVDO
|
||||||
|
fieldset/VOSCR:
|
||||||
|
description: PWR voltage scaling control register
|
||||||
|
fields:
|
||||||
|
- name: VOS
|
||||||
|
description: "voltage scaling selection according to performance\r These bits control the V<sub>CORE</sub> voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 2
|
||||||
|
enum: VOS
|
||||||
|
fieldset/VOSSR:
|
||||||
|
description: PWR voltage scaling status register
|
||||||
|
fields:
|
||||||
|
- name: VOSRDY
|
||||||
|
description: Ready bit for V<sub>CORE</sub> voltage scaling output selection.
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
- name: ACTVOSRDY
|
||||||
|
description: Voltage level ready for currently used VOS
|
||||||
|
bit_offset: 13
|
||||||
|
bit_size: 1
|
||||||
|
- name: ACTVOS
|
||||||
|
description: "voltage output scaling currently applied to V<sub>CORE</sub>\r This field provides the last VOS value."
|
||||||
|
bit_offset: 14
|
||||||
|
bit_size: 2
|
||||||
|
enum: ACTVOS
|
||||||
|
fieldset/WUCR:
|
||||||
|
description: PWR wakeup configuration register
|
||||||
|
fields:
|
||||||
|
- name: WUPEN
|
||||||
|
description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 5
|
||||||
|
stride: 1
|
||||||
|
- name: WUPP
|
||||||
|
description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 5
|
||||||
|
stride: 1
|
||||||
|
enum: WUPP
|
||||||
|
- name: WUPPUPD
|
||||||
|
description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 2
|
||||||
|
array:
|
||||||
|
len: 5
|
||||||
|
stride: 2
|
||||||
|
enum: WUPPUPD
|
||||||
|
fieldset/WUSCR:
|
||||||
|
description: PWR wakeup status clear register
|
||||||
|
fields:
|
||||||
|
- name: CWUF
|
||||||
|
description: "clear wakeup pin flag for WUFx\r These bits are always read as 0."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 5
|
||||||
|
stride: 1
|
||||||
|
fieldset/WUSR:
|
||||||
|
description: PWR wakeup status register
|
||||||
|
fields:
|
||||||
|
- name: WUF
|
||||||
|
description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 5
|
||||||
|
stride: 1
|
||||||
|
enum/ACTVOS:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: VOS3 (lowest power)
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: VOS2
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: VOS1
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: VOS0 (highest frequency)
|
||||||
|
value: 3
|
||||||
|
enum/ALS:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: 1.7 V
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: 2.1 V
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: 2.5 V
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: 2.8 V
|
||||||
|
value: 3
|
||||||
|
enum/AVDO:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "V<sub>DDA</sub> is equal or higher than the AVD threshold selected with the ALS[2:0] bits."
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "V<sub>DDA</sub> is lower than the AVD threshold selected with the ALS[2:0] bits."
|
||||||
|
value: 1
|
||||||
|
enum/PLS:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: 1.95 V
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: 2.1 V
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: 2.25 V
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: 2.4 V
|
||||||
|
value: 3
|
||||||
|
- name: B_0x4
|
||||||
|
description: 2.55 V
|
||||||
|
value: 4
|
||||||
|
- name: B_0x5
|
||||||
|
description: 2.7 V
|
||||||
|
value: 5
|
||||||
|
- name: B_0x6
|
||||||
|
description: 2.85 V
|
||||||
|
value: 6
|
||||||
|
- name: B_0x7
|
||||||
|
description: PVD_IN pin
|
||||||
|
value: 7
|
||||||
|
enum/PRIV:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Read and write to PWR functions can be done by privileged or unprivileged access.
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Read and write to PWR functions can be done by privileged access only.
|
||||||
|
value: 1
|
||||||
|
enum/PVDO:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: "V<sub>DD</sub> is equal or higher than the PVD threshold selected through the PLS[2:0] bits."
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: "V<sub>DD</sub> is lower than the PVD threshold selected through the PLS[2:0] bits."
|
||||||
|
value: 1
|
||||||
|
enum/SVOS:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: reserved
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: SVOS5 scale 5
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: SVOS4 scale 4
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: SVOS3 scale 3 (default).
|
||||||
|
value: 3
|
||||||
|
enum/VBRS:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: Charge V<sub>BAT</sub> through a 5 kΩ resistor.
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: Charge V<sub>BAT</sub> through a 1.5 kΩ resistor.
|
||||||
|
value: 1
|
||||||
|
enum/VOS:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: scale 3 (default)
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: scale 2
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: scale 1
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: scale 0
|
||||||
|
value: 3
|
||||||
|
enum/WUPP:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: detection on high level (rising edge)
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: detection on low level (falling edge)
|
||||||
|
value: 1
|
||||||
|
enum/WUPPUPD:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: no pull-up
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: pull-up
|
||||||
|
value: 1
|
||||||
|
- name: B_0x2
|
||||||
|
description: pull-down
|
||||||
|
value: 2
|
||||||
|
- name: B_0x3
|
||||||
|
description: reserved
|
||||||
|
value: 3
|
||||||
@ -475,7 +475,7 @@ fieldset/AHB3ENR:
|
|||||||
description: Flexible static memory controller module clock enable
|
description: Flexible static memory controller module clock enable
|
||||||
bit_offset: 0
|
bit_offset: 0
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
- name: QSPIEN
|
- name: QUADSPIEN
|
||||||
description: QUADSPI memory controller module clock enable
|
description: QUADSPI memory controller module clock enable
|
||||||
bit_offset: 1
|
bit_offset: 1
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
|
|||||||
@ -425,7 +425,7 @@ fieldset/AHB3ENR:
|
|||||||
description: Flexible memory controller clock enable
|
description: Flexible memory controller clock enable
|
||||||
bit_offset: 0
|
bit_offset: 0
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
- name: QSPIEN
|
- name: QUADSPIEN
|
||||||
description: QUADSPI memory interface clock enable
|
description: QUADSPI memory interface clock enable
|
||||||
bit_offset: 8
|
bit_offset: 8
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
|
|||||||
2754
data/registers/rcc_h5.yaml
Normal file
2754
data/registers/rcc_h5.yaml
Normal file
File diff suppressed because it is too large
Load Diff
1748
data/registers/rcc_h50.yaml
Normal file
1748
data/registers/rcc_h50.yaml
Normal file
File diff suppressed because it is too large
Load Diff
@ -551,7 +551,7 @@ fieldset/AHB3ENR:
|
|||||||
description: FMC Peripheral Clocks Enable
|
description: FMC Peripheral Clocks Enable
|
||||||
bit_offset: 12
|
bit_offset: 12
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
- name: QSPIEN
|
- name: QUADSPIEN
|
||||||
description: QUADSPI and QUADSPI Delay Clock Enable
|
description: QUADSPI and QUADSPI Delay Clock Enable
|
||||||
bit_offset: 14
|
bit_offset: 14
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
@ -1959,7 +1959,7 @@ fieldset/C1_AHB3ENR:
|
|||||||
description: FMC Peripheral Clocks Enable
|
description: FMC Peripheral Clocks Enable
|
||||||
bit_offset: 12
|
bit_offset: 12
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
- name: QSPIEN
|
- name: QUADSPIEN
|
||||||
description: QUADSPI and QUADSPI Delay Clock Enable
|
description: QUADSPI and QUADSPI Delay Clock Enable
|
||||||
bit_offset: 14
|
bit_offset: 14
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
|
|||||||
@ -487,7 +487,7 @@ fieldset/AHB3ENR:
|
|||||||
description: FMC Peripheral Clocks Enable
|
description: FMC Peripheral Clocks Enable
|
||||||
bit_offset: 12
|
bit_offset: 12
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
- name: QSPIEN
|
- name: QUADSPIEN
|
||||||
description: QUADSPI and QUADSPI Delay Clock Enable
|
description: QUADSPI and QUADSPI Delay Clock Enable
|
||||||
bit_offset: 14
|
bit_offset: 14
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
|
|||||||
@ -473,8 +473,8 @@ fieldset/AHB3ENR:
|
|||||||
description: Flexible memory controller clock enable
|
description: Flexible memory controller clock enable
|
||||||
bit_offset: 0
|
bit_offset: 0
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
- name: QSPIEN
|
- name: QUADSPIEN
|
||||||
description: QSPIEN
|
description: QUADSPIEN
|
||||||
bit_offset: 8
|
bit_offset: 8
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
- name: OSPI2EN
|
- name: OSPI2EN
|
||||||
|
|||||||
@ -377,8 +377,8 @@ fieldset/AHB2SMENR:
|
|||||||
fieldset/AHB3ENR:
|
fieldset/AHB3ENR:
|
||||||
description: AHB3 peripheral clock enable register
|
description: AHB3 peripheral clock enable register
|
||||||
fields:
|
fields:
|
||||||
- name: QSPIEN
|
- name: QUADSPIEN
|
||||||
description: QSPIEN
|
description: QUADSPIEN
|
||||||
bit_offset: 8
|
bit_offset: 8
|
||||||
bit_size: 1
|
bit_size: 1
|
||||||
- name: PKAEN
|
- name: PKAEN
|
||||||
|
|||||||
410
data/registers/sbs_h5.yaml
Normal file
410
data/registers/sbs_h5.yaml
Normal file
@ -0,0 +1,410 @@
|
|||||||
|
---
|
||||||
|
block/SBS:
|
||||||
|
description: SBS register block
|
||||||
|
items:
|
||||||
|
- name: HDPLCR
|
||||||
|
description: "SBS temporal isolation control register "
|
||||||
|
byte_offset: 16
|
||||||
|
fieldset: HDPLCR
|
||||||
|
- name: HDPLSR
|
||||||
|
description: "SBS temporal isolation status register "
|
||||||
|
byte_offset: 20
|
||||||
|
fieldset: HDPLSR
|
||||||
|
- name: NEXTHDPLCR
|
||||||
|
description: "SBS next HDPL control register "
|
||||||
|
byte_offset: 24
|
||||||
|
fieldset: NEXTHDPLCR
|
||||||
|
- name: DBGCR
|
||||||
|
description: "SBS debug control register "
|
||||||
|
byte_offset: 32
|
||||||
|
fieldset: DBGCR
|
||||||
|
- name: DBGLOCKR
|
||||||
|
description: "SBS debug lock register "
|
||||||
|
byte_offset: 36
|
||||||
|
fieldset: DBGLOCKR
|
||||||
|
- name: RSSCMDR
|
||||||
|
description: "SBS RSS command register "
|
||||||
|
byte_offset: 52
|
||||||
|
fieldset: RSSCMDR
|
||||||
|
- name: EPOCHSELCR
|
||||||
|
description: "SBS EPOCH selection control register "
|
||||||
|
byte_offset: 160
|
||||||
|
fieldset: EPOCHSELCR
|
||||||
|
- name: SECCFGR
|
||||||
|
description: "SBS security mode configuration control register "
|
||||||
|
byte_offset: 192
|
||||||
|
fieldset: SECCFGR
|
||||||
|
- name: PMCR
|
||||||
|
description: "SBS product mode and configuration register "
|
||||||
|
byte_offset: 256
|
||||||
|
fieldset: PMCR
|
||||||
|
- name: FPUIMR
|
||||||
|
description: "SBS FPU interrupt mask register "
|
||||||
|
byte_offset: 260
|
||||||
|
fieldset: FPUIMR
|
||||||
|
- name: MESR
|
||||||
|
description: "SBS memory erase status register "
|
||||||
|
byte_offset: 264
|
||||||
|
fieldset: MESR
|
||||||
|
- name: CCCSR
|
||||||
|
description: "SBS compensation cell for I/Os control and status register\t"
|
||||||
|
byte_offset: 272
|
||||||
|
fieldset: CCCSR
|
||||||
|
- name: CCVALR
|
||||||
|
description: "SBS compensation cell for I/Os value register "
|
||||||
|
byte_offset: 276
|
||||||
|
fieldset: CCVALR
|
||||||
|
- name: CCSWCR
|
||||||
|
description: "SBS compensation cell for I/Os software code register\t"
|
||||||
|
byte_offset: 280
|
||||||
|
fieldset: CCSWCR
|
||||||
|
- name: CFGR2
|
||||||
|
description: "SBS Class B register "
|
||||||
|
byte_offset: 288
|
||||||
|
fieldset: CFGR2
|
||||||
|
- name: CNSLCKR
|
||||||
|
description: "SBS CPU non-secure lock register "
|
||||||
|
byte_offset: 324
|
||||||
|
fieldset: CNSLCKR
|
||||||
|
- name: CSLCKR
|
||||||
|
description: "SBS CPU secure lock register "
|
||||||
|
byte_offset: 328
|
||||||
|
fieldset: CSLCKR
|
||||||
|
- name: ECCNMIR
|
||||||
|
description: "SBS flift ECC NMI mask register "
|
||||||
|
byte_offset: 332
|
||||||
|
fieldset: ECCNMIR
|
||||||
|
fieldset/CCCSR:
|
||||||
|
description: "SBS compensation cell for I/Os control and status register\t"
|
||||||
|
fields:
|
||||||
|
- name: EN
|
||||||
|
description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 2
|
||||||
|
- name: RDY
|
||||||
|
description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
- name: CS
|
||||||
|
description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 2
|
||||||
|
enum: CS
|
||||||
|
fieldset/CCSWCR:
|
||||||
|
description: "SBS compensation cell for I/Os software code register\t"
|
||||||
|
fields:
|
||||||
|
- name: SW_ANSRC1
|
||||||
|
description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: SW_APSRC1
|
||||||
|
description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 4
|
||||||
|
- name: SW_ANSRC2
|
||||||
|
description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 4
|
||||||
|
- name: SW_APSRC2
|
||||||
|
description: "PMOS compensation code for the VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR."
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 4
|
||||||
|
fieldset/CCVALR:
|
||||||
|
description: "SBS compensation cell for I/Os value register "
|
||||||
|
fields:
|
||||||
|
- name: ANSRC1
|
||||||
|
description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: APSRC1
|
||||||
|
description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 4
|
||||||
|
- name: ANSRC2
|
||||||
|
description: "Compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 4
|
||||||
|
- name: APSRC2
|
||||||
|
description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 4
|
||||||
|
fieldset/CFGR2:
|
||||||
|
description: "SBS Class B register "
|
||||||
|
fields:
|
||||||
|
- name: CLL
|
||||||
|
description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: SEL
|
||||||
|
description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: PVDL
|
||||||
|
description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs."
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: ECCL
|
||||||
|
description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1/8/15/6/17."
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CNSLCKR:
|
||||||
|
description: "SBS CPU non-secure lock register "
|
||||||
|
fields:
|
||||||
|
- name: LOCKNSVTOR
|
||||||
|
description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: LOCKNSMPU
|
||||||
|
description: "non-secure MPU register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CSLCKR:
|
||||||
|
description: "SBS CPU secure lock register "
|
||||||
|
fields:
|
||||||
|
- name: LOCKSVTAIRCR
|
||||||
|
description: "VTOR_S and AIRCR register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: LOCKSMPU
|
||||||
|
description: "secure MPU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: LOCKSAU
|
||||||
|
description: "SAU registers lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers."
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/DBGCR:
|
||||||
|
description: "SBS debug control register "
|
||||||
|
fields:
|
||||||
|
- name: AP_UNLOCK
|
||||||
|
description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
- name: DBG_UNLOCK
|
||||||
|
description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: DBG_AUTH_HDPL
|
||||||
|
description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 8
|
||||||
|
enum: DBG_AUTH_HDPL
|
||||||
|
- name: DBG_AUTH_SEC
|
||||||
|
description: "control debug opening secure/non-secure\r Write 0xB4 to this bitfield to open debug for secure and non-secure.\r Writing any other values only open non-secure."
|
||||||
|
bit_offset: 24
|
||||||
|
bit_size: 8
|
||||||
|
fieldset/DBGLOCKR:
|
||||||
|
description: "SBS debug lock register "
|
||||||
|
fields:
|
||||||
|
- name: DBGCFG_LOCK
|
||||||
|
description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: DBGCFG_LOCK
|
||||||
|
fieldset/ECCNMIR:
|
||||||
|
description: "SBS flift ECC NMI mask register "
|
||||||
|
fields:
|
||||||
|
- name: ECCNMI_MASK_EN
|
||||||
|
description: NMI behavior setup when a double ECC error occurs on flitf data part
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/EPOCHSELCR:
|
||||||
|
description: "SBS EPOCH selection control register "
|
||||||
|
fields:
|
||||||
|
- name: EPOCH_SEL
|
||||||
|
description: "select EPOCH value to be sent to the SAES\r 1x: EPOCH forced to zero (value used to retrieve PUF reference value at boot time)"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 2
|
||||||
|
enum: EPOCH_SEL
|
||||||
|
fieldset/FPUIMR:
|
||||||
|
description: "SBS FPU interrupt mask register "
|
||||||
|
fields:
|
||||||
|
- name: FPU_IE
|
||||||
|
description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 6
|
||||||
|
fieldset/HDPLCR:
|
||||||
|
description: "SBS temporal isolation control register "
|
||||||
|
fields:
|
||||||
|
- name: INCR_HDPL
|
||||||
|
description: "increment HDPL value\r Other: all other values allow a HDPL level increment."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: INCR_HDPL
|
||||||
|
fieldset/HDPLSR:
|
||||||
|
description: "SBS temporal isolation status register "
|
||||||
|
fields:
|
||||||
|
- name: HDPL
|
||||||
|
description: "temporal isolation level\r This bitfield returns the current temporal isolation level."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: HDPL
|
||||||
|
fieldset/MESR:
|
||||||
|
description: "SBS memory erase status register "
|
||||||
|
fields:
|
||||||
|
- name: MCLR
|
||||||
|
description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, DCACHE, ICACHE and PKA. It is set by hardware and reset by software"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: IPMEE
|
||||||
|
description: "end-of-erase status for ICACHE and PKA RAM\r This bit shows the status of the protection for ICACHE and PKA. It is set by hardware and reset by software."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/NEXTHDPLCR:
|
||||||
|
description: "SBS next HDPL control register "
|
||||||
|
fields:
|
||||||
|
- name: NEXTHDPL
|
||||||
|
description: "index to point to a higher HDPL than the current one\r Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas (OBK-HDPL = HDPL + NEXTHDPL). See for more details."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 2
|
||||||
|
fieldset/PMCR:
|
||||||
|
description: "SBS product mode and configuration register "
|
||||||
|
fields:
|
||||||
|
- name: BOOSTEN
|
||||||
|
description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: BOOSTVDDSEL
|
||||||
|
description: "booster VDD selection\r Note: Booster must not be used when VDDA < 2.7 V, but VDD > 2.7 V (add current consumption).\r When both VDD < 2.7 V and VDDA < 2.7 V, booster is needed to get full AC performances from I/O analog switches."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: PB6_FMPLUS
|
||||||
|
description: Fast-mode Plus command on PB(6)
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: PB7_FMPLUS
|
||||||
|
description: Fast-mode Plus command on PB(7)
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: PB8_FMPLUS
|
||||||
|
description: Fast-mode Plus command on PB(8)
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
- name: PB9_FMPLUS
|
||||||
|
description: Fast-mode Plus command on PB(9)
|
||||||
|
bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
- name: ETH_SEL_PHY
|
||||||
|
description: "Ethernet PHY interface selection\r Other: reserved"
|
||||||
|
bit_offset: 21
|
||||||
|
bit_size: 3
|
||||||
|
enum: ETH_SEL_PHY
|
||||||
|
fieldset/RSSCMDR:
|
||||||
|
description: "SBS RSS command register "
|
||||||
|
fields:
|
||||||
|
- name: RSSCMD
|
||||||
|
description: "RSS command\r The application can use this bitfield to pass on a command to the RSS, executed at the next reset.\r When RSSCMD ≠ 0 and PRODUCT_STATE is in Open, then the system always boots on RSS whatever is the boot pin value."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 16
|
||||||
|
fieldset/SECCFGR:
|
||||||
|
description: "SBS security mode configuration control register "
|
||||||
|
fields:
|
||||||
|
- name: SBSSEC
|
||||||
|
description: "SBS clock control, memory-erase status register and compensation cell register security enable"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: CLASSBSEC
|
||||||
|
description: ClassB security enable
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: FPUSEC
|
||||||
|
description: "FPU security enable\r Note: This bit can only be written through privilege transaction."
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
enum: SEC
|
||||||
|
- name: SDCE_SEC_EN
|
||||||
|
description: control accessibility of SMPS_DIV_CLOCK _EN in SBS_PMCR
|
||||||
|
bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
enum/CS:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Cell
|
||||||
|
description: Code from the cell (available in the SBS_CCVR)
|
||||||
|
value: 0
|
||||||
|
- name: Software
|
||||||
|
description: "Code from SBS_CCCR "
|
||||||
|
value: 1
|
||||||
|
enum/DBGCFG_LOCK:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0xB4
|
||||||
|
description: Writes to SBS_DBGCR allowed (default)
|
||||||
|
value: 180
|
||||||
|
enum/DBG_AUTH_HDPL:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0x51
|
||||||
|
description: HDPL1
|
||||||
|
value: 81
|
||||||
|
- name: B_0x6F
|
||||||
|
description: HDPL3
|
||||||
|
value: 111
|
||||||
|
- name: B_0x8A
|
||||||
|
description: HDPL2
|
||||||
|
value: 138
|
||||||
|
enum/EPOCH_SEL:
|
||||||
|
bit_size: 2
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: SEC_EPOCH counter input selected
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: NS_EPOCH (non-secure) input selected
|
||||||
|
value: 1
|
||||||
|
enum/ETH_SEL_PHY:
|
||||||
|
bit_size: 3
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: GMII or MII
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: reserved (RGMII)
|
||||||
|
value: 1
|
||||||
|
- name: B_0x4
|
||||||
|
description: RMII
|
||||||
|
value: 4
|
||||||
|
enum/HDPL:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0x51
|
||||||
|
description: "HDPL1, iRoT"
|
||||||
|
value: 81
|
||||||
|
- name: B_0x6F
|
||||||
|
description: "HDPL3, application (secure/non-secure)"
|
||||||
|
value: 111
|
||||||
|
- name: B_0x8A
|
||||||
|
description: "HDPL2, uRoT"
|
||||||
|
value: 138
|
||||||
|
- name: B_0xB4
|
||||||
|
description: "HDPL0, RSS"
|
||||||
|
value: 180
|
||||||
|
enum/INCR_HDPL:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0x6A
|
||||||
|
description: recommended value to increment HDPL level by one
|
||||||
|
value: 106
|
||||||
|
- name: B_0xB4
|
||||||
|
description: no increment
|
||||||
|
value: 180
|
||||||
|
enum/SEC:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: B_0x0
|
||||||
|
description: SBS_CFGR2 register accessible through secure or non-secure transaction
|
||||||
|
value: 0
|
||||||
|
- name: B_0x1
|
||||||
|
description: SBS_CFGR2 register only accessible through secure transaction
|
||||||
|
value: 1
|
||||||
288
data/registers/sbs_h50.yaml
Normal file
288
data/registers/sbs_h50.yaml
Normal file
@ -0,0 +1,288 @@
|
|||||||
|
---
|
||||||
|
block/SBS:
|
||||||
|
description: "System configuration, boot and security"
|
||||||
|
items:
|
||||||
|
- name: HDPLCR
|
||||||
|
description: SBS temporal isolation control register
|
||||||
|
byte_offset: 16
|
||||||
|
fieldset: HDPLCR
|
||||||
|
- name: HDPLSR
|
||||||
|
description: SBS temporal isolation status register
|
||||||
|
byte_offset: 20
|
||||||
|
fieldset: HDPLSR
|
||||||
|
- name: DBGCR
|
||||||
|
description: SBS debug control register
|
||||||
|
byte_offset: 32
|
||||||
|
fieldset: DBGCR
|
||||||
|
- name: DBGLOCKR
|
||||||
|
description: SBS debug lock register
|
||||||
|
byte_offset: 36
|
||||||
|
fieldset: DBGLOCKR
|
||||||
|
- name: PMCR
|
||||||
|
description: SBS product mode and configuration register
|
||||||
|
byte_offset: 256
|
||||||
|
fieldset: PMCR
|
||||||
|
- name: FPUIMR
|
||||||
|
description: SBS FPU interrupt mask register
|
||||||
|
byte_offset: 260
|
||||||
|
fieldset: FPUIMR
|
||||||
|
- name: MESR
|
||||||
|
description: SBS memory erase status register
|
||||||
|
byte_offset: 264
|
||||||
|
fieldset: MESR
|
||||||
|
- name: CCCSR
|
||||||
|
description: SBS compensation cell for I/Os control and status register
|
||||||
|
byte_offset: 272
|
||||||
|
fieldset: CCCSR
|
||||||
|
- name: CCVALR
|
||||||
|
description: SBS compensation cell for I/Os value register
|
||||||
|
byte_offset: 276
|
||||||
|
fieldset: CCVALR
|
||||||
|
- name: CCSWCR
|
||||||
|
description: SBS compensation cell for I/Os software code register
|
||||||
|
byte_offset: 280
|
||||||
|
fieldset: CCSWCR
|
||||||
|
- name: CFGR2
|
||||||
|
description: SBS Class B register
|
||||||
|
byte_offset: 288
|
||||||
|
fieldset: CFGR2
|
||||||
|
- name: CNSLCKR
|
||||||
|
description: SBS CPU lock register
|
||||||
|
byte_offset: 324
|
||||||
|
fieldset: CNSLCKR
|
||||||
|
- name: ECCNMIR
|
||||||
|
description: SBS flift ECC NMI mask register
|
||||||
|
byte_offset: 332
|
||||||
|
fieldset: ECCNMIR
|
||||||
|
fieldset/CCCSR:
|
||||||
|
description: SBS compensation cell for I/Os control and status register
|
||||||
|
fields:
|
||||||
|
- name: RDY
|
||||||
|
description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 1
|
||||||
|
- name: CS
|
||||||
|
description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 2
|
||||||
|
enum: CS
|
||||||
|
- name: EN
|
||||||
|
description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
array:
|
||||||
|
len: 2
|
||||||
|
stride: 2
|
||||||
|
fieldset/CCSWCR:
|
||||||
|
description: SBS compensation cell for I/Os software code register
|
||||||
|
fields:
|
||||||
|
- name: SW_ANSRC1
|
||||||
|
description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: SW_APSRC1
|
||||||
|
description: "PMOS compensation code for the VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 4
|
||||||
|
- name: SW_ANSRC2
|
||||||
|
description: "NMOS compensation code for VDDIO power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 4
|
||||||
|
- name: SW_APSRC2
|
||||||
|
description: "PMOS compensation code for the V<sub>DDIO</sub> power rails\r This bitfield is written by software to define an I/O compensation cell code for PMOS transistors of the VDDIO power rail. This code is applied to the I/O when CS2 is set in SBS_CCSR."
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 4
|
||||||
|
fieldset/CCVALR:
|
||||||
|
description: SBS compensation cell for I/Os value register
|
||||||
|
fields:
|
||||||
|
- name: ANSRC1
|
||||||
|
description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 4
|
||||||
|
- name: APSRC1
|
||||||
|
description: "compensation value for the PMOS transistor \r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
|
||||||
|
bit_offset: 4
|
||||||
|
bit_size: 4
|
||||||
|
- name: ANSRC2
|
||||||
|
description: "Compensation value for the NMOS transistor \r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 4
|
||||||
|
- name: APSRC2
|
||||||
|
description: "compensation value for the PMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range."
|
||||||
|
bit_offset: 12
|
||||||
|
bit_size: 4
|
||||||
|
fieldset/CFGR2:
|
||||||
|
description: SBS Class B register
|
||||||
|
fields:
|
||||||
|
- name: CLL
|
||||||
|
description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1 break inputs."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: SEL
|
||||||
|
description: "SRAM ECC error lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
- name: PVDL
|
||||||
|
description: "PVD lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1 break inputs."
|
||||||
|
bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
- name: ECCL
|
||||||
|
description: "ECC lock\r This bit is set and cleared by software. It can be used to enable and lock the Flash memory double ECC error with break input of TIM1."
|
||||||
|
bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/CNSLCKR:
|
||||||
|
description: SBS CPU lock register
|
||||||
|
fields:
|
||||||
|
- name: LOCKNSVTOR
|
||||||
|
description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: LOCKNSMPU
|
||||||
|
description: "MPU register lock \r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers."
|
||||||
|
bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/DBGCR:
|
||||||
|
description: SBS debug control register
|
||||||
|
fields:
|
||||||
|
- name: AP_UNLOCK
|
||||||
|
description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
- name: DBG_UNLOCK
|
||||||
|
description: "debug unlock when DBG_AUTH_HDPL is reached\r Write 0xB4 to this bitfield to open the debug when HDPL in SBS_HDPLSR equals to DBG_AUTH_HDPL in this register."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 8
|
||||||
|
- name: DBG_AUTH_HDPL
|
||||||
|
description: "authenticated debug temporal isolation level\r Writing to this bitfield defines at which HDPL the authenticated debug opens.\r Note: Writing any other values is ignored. Reading any other value means the debug never opens."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 8
|
||||||
|
enum: DBG_AUTH_HDPL
|
||||||
|
fieldset/DBGLOCKR:
|
||||||
|
description: SBS debug lock register
|
||||||
|
fields:
|
||||||
|
- name: DBGCFG_LOCK
|
||||||
|
description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: DBGCFG_LOCK
|
||||||
|
fieldset/ECCNMIR:
|
||||||
|
description: SBS flift ECC NMI mask register
|
||||||
|
fields:
|
||||||
|
- name: ECCNMI_MASK_EN
|
||||||
|
description: NMI behavior setup when a double ECC error occurs on flitf data part
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/FPUIMR:
|
||||||
|
description: SBS FPU interrupt mask register
|
||||||
|
fields:
|
||||||
|
- name: FPU_IE
|
||||||
|
description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 6
|
||||||
|
fieldset/HDPLCR:
|
||||||
|
description: SBS temporal isolation control register
|
||||||
|
fields:
|
||||||
|
- name: INCR_HDPL
|
||||||
|
description: "increment HDPL value\r Other: all other values allow a HDPL level increment."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: INCR_HDPL
|
||||||
|
fieldset/HDPLSR:
|
||||||
|
description: SBS temporal isolation status register
|
||||||
|
fields:
|
||||||
|
- name: HDPL
|
||||||
|
description: "temporal isolation level\r This bitfield returns the current temporal isolation level."
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
enum: HDPL
|
||||||
|
fieldset/MESR:
|
||||||
|
description: SBS memory erase status register
|
||||||
|
fields:
|
||||||
|
- name: MCLR
|
||||||
|
description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, ICACHE. It is set by hardware and reset by software"
|
||||||
|
bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
- name: IPMEE
|
||||||
|
description: "end-of-erase status for ICACHE\r This bit shows the status of the protection for ICACHE. It is set by hardware and reset by software."
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
fieldset/PMCR:
|
||||||
|
description: SBS product mode and configuration register
|
||||||
|
fields:
|
||||||
|
- name: BOOSTEN
|
||||||
|
description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range."
|
||||||
|
bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
- name: BOOSTVDDSEL
|
||||||
|
description: "booster V<sub>DD</sub> selection\r Note: Booster must not be used when V<sub>DDA</sub> < 2.7 V, but V<sub>DD</sub> > 2.7 V (add current consumption).\r Note: When both V<sub>DD</sub> < 2.7 V and V<sub>DDA</sub> < 2.7 V, booster is needed to get full AC performances from I/O analog switches."
|
||||||
|
bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
- name: PB6_FMPLUS
|
||||||
|
description: Fast-mode Plus command on PB(6)
|
||||||
|
bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
- name: PB7_FMPLUS
|
||||||
|
description: Fast-mode Plus command on PB(7)
|
||||||
|
bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
- name: PB8_FMPLUS
|
||||||
|
description: Fast-mode Plus command on PB(8)
|
||||||
|
bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
enum/CS:
|
||||||
|
bit_size: 1
|
||||||
|
variants:
|
||||||
|
- name: Cell
|
||||||
|
description: Code from the cell (available in SBS_CCVR)
|
||||||
|
value: 0
|
||||||
|
- name: Software
|
||||||
|
description: Code from SBS_CCCR
|
||||||
|
value: 1
|
||||||
|
enum/DBGCFG_LOCK:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0xB4
|
||||||
|
description: Writes to SBS_DBGCR allowed (default)
|
||||||
|
value: 180
|
||||||
|
enum/DBG_AUTH_HDPL:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0x51
|
||||||
|
description: HDPL1
|
||||||
|
value: 81
|
||||||
|
- name: B_0x6F
|
||||||
|
description: HDPL3
|
||||||
|
value: 111
|
||||||
|
- name: B_0x8A
|
||||||
|
description: HDPL2
|
||||||
|
value: 138
|
||||||
|
enum/HDPL:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0x51
|
||||||
|
description: "HDPL1, iRoT"
|
||||||
|
value: 81
|
||||||
|
- name: B_0x6F
|
||||||
|
description: "HDPL3, application"
|
||||||
|
value: 111
|
||||||
|
- name: B_0x8A
|
||||||
|
description: "HDPL2, uRoT"
|
||||||
|
value: 138
|
||||||
|
- name: B_0xB4
|
||||||
|
description: "HDPL0, RSS"
|
||||||
|
value: 180
|
||||||
|
enum/INCR_HDPL:
|
||||||
|
bit_size: 8
|
||||||
|
variants:
|
||||||
|
- name: B_0x6A
|
||||||
|
description: recommended value to increment HDPL level by one
|
||||||
|
value: 106
|
||||||
|
- name: B_0xB4
|
||||||
|
description: no increment
|
||||||
|
value: 180
|
||||||
@ -22,3 +22,5 @@ serde_json = "1.0.94"
|
|||||||
rayon = { version = "1.7.0", optional = true }
|
rayon = { version = "1.7.0", optional = true }
|
||||||
stm32-data-serde = { version = "0.1.0", path = "../stm32-data-serde" }
|
stm32-data-serde = { version = "0.1.0", path = "../stm32-data-serde" }
|
||||||
ref_thread_local = "0.1.1"
|
ref_thread_local = "0.1.1"
|
||||||
|
log = "0.4.17"
|
||||||
|
pretty_env_logger = "0.4.0"
|
||||||
|
|||||||
@ -84,6 +84,8 @@ fn chip_name_from_package_name(x: &str) -> String {
|
|||||||
(regex!("^(STM32L0....).xS$"), "$1"),
|
(regex!("^(STM32L0....).xS$"), "$1"),
|
||||||
(regex!("^(STM32H7....).xQ$"), "$1"),
|
(regex!("^(STM32H7....).xQ$"), "$1"),
|
||||||
(regex!("^(STM32U5....).xQ$"), "$1"),
|
(regex!("^(STM32U5....).xQ$"), "$1"),
|
||||||
|
(regex!("^(STM32H5....).xQ$"), "$1"),
|
||||||
|
(regex!("^(STM32WBA....).x$"), "$1"),
|
||||||
(regex!("^(STM32......).x$"), "$1"),
|
(regex!("^(STM32......).x$"), "$1"),
|
||||||
];
|
];
|
||||||
|
|
||||||
@ -184,6 +186,8 @@ impl PeriMatcher {
|
|||||||
("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")),
|
("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")),
|
||||||
("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")),
|
("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")),
|
||||||
("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")),
|
("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")),
|
||||||
|
("STM32H50.*:SBS:.*", ("sbs", "h50", "SBS")),
|
||||||
|
("STM32H5.*:SBS:.*", ("sbs", "h5", "SBS")),
|
||||||
(".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")),
|
(".*:IWDG:iwdg1_v1_1", ("iwdg", "v1", "IWDG")),
|
||||||
(".*:IWDG:iwdg1_v2_0", ("iwdg", "v2", "IWDG")),
|
(".*:IWDG:iwdg1_v2_0", ("iwdg", "v2", "IWDG")),
|
||||||
(".*:WWDG:wwdg1_v1_0", ("wwdg", "v1", "WWDG")),
|
(".*:WWDG:wwdg1_v1_0", ("wwdg", "v1", "WWDG")),
|
||||||
@ -244,6 +248,8 @@ impl PeriMatcher {
|
|||||||
("STM32L4.*:RCC:.*", ("rcc", "l4", "RCC")),
|
("STM32L4.*:RCC:.*", ("rcc", "l4", "RCC")),
|
||||||
("STM32L5.*:RCC:.*", ("rcc", "l5", "RCC")),
|
("STM32L5.*:RCC:.*", ("rcc", "l5", "RCC")),
|
||||||
("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")),
|
("STM32U5.*:RCC:.*", ("rcc", "u5", "RCC")),
|
||||||
|
("STM32H50.*:RCC:.*", ("rcc", "h50", "RCC")),
|
||||||
|
("STM32H5.*:RCC:.*", ("rcc", "h5", "RCC")),
|
||||||
("STM32WB.*:RCC:.*", ("rcc", "wb", "RCC")),
|
("STM32WB.*:RCC:.*", ("rcc", "wb", "RCC")),
|
||||||
("STM32WL5.*:RCC:.*", ("rcc", "wl5", "RCC")),
|
("STM32WL5.*:RCC:.*", ("rcc", "wl5", "RCC")),
|
||||||
("STM32WLE.*:RCC:.*", ("rcc", "wle", "RCC")),
|
("STM32WLE.*:RCC:.*", ("rcc", "wle", "RCC")),
|
||||||
@ -276,6 +282,8 @@ impl PeriMatcher {
|
|||||||
("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")),
|
("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")),
|
||||||
("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")),
|
("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")),
|
||||||
("STM32WB.*:PWR:.*", ("pwr", "wb55", "PWR")),
|
("STM32WB.*:PWR:.*", ("pwr", "wb55", "PWR")),
|
||||||
|
("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")),
|
||||||
|
("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")),
|
||||||
("STM32H7.*:FLASH:.*", ("flash", "h7", "FLASH")),
|
("STM32H7.*:FLASH:.*", ("flash", "h7", "FLASH")),
|
||||||
("STM32F0.*:FLASH:.*", ("flash", "f0", "FLASH")),
|
("STM32F0.*:FLASH:.*", ("flash", "f0", "FLASH")),
|
||||||
("STM32F1.*:FLASH:.*", ("flash", "f1", "FLASH")),
|
("STM32F1.*:FLASH:.*", ("flash", "f1", "FLASH")),
|
||||||
@ -292,6 +300,8 @@ impl PeriMatcher {
|
|||||||
("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")),
|
("STM32WL.*:FLASH:.*", ("flash", "wl", "FLASH")),
|
||||||
("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")),
|
("STM32C0.*:FLASH:.*", ("flash", "c0", "FLASH")),
|
||||||
("STM32G0.*:FLASH:.*", ("flash", "g0", "FLASH")),
|
("STM32G0.*:FLASH:.*", ("flash", "g0", "FLASH")),
|
||||||
|
("STM32H50.*:FLASH:.*", ("flash", "h50", "FLASH")),
|
||||||
|
("STM32H5.*:FLASH:.*", ("flash", "h5", "FLASH")),
|
||||||
("STM32F107.*:ETH:.*", ("eth", "v1a", "ETH")),
|
("STM32F107.*:ETH:.*", ("eth", "v1a", "ETH")),
|
||||||
("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")),
|
("STM32F[24].*:ETH:.*", ("eth", "v1b", "ETH")),
|
||||||
("STM32F7.*:ETH:.*", ("eth", "v1c", "ETH")),
|
("STM32F7.*:ETH:.*", ("eth", "v1c", "ETH")),
|
||||||
@ -474,13 +484,13 @@ pub fn parse_groups() -> Result<(HashMap<String, Chip>, Vec<ChipGroup>), anyhow:
|
|||||||
}
|
}
|
||||||
|
|
||||||
static NOPELIST: &[&str] = &[
|
static NOPELIST: &[&str] = &[
|
||||||
// Not supported
|
// Not supported, not planned unless someone wants to do it.
|
||||||
"STM32MP",
|
"STM32MP",
|
||||||
|
// Not supported yet, planned.
|
||||||
|
"STM32WBA",
|
||||||
// Does not exist in ST website. No datasheet, no RM.
|
// Does not exist in ST website. No datasheet, no RM.
|
||||||
"STM32GBK",
|
"STM32GBK",
|
||||||
"STM32L485",
|
"STM32L485",
|
||||||
"STM32U59",
|
|
||||||
"STM32U5A",
|
|
||||||
// STM32WxM modules. These are based on a chip that's supported on its own,
|
// STM32WxM modules. These are based on a chip that's supported on its own,
|
||||||
// not sure why we want a separate target for it.
|
// not sure why we want a separate target for it.
|
||||||
"STM32WL5M",
|
"STM32WL5M",
|
||||||
@ -687,10 +697,18 @@ fn process_core(
|
|||||||
if ["L5", "U5"].contains(&&chip_name[5..7]) {
|
if ["L5", "U5"].contains(&&chip_name[5..7]) {
|
||||||
want_nvic_name = "NVIC2"
|
want_nvic_name = "NVIC2"
|
||||||
}
|
}
|
||||||
|
if ["H56", "H57"].contains(&&chip_name[5..8]) {
|
||||||
|
want_nvic_name = "NVIC2"
|
||||||
|
}
|
||||||
|
|
||||||
want_nvic_name
|
want_nvic_name
|
||||||
};
|
};
|
||||||
let chip_nvic = group.ips.values().find(|x| x.name == want_nvic_name).unwrap();
|
let chip_nvic = group
|
||||||
|
.ips
|
||||||
|
.values()
|
||||||
|
.find(|x| x.name == want_nvic_name)
|
||||||
|
.ok_or_else(|| format!("couldn't find nvic. chip_name={chip_name} want_nvic_name={want_nvic_name}"))
|
||||||
|
.unwrap();
|
||||||
|
|
||||||
// With the current data sources, this value is always either 2 or 4, and never resolves to None
|
// With the current data sources, this value is always either 2 or 4, and never resolves to None
|
||||||
let nvic_priority_bits = defines.0.get("__NVIC_PRIO_BITS").map(|bits| *bits as u8);
|
let nvic_priority_bits = defines.0.get("__NVIC_PRIO_BITS").map(|bits| *bits as u8);
|
||||||
@ -778,7 +796,7 @@ fn process_core(
|
|||||||
const GHOST_PERIS: &[&str] = &[
|
const GHOST_PERIS: &[&str] = &[
|
||||||
"GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", "GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL",
|
"GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG", "GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL",
|
||||||
"GPIOM", "GPION", "GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "DMA1", "DMA2", "BDMA", "DMAMUX",
|
"GPIOM", "GPION", "GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "DMA1", "DMA2", "BDMA", "DMAMUX",
|
||||||
"DMAMUX1", "DMAMUX2", "SYSCFG", "EXTI", "FLASH", "DBGMCU", "CRS", "PWR", "AFIO", "BKP",
|
"DMAMUX1", "DMAMUX2", "SBS", "SYSCFG", "EXTI", "FLASH", "DBGMCU", "CRS", "PWR", "AFIO", "BKP",
|
||||||
];
|
];
|
||||||
for pname in GHOST_PERIS {
|
for pname in GHOST_PERIS {
|
||||||
if let Entry::Vacant(entry) = peri_kinds.entry(pname.to_string()) {
|
if let Entry::Vacant(entry) = peri_kinds.entry(pname.to_string()) {
|
||||||
@ -857,7 +875,7 @@ fn process_core(
|
|||||||
}
|
}
|
||||||
|
|
||||||
if let Some(rcc_info) = peripheral_to_clock.match_peri_clock(
|
if let Some(rcc_info) = peripheral_to_clock.match_peri_clock(
|
||||||
(
|
&(
|
||||||
rcc_block.0.to_string(),
|
rcc_block.0.to_string(),
|
||||||
rcc_block.1.to_string(),
|
rcc_block.1.to_string(),
|
||||||
rcc_block.2.to_string(),
|
rcc_block.2.to_string(),
|
||||||
|
|||||||
@ -292,52 +292,57 @@ impl DmaChannels {
|
|||||||
dma_channels.insert(ff, chip_dma);
|
dma_channels.insert(ff, chip_dma);
|
||||||
}
|
}
|
||||||
|
|
||||||
// STM32U5
|
// GPDMA
|
||||||
|
|
||||||
let mut chip_dma = ChipDma {
|
for (file, gpdmax, instance) in [
|
||||||
peripherals: HashMap::new(),
|
("data/dmamux/H5_GPDMA.yaml", "GPDMA1", "STM32H5_dma3_Cube"),
|
||||||
channels: Vec::new(),
|
("data/dmamux/H5_GPDMA.yaml", "GPDMA2", "Instance2_STM32H5_dma3_Cube"),
|
||||||
};
|
("data/dmamux/U5_GPDMA1.yaml", "GPDMA1", "STM32U5_dma3_Cube"),
|
||||||
|
] {
|
||||||
let parsed: HashMap<String, u8> =
|
let mut chip_dma = ChipDma {
|
||||||
serde_yaml::from_str(&std::fs::read_to_string("data/dmamux/U5_GPDMA1.yaml")?)?;
|
peripherals: HashMap::new(),
|
||||||
|
channels: Vec::new(),
|
||||||
for (request_name, request_num) in parsed {
|
|
||||||
let parts: Vec<_> = request_name.split('_').collect();
|
|
||||||
let target_peri_name = parts[0];
|
|
||||||
let request = {
|
|
||||||
if parts.len() < 2 {
|
|
||||||
target_peri_name
|
|
||||||
} else {
|
|
||||||
parts[1]
|
|
||||||
}
|
|
||||||
};
|
};
|
||||||
chip_dma
|
|
||||||
.peripherals
|
let parsed: HashMap<String, u8> = serde_yaml::from_str(&std::fs::read_to_string(file)?)?;
|
||||||
.entry(target_peri_name.to_string())
|
|
||||||
.or_default()
|
for (request_name, request_num) in parsed {
|
||||||
.push(stm32_data_serde::chip::core::peripheral::DmaChannel {
|
let parts: Vec<_> = request_name.split('_').collect();
|
||||||
signal: request.to_string(),
|
let target_peri_name = parts[0];
|
||||||
dma: Some("GPDMA1".to_string()),
|
let request = {
|
||||||
channel: None,
|
if parts.len() < 2 {
|
||||||
|
target_peri_name
|
||||||
|
} else {
|
||||||
|
parts[1]
|
||||||
|
}
|
||||||
|
};
|
||||||
|
chip_dma
|
||||||
|
.peripherals
|
||||||
|
.entry(target_peri_name.to_string())
|
||||||
|
.or_default()
|
||||||
|
.push(stm32_data_serde::chip::core::peripheral::DmaChannel {
|
||||||
|
signal: request.to_string(),
|
||||||
|
dma: Some(gpdmax.to_string()),
|
||||||
|
channel: None,
|
||||||
|
dmamux: None,
|
||||||
|
request: Some(request_num),
|
||||||
|
});
|
||||||
|
}
|
||||||
|
|
||||||
|
for i in 0..16 {
|
||||||
|
chip_dma.channels.push(stm32_data_serde::chip::core::DmaChannels {
|
||||||
|
name: format!("{gpdmax}_CH{i}"),
|
||||||
|
dma: gpdmax.to_string(),
|
||||||
|
channel: i,
|
||||||
dmamux: None,
|
dmamux: None,
|
||||||
request: Some(request_num),
|
dmamux_channel: None,
|
||||||
|
supports_2d: Some(i >= 12),
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
|
|
||||||
for i in 0..16 {
|
dma_channels.insert(instance.to_string(), chip_dma);
|
||||||
chip_dma.channels.push(stm32_data_serde::chip::core::DmaChannels {
|
|
||||||
name: format!("GPDMA1_CH{i}"),
|
|
||||||
dma: "GPDMA1".to_string(),
|
|
||||||
channel: i,
|
|
||||||
dmamux: None,
|
|
||||||
dmamux_channel: None,
|
|
||||||
supports_2d: Some(i >= 12),
|
|
||||||
});
|
|
||||||
}
|
}
|
||||||
|
|
||||||
dma_channels.insert("STM32U5_dma3_Cube".to_string(), chip_dma);
|
|
||||||
|
|
||||||
Ok(Self(dma_channels))
|
Ok(Self(dma_channels))
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
@ -1,5 +1,7 @@
|
|||||||
use std::collections::{HashMap, HashSet};
|
use std::collections::{HashMap, HashSet};
|
||||||
|
|
||||||
|
use log::*;
|
||||||
|
|
||||||
use crate::regex;
|
use crate::regex;
|
||||||
|
|
||||||
mod xml {
|
mod xml {
|
||||||
@ -48,6 +50,7 @@ impl ChipInterrupts {
|
|||||||
files.sort();
|
files.sort();
|
||||||
|
|
||||||
for f in files {
|
for f in files {
|
||||||
|
trace!("parsing {f:?}");
|
||||||
let mut irqs = HashMap::<String, _>::new();
|
let mut irqs = HashMap::<String, _>::new();
|
||||||
let file = std::fs::read_to_string(f)?;
|
let file = std::fs::read_to_string(f)?;
|
||||||
let parsed: xml::Ip = quick_xml::de::from_str(&file)?;
|
let parsed: xml::Ip = quick_xml::de::from_str(&file)?;
|
||||||
@ -57,6 +60,7 @@ impl ChipInterrupts {
|
|||||||
.filter(|param| param.name == "IRQn")
|
.filter(|param| param.name == "IRQn")
|
||||||
.flat_map(|param| param.possible_values)
|
.flat_map(|param| param.possible_values)
|
||||||
{
|
{
|
||||||
|
trace!(" irq={irq:?}");
|
||||||
let parts = {
|
let parts = {
|
||||||
let mut iter = irq.value.split(':');
|
let mut iter = irq.value.split(':');
|
||||||
let parts = [(); 5].map(|_| iter.next().unwrap());
|
let parts = [(); 5].map(|_| iter.next().unwrap());
|
||||||
@ -64,17 +68,16 @@ impl ChipInterrupts {
|
|||||||
parts
|
parts
|
||||||
};
|
};
|
||||||
|
|
||||||
let name = {
|
let mut name = parts[0].strip_suffix("_IRQn").unwrap().to_string();
|
||||||
let name = parts[0].strip_suffix("_IRQn").unwrap();
|
|
||||||
|
|
||||||
// Fix typo in STM32Lxx and L083 devices
|
// Fix typo in STM32Lxx and L083 devices
|
||||||
let contains_rng = || parts[2..].iter().flat_map(|x| x.split(',')).any(|x| x == "RNG");
|
let contains_rng = || parts[2..].iter().flat_map(|x| x.split(',')).any(|x| x == "RNG");
|
||||||
if name == "AES_RNG_LPUART1" && !contains_rng() {
|
if name == "AES_RNG_LPUART1" && !contains_rng() {
|
||||||
"AES_LPUART1"
|
name = "AES_LPUART1".to_string()
|
||||||
} else {
|
}
|
||||||
name
|
|
||||||
}
|
// More typos
|
||||||
};
|
let name = name.replace("USAR11", "USART11");
|
||||||
|
|
||||||
let entry = match irqs.entry(name.to_string()) {
|
let entry = match irqs.entry(name.to_string()) {
|
||||||
std::collections::hash_map::Entry::Occupied(_) => continue,
|
std::collections::hash_map::Entry::Occupied(_) => continue,
|
||||||
@ -105,6 +108,11 @@ impl ChipInterrupts {
|
|||||||
if parsed.version.starts_with("STM32F3") && irq.comment.contains("remap") {
|
if parsed.version.starts_with("STM32F3") && irq.comment.contains("remap") {
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
// not supported
|
||||||
|
if name == "LSECSSD" {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
let mut signals = HashSet::<(String, String)>::new();
|
let mut signals = HashSet::<(String, String)>::new();
|
||||||
if [
|
if [
|
||||||
"NonMaskableInt",
|
"NonMaskableInt",
|
||||||
@ -117,7 +125,7 @@ impl ChipInterrupts {
|
|||||||
"PendSV",
|
"PendSV",
|
||||||
"SysTick",
|
"SysTick",
|
||||||
]
|
]
|
||||||
.contains(&name)
|
.contains(&name.as_str())
|
||||||
{
|
{
|
||||||
// pass
|
// pass
|
||||||
} else if flags
|
} else if flags
|
||||||
@ -171,7 +179,7 @@ impl ChipInterrupts {
|
|||||||
if name == "USBWakeUp" || name == "USBWakeUp_RMP" {
|
if name == "USBWakeUp" || name == "USBWakeUp_RMP" {
|
||||||
"USB_WKUP"
|
"USB_WKUP"
|
||||||
} else {
|
} else {
|
||||||
name.strip_suffix("_S").unwrap_or(name)
|
name.strip_suffix("_S").unwrap_or(&name)
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -205,6 +213,7 @@ impl ChipInterrupts {
|
|||||||
signals.insert(("RCC".to_string(), "CRS".to_string()));
|
signals.insert(("RCC".to_string(), "CRS".to_string()));
|
||||||
} else {
|
} else {
|
||||||
let pp = match_peris(&peri_names, &part);
|
let pp = match_peris(&peri_names, &part);
|
||||||
|
trace!(" part={part}, pp={pp:?}");
|
||||||
if !pp.is_empty() {
|
if !pp.is_empty() {
|
||||||
curr_peris = pp;
|
curr_peris = pp;
|
||||||
} else {
|
} else {
|
||||||
@ -230,7 +239,7 @@ impl ChipInterrupts {
|
|||||||
|
|
||||||
for s in ss {
|
for s in ss {
|
||||||
if !known.contains(&s.clone()) {
|
if !known.contains(&s.clone()) {
|
||||||
panic!("Unknown signal {s} for peri {p}, known={known:?}");
|
panic!("Unknown signal {s} for peri {p}, known={known:?}, parts={parts:?}");
|
||||||
}
|
}
|
||||||
signals.insert((p.clone(), s));
|
signals.insert((p.clone(), s));
|
||||||
}
|
}
|
||||||
@ -282,7 +291,8 @@ impl ChipInterrupts {
|
|||||||
fn tokenize_name(name: &str) -> Vec<String> {
|
fn tokenize_name(name: &str) -> Vec<String> {
|
||||||
// Treat IRQ names are "tokens" separated by `_`, except some tokens
|
// Treat IRQ names are "tokens" separated by `_`, except some tokens
|
||||||
// contain `_` themselves, such as `C1_RX`.
|
// contain `_` themselves, such as `C1_RX`.
|
||||||
let r = regex!(r"(SPDIF_RX|EP\d+_(IN|OUT)|OTG_FS|OTG_HS|USB_FS|C1_RX|C1_TX|C2_RX|C2_TX|[A-Z0-9]+(_\d+)*)_*");
|
let r =
|
||||||
|
regex!(r"(SPDIF_RX|EP\d+_(IN|OUT)|OTG_FS|OTG_HS|USB_DRD_FS|USB_FS|C1_RX|C1_TX|C2_RX|C2_TX|[A-Z0-9]+(_\d+)*)_*");
|
||||||
let name = name.to_ascii_uppercase();
|
let name = name.to_ascii_uppercase();
|
||||||
|
|
||||||
r.captures_iter(&name)
|
r.captures_iter(&name)
|
||||||
@ -296,6 +306,7 @@ fn match_peris(peris: &[String], name: &str) -> Vec<String> {
|
|||||||
("OTG_HS", &["USB_OTG_HS"]),
|
("OTG_HS", &["USB_OTG_HS"]),
|
||||||
("OTG_FS", &["USB_OTG_FS"]),
|
("OTG_FS", &["USB_OTG_FS"]),
|
||||||
("USB", &["USB_DRD_FS"]),
|
("USB", &["USB_DRD_FS"]),
|
||||||
|
("USB_DRD_FS", &["USB"]),
|
||||||
("UCPD1_2", &["UCPD1", "UCPD2"]),
|
("UCPD1_2", &["UCPD1", "UCPD2"]),
|
||||||
("ADC1", &["ADC"]),
|
("ADC1", &["ADC"]),
|
||||||
("CEC", &["HDMI_CEC"]),
|
("CEC", &["HDMI_CEC"]),
|
||||||
@ -348,6 +359,7 @@ fn valid_signals(peri: &str) -> Vec<String> {
|
|||||||
("CAN", &["TX", "RX0", "RX1", "SCE"]),
|
("CAN", &["TX", "RX0", "RX1", "SCE"]),
|
||||||
("FDCAN", &["IT0", "IT1", "CAL"]),
|
("FDCAN", &["IT0", "IT1", "CAL"]),
|
||||||
("I2C", &["ER", "EV"]),
|
("I2C", &["ER", "EV"]),
|
||||||
|
("I3C", &["ER", "EV"]),
|
||||||
("FMPI2C", &["ER", "EV"]),
|
("FMPI2C", &["ER", "EV"]),
|
||||||
("TIM", &["BRK", "UP", "TRG", "COM", "CC"]),
|
("TIM", &["BRK", "UP", "TRG", "COM", "CC"]),
|
||||||
// ("HRTIM", &["Master", "TIMA", "TIMB", "TIMC", "TIMD", "TIME", "TIMF"]),
|
// ("HRTIM", &["Master", "TIMA", "TIMB", "TIMC", "TIMD", "TIME", "TIMF"]),
|
||||||
@ -368,7 +380,7 @@ fn valid_signals(peri: &str) -> Vec<String> {
|
|||||||
&["FLT0", "FLT1", "FLT2", "FLT3", "FLT4", "FLT5", "FLT6", "FLT7"],
|
&["FLT0", "FLT1", "FLT2", "FLT3", "FLT4", "FLT5", "FLT6", "FLT7"],
|
||||||
),
|
),
|
||||||
("MDF", &["FLT0", "FLT1", "FLT2", "FLT3", "FLT4", "FLT5", "FLT6", "FLT7"]),
|
("MDF", &["FLT0", "FLT1", "FLT2", "FLT3", "FLT4", "FLT5", "FLT6", "FLT7"]),
|
||||||
("PWR", &["S3WU"]),
|
("PWR", &["S3WU", "WKUP"]),
|
||||||
("GTZC", &["GLOBAL", "ILA"]),
|
("GTZC", &["GLOBAL", "ILA"]),
|
||||||
("WWDG", &["GLOBAL", "RST"]),
|
("WWDG", &["GLOBAL", "RST"]),
|
||||||
("USB_OTG_FS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]),
|
("USB_OTG_FS", &["GLOBAL", "EP1_OUT", "EP1_IN", "WKUP"]),
|
||||||
|
|||||||
@ -56,6 +56,8 @@ impl Stopwatch {
|
|||||||
}
|
}
|
||||||
|
|
||||||
fn main() -> anyhow::Result<()> {
|
fn main() -> anyhow::Result<()> {
|
||||||
|
pretty_env_logger::init();
|
||||||
|
|
||||||
let mut stopwatch = Stopwatch::new();
|
let mut stopwatch = Stopwatch::new();
|
||||||
|
|
||||||
stopwatch.section("Parsing headers");
|
stopwatch.section("Parsing headers");
|
||||||
|
|||||||
@ -73,14 +73,23 @@ impl PeripheralToClock {
|
|||||||
|
|
||||||
pub fn match_peri_clock(
|
pub fn match_peri_clock(
|
||||||
&self,
|
&self,
|
||||||
rcc_block: (String, String, String),
|
rcc_block: &(String, String, String),
|
||||||
peri_name: &str,
|
peri_name: &str,
|
||||||
) -> Option<&stm32_data_serde::chip::core::peripheral::Rcc> {
|
) -> Option<&stm32_data_serde::chip::core::peripheral::Rcc> {
|
||||||
let clocks = self.0.get(&rcc_block)?;
|
const PERI_OVERRIDE: &[(&str, &[&str])] = &[("DCMI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"])];
|
||||||
|
|
||||||
|
let clocks = self.0.get(rcc_block)?;
|
||||||
if let Some(res) = clocks.get(peri_name) {
|
if let Some(res) = clocks.get(peri_name) {
|
||||||
Some(res)
|
Some(res)
|
||||||
} else if let Some(peri_name) = peri_name.strip_suffix('1') {
|
} else if let Some(peri_name) = peri_name.strip_suffix('1') {
|
||||||
self.match_peri_clock(rcc_block, peri_name)
|
self.match_peri_clock(rcc_block, peri_name)
|
||||||
|
} else if let Some((_, rename)) = PERI_OVERRIDE.iter().find(|(n, _)| *n == peri_name) {
|
||||||
|
for n in *rename {
|
||||||
|
if let Some(res) = self.match_peri_clock(rcc_block, n) {
|
||||||
|
return Some(res);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
None
|
||||||
} else {
|
} else {
|
||||||
None
|
None
|
||||||
}
|
}
|
||||||
|
|||||||
@ -1,6 +1,6 @@
|
|||||||
[package]
|
[package]
|
||||||
name = "stm32-metapac"
|
name = "stm32-metapac"
|
||||||
version = "1.0.0"
|
version = "2.0.0"
|
||||||
edition = "2021"
|
edition = "2021"
|
||||||
license = "MIT OR Apache-2.0"
|
license = "MIT OR Apache-2.0"
|
||||||
repository = "https://github.com/embassy-rs/stm32-data"
|
repository = "https://github.com/embassy-rs/stm32-data"
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user